./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.07.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.07.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 19:49:16,660 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 19:49:16,662 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 19:49:16,679 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 19:49:16,679 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 19:49:16,680 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 19:49:16,681 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 19:49:16,683 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 19:49:16,684 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 19:49:16,685 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 19:49:16,686 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 19:49:16,687 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 19:49:16,687 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 19:49:16,688 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 19:49:16,689 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 19:49:16,690 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 19:49:16,691 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 19:49:16,691 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 19:49:16,693 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 19:49:16,694 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 19:49:16,696 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 19:49:16,697 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 19:49:16,698 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 19:49:16,698 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 19:49:16,701 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 19:49:16,702 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 19:49:16,702 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 19:49:16,703 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 19:49:16,703 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 19:49:16,704 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 19:49:16,704 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 19:49:16,705 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 19:49:16,706 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 19:49:16,706 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 19:49:16,707 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 19:49:16,707 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 19:49:16,708 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 19:49:16,708 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 19:49:16,708 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 19:49:16,709 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 19:49:16,710 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 19:49:16,711 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 19:49:16,731 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 19:49:16,731 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 19:49:16,732 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 19:49:16,732 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 19:49:16,733 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 19:49:16,733 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 19:49:16,733 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 19:49:16,733 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 19:49:16,733 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 19:49:16,734 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 19:49:16,734 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 19:49:16,734 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 19:49:16,734 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 19:49:16,734 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 19:49:16,734 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 19:49:16,734 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 19:49:16,735 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 19:49:16,735 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 19:49:16,735 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 19:49:16,735 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 19:49:16,735 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 19:49:16,736 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 19:49:16,736 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 19:49:16,736 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 19:49:16,736 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 19:49:16,736 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 19:49:16,736 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 19:49:16,736 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 19:49:16,737 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 19:49:16,737 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 19:49:16,737 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 19:49:16,738 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 19:49:16,738 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f [2022-12-13 19:49:16,914 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 19:49:16,931 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 19:49:16,933 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 19:49:16,934 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 19:49:16,934 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 19:49:16,935 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/transmitter.07.cil.c [2022-12-13 19:49:19,617 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 19:49:19,787 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 19:49:19,787 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/sv-benchmarks/c/systemc/transmitter.07.cil.c [2022-12-13 19:49:19,794 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/data/6c34cc9be/7bfa3a27abd741a4a62d0eb710134340/FLAGd68ccd930 [2022-12-13 19:49:19,804 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/data/6c34cc9be/7bfa3a27abd741a4a62d0eb710134340 [2022-12-13 19:49:19,806 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 19:49:19,807 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 19:49:19,808 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 19:49:19,808 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 19:49:19,812 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 19:49:19,812 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 07:49:19" (1/1) ... [2022-12-13 19:49:19,813 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@494bdc0d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:19, skipping insertion in model container [2022-12-13 19:49:19,813 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 07:49:19" (1/1) ... [2022-12-13 19:49:19,820 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 19:49:19,851 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 19:49:19,950 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/sv-benchmarks/c/systemc/transmitter.07.cil.c[706,719] [2022-12-13 19:49:20,023 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 19:49:20,033 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 19:49:20,041 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/sv-benchmarks/c/systemc/transmitter.07.cil.c[706,719] [2022-12-13 19:49:20,073 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 19:49:20,090 INFO L208 MainTranslator]: Completed translation [2022-12-13 19:49:20,090 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:20 WrapperNode [2022-12-13 19:49:20,090 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 19:49:20,091 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 19:49:20,092 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 19:49:20,092 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 19:49:20,099 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:20" (1/1) ... [2022-12-13 19:49:20,109 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:20" (1/1) ... [2022-12-13 19:49:20,160 INFO L138 Inliner]: procedures = 42, calls = 51, calls flagged for inlining = 46, calls inlined = 124, statements flattened = 1845 [2022-12-13 19:49:20,161 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 19:49:20,161 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 19:49:20,161 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 19:49:20,161 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 19:49:20,170 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:20" (1/1) ... [2022-12-13 19:49:20,170 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:20" (1/1) ... [2022-12-13 19:49:20,174 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:20" (1/1) ... [2022-12-13 19:49:20,174 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:20" (1/1) ... [2022-12-13 19:49:20,193 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:20" (1/1) ... [2022-12-13 19:49:20,210 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:20" (1/1) ... [2022-12-13 19:49:20,213 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:20" (1/1) ... [2022-12-13 19:49:20,218 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:20" (1/1) ... [2022-12-13 19:49:20,226 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 19:49:20,227 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 19:49:20,227 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 19:49:20,227 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 19:49:20,229 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:20" (1/1) ... [2022-12-13 19:49:20,235 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 19:49:20,248 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 19:49:20,260 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 19:49:20,262 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 19:49:20,301 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 19:49:20,301 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 19:49:20,301 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 19:49:20,302 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 19:49:20,381 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 19:49:20,383 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 19:49:21,288 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 19:49:21,297 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 19:49:21,297 INFO L300 CfgBuilder]: Removed 11 assume(true) statements. [2022-12-13 19:49:21,299 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:49:21 BoogieIcfgContainer [2022-12-13 19:49:21,299 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 19:49:21,300 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 19:49:21,300 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 19:49:21,303 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 19:49:21,303 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:49:21,303 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 07:49:19" (1/3) ... [2022-12-13 19:49:21,304 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@27fe3ba3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 07:49:21, skipping insertion in model container [2022-12-13 19:49:21,304 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:49:21,304 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:49:20" (2/3) ... [2022-12-13 19:49:21,305 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@27fe3ba3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 07:49:21, skipping insertion in model container [2022-12-13 19:49:21,305 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:49:21,305 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:49:21" (3/3) ... [2022-12-13 19:49:21,306 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.07.cil.c [2022-12-13 19:49:21,352 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 19:49:21,352 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 19:49:21,353 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 19:49:21,353 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 19:49:21,353 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 19:49:21,353 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 19:49:21,353 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 19:49:21,353 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 19:49:21,358 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:21,389 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 670 [2022-12-13 19:49:21,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:21,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:21,396 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:21,397 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:21,397 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 19:49:21,398 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:21,407 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 670 [2022-12-13 19:49:21,407 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:21,407 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:21,409 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:21,410 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:21,416 INFO L748 eck$LassoCheckResult]: Stem: 107#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 709#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 565#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 706#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 642#L521true assume !(1 == ~m_i~0);~m_st~0 := 2; 606#L521-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 635#L526-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 191#L531-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 545#L536-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 238#L541-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 138#L546-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 597#L551-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 122#L556-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 680#L754true assume !(0 == ~M_E~0); 727#L754-2true assume !(0 == ~T1_E~0); 505#L759-1true assume !(0 == ~T2_E~0); 375#L764-1true assume !(0 == ~T3_E~0); 337#L769-1true assume !(0 == ~T4_E~0); 376#L774-1true assume !(0 == ~T5_E~0); 628#L779-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 515#L784-1true assume !(0 == ~T7_E~0); 335#L789-1true assume !(0 == ~E_1~0); 420#L794-1true assume !(0 == ~E_2~0); 755#L799-1true assume !(0 == ~E_3~0); 344#L804-1true assume !(0 == ~E_4~0); 371#L809-1true assume !(0 == ~E_5~0); 546#L814-1true assume !(0 == ~E_6~0); 9#L819-1true assume 0 == ~E_7~0;~E_7~0 := 1; 170#L824-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137#L361true assume 1 == ~m_pc~0; 667#L362true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 703#L372true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 495#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 625#L930true assume !(0 != activate_threads_~tmp~1#1); 269#L930-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134#L380true assume !(1 == ~t1_pc~0); 756#L380-2true is_transmit1_triggered_~__retres1~1#1 := 0; 636#L391true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 760#L938true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 457#L938-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 435#L399true assume 1 == ~t2_pc~0; 630#L400true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 646#L410true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 177#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 174#L946true assume !(0 != activate_threads_~tmp___1~0#1); 411#L946-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13#L418true assume !(1 == ~t3_pc~0); 689#L418-2true is_transmit3_triggered_~__retres1~3#1 := 0; 548#L429true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 768#L954true assume !(0 != activate_threads_~tmp___2~0#1); 360#L954-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 682#L437true assume 1 == ~t4_pc~0; 745#L438true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 490#L448true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 207#L962true assume !(0 != activate_threads_~tmp___3~0#1); 588#L962-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 475#L456true assume !(1 == ~t5_pc~0); 328#L456-2true is_transmit5_triggered_~__retres1~5#1 := 0; 672#L467true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 498#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 407#L970true assume !(0 != activate_threads_~tmp___4~0#1); 724#L970-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45#L475true assume 1 == ~t6_pc~0; 219#L476true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66#L486true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 399#L978true assume !(0 != activate_threads_~tmp___5~0#1); 350#L978-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 543#L494true assume 1 == ~t7_pc~0; 301#L495true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 314#L505true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 721#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 377#L986true assume !(0 != activate_threads_~tmp___6~0#1); 751#L986-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 660#L837true assume !(1 == ~M_E~0); 564#L837-2true assume !(1 == ~T1_E~0); 430#L842-1true assume !(1 == ~T2_E~0); 214#L847-1true assume !(1 == ~T3_E~0); 262#L852-1true assume !(1 == ~T4_E~0); 772#L857-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 180#L862-1true assume !(1 == ~T6_E~0); 187#L867-1true assume !(1 == ~T7_E~0); 237#L872-1true assume !(1 == ~E_1~0); 389#L877-1true assume !(1 == ~E_2~0); 573#L882-1true assume !(1 == ~E_3~0); 698#L887-1true assume !(1 == ~E_4~0); 451#L892-1true assume !(1 == ~E_5~0); 652#L897-1true assume 1 == ~E_6~0;~E_6~0 := 2; 197#L902-1true assume !(1 == ~E_7~0); 474#L907-1true assume { :end_inline_reset_delta_events } true; 228#L1148-2true [2022-12-13 19:49:21,418 INFO L750 eck$LassoCheckResult]: Loop: 228#L1148-2true assume !false; 10#L1149true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 109#L729true assume !true; 452#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 268#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 146#L754-3true assume 0 == ~M_E~0;~M_E~0 := 1; 16#L754-5true assume !(0 == ~T1_E~0); 526#L759-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 223#L764-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 610#L769-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 361#L774-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 93#L779-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 14#L784-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 765#L789-3true assume 0 == ~E_1~0;~E_1~0 := 1; 11#L794-3true assume !(0 == ~E_2~0); 35#L799-3true assume 0 == ~E_3~0;~E_3~0 := 1; 149#L804-3true assume 0 == ~E_4~0;~E_4~0 := 1; 291#L809-3true assume 0 == ~E_5~0;~E_5~0 := 1; 33#L814-3true assume 0 == ~E_6~0;~E_6~0 := 1; 522#L819-3true assume 0 == ~E_7~0;~E_7~0 := 1; 484#L824-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 234#L361-24true assume !(1 == ~m_pc~0); 528#L361-26true is_master_triggered_~__retres1~0#1 := 0; 299#L372-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59#is_master_triggered_returnLabel#9true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 549#L930-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 579#L930-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 341#L380-24true assume !(1 == ~t1_pc~0); 50#L380-26true is_transmit1_triggered_~__retres1~1#1 := 0; 618#L391-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 295#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 144#L938-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 436#L938-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 501#L399-24true assume 1 == ~t2_pc~0; 738#L400-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 111#L410-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 380#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 261#L946-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 142#L946-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 617#L418-24true assume !(1 == ~t3_pc~0); 32#L418-26true is_transmit3_triggered_~__retres1~3#1 := 0; 183#L429-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 587#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95#L954-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 409#L954-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 552#L437-24true assume !(1 == ~t4_pc~0); 775#L437-26true is_transmit4_triggered_~__retres1~4#1 := 0; 730#L448-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 260#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 87#L962-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 349#L962-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 637#L456-24true assume 1 == ~t5_pc~0; 326#L457-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 304#L467-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 529#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 569#L970-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 270#L970-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 759#L475-24true assume !(1 == ~t6_pc~0); 582#L475-26true is_transmit6_triggered_~__retres1~6#1 := 0; 313#L486-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 345#L978-24true assume !(0 != activate_threads_~tmp___5~0#1); 6#L978-26true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 307#L494-24true assume 1 == ~t7_pc~0; 246#L495-8true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 173#L505-8true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 254#is_transmit7_triggered_returnLabel#9true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 140#L986-24true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 486#L986-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 511#L837-3true assume !(1 == ~M_E~0); 662#L837-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 266#L842-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 602#L847-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 405#L852-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 311#L857-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 736#L862-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 694#L867-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 245#L872-3true assume !(1 == ~E_1~0); 303#L877-3true assume 1 == ~E_2~0;~E_2~0 := 2; 718#L882-3true assume 1 == ~E_3~0;~E_3~0 := 2; 353#L887-3true assume 1 == ~E_4~0;~E_4~0 := 2; 104#L892-3true assume 1 == ~E_5~0;~E_5~0 := 2; 510#L897-3true assume 1 == ~E_6~0;~E_6~0 := 2; 763#L902-3true assume 1 == ~E_7~0;~E_7~0 := 2; 194#L907-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 576#L569-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 364#L611-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 154#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 677#L1167true assume !(0 == start_simulation_~tmp~3#1); 231#L1167-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 735#L569-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 252#L611-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 306#L1122true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 220#L1129true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 279#stop_simulation_returnLabel#1true start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 121#L1180true assume !(0 != start_simulation_~tmp___0~1#1); 228#L1148-2true [2022-12-13 19:49:21,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:21,422 INFO L85 PathProgramCache]: Analyzing trace with hash -171938705, now seen corresponding path program 1 times [2022-12-13 19:49:21,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:21,429 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947486344] [2022-12-13 19:49:21,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:21,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:21,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:21,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:21,597 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:21,598 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1947486344] [2022-12-13 19:49:21,598 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1947486344] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:21,598 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:21,599 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:21,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1965327182] [2022-12-13 19:49:21,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:21,604 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:21,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:21,605 INFO L85 PathProgramCache]: Analyzing trace with hash -183342863, now seen corresponding path program 1 times [2022-12-13 19:49:21,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:21,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699058827] [2022-12-13 19:49:21,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:21,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:21,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:21,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:21,637 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:21,637 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1699058827] [2022-12-13 19:49:21,637 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1699058827] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:21,637 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:21,638 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:49:21,638 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [738534807] [2022-12-13 19:49:21,638 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:21,639 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:21,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:21,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:21,661 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:21,663 INFO L87 Difference]: Start difference. First operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:21,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:21,709 INFO L93 Difference]: Finished difference Result 774 states and 1154 transitions. [2022-12-13 19:49:21,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 774 states and 1154 transitions. [2022-12-13 19:49:21,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:21,721 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 774 states to 768 states and 1148 transitions. [2022-12-13 19:49:21,722 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-12-13 19:49:21,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-12-13 19:49:21,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1148 transitions. [2022-12-13 19:49:21,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:21,726 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1148 transitions. [2022-12-13 19:49:21,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1148 transitions. [2022-12-13 19:49:21,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-12-13 19:49:21,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4947916666666667) internal successors, (1148), 767 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:21,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1148 transitions. [2022-12-13 19:49:21,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1148 transitions. [2022-12-13 19:49:21,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:21,769 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1148 transitions. [2022-12-13 19:49:21,769 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 19:49:21,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1148 transitions. [2022-12-13 19:49:21,774 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:21,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:21,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:21,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:21,777 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:21,777 INFO L748 eck$LassoCheckResult]: Stem: 1979#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1980#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2134#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2135#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2250#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 2198#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2199#L526-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2163#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2071#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2072#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2059#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2060#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2018#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2019#L754 assume !(0 == ~M_E~0); 2282#L754-2 assume !(0 == ~T1_E~0); 1961#L759-1 assume !(0 == ~T2_E~0); 1962#L764-1 assume !(0 == ~T3_E~0); 2314#L769-1 assume !(0 == ~T4_E~0); 2315#L774-1 assume !(0 == ~T5_E~0); 2228#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1989#L784-1 assume !(0 == ~T7_E~0); 1990#L789-1 assume !(0 == ~E_1~0); 1682#L794-1 assume !(0 == ~E_2~0); 1683#L799-1 assume !(0 == ~E_3~0); 2317#L804-1 assume !(0 == ~E_4~0); 2318#L809-1 assume !(0 == ~E_5~0); 2075#L814-1 assume !(0 == ~E_6~0); 1592#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1593#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2056#L361 assume 1 == ~m_pc~0; 2057#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2107#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1928#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1929#L930 assume !(0 != activate_threads_~tmp~1#1); 2225#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2049#L380 assume !(1 == ~t1_pc~0); 1735#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1734#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1649#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1650#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1810#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1736#L399 assume 1 == ~t2_pc~0; 1737#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1934#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2139#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2130#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1630#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1602#L418 assume !(1 == ~t3_pc~0); 1563#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1564#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1590#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1591#L954 assume !(0 != activate_threads_~tmp___2~0#1); 2323#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2284#L437 assume 1 == ~t4_pc~0; 2285#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1903#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1777#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1778#L962 assume !(0 != activate_threads_~tmp___3~0#1); 2176#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1865#L456 assume !(1 == ~t5_pc~0); 1866#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1960#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1940#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1620#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1621#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1755#L475 assume 1 == ~t6_pc~0; 1756#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1830#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1831#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1582#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1583#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2063#L494 assume 1 == ~t7_pc~0; 2064#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2115#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2301#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2316#L986 assume !(0 != activate_threads_~tmp___6~0#1); 2325#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2268#L837 assume !(1 == ~M_E~0); 2133#L837-2 assume !(1 == ~T1_E~0); 1717#L842-1 assume !(1 == ~T2_E~0); 1718#L847-1 assume !(1 == ~T3_E~0); 2193#L852-1 assume !(1 == ~T4_E~0); 2262#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2143#L862-1 assume !(1 == ~T6_E~0); 2144#L867-1 assume !(1 == ~T7_E~0); 2155#L872-1 assume !(1 == ~E_1~0); 2227#L877-1 assume !(1 == ~E_2~0); 2150#L882-1 assume !(1 == ~E_3~0); 2151#L887-1 assume !(1 == ~E_4~0); 1780#L892-1 assume !(1 == ~E_5~0); 1781#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2171#L902-1 assume !(1 == ~E_7~0); 1857#L907-1 assume { :end_inline_reset_delta_events } true; 1858#L1148-2 [2022-12-13 19:49:21,778 INFO L750 eck$LassoCheckResult]: Loop: 1858#L1148-2 assume !false; 1594#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1595#L729 assume !false; 1985#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1982#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1938#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2007#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2045#L626 assume !(0 != eval_~tmp~0#1); 1785#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1786#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2080#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1633#L754-5 assume !(0 == ~T1_E~0); 1634#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2014#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2204#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2205#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1950#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1611#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1612#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1596#L794-3 assume !(0 == ~E_2~0); 1597#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1700#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2088#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1690#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1691#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1888#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1889#L361-24 assume 1 == ~m_pc~0; 1920#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1921#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1805#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1806#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2079#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2161#L380-24 assume 1 == ~t1_pc~0; 2162#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1784#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2223#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2076#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1739#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1740#L399-24 assume 1 == ~t2_pc~0; 1945#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1987#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1988#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2259#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2069#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2070#L418-24 assume !(1 == ~t3_pc~0); 1686#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1687#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2148#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1949#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1622#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1623#L437-24 assume 1 == ~t4_pc~0; 1898#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1899#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2257#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1923#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1924#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2241#L456-24 assume 1 == ~t5_pc~0; 2242#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2296#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2020#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2021#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2140#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2270#L475-24 assume 1 == ~t6_pc~0; 1624#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1625#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1917#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1918#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 1573#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1574#L494-24 assume 1 == ~t7_pc~0; 2240#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2127#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2128#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2062#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1896#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1897#L837-3 assume !(1 == ~M_E~0); 1973#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2267#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2191#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1613#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1614#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2300#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2289#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2238#L872-3 assume !(1 == ~E_1~0); 2239#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2295#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2311#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1975#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1969#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1970#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2164#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2157#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1599#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2096#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2097#L1167 assume !(0 == start_simulation_~tmp~3#1); 2192#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2221#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2004#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1644#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1645#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2206#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2207#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2017#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1858#L1148-2 [2022-12-13 19:49:21,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:21,779 INFO L85 PathProgramCache]: Analyzing trace with hash 598794861, now seen corresponding path program 1 times [2022-12-13 19:49:21,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:21,779 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1897901756] [2022-12-13 19:49:21,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:21,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:21,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:21,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:21,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:21,854 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1897901756] [2022-12-13 19:49:21,854 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1897901756] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:21,854 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:21,854 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:21,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767279735] [2022-12-13 19:49:21,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:21,855 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:21,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:21,855 INFO L85 PathProgramCache]: Analyzing trace with hash 1141273896, now seen corresponding path program 1 times [2022-12-13 19:49:21,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:21,856 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129307217] [2022-12-13 19:49:21,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:21,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:21,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:21,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:21,944 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:21,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129307217] [2022-12-13 19:49:21,944 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1129307217] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:21,944 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:21,944 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:21,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [54964284] [2022-12-13 19:49:21,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:21,945 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:21,945 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:21,945 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:21,946 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:21,946 INFO L87 Difference]: Start difference. First operand 768 states and 1148 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:21,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:21,968 INFO L93 Difference]: Finished difference Result 768 states and 1147 transitions. [2022-12-13 19:49:21,968 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1147 transitions. [2022-12-13 19:49:21,973 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:21,977 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1147 transitions. [2022-12-13 19:49:21,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-12-13 19:49:21,978 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-12-13 19:49:21,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1147 transitions. [2022-12-13 19:49:21,980 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:21,980 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1147 transitions. [2022-12-13 19:49:21,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1147 transitions. [2022-12-13 19:49:21,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-12-13 19:49:21,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4934895833333333) internal successors, (1147), 767 states have internal predecessors, (1147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:21,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1147 transitions. [2022-12-13 19:49:21,999 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1147 transitions. [2022-12-13 19:49:21,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:22,000 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1147 transitions. [2022-12-13 19:49:22,000 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 19:49:22,000 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1147 transitions. [2022-12-13 19:49:22,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:22,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:22,004 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:22,006 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,006 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,007 INFO L748 eck$LassoCheckResult]: Stem: 3522#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 3523#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3677#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3678#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3792#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 3741#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3742#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3706#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3612#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3613#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3602#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3603#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3561#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3562#L754 assume !(0 == ~M_E~0); 3825#L754-2 assume !(0 == ~T1_E~0); 3504#L759-1 assume !(0 == ~T2_E~0); 3505#L764-1 assume !(0 == ~T3_E~0); 3857#L769-1 assume !(0 == ~T4_E~0); 3858#L774-1 assume !(0 == ~T5_E~0); 3771#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3532#L784-1 assume !(0 == ~T7_E~0); 3533#L789-1 assume !(0 == ~E_1~0); 3221#L794-1 assume !(0 == ~E_2~0); 3222#L799-1 assume !(0 == ~E_3~0); 3860#L804-1 assume !(0 == ~E_4~0); 3861#L809-1 assume !(0 == ~E_5~0); 3616#L814-1 assume !(0 == ~E_6~0); 3135#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3136#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3599#L361 assume 1 == ~m_pc~0; 3600#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3650#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3471#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3472#L930 assume !(0 != activate_threads_~tmp~1#1); 3768#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3592#L380 assume !(1 == ~t1_pc~0); 3278#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3277#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3192#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3193#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3353#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3279#L399 assume 1 == ~t2_pc~0; 3280#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3477#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3682#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3673#L946 assume !(0 != activate_threads_~tmp___1~0#1); 3173#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3143#L418 assume !(1 == ~t3_pc~0); 3106#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3107#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3133#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3134#L954 assume !(0 != activate_threads_~tmp___2~0#1); 3866#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3826#L437 assume 1 == ~t4_pc~0; 3827#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3446#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3319#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3320#L962 assume !(0 != activate_threads_~tmp___3~0#1); 3718#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3403#L456 assume !(1 == ~t5_pc~0); 3404#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3503#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3483#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3160#L970 assume !(0 != activate_threads_~tmp___4~0#1); 3161#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3293#L475 assume 1 == ~t6_pc~0; 3294#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3373#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3374#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3125#L978 assume !(0 != activate_threads_~tmp___5~0#1); 3126#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3606#L494 assume 1 == ~t7_pc~0; 3607#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3658#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3844#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3859#L986 assume !(0 != activate_threads_~tmp___6~0#1); 3868#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3809#L837 assume !(1 == ~M_E~0); 3676#L837-2 assume !(1 == ~T1_E~0); 3260#L842-1 assume !(1 == ~T2_E~0); 3261#L847-1 assume !(1 == ~T3_E~0); 3736#L852-1 assume !(1 == ~T4_E~0); 3803#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3686#L862-1 assume !(1 == ~T6_E~0); 3687#L867-1 assume !(1 == ~T7_E~0); 3696#L872-1 assume !(1 == ~E_1~0); 3770#L877-1 assume !(1 == ~E_2~0); 3693#L882-1 assume !(1 == ~E_3~0); 3694#L887-1 assume !(1 == ~E_4~0); 3323#L892-1 assume !(1 == ~E_5~0); 3324#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3712#L902-1 assume !(1 == ~E_7~0); 3400#L907-1 assume { :end_inline_reset_delta_events } true; 3401#L1148-2 [2022-12-13 19:49:22,007 INFO L750 eck$LassoCheckResult]: Loop: 3401#L1148-2 assume !false; 3137#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3138#L729 assume !false; 3528#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3525#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3481#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3550#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3587#L626 assume !(0 != eval_~tmp~0#1); 3328#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3329#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3623#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3174#L754-5 assume !(0 == ~T1_E~0); 3175#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3557#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3747#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3748#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3488#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3152#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3153#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3139#L794-3 assume !(0 == ~E_2~0); 3140#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3243#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3631#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3236#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3237#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3431#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3432#L361-24 assume 1 == ~m_pc~0; 3463#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3464#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3348#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3349#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3622#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3704#L380-24 assume 1 == ~t1_pc~0; 3705#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3327#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3766#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3619#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3282#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3283#L399-24 assume 1 == ~t2_pc~0; 3489#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3530#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3531#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3802#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3614#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3615#L418-24 assume 1 == ~t3_pc~0; 3617#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3230#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3691#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3493#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3165#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3166#L437-24 assume 1 == ~t4_pc~0; 3441#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3442#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3800#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3466#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3467#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3784#L456-24 assume 1 == ~t5_pc~0; 3785#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3839#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3563#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3564#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3685#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3813#L475-24 assume !(1 == ~t6_pc~0); 3169#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 3168#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3460#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3461#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 3116#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3117#L494-24 assume 1 == ~t7_pc~0; 3783#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3670#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3671#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3605#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3439#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3440#L837-3 assume !(1 == ~M_E~0); 3516#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3811#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3735#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3156#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3157#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3843#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3832#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3781#L872-3 assume !(1 == ~E_1~0); 3782#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3838#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3854#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3520#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3514#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3515#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3707#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3700#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3142#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3639#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3640#L1167 assume !(0 == start_simulation_~tmp~3#1); 3734#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3764#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3548#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3187#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 3188#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3749#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3750#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3560#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 3401#L1148-2 [2022-12-13 19:49:22,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,008 INFO L85 PathProgramCache]: Analyzing trace with hash 1185071083, now seen corresponding path program 1 times [2022-12-13 19:49:22,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002074297] [2022-12-13 19:49:22,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1002074297] [2022-12-13 19:49:22,062 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1002074297] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,062 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,062 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:22,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1127486245] [2022-12-13 19:49:22,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,063 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:22,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,063 INFO L85 PathProgramCache]: Analyzing trace with hash -1612054808, now seen corresponding path program 1 times [2022-12-13 19:49:22,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,064 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969259033] [2022-12-13 19:49:22,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,115 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969259033] [2022-12-13 19:49:22,115 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969259033] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,115 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,115 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:22,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2099693630] [2022-12-13 19:49:22,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,116 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:22,116 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:22,116 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:22,116 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:22,116 INFO L87 Difference]: Start difference. First operand 768 states and 1147 transitions. cyclomatic complexity: 380 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:22,129 INFO L93 Difference]: Finished difference Result 768 states and 1146 transitions. [2022-12-13 19:49:22,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1146 transitions. [2022-12-13 19:49:22,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:22,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1146 transitions. [2022-12-13 19:49:22,134 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-12-13 19:49:22,135 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-12-13 19:49:22,135 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1146 transitions. [2022-12-13 19:49:22,136 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:22,136 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1146 transitions. [2022-12-13 19:49:22,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1146 transitions. [2022-12-13 19:49:22,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-12-13 19:49:22,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4921875) internal successors, (1146), 767 states have internal predecessors, (1146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1146 transitions. [2022-12-13 19:49:22,144 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1146 transitions. [2022-12-13 19:49:22,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:22,145 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1146 transitions. [2022-12-13 19:49:22,145 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 19:49:22,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1146 transitions. [2022-12-13 19:49:22,147 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:22,147 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:22,147 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:22,148 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,148 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,149 INFO L748 eck$LassoCheckResult]: Stem: 5065#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 5066#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5220#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5221#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5336#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 5284#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5285#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5249#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5157#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5158#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5145#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5146#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5104#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5105#L754 assume !(0 == ~M_E~0); 5368#L754-2 assume !(0 == ~T1_E~0); 5047#L759-1 assume !(0 == ~T2_E~0); 5048#L764-1 assume !(0 == ~T3_E~0); 5400#L769-1 assume !(0 == ~T4_E~0); 5401#L774-1 assume !(0 == ~T5_E~0); 5314#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5075#L784-1 assume !(0 == ~T7_E~0); 5076#L789-1 assume !(0 == ~E_1~0); 4768#L794-1 assume !(0 == ~E_2~0); 4769#L799-1 assume !(0 == ~E_3~0); 5403#L804-1 assume !(0 == ~E_4~0); 5404#L809-1 assume !(0 == ~E_5~0); 5161#L814-1 assume !(0 == ~E_6~0); 4678#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 4679#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5142#L361 assume 1 == ~m_pc~0; 5143#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5193#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5014#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5015#L930 assume !(0 != activate_threads_~tmp~1#1); 5311#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5135#L380 assume !(1 == ~t1_pc~0); 4821#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4820#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4735#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4736#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4896#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4822#L399 assume 1 == ~t2_pc~0; 4823#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5020#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5225#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5216#L946 assume !(0 != activate_threads_~tmp___1~0#1); 4716#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4688#L418 assume !(1 == ~t3_pc~0); 4649#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4650#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4676#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4677#L954 assume !(0 != activate_threads_~tmp___2~0#1); 5409#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5370#L437 assume 1 == ~t4_pc~0; 5371#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4990#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4863#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4864#L962 assume !(0 != activate_threads_~tmp___3~0#1); 5262#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4951#L456 assume !(1 == ~t5_pc~0); 4952#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5046#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5026#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4706#L970 assume !(0 != activate_threads_~tmp___4~0#1); 4707#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4841#L475 assume 1 == ~t6_pc~0; 4842#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4916#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4917#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4668#L978 assume !(0 != activate_threads_~tmp___5~0#1); 4669#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5149#L494 assume 1 == ~t7_pc~0; 5150#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5201#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5387#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5402#L986 assume !(0 != activate_threads_~tmp___6~0#1); 5411#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5354#L837 assume !(1 == ~M_E~0); 5219#L837-2 assume !(1 == ~T1_E~0); 4803#L842-1 assume !(1 == ~T2_E~0); 4804#L847-1 assume !(1 == ~T3_E~0); 5279#L852-1 assume !(1 == ~T4_E~0); 5348#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5229#L862-1 assume !(1 == ~T6_E~0); 5230#L867-1 assume !(1 == ~T7_E~0); 5241#L872-1 assume !(1 == ~E_1~0); 5313#L877-1 assume !(1 == ~E_2~0); 5236#L882-1 assume !(1 == ~E_3~0); 5237#L887-1 assume !(1 == ~E_4~0); 4866#L892-1 assume !(1 == ~E_5~0); 4867#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5257#L902-1 assume !(1 == ~E_7~0); 4943#L907-1 assume { :end_inline_reset_delta_events } true; 4944#L1148-2 [2022-12-13 19:49:22,149 INFO L750 eck$LassoCheckResult]: Loop: 4944#L1148-2 assume !false; 4680#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4681#L729 assume !false; 5071#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5068#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5024#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5093#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5131#L626 assume !(0 != eval_~tmp~0#1); 4871#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4872#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5166#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4719#L754-5 assume !(0 == ~T1_E~0); 4720#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5100#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5290#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5291#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5036#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4697#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4698#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4682#L794-3 assume !(0 == ~E_2~0); 4683#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4783#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5174#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4776#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4777#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4974#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4975#L361-24 assume !(1 == ~m_pc~0); 5008#L361-26 is_master_triggered_~__retres1~0#1 := 0; 5007#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4891#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4892#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5165#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5247#L380-24 assume 1 == ~t1_pc~0; 5248#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4870#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5309#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5162#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4825#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4826#L399-24 assume 1 == ~t2_pc~0; 5031#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5073#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5074#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5345#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5155#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5156#L418-24 assume !(1 == ~t3_pc~0); 4772#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 4773#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5234#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5035#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4708#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4709#L437-24 assume 1 == ~t4_pc~0; 4984#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4985#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5343#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5009#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5010#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5327#L456-24 assume 1 == ~t5_pc~0; 5328#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5382#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5106#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5107#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5226#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5356#L475-24 assume 1 == ~t6_pc~0; 4710#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4711#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5003#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5004#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 4659#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4660#L494-24 assume !(1 == ~t7_pc~0); 5235#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 5213#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5214#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5148#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4982#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4983#L837-3 assume !(1 == ~M_E~0); 5059#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5353#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5277#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4699#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4700#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5386#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5375#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5324#L872-3 assume !(1 == ~E_1~0); 5325#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5381#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5397#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5061#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5055#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5056#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5250#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5243#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4685#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5182#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5183#L1167 assume !(0 == start_simulation_~tmp~3#1); 5278#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5307#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5090#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 4730#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4731#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5292#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5293#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5103#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 4944#L1148-2 [2022-12-13 19:49:22,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,149 INFO L85 PathProgramCache]: Analyzing trace with hash -1151321427, now seen corresponding path program 1 times [2022-12-13 19:49:22,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,150 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958059001] [2022-12-13 19:49:22,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,176 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [958059001] [2022-12-13 19:49:22,176 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [958059001] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,176 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,176 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:22,176 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550140402] [2022-12-13 19:49:22,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,176 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:22,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,177 INFO L85 PathProgramCache]: Analyzing trace with hash -408258522, now seen corresponding path program 1 times [2022-12-13 19:49:22,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,177 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1617501690] [2022-12-13 19:49:22,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,212 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,212 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1617501690] [2022-12-13 19:49:22,212 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1617501690] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,212 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,213 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:22,213 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953481385] [2022-12-13 19:49:22,213 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,213 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:22,213 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:22,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:22,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:22,214 INFO L87 Difference]: Start difference. First operand 768 states and 1146 transitions. cyclomatic complexity: 379 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:22,226 INFO L93 Difference]: Finished difference Result 768 states and 1145 transitions. [2022-12-13 19:49:22,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1145 transitions. [2022-12-13 19:49:22,229 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:22,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1145 transitions. [2022-12-13 19:49:22,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-12-13 19:49:22,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-12-13 19:49:22,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1145 transitions. [2022-12-13 19:49:22,232 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:22,232 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1145 transitions. [2022-12-13 19:49:22,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1145 transitions. [2022-12-13 19:49:22,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-12-13 19:49:22,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4908854166666667) internal successors, (1145), 767 states have internal predecessors, (1145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1145 transitions. [2022-12-13 19:49:22,240 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1145 transitions. [2022-12-13 19:49:22,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:22,241 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1145 transitions. [2022-12-13 19:49:22,241 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 19:49:22,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1145 transitions. [2022-12-13 19:49:22,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:22,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:22,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:22,245 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,245 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,245 INFO L748 eck$LassoCheckResult]: Stem: 6608#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 6609#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6763#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6764#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6878#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 6827#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6828#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6792#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6698#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6699#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6688#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6689#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6647#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6648#L754 assume !(0 == ~M_E~0); 6911#L754-2 assume !(0 == ~T1_E~0); 6590#L759-1 assume !(0 == ~T2_E~0); 6591#L764-1 assume !(0 == ~T3_E~0); 6943#L769-1 assume !(0 == ~T4_E~0); 6944#L774-1 assume !(0 == ~T5_E~0); 6857#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6618#L784-1 assume !(0 == ~T7_E~0); 6619#L789-1 assume !(0 == ~E_1~0); 6307#L794-1 assume !(0 == ~E_2~0); 6308#L799-1 assume !(0 == ~E_3~0); 6946#L804-1 assume !(0 == ~E_4~0); 6947#L809-1 assume !(0 == ~E_5~0); 6702#L814-1 assume !(0 == ~E_6~0); 6221#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6222#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6685#L361 assume 1 == ~m_pc~0; 6686#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6736#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6557#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6558#L930 assume !(0 != activate_threads_~tmp~1#1); 6854#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6678#L380 assume !(1 == ~t1_pc~0); 6364#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6363#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6278#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6279#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6439#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6365#L399 assume 1 == ~t2_pc~0; 6366#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6563#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6768#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6759#L946 assume !(0 != activate_threads_~tmp___1~0#1); 6259#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6229#L418 assume !(1 == ~t3_pc~0); 6192#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6193#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6219#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6220#L954 assume !(0 != activate_threads_~tmp___2~0#1); 6952#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6912#L437 assume 1 == ~t4_pc~0; 6913#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6532#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6405#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6406#L962 assume !(0 != activate_threads_~tmp___3~0#1); 6804#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6489#L456 assume !(1 == ~t5_pc~0); 6490#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6589#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6569#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6246#L970 assume !(0 != activate_threads_~tmp___4~0#1); 6247#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6379#L475 assume 1 == ~t6_pc~0; 6380#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6459#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6460#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6211#L978 assume !(0 != activate_threads_~tmp___5~0#1); 6212#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6692#L494 assume 1 == ~t7_pc~0; 6693#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6744#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6930#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6945#L986 assume !(0 != activate_threads_~tmp___6~0#1); 6954#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6895#L837 assume !(1 == ~M_E~0); 6762#L837-2 assume !(1 == ~T1_E~0); 6346#L842-1 assume !(1 == ~T2_E~0); 6347#L847-1 assume !(1 == ~T3_E~0); 6822#L852-1 assume !(1 == ~T4_E~0); 6889#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6772#L862-1 assume !(1 == ~T6_E~0); 6773#L867-1 assume !(1 == ~T7_E~0); 6782#L872-1 assume !(1 == ~E_1~0); 6856#L877-1 assume !(1 == ~E_2~0); 6779#L882-1 assume !(1 == ~E_3~0); 6780#L887-1 assume !(1 == ~E_4~0); 6409#L892-1 assume !(1 == ~E_5~0); 6410#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6798#L902-1 assume !(1 == ~E_7~0); 6486#L907-1 assume { :end_inline_reset_delta_events } true; 6487#L1148-2 [2022-12-13 19:49:22,245 INFO L750 eck$LassoCheckResult]: Loop: 6487#L1148-2 assume !false; 6223#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6224#L729 assume !false; 6614#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6611#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6567#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6636#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6673#L626 assume !(0 != eval_~tmp~0#1); 6414#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6415#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6709#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6260#L754-5 assume !(0 == ~T1_E~0); 6261#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6643#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6833#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6834#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6574#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6240#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6241#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6225#L794-3 assume !(0 == ~E_2~0); 6226#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6329#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6717#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6322#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6323#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6517#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6518#L361-24 assume 1 == ~m_pc~0; 6549#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6550#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6434#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6435#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6708#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6790#L380-24 assume 1 == ~t1_pc~0; 6791#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6413#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6852#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6705#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6368#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6369#L399-24 assume !(1 == ~t2_pc~0); 6576#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 6616#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6617#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6888#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6700#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6701#L418-24 assume !(1 == ~t3_pc~0); 6315#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 6316#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6777#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6579#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6251#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6252#L437-24 assume !(1 == ~t4_pc~0); 6529#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 6528#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6886#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6552#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6553#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6870#L456-24 assume 1 == ~t5_pc~0; 6871#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6925#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6649#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6650#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6771#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6899#L475-24 assume 1 == ~t6_pc~0; 6253#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6254#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6546#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6547#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 6202#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6203#L494-24 assume 1 == ~t7_pc~0; 6869#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6756#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6757#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6691#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6525#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6526#L837-3 assume !(1 == ~M_E~0); 6602#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6897#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6821#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6242#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6243#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6929#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6918#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6867#L872-3 assume !(1 == ~E_1~0); 6868#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6924#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6940#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6606#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6600#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6601#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6793#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6786#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6228#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6725#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6726#L1167 assume !(0 == start_simulation_~tmp~3#1); 6820#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6850#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6634#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6273#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 6274#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6835#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6836#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 6646#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 6487#L1148-2 [2022-12-13 19:49:22,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,246 INFO L85 PathProgramCache]: Analyzing trace with hash 1267163051, now seen corresponding path program 1 times [2022-12-13 19:49:22,246 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,246 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411236825] [2022-12-13 19:49:22,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,284 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,284 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1411236825] [2022-12-13 19:49:22,284 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1411236825] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,284 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,284 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:22,284 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [427531574] [2022-12-13 19:49:22,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,285 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:22,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,285 INFO L85 PathProgramCache]: Analyzing trace with hash 1144624358, now seen corresponding path program 1 times [2022-12-13 19:49:22,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,286 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [191508426] [2022-12-13 19:49:22,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,321 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [191508426] [2022-12-13 19:49:22,321 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [191508426] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,321 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,321 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:22,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379508603] [2022-12-13 19:49:22,322 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,322 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:22,322 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:22,323 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:22,323 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:22,323 INFO L87 Difference]: Start difference. First operand 768 states and 1145 transitions. cyclomatic complexity: 378 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:22,342 INFO L93 Difference]: Finished difference Result 768 states and 1144 transitions. [2022-12-13 19:49:22,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1144 transitions. [2022-12-13 19:49:22,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:22,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1144 transitions. [2022-12-13 19:49:22,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-12-13 19:49:22,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-12-13 19:49:22,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1144 transitions. [2022-12-13 19:49:22,351 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:22,351 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1144 transitions. [2022-12-13 19:49:22,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1144 transitions. [2022-12-13 19:49:22,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-12-13 19:49:22,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4895833333333333) internal successors, (1144), 767 states have internal predecessors, (1144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1144 transitions. [2022-12-13 19:49:22,359 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1144 transitions. [2022-12-13 19:49:22,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:22,360 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1144 transitions. [2022-12-13 19:49:22,360 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 19:49:22,360 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1144 transitions. [2022-12-13 19:49:22,362 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:22,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:22,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:22,363 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,363 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,363 INFO L748 eck$LassoCheckResult]: Stem: 8151#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 8152#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8306#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8307#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8422#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 8370#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8371#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8335#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8243#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8244#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8231#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8232#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8190#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8191#L754 assume !(0 == ~M_E~0); 8454#L754-2 assume !(0 == ~T1_E~0); 8134#L759-1 assume !(0 == ~T2_E~0); 8135#L764-1 assume !(0 == ~T3_E~0); 8486#L769-1 assume !(0 == ~T4_E~0); 8487#L774-1 assume !(0 == ~T5_E~0); 8400#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8161#L784-1 assume !(0 == ~T7_E~0); 8162#L789-1 assume !(0 == ~E_1~0); 7854#L794-1 assume !(0 == ~E_2~0); 7855#L799-1 assume !(0 == ~E_3~0); 8489#L804-1 assume !(0 == ~E_4~0); 8490#L809-1 assume !(0 == ~E_5~0); 8247#L814-1 assume !(0 == ~E_6~0); 7766#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 7767#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8228#L361 assume 1 == ~m_pc~0; 8229#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8279#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8100#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8101#L930 assume !(0 != activate_threads_~tmp~1#1); 8397#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8221#L380 assume !(1 == ~t1_pc~0); 7907#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7906#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7821#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7822#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7982#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7908#L399 assume 1 == ~t2_pc~0; 7909#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8106#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8311#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8302#L946 assume !(0 != activate_threads_~tmp___1~0#1); 7802#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7774#L418 assume !(1 == ~t3_pc~0); 7735#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7736#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7762#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7763#L954 assume !(0 != activate_threads_~tmp___2~0#1); 8495#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8456#L437 assume 1 == ~t4_pc~0; 8457#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8076#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7949#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7950#L962 assume !(0 != activate_threads_~tmp___3~0#1); 8348#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8037#L456 assume !(1 == ~t5_pc~0); 8038#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8132#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8112#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7792#L970 assume !(0 != activate_threads_~tmp___4~0#1); 7793#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7927#L475 assume 1 == ~t6_pc~0; 7928#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8002#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8003#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7754#L978 assume !(0 != activate_threads_~tmp___5~0#1); 7755#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8235#L494 assume 1 == ~t7_pc~0; 8236#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8287#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8473#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8488#L986 assume !(0 != activate_threads_~tmp___6~0#1); 8497#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8440#L837 assume !(1 == ~M_E~0); 8305#L837-2 assume !(1 == ~T1_E~0); 7889#L842-1 assume !(1 == ~T2_E~0); 7890#L847-1 assume !(1 == ~T3_E~0); 8365#L852-1 assume !(1 == ~T4_E~0); 8434#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8315#L862-1 assume !(1 == ~T6_E~0); 8316#L867-1 assume !(1 == ~T7_E~0); 8327#L872-1 assume !(1 == ~E_1~0); 8399#L877-1 assume !(1 == ~E_2~0); 8322#L882-1 assume !(1 == ~E_3~0); 8323#L887-1 assume !(1 == ~E_4~0); 7952#L892-1 assume !(1 == ~E_5~0); 7953#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 8343#L902-1 assume !(1 == ~E_7~0); 8029#L907-1 assume { :end_inline_reset_delta_events } true; 8030#L1148-2 [2022-12-13 19:49:22,364 INFO L750 eck$LassoCheckResult]: Loop: 8030#L1148-2 assume !false; 7768#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7769#L729 assume !false; 8157#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8154#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8110#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8179#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8217#L626 assume !(0 != eval_~tmp~0#1); 7957#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7958#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8252#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7805#L754-5 assume !(0 == ~T1_E~0); 7806#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8186#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8376#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8377#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8122#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7783#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7784#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7764#L794-3 assume !(0 == ~E_2~0); 7765#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7869#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8260#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7862#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7863#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8060#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8061#L361-24 assume 1 == ~m_pc~0; 8092#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8093#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7977#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7978#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8251#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8333#L380-24 assume !(1 == ~t1_pc~0); 7955#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 7956#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8395#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8248#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7911#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7912#L399-24 assume 1 == ~t2_pc~0; 8117#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8159#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8160#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8431#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8241#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8242#L418-24 assume !(1 == ~t3_pc~0); 7858#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 7859#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8320#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8121#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7794#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7795#L437-24 assume 1 == ~t4_pc~0; 8070#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8071#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8429#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8095#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8096#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8413#L456-24 assume 1 == ~t5_pc~0; 8414#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8468#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8192#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8193#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8312#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8442#L475-24 assume 1 == ~t6_pc~0; 7796#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7797#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8089#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8090#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 7745#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7746#L494-24 assume !(1 == ~t7_pc~0); 8321#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 8299#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8300#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8234#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8068#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8069#L837-3 assume !(1 == ~M_E~0); 8145#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8439#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8363#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7785#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7786#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8472#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8461#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8410#L872-3 assume !(1 == ~E_1~0); 8411#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8467#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8483#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8147#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8141#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8142#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8336#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8329#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 7771#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8268#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8269#L1167 assume !(0 == start_simulation_~tmp~3#1); 8364#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8393#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8176#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7816#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7817#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8378#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8379#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8189#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 8030#L1148-2 [2022-12-13 19:49:22,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,364 INFO L85 PathProgramCache]: Analyzing trace with hash -1148673299, now seen corresponding path program 1 times [2022-12-13 19:49:22,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,364 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241479875] [2022-12-13 19:49:22,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241479875] [2022-12-13 19:49:22,387 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241479875] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,388 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,388 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:22,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538677193] [2022-12-13 19:49:22,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,388 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:22,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,389 INFO L85 PathProgramCache]: Analyzing trace with hash 419380070, now seen corresponding path program 1 times [2022-12-13 19:49:22,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,389 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1202627335] [2022-12-13 19:49:22,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,421 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1202627335] [2022-12-13 19:49:22,422 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1202627335] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,422 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,422 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:22,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [346306009] [2022-12-13 19:49:22,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,423 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:22,423 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:22,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:22,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:22,423 INFO L87 Difference]: Start difference. First operand 768 states and 1144 transitions. cyclomatic complexity: 377 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:22,437 INFO L93 Difference]: Finished difference Result 768 states and 1143 transitions. [2022-12-13 19:49:22,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1143 transitions. [2022-12-13 19:49:22,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:22,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1143 transitions. [2022-12-13 19:49:22,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-12-13 19:49:22,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-12-13 19:49:22,443 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1143 transitions. [2022-12-13 19:49:22,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:22,444 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1143 transitions. [2022-12-13 19:49:22,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1143 transitions. [2022-12-13 19:49:22,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-12-13 19:49:22,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.48828125) internal successors, (1143), 767 states have internal predecessors, (1143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1143 transitions. [2022-12-13 19:49:22,460 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1143 transitions. [2022-12-13 19:49:22,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:22,461 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1143 transitions. [2022-12-13 19:49:22,461 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 19:49:22,461 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1143 transitions. [2022-12-13 19:49:22,465 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:22,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:22,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:22,466 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,466 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,467 INFO L748 eck$LassoCheckResult]: Stem: 9694#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 9695#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9849#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9850#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9964#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 9913#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9914#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9878#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9784#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9785#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9774#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9775#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9733#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9734#L754 assume !(0 == ~M_E~0); 9997#L754-2 assume !(0 == ~T1_E~0); 9676#L759-1 assume !(0 == ~T2_E~0); 9677#L764-1 assume !(0 == ~T3_E~0); 10029#L769-1 assume !(0 == ~T4_E~0); 10030#L774-1 assume !(0 == ~T5_E~0); 9943#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9704#L784-1 assume !(0 == ~T7_E~0); 9705#L789-1 assume !(0 == ~E_1~0); 9393#L794-1 assume !(0 == ~E_2~0); 9394#L799-1 assume !(0 == ~E_3~0); 10032#L804-1 assume !(0 == ~E_4~0); 10033#L809-1 assume !(0 == ~E_5~0); 9788#L814-1 assume !(0 == ~E_6~0); 9307#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9308#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9771#L361 assume 1 == ~m_pc~0; 9772#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9822#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9643#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9644#L930 assume !(0 != activate_threads_~tmp~1#1); 9940#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9764#L380 assume !(1 == ~t1_pc~0); 9450#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9449#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9364#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9365#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9525#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9451#L399 assume 1 == ~t2_pc~0; 9452#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9649#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9854#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9845#L946 assume !(0 != activate_threads_~tmp___1~0#1); 9345#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9315#L418 assume !(1 == ~t3_pc~0); 9278#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9279#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9305#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9306#L954 assume !(0 != activate_threads_~tmp___2~0#1); 10038#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9998#L437 assume 1 == ~t4_pc~0; 9999#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9618#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9491#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9492#L962 assume !(0 != activate_threads_~tmp___3~0#1); 9890#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9575#L456 assume !(1 == ~t5_pc~0); 9576#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9675#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9655#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9332#L970 assume !(0 != activate_threads_~tmp___4~0#1); 9333#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9465#L475 assume 1 == ~t6_pc~0; 9466#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9545#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9546#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9297#L978 assume !(0 != activate_threads_~tmp___5~0#1); 9298#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9778#L494 assume 1 == ~t7_pc~0; 9779#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9830#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10016#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10031#L986 assume !(0 != activate_threads_~tmp___6~0#1); 10040#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9981#L837 assume !(1 == ~M_E~0); 9848#L837-2 assume !(1 == ~T1_E~0); 9432#L842-1 assume !(1 == ~T2_E~0); 9433#L847-1 assume !(1 == ~T3_E~0); 9908#L852-1 assume !(1 == ~T4_E~0); 9975#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9858#L862-1 assume !(1 == ~T6_E~0); 9859#L867-1 assume !(1 == ~T7_E~0); 9868#L872-1 assume !(1 == ~E_1~0); 9942#L877-1 assume !(1 == ~E_2~0); 9865#L882-1 assume !(1 == ~E_3~0); 9866#L887-1 assume !(1 == ~E_4~0); 9495#L892-1 assume !(1 == ~E_5~0); 9496#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 9884#L902-1 assume !(1 == ~E_7~0); 9572#L907-1 assume { :end_inline_reset_delta_events } true; 9573#L1148-2 [2022-12-13 19:49:22,467 INFO L750 eck$LassoCheckResult]: Loop: 9573#L1148-2 assume !false; 9309#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9310#L729 assume !false; 9700#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9697#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9653#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9722#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9759#L626 assume !(0 != eval_~tmp~0#1); 9500#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9501#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9795#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9346#L754-5 assume !(0 == ~T1_E~0); 9347#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9729#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9919#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9920#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9660#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9326#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9327#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9311#L794-3 assume !(0 == ~E_2~0); 9312#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9415#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9803#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9408#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9409#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9603#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9604#L361-24 assume 1 == ~m_pc~0; 9635#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9636#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9520#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9521#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9794#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9876#L380-24 assume 1 == ~t1_pc~0; 9877#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9499#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9938#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9791#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9454#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9455#L399-24 assume 1 == ~t2_pc~0; 9661#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9702#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9703#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9974#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9786#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9787#L418-24 assume !(1 == ~t3_pc~0); 9401#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 9402#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9863#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9665#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9337#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9338#L437-24 assume 1 == ~t4_pc~0; 9613#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9614#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9972#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9638#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9639#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9956#L456-24 assume 1 == ~t5_pc~0; 9957#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10011#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9735#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9736#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9857#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9985#L475-24 assume 1 == ~t6_pc~0; 9339#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9340#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9632#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9633#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 9288#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9289#L494-24 assume 1 == ~t7_pc~0; 9955#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9842#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9843#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9777#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9611#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9612#L837-3 assume !(1 == ~M_E~0); 9688#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9983#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9907#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9328#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9329#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10015#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10004#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9953#L872-3 assume !(1 == ~E_1~0); 9954#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10010#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10026#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9692#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9686#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9687#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9879#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9872#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9314#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9811#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 9812#L1167 assume !(0 == start_simulation_~tmp~3#1); 9906#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9936#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9720#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9359#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 9360#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9921#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9922#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 9732#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 9573#L1148-2 [2022-12-13 19:49:22,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,467 INFO L85 PathProgramCache]: Analyzing trace with hash 1821437803, now seen corresponding path program 1 times [2022-12-13 19:49:22,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717846680] [2022-12-13 19:49:22,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,500 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [717846680] [2022-12-13 19:49:22,500 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [717846680] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,500 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,500 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:22,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499923743] [2022-12-13 19:49:22,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,501 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:22,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1141273896, now seen corresponding path program 2 times [2022-12-13 19:49:22,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,501 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78916000] [2022-12-13 19:49:22,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [78916000] [2022-12-13 19:49:22,546 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [78916000] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,546 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,547 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:22,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1185896878] [2022-12-13 19:49:22,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,547 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:22,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:22,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:22,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:22,547 INFO L87 Difference]: Start difference. First operand 768 states and 1143 transitions. cyclomatic complexity: 376 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:22,558 INFO L93 Difference]: Finished difference Result 768 states and 1142 transitions. [2022-12-13 19:49:22,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1142 transitions. [2022-12-13 19:49:22,561 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:22,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1142 transitions. [2022-12-13 19:49:22,563 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-12-13 19:49:22,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-12-13 19:49:22,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1142 transitions. [2022-12-13 19:49:22,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:22,564 INFO L218 hiAutomatonCegarLoop]: Abstraction has 768 states and 1142 transitions. [2022-12-13 19:49:22,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1142 transitions. [2022-12-13 19:49:22,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-12-13 19:49:22,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4869791666666667) internal successors, (1142), 767 states have internal predecessors, (1142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1142 transitions. [2022-12-13 19:49:22,573 INFO L240 hiAutomatonCegarLoop]: Abstraction has 768 states and 1142 transitions. [2022-12-13 19:49:22,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:22,574 INFO L428 stractBuchiCegarLoop]: Abstraction has 768 states and 1142 transitions. [2022-12-13 19:49:22,574 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 19:49:22,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1142 transitions. [2022-12-13 19:49:22,576 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-12-13 19:49:22,576 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:22,576 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:22,577 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,577 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,577 INFO L748 eck$LassoCheckResult]: Stem: 11237#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 11238#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11392#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11393#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11508#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 11456#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11457#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11421#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11329#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11330#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11317#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11318#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11276#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11277#L754 assume !(0 == ~M_E~0); 11540#L754-2 assume !(0 == ~T1_E~0); 11220#L759-1 assume !(0 == ~T2_E~0); 11221#L764-1 assume !(0 == ~T3_E~0); 11572#L769-1 assume !(0 == ~T4_E~0); 11573#L774-1 assume !(0 == ~T5_E~0); 11486#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11247#L784-1 assume !(0 == ~T7_E~0); 11248#L789-1 assume !(0 == ~E_1~0); 10940#L794-1 assume !(0 == ~E_2~0); 10941#L799-1 assume !(0 == ~E_3~0); 11575#L804-1 assume !(0 == ~E_4~0); 11576#L809-1 assume !(0 == ~E_5~0); 11333#L814-1 assume !(0 == ~E_6~0); 10852#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 10853#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11314#L361 assume 1 == ~m_pc~0; 11315#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11365#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11186#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11187#L930 assume !(0 != activate_threads_~tmp~1#1); 11483#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11307#L380 assume !(1 == ~t1_pc~0); 10993#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10992#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10907#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10908#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11068#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10994#L399 assume 1 == ~t2_pc~0; 10995#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11192#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11397#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11388#L946 assume !(0 != activate_threads_~tmp___1~0#1); 10888#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10860#L418 assume !(1 == ~t3_pc~0); 10821#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10822#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10848#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10849#L954 assume !(0 != activate_threads_~tmp___2~0#1); 11581#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11542#L437 assume 1 == ~t4_pc~0; 11543#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11162#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11035#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11036#L962 assume !(0 != activate_threads_~tmp___3~0#1); 11434#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11123#L456 assume !(1 == ~t5_pc~0); 11124#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11218#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11198#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10878#L970 assume !(0 != activate_threads_~tmp___4~0#1); 10879#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11013#L475 assume 1 == ~t6_pc~0; 11014#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11088#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11089#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10840#L978 assume !(0 != activate_threads_~tmp___5~0#1); 10841#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11321#L494 assume 1 == ~t7_pc~0; 11322#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11373#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11559#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11574#L986 assume !(0 != activate_threads_~tmp___6~0#1); 11583#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11526#L837 assume !(1 == ~M_E~0); 11391#L837-2 assume !(1 == ~T1_E~0); 10975#L842-1 assume !(1 == ~T2_E~0); 10976#L847-1 assume !(1 == ~T3_E~0); 11451#L852-1 assume !(1 == ~T4_E~0); 11520#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11401#L862-1 assume !(1 == ~T6_E~0); 11402#L867-1 assume !(1 == ~T7_E~0); 11413#L872-1 assume !(1 == ~E_1~0); 11485#L877-1 assume !(1 == ~E_2~0); 11408#L882-1 assume !(1 == ~E_3~0); 11409#L887-1 assume !(1 == ~E_4~0); 11038#L892-1 assume !(1 == ~E_5~0); 11039#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 11429#L902-1 assume !(1 == ~E_7~0); 11115#L907-1 assume { :end_inline_reset_delta_events } true; 11116#L1148-2 [2022-12-13 19:49:22,577 INFO L750 eck$LassoCheckResult]: Loop: 11116#L1148-2 assume !false; 10854#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10855#L729 assume !false; 11243#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11240#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11196#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11265#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11303#L626 assume !(0 != eval_~tmp~0#1); 11043#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11044#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11338#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10891#L754-5 assume !(0 == ~T1_E~0); 10892#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11272#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11462#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11463#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11208#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10869#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10870#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10850#L794-3 assume !(0 == ~E_2~0); 10851#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10955#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11346#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10951#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10952#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11146#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11147#L361-24 assume 1 == ~m_pc~0; 11178#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11179#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11063#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11064#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11337#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11419#L380-24 assume !(1 == ~t1_pc~0); 11041#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 11042#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11481#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11334#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10997#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10998#L399-24 assume 1 == ~t2_pc~0; 11203#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11245#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11246#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11517#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11327#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11328#L418-24 assume !(1 == ~t3_pc~0); 10944#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 10945#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11406#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11207#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10880#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10881#L437-24 assume 1 == ~t4_pc~0; 11156#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11157#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11515#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11181#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11182#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11499#L456-24 assume 1 == ~t5_pc~0; 11500#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11554#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11278#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11279#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11398#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11528#L475-24 assume 1 == ~t6_pc~0; 10882#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10883#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11175#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11176#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 10831#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10832#L494-24 assume 1 == ~t7_pc~0; 11498#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11385#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11386#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11320#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11154#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11155#L837-3 assume !(1 == ~M_E~0); 11231#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11525#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11449#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10871#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10872#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11558#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11547#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11496#L872-3 assume !(1 == ~E_1~0); 11497#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11553#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11569#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11233#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11227#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11228#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11422#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11415#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10857#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11354#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11355#L1167 assume !(0 == start_simulation_~tmp~3#1); 11450#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11479#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11262#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10902#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 10903#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11464#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11465#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 11275#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 11116#L1148-2 [2022-12-13 19:49:22,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,578 INFO L85 PathProgramCache]: Analyzing trace with hash 254679853, now seen corresponding path program 1 times [2022-12-13 19:49:22,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,578 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685287683] [2022-12-13 19:49:22,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,623 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,623 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [685287683] [2022-12-13 19:49:22,623 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [685287683] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,623 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,623 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:22,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315719688] [2022-12-13 19:49:22,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,623 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:22,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,624 INFO L85 PathProgramCache]: Analyzing trace with hash 2048030343, now seen corresponding path program 1 times [2022-12-13 19:49:22,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,624 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [343584167] [2022-12-13 19:49:22,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,652 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,652 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [343584167] [2022-12-13 19:49:22,653 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [343584167] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,653 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,653 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:22,653 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [940043327] [2022-12-13 19:49:22,653 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,653 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:22,653 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:22,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:49:22,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:49:22,654 INFO L87 Difference]: Start difference. First operand 768 states and 1142 transitions. cyclomatic complexity: 375 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:22,733 INFO L93 Difference]: Finished difference Result 1448 states and 2148 transitions. [2022-12-13 19:49:22,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1448 states and 2148 transitions. [2022-12-13 19:49:22,741 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2022-12-13 19:49:22,745 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1448 states to 1448 states and 2148 transitions. [2022-12-13 19:49:22,745 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1448 [2022-12-13 19:49:22,746 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1448 [2022-12-13 19:49:22,746 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1448 states and 2148 transitions. [2022-12-13 19:49:22,747 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:22,747 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1448 states and 2148 transitions. [2022-12-13 19:49:22,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1448 states and 2148 transitions. [2022-12-13 19:49:22,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1448 to 1448. [2022-12-13 19:49:22,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1448 states, 1448 states have (on average 1.4834254143646408) internal successors, (2148), 1447 states have internal predecessors, (2148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1448 states to 1448 states and 2148 transitions. [2022-12-13 19:49:22,766 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1448 states and 2148 transitions. [2022-12-13 19:49:22,767 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:49:22,767 INFO L428 stractBuchiCegarLoop]: Abstraction has 1448 states and 2148 transitions. [2022-12-13 19:49:22,767 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 19:49:22,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1448 states and 2148 transitions. [2022-12-13 19:49:22,771 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2022-12-13 19:49:22,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:22,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:22,772 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,772 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,772 INFO L748 eck$LassoCheckResult]: Stem: 13467#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 13468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13630#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13631#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13754#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 13701#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13702#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13660#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13562#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13563#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13550#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13551#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13508#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13509#L754 assume !(0 == ~M_E~0); 13798#L754-2 assume !(0 == ~T1_E~0); 13447#L759-1 assume !(0 == ~T2_E~0); 13448#L764-1 assume !(0 == ~T3_E~0); 13833#L769-1 assume !(0 == ~T4_E~0); 13834#L774-1 assume !(0 == ~T5_E~0); 13733#L779-1 assume !(0 == ~T6_E~0); 13478#L784-1 assume !(0 == ~T7_E~0); 13479#L789-1 assume !(0 == ~E_1~0); 13166#L794-1 assume !(0 == ~E_2~0); 13167#L799-1 assume !(0 == ~E_3~0); 13836#L804-1 assume !(0 == ~E_4~0); 13837#L809-1 assume !(0 == ~E_5~0); 13566#L814-1 assume !(0 == ~E_6~0); 13076#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 13077#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13547#L361 assume 1 == ~m_pc~0; 13548#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13598#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13414#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13415#L930 assume !(0 != activate_threads_~tmp~1#1); 13730#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13540#L380 assume !(1 == ~t1_pc~0); 13220#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13219#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13133#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13134#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13296#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13221#L399 assume 1 == ~t2_pc~0; 13222#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13420#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13635#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13624#L946 assume !(0 != activate_threads_~tmp___1~0#1); 13114#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13086#L418 assume !(1 == ~t3_pc~0); 13047#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13048#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13074#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13075#L954 assume !(0 != activate_threads_~tmp___2~0#1); 13844#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13799#L437 assume 1 == ~t4_pc~0; 13800#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13389#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13261#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13262#L962 assume !(0 != activate_threads_~tmp___3~0#1); 13675#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13351#L456 assume !(1 == ~t5_pc~0); 13352#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13446#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13426#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13104#L970 assume !(0 != activate_threads_~tmp___4~0#1); 13105#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13238#L475 assume 1 == ~t6_pc~0; 13239#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13316#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13317#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13066#L978 assume !(0 != activate_threads_~tmp___5~0#1); 13067#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13554#L494 assume 1 == ~t7_pc~0; 13555#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13606#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13817#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13835#L986 assume !(0 != activate_threads_~tmp___6~0#1); 13849#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13780#L837 assume !(1 == ~M_E~0); 13629#L837-2 assume !(1 == ~T1_E~0); 13201#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13202#L847-1 assume !(1 == ~T3_E~0); 13696#L852-1 assume !(1 == ~T4_E~0); 13773#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13639#L862-1 assume !(1 == ~T6_E~0); 13640#L867-1 assume !(1 == ~T7_E~0); 13651#L872-1 assume !(1 == ~E_1~0); 13732#L877-1 assume !(1 == ~E_2~0); 13646#L882-1 assume !(1 == ~E_3~0); 13647#L887-1 assume !(1 == ~E_4~0); 13265#L892-1 assume !(1 == ~E_5~0); 13266#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 13667#L902-1 assume !(1 == ~E_7~0); 13668#L907-1 assume { :end_inline_reset_delta_events } true; 13723#L1148-2 [2022-12-13 19:49:22,772 INFO L750 eck$LassoCheckResult]: Loop: 13723#L1148-2 assume !false; 13724#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13473#L729 assume !false; 13474#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13470#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13424#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13497#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13534#L626 assume !(0 != eval_~tmp~0#1); 13270#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13271#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13862#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13861#L754-5 assume !(0 == ~T1_E~0); 13859#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13860#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14479#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14478#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14477#L779-3 assume !(0 == ~T6_E~0); 14476#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14475#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14474#L794-3 assume !(0 == ~E_2~0); 14473#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14472#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14471#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14470#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14469#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14468#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14467#L361-24 assume 1 == ~m_pc~0; 14465#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14464#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14463#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14462#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14461#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14460#L380-24 assume !(1 == ~t1_pc~0); 14458#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 14457#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14456#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14455#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14454#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14453#L399-24 assume 1 == ~t2_pc~0; 14451#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14450#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14449#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14448#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14447#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14446#L418-24 assume !(1 == ~t3_pc~0); 14444#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 14443#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14442#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14441#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14440#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14439#L437-24 assume 1 == ~t4_pc~0; 14437#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14436#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14435#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14434#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14433#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14432#L456-24 assume !(1 == ~t5_pc~0); 14430#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 14429#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14428#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14427#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14426#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14425#L475-24 assume 1 == ~t6_pc~0; 14423#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14422#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14421#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14420#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 14419#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14418#L494-24 assume 1 == ~t7_pc~0; 14416#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14415#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14414#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14413#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14412#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14411#L837-3 assume !(1 == ~M_E~0); 14410#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14409#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13779#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14408#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14407#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14406#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13841#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14405#L872-3 assume !(1 == ~E_1~0); 14404#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14403#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14402#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14401#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14400#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14399#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14398#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14328#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14321#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14320#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 14318#L1167 assume !(0 == start_simulation_~tmp~3#1); 14316#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14312#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14307#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14306#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 14305#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14304#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14302#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 14301#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 13723#L1148-2 [2022-12-13 19:49:22,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,773 INFO L85 PathProgramCache]: Analyzing trace with hash -2141947347, now seen corresponding path program 1 times [2022-12-13 19:49:22,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,773 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [472534753] [2022-12-13 19:49:22,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,811 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [472534753] [2022-12-13 19:49:22,811 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [472534753] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,811 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,811 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:49:22,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [278617151] [2022-12-13 19:49:22,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,812 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:22,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,812 INFO L85 PathProgramCache]: Analyzing trace with hash -1218549212, now seen corresponding path program 1 times [2022-12-13 19:49:22,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220456451] [2022-12-13 19:49:22,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,853 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [220456451] [2022-12-13 19:49:22,853 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [220456451] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,853 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,853 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:22,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [655125701] [2022-12-13 19:49:22,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,854 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:22,854 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:22,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:22,854 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:22,854 INFO L87 Difference]: Start difference. First operand 1448 states and 2148 transitions. cyclomatic complexity: 702 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:22,902 INFO L93 Difference]: Finished difference Result 1448 states and 2122 transitions. [2022-12-13 19:49:22,902 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1448 states and 2122 transitions. [2022-12-13 19:49:22,912 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2022-12-13 19:49:22,916 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1448 states to 1448 states and 2122 transitions. [2022-12-13 19:49:22,916 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1448 [2022-12-13 19:49:22,917 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1448 [2022-12-13 19:49:22,917 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1448 states and 2122 transitions. [2022-12-13 19:49:22,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:22,918 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1448 states and 2122 transitions. [2022-12-13 19:49:22,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1448 states and 2122 transitions. [2022-12-13 19:49:22,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1448 to 1448. [2022-12-13 19:49:22,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1448 states, 1448 states have (on average 1.4654696132596685) internal successors, (2122), 1447 states have internal predecessors, (2122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:22,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1448 states to 1448 states and 2122 transitions. [2022-12-13 19:49:22,940 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1448 states and 2122 transitions. [2022-12-13 19:49:22,941 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:22,941 INFO L428 stractBuchiCegarLoop]: Abstraction has 1448 states and 2122 transitions. [2022-12-13 19:49:22,941 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 19:49:22,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1448 states and 2122 transitions. [2022-12-13 19:49:22,945 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2022-12-13 19:49:22,945 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:22,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:22,946 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,946 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:22,947 INFO L748 eck$LassoCheckResult]: Stem: 16370#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 16371#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 16527#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16528#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16666#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 16603#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16604#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16560#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16461#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16462#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16451#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16452#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16410#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16411#L754 assume !(0 == ~M_E~0); 16722#L754-2 assume !(0 == ~T1_E~0); 16349#L759-1 assume !(0 == ~T2_E~0); 16350#L764-1 assume !(0 == ~T3_E~0); 16765#L769-1 assume !(0 == ~T4_E~0); 16766#L774-1 assume !(0 == ~T5_E~0); 16643#L779-1 assume !(0 == ~T6_E~0); 16380#L784-1 assume !(0 == ~T7_E~0); 16381#L789-1 assume !(0 == ~E_1~0); 16065#L794-1 assume !(0 == ~E_2~0); 16066#L799-1 assume !(0 == ~E_3~0); 16768#L804-1 assume !(0 == ~E_4~0); 16769#L809-1 assume !(0 == ~E_5~0); 16465#L814-1 assume !(0 == ~E_6~0); 15979#L819-1 assume !(0 == ~E_7~0); 15980#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16448#L361 assume 1 == ~m_pc~0; 16449#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16499#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16316#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16317#L930 assume !(0 != activate_threads_~tmp~1#1); 16638#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16441#L380 assume !(1 == ~t1_pc~0); 16123#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16122#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16033#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16034#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16198#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16124#L399 assume 1 == ~t2_pc~0; 16125#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16322#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16532#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16523#L946 assume !(0 != activate_threads_~tmp___1~0#1); 16017#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15987#L418 assume !(1 == ~t3_pc~0); 15950#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15951#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15977#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15978#L954 assume !(0 != activate_threads_~tmp___2~0#1); 16782#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16723#L437 assume 1 == ~t4_pc~0; 16724#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16291#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16163#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16164#L962 assume !(0 != activate_threads_~tmp___3~0#1); 16573#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16248#L456 assume !(1 == ~t5_pc~0); 16249#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16348#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16328#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16004#L970 assume !(0 != activate_threads_~tmp___4~0#1); 16005#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16138#L475 assume 1 == ~t6_pc~0; 16139#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16218#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16219#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15969#L978 assume !(0 != activate_threads_~tmp___5~0#1); 15970#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16455#L494 assume !(1 == ~t7_pc~0); 16457#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16507#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16747#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16767#L986 assume !(0 != activate_threads_~tmp___6~0#1); 16788#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16695#L837 assume !(1 == ~M_E~0); 16526#L837-2 assume !(1 == ~T1_E~0); 16104#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16105#L847-1 assume !(1 == ~T3_E~0); 17046#L852-1 assume !(1 == ~T4_E~0); 17045#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17044#L862-1 assume !(1 == ~T6_E~0); 16537#L867-1 assume !(1 == ~T7_E~0); 17043#L872-1 assume !(1 == ~E_1~0); 17042#L877-1 assume !(1 == ~E_2~0); 16544#L882-1 assume !(1 == ~E_3~0); 16545#L887-1 assume !(1 == ~E_4~0); 16167#L892-1 assume !(1 == ~E_5~0); 16168#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 16566#L902-1 assume !(1 == ~E_7~0); 16245#L907-1 assume { :end_inline_reset_delta_events } true; 16246#L1148-2 [2022-12-13 19:49:22,947 INFO L750 eck$LassoCheckResult]: Loop: 16246#L1148-2 assume !false; 15981#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15982#L729 assume !false; 16376#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16373#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16326#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16399#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16436#L626 assume !(0 != eval_~tmp~0#1); 16172#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16173#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16796#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16795#L754-5 assume !(0 == ~T1_E~0); 16794#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16615#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16609#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16610#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16333#L779-3 assume !(0 == ~T6_E~0); 15996#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15997#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15983#L794-3 assume !(0 == ~E_2~0); 15984#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16087#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16480#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16080#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16081#L819-3 assume !(0 == ~E_7~0); 16276#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16277#L361-24 assume !(1 == ~m_pc~0); 16640#L361-26 is_master_triggered_~__retres1~0#1 := 0; 17185#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17184#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17183#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17182#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17181#L380-24 assume !(1 == ~t1_pc~0); 17179#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 17178#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17177#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17176#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17175#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17174#L399-24 assume 1 == ~t2_pc~0; 17172#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17171#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17170#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17169#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17168#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17167#L418-24 assume !(1 == ~t3_pc~0); 17165#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 17164#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17163#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17162#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17161#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17160#L437-24 assume 1 == ~t4_pc~0; 17158#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17157#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17156#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17155#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17154#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17153#L456-24 assume 1 == ~t5_pc~0; 17152#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17150#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17149#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17148#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17147#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17146#L475-24 assume 1 == ~t6_pc~0; 17144#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17143#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17142#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17141#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 17140#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17139#L494-24 assume !(1 == ~t7_pc~0); 17137#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 17136#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17135#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17134#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17133#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17132#L837-3 assume !(1 == ~M_E~0); 17131#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17130#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16698#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17129#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17128#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17127#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16777#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17126#L872-3 assume !(1 == ~E_1~0); 17125#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17124#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17123#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17122#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17121#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17120#L902-3 assume !(1 == ~E_7~0); 17119#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 17058#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 17050#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16488#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 16489#L1167 assume !(0 == start_simulation_~tmp~3#1); 16629#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16630#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16668#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16669#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 16739#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16740#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17034#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 16409#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 16246#L1148-2 [2022-12-13 19:49:22,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1307665866, now seen corresponding path program 1 times [2022-12-13 19:49:22,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014276644] [2022-12-13 19:49:22,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:22,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:22,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:22,984 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014276644] [2022-12-13 19:49:22,984 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2014276644] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:22,984 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:22,984 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:49:22,984 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366238412] [2022-12-13 19:49:22,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:22,985 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:22,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:22,985 INFO L85 PathProgramCache]: Analyzing trace with hash -1632160449, now seen corresponding path program 1 times [2022-12-13 19:49:22,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:22,985 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [755792066] [2022-12-13 19:49:22,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:22,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:22,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:23,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:23,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:23,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [755792066] [2022-12-13 19:49:23,016 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [755792066] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:23,016 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:23,016 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:23,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2144559260] [2022-12-13 19:49:23,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:23,017 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:23,017 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:23,017 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:23,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:23,018 INFO L87 Difference]: Start difference. First operand 1448 states and 2122 transitions. cyclomatic complexity: 676 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:23,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:23,089 INFO L93 Difference]: Finished difference Result 2759 states and 4004 transitions. [2022-12-13 19:49:23,089 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2759 states and 4004 transitions. [2022-12-13 19:49:23,102 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2644 [2022-12-13 19:49:23,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2759 states to 2759 states and 4004 transitions. [2022-12-13 19:49:23,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2759 [2022-12-13 19:49:23,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2759 [2022-12-13 19:49:23,115 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2759 states and 4004 transitions. [2022-12-13 19:49:23,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:23,118 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2759 states and 4004 transitions. [2022-12-13 19:49:23,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2759 states and 4004 transitions. [2022-12-13 19:49:23,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2759 to 2645. [2022-12-13 19:49:23,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2645 states, 2645 states have (on average 1.454820415879017) internal successors, (3848), 2644 states have internal predecessors, (3848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:23,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2645 states to 2645 states and 3848 transitions. [2022-12-13 19:49:23,152 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2645 states and 3848 transitions. [2022-12-13 19:49:23,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:23,153 INFO L428 stractBuchiCegarLoop]: Abstraction has 2645 states and 3848 transitions. [2022-12-13 19:49:23,153 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 19:49:23,153 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2645 states and 3848 transitions. [2022-12-13 19:49:23,159 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2530 [2022-12-13 19:49:23,159 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:23,159 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:23,160 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:23,160 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:23,160 INFO L748 eck$LassoCheckResult]: Stem: 20583#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 20584#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 20749#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20750#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20884#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 20822#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20823#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20780#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20677#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20678#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20666#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20667#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20625#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20626#L754 assume !(0 == ~M_E~0); 20931#L754-2 assume !(0 == ~T1_E~0); 20562#L759-1 assume !(0 == ~T2_E~0); 20563#L764-1 assume !(0 == ~T3_E~0); 20976#L769-1 assume !(0 == ~T4_E~0); 20977#L774-1 assume !(0 == ~T5_E~0); 20857#L779-1 assume !(0 == ~T6_E~0); 20593#L784-1 assume !(0 == ~T7_E~0); 20594#L789-1 assume !(0 == ~E_1~0); 20280#L794-1 assume !(0 == ~E_2~0); 20281#L799-1 assume !(0 == ~E_3~0); 20979#L804-1 assume !(0 == ~E_4~0); 20980#L809-1 assume !(0 == ~E_5~0); 20681#L814-1 assume !(0 == ~E_6~0); 20193#L819-1 assume !(0 == ~E_7~0); 20194#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20664#L361 assume !(1 == ~m_pc~0); 20665#L361-2 is_master_triggered_~__retres1~0#1 := 0; 20716#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20529#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20530#L930 assume !(0 != activate_threads_~tmp~1#1); 20854#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20657#L380 assume !(1 == ~t1_pc~0); 20338#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20337#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20248#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20249#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20413#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20339#L399 assume 1 == ~t2_pc~0; 20340#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20535#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20754#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20743#L946 assume !(0 != activate_threads_~tmp___1~0#1); 20231#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20201#L418 assume !(1 == ~t3_pc~0); 20164#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20165#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20191#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20192#L954 assume !(0 != activate_threads_~tmp___2~0#1); 20991#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20933#L437 assume 1 == ~t4_pc~0; 20934#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20505#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20378#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20379#L962 assume !(0 != activate_threads_~tmp___3~0#1); 20794#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20462#L456 assume !(1 == ~t5_pc~0); 20463#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20561#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20542#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20218#L970 assume !(0 != activate_threads_~tmp___4~0#1); 20219#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20353#L475 assume 1 == ~t6_pc~0; 20354#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20432#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20433#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20183#L978 assume !(0 != activate_threads_~tmp___5~0#1); 20184#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20671#L494 assume !(1 == ~t7_pc~0); 20673#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20726#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20959#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20978#L986 assume !(0 != activate_threads_~tmp___6~0#1); 20995#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20907#L837 assume !(1 == ~M_E~0); 20748#L837-2 assume !(1 == ~T1_E~0); 20319#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20320#L847-1 assume !(1 == ~T3_E~0); 22282#L852-1 assume !(1 == ~T4_E~0); 22280#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22278#L862-1 assume !(1 == ~T6_E~0); 20759#L867-1 assume !(1 == ~T7_E~0); 22275#L872-1 assume !(1 == ~E_1~0); 21001#L877-1 assume !(1 == ~E_2~0); 20766#L882-1 assume !(1 == ~E_3~0); 20767#L887-1 assume !(1 == ~E_4~0); 22174#L892-1 assume !(1 == ~E_5~0); 22172#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 20787#L902-1 assume !(1 == ~E_7~0); 20788#L907-1 assume { :end_inline_reset_delta_events } true; 20844#L1148-2 [2022-12-13 19:49:23,161 INFO L750 eck$LassoCheckResult]: Loop: 20844#L1148-2 assume !false; 20845#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22119#L729 assume !false; 20993#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20586#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20540#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20611#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20781#L626 assume !(0 != eval_~tmp~0#1); 22107#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20911#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20688#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20689#L754-5 assume !(0 == ~T1_E~0); 22104#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22105#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22604#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22601#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22599#L779-3 assume !(0 == ~T6_E~0); 22597#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22595#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22593#L794-3 assume !(0 == ~E_2~0); 22591#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22588#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22586#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22584#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22582#L819-3 assume !(0 == ~E_7~0); 22580#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22578#L361-24 assume !(1 == ~m_pc~0); 22575#L361-26 is_master_triggered_~__retres1~0#1 := 0; 22573#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22571#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22569#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22567#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22564#L380-24 assume !(1 == ~t1_pc~0); 22561#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 22559#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22557#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22555#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22553#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22552#L399-24 assume 1 == ~t2_pc~0; 22550#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22549#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22546#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22544#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22542#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22541#L418-24 assume !(1 == ~t3_pc~0); 22539#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 22538#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22537#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22536#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22535#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22534#L437-24 assume 1 == ~t4_pc~0; 22532#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22531#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22530#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22529#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22528#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22527#L456-24 assume !(1 == ~t5_pc~0); 22525#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 22524#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22523#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22522#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22521#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22520#L475-24 assume 1 == ~t6_pc~0; 22518#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22517#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22516#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22515#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 22514#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22513#L494-24 assume !(1 == ~t7_pc~0); 20765#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 20740#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20741#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20670#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20498#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20499#L837-3 assume !(1 == ~M_E~0); 20577#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20912#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20910#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22457#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22456#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22455#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20988#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22454#L872-3 assume !(1 == ~E_1~0); 22453#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22452#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22451#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22450#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22449#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22448#L902-3 assume !(1 == ~E_7~0); 22447#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20774#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20200#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20705#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 20706#L1167 assume !(0 == start_simulation_~tmp~3#1); 20817#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20848#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20608#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20246#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 20247#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20830#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20831#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 20924#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 20844#L1148-2 [2022-12-13 19:49:23,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:23,161 INFO L85 PathProgramCache]: Analyzing trace with hash 2012584553, now seen corresponding path program 1 times [2022-12-13 19:49:23,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:23,161 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687564934] [2022-12-13 19:49:23,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:23,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:23,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:23,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:23,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:23,200 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687564934] [2022-12-13 19:49:23,200 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1687564934] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:23,200 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:23,200 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:49:23,200 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485537351] [2022-12-13 19:49:23,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:23,201 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:23,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:23,201 INFO L85 PathProgramCache]: Analyzing trace with hash 1354802078, now seen corresponding path program 1 times [2022-12-13 19:49:23,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:23,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1992050387] [2022-12-13 19:49:23,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:23,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:23,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:23,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:23,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:23,229 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1992050387] [2022-12-13 19:49:23,229 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1992050387] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:23,229 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:23,230 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:23,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1105103527] [2022-12-13 19:49:23,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:23,230 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:23,230 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:23,230 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:49:23,230 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:49:23,230 INFO L87 Difference]: Start difference. First operand 2645 states and 3848 transitions. cyclomatic complexity: 1207 Second operand has 5 states, 5 states have (on average 18.6) internal successors, (93), 5 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:23,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:23,429 INFO L93 Difference]: Finished difference Result 7326 states and 10627 transitions. [2022-12-13 19:49:23,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7326 states and 10627 transitions. [2022-12-13 19:49:23,461 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7060 [2022-12-13 19:49:23,481 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7326 states to 7326 states and 10627 transitions. [2022-12-13 19:49:23,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7326 [2022-12-13 19:49:23,485 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7326 [2022-12-13 19:49:23,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7326 states and 10627 transitions. [2022-12-13 19:49:23,491 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:23,491 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7326 states and 10627 transitions. [2022-12-13 19:49:23,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7326 states and 10627 transitions. [2022-12-13 19:49:23,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7326 to 2750. [2022-12-13 19:49:23,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2750 states, 2750 states have (on average 1.4374545454545455) internal successors, (3953), 2749 states have internal predecessors, (3953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:23,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2750 states to 2750 states and 3953 transitions. [2022-12-13 19:49:23,541 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2750 states and 3953 transitions. [2022-12-13 19:49:23,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 19:49:23,541 INFO L428 stractBuchiCegarLoop]: Abstraction has 2750 states and 3953 transitions. [2022-12-13 19:49:23,542 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 19:49:23,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2750 states and 3953 transitions. [2022-12-13 19:49:23,548 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2632 [2022-12-13 19:49:23,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:23,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:23,549 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:23,549 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:23,549 INFO L748 eck$LassoCheckResult]: Stem: 30582#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 30583#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 30748#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30749#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30889#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 30824#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30825#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30787#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30677#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30678#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30666#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30667#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30623#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30624#L754 assume !(0 == ~M_E~0); 30936#L754-2 assume !(0 == ~T1_E~0); 30557#L759-1 assume !(0 == ~T2_E~0); 30558#L764-1 assume !(0 == ~T3_E~0); 30996#L769-1 assume !(0 == ~T4_E~0); 30997#L774-1 assume !(0 == ~T5_E~0); 30865#L779-1 assume !(0 == ~T6_E~0); 30592#L784-1 assume !(0 == ~T7_E~0); 30593#L789-1 assume !(0 == ~E_1~0); 30263#L794-1 assume !(0 == ~E_2~0); 30264#L799-1 assume !(0 == ~E_3~0); 31003#L804-1 assume !(0 == ~E_4~0); 31004#L809-1 assume !(0 == ~E_5~0); 30681#L814-1 assume !(0 == ~E_6~0); 30177#L819-1 assume !(0 == ~E_7~0); 30178#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30664#L361 assume !(1 == ~m_pc~0); 30665#L361-2 is_master_triggered_~__retres1~0#1 := 0; 30717#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30525#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30526#L930 assume !(0 != activate_threads_~tmp~1#1); 30859#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30657#L380 assume !(1 == ~t1_pc~0); 30322#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30878#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30879#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31026#L938 assume !(0 != activate_threads_~tmp___0~0#1); 30401#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30323#L399 assume 1 == ~t2_pc~0; 30324#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30531#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30754#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30744#L946 assume !(0 != activate_threads_~tmp___1~0#1); 30215#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30185#L418 assume !(1 == ~t3_pc~0); 30148#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30149#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30175#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30176#L954 assume !(0 != activate_threads_~tmp___2~0#1); 31019#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30937#L437 assume 1 == ~t4_pc~0; 30938#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30499#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30362#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30363#L962 assume !(0 != activate_threads_~tmp___3~0#1); 30799#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30452#L456 assume !(1 == ~t5_pc~0); 30453#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30556#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30537#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30202#L970 assume !(0 != activate_threads_~tmp___4~0#1); 30203#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30337#L475 assume 1 == ~t6_pc~0; 30338#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30422#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30423#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30167#L978 assume !(0 != activate_threads_~tmp___5~0#1); 30168#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30671#L494 assume !(1 == ~t7_pc~0); 30673#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 30725#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30974#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30998#L986 assume !(0 != activate_threads_~tmp___6~0#1); 31024#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30910#L837 assume !(1 == ~M_E~0); 30747#L837-2 assume !(1 == ~T1_E~0); 30302#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30303#L847-1 assume !(1 == ~T3_E~0); 31243#L852-1 assume !(1 == ~T4_E~0); 31241#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31240#L862-1 assume !(1 == ~T6_E~0); 30759#L867-1 assume !(1 == ~T7_E~0); 31235#L872-1 assume !(1 == ~E_1~0); 31233#L877-1 assume !(1 == ~E_2~0); 31208#L882-1 assume !(1 == ~E_3~0); 30969#L887-1 assume !(1 == ~E_4~0); 30366#L892-1 assume !(1 == ~E_5~0); 30367#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 30792#L902-1 assume !(1 == ~E_7~0); 30793#L907-1 assume { :end_inline_reset_delta_events } true; 31172#L1148-2 [2022-12-13 19:49:23,550 INFO L750 eck$LassoCheckResult]: Loop: 31172#L1148-2 assume !false; 31167#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31166#L729 assume !false; 31165#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 31161#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 31156#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 31155#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31153#L626 assume !(0 != eval_~tmp~0#1); 31152#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31150#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31148#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31146#L754-5 assume !(0 == ~T1_E~0); 31143#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31139#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31140#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31133#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31134#L779-3 assume !(0 == ~T6_E~0); 31127#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31128#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31107#L794-3 assume !(0 == ~E_2~0); 31108#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31096#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31097#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 31085#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31086#L819-3 assume !(0 == ~E_7~0); 30484#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30485#L361-24 assume !(1 == ~m_pc~0); 30860#L361-26 is_master_triggered_~__retres1~0#1 := 0; 31743#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31742#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31741#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31740#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31739#L380-24 assume 1 == ~t1_pc~0; 31737#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31735#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31733#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31731#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31729#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31726#L399-24 assume 1 == ~t2_pc~0; 31721#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31720#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31719#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31718#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31717#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31716#L418-24 assume !(1 == ~t3_pc~0); 31714#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 31713#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31712#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31711#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31710#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31709#L437-24 assume 1 == ~t4_pc~0; 31707#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31706#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31690#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31688#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31671#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31667#L456-24 assume 1 == ~t5_pc~0; 31664#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31659#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31656#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31572#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31567#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31563#L475-24 assume 1 == ~t6_pc~0; 31557#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31552#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31548#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31544#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 31539#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31535#L494-24 assume !(1 == ~t7_pc~0); 31528#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 31524#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31520#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31516#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31511#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31507#L837-3 assume !(1 == ~M_E~0); 31502#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31498#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31493#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31488#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31484#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31481#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31476#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31473#L872-3 assume !(1 == ~E_1~0); 31470#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31467#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31464#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31460#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31456#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31453#L902-3 assume !(1 == ~E_7~0); 31450#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 31430#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 31384#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 31371#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 31362#L1167 assume !(0 == start_simulation_~tmp~3#1); 31355#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 31213#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 31199#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 31198#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 31197#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31195#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31186#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 31178#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 31172#L1148-2 [2022-12-13 19:49:23,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:23,550 INFO L85 PathProgramCache]: Analyzing trace with hash -1406363737, now seen corresponding path program 1 times [2022-12-13 19:49:23,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:23,550 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765163590] [2022-12-13 19:49:23,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:23,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:23,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:23,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:23,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:23,593 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765163590] [2022-12-13 19:49:23,593 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [765163590] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:23,593 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:23,593 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:23,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1069937290] [2022-12-13 19:49:23,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:23,593 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:23,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:23,594 INFO L85 PathProgramCache]: Analyzing trace with hash 1756050400, now seen corresponding path program 1 times [2022-12-13 19:49:23,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:23,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [127630788] [2022-12-13 19:49:23,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:23,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:23,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:23,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:23,634 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:23,634 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [127630788] [2022-12-13 19:49:23,634 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [127630788] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:23,634 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:23,634 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:23,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148867536] [2022-12-13 19:49:23,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:23,635 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:23,635 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:23,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:49:23,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:49:23,636 INFO L87 Difference]: Start difference. First operand 2750 states and 3953 transitions. cyclomatic complexity: 1207 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:23,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:23,766 INFO L93 Difference]: Finished difference Result 6499 states and 9249 transitions. [2022-12-13 19:49:23,766 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6499 states and 9249 transitions. [2022-12-13 19:49:23,795 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6246 [2022-12-13 19:49:23,812 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6499 states to 6499 states and 9249 transitions. [2022-12-13 19:49:23,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6499 [2022-12-13 19:49:23,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6499 [2022-12-13 19:49:23,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6499 states and 9249 transitions. [2022-12-13 19:49:23,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:23,820 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6499 states and 9249 transitions. [2022-12-13 19:49:23,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6499 states and 9249 transitions. [2022-12-13 19:49:23,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6499 to 5099. [2022-12-13 19:49:23,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5099 states, 5099 states have (on average 1.4300843302608355) internal successors, (7292), 5098 states have internal predecessors, (7292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:23,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5099 states to 5099 states and 7292 transitions. [2022-12-13 19:49:23,880 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5099 states and 7292 transitions. [2022-12-13 19:49:23,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:49:23,881 INFO L428 stractBuchiCegarLoop]: Abstraction has 5099 states and 7292 transitions. [2022-12-13 19:49:23,881 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 19:49:23,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5099 states and 7292 transitions. [2022-12-13 19:49:23,893 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4980 [2022-12-13 19:49:23,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:23,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:23,894 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:23,894 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:23,895 INFO L748 eck$LassoCheckResult]: Stem: 39826#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 39827#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 39993#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39994#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40121#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 40067#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40068#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40026#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39926#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39927#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39915#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39916#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39875#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39876#L754 assume !(0 == ~M_E~0); 40161#L754-2 assume !(0 == ~T1_E~0); 39806#L759-1 assume !(0 == ~T2_E~0); 39807#L764-1 assume !(0 == ~T3_E~0); 40210#L769-1 assume !(0 == ~T4_E~0); 40211#L774-1 assume !(0 == ~T5_E~0); 40099#L779-1 assume !(0 == ~T6_E~0); 39841#L784-1 assume !(0 == ~T7_E~0); 39842#L789-1 assume !(0 == ~E_1~0); 39523#L794-1 assume !(0 == ~E_2~0); 39524#L799-1 assume !(0 == ~E_3~0); 40213#L804-1 assume !(0 == ~E_4~0); 40214#L809-1 assume !(0 == ~E_5~0); 39930#L814-1 assume !(0 == ~E_6~0); 39436#L819-1 assume !(0 == ~E_7~0); 39437#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39913#L361 assume !(1 == ~m_pc~0); 39914#L361-2 is_master_triggered_~__retres1~0#1 := 0; 39963#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39774#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39775#L930 assume !(0 != activate_threads_~tmp~1#1); 40095#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39906#L380 assume !(1 == ~t1_pc~0); 39581#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40228#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39491#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 39492#L938 assume !(0 != activate_threads_~tmp___0~0#1); 39657#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39582#L399 assume !(1 == ~t2_pc~0); 39583#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39780#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39998#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39989#L946 assume !(0 != activate_threads_~tmp___1~0#1); 39474#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39444#L418 assume !(1 == ~t3_pc~0); 39407#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39408#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39434#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39435#L954 assume !(0 != activate_threads_~tmp___2~0#1); 40225#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40163#L437 assume 1 == ~t4_pc~0; 40164#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39750#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39620#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 39621#L962 assume !(0 != activate_threads_~tmp___3~0#1); 40039#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39705#L456 assume !(1 == ~t5_pc~0); 39706#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39805#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39787#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39461#L970 assume !(0 != activate_threads_~tmp___4~0#1); 39462#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39595#L475 assume 1 == ~t6_pc~0; 39596#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39675#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39676#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39426#L978 assume !(0 != activate_threads_~tmp___5~0#1); 39427#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39920#L494 assume !(1 == ~t7_pc~0); 39922#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 39973#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40194#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40212#L986 assume !(0 != activate_threads_~tmp___6~0#1); 40227#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40144#L837 assume !(1 == ~M_E~0); 39992#L837-2 assume !(1 == ~T1_E~0); 39562#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39563#L847-1 assume !(1 == ~T3_E~0); 40063#L852-1 assume !(1 == ~T4_E~0); 40234#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40235#L862-1 assume !(1 == ~T6_E~0); 40003#L867-1 assume !(1 == ~T7_E~0); 40015#L872-1 assume !(1 == ~E_1~0); 40232#L877-1 assume !(1 == ~E_2~0); 40233#L882-1 assume !(1 == ~E_3~0); 40185#L887-1 assume !(1 == ~E_4~0); 40186#L892-1 assume !(1 == ~E_5~0); 40135#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 40136#L902-1 assume !(1 == ~E_7~0); 39702#L907-1 assume { :end_inline_reset_delta_events } true; 39703#L1148-2 [2022-12-13 19:49:23,895 INFO L750 eck$LassoCheckResult]: Loop: 39703#L1148-2 assume !false; 39438#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39439#L729 assume !false; 39835#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 39830#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 39785#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 39861#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 39901#L626 assume !(0 != eval_~tmp~0#1); 39631#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39632#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39937#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 39475#L754-5 assume !(0 == ~T1_E~0); 39476#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39869#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40073#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40074#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 39792#L779-3 assume !(0 == ~T6_E~0); 39453#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 39454#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39440#L794-3 assume !(0 == ~E_2~0); 39441#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39545#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 39945#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39538#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 39539#L819-3 assume !(0 == ~E_7~0); 39735#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39736#L361-24 assume !(1 == ~m_pc~0); 39872#L361-26 is_master_triggered_~__retres1~0#1 := 0; 39873#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39651#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39652#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39936#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40023#L380-24 assume 1 == ~t1_pc~0; 40024#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40025#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44434#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44433#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39584#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39585#L399-24 assume !(1 == ~t2_pc~0); 39793#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 39839#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39840#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 40134#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39928#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39929#L418-24 assume !(1 == ~t3_pc~0); 39531#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 39532#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40009#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39794#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39466#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39467#L437-24 assume 1 == ~t4_pc~0; 39745#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39746#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40129#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 39770#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39771#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40113#L456-24 assume 1 == ~t5_pc~0; 40114#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40184#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39877#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39878#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40001#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40148#L475-24 assume 1 == ~t6_pc~0; 39468#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39469#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39764#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39765#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 39417#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39418#L494-24 assume !(1 == ~t7_pc~0); 40010#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 39986#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39987#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39919#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39743#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39744#L837-3 assume !(1 == ~M_E~0); 39820#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40146#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40061#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39457#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39458#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40193#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40176#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40109#L872-3 assume !(1 == ~E_1~0); 40110#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40182#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40207#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39822#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39818#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39819#L902-3 assume !(1 == ~E_7~0); 40027#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 40019#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 39443#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 39952#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 39953#L1167 assume !(0 == start_simulation_~tmp~3#1); 40062#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 40090#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 39857#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 39489#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 39490#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40075#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40076#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 39874#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 39703#L1148-2 [2022-12-13 19:49:23,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:23,895 INFO L85 PathProgramCache]: Analyzing trace with hash -2107931962, now seen corresponding path program 1 times [2022-12-13 19:49:23,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:23,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922166830] [2022-12-13 19:49:23,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:23,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:23,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:23,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:23,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:23,936 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1922166830] [2022-12-13 19:49:23,936 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1922166830] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:23,936 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:23,936 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:49:23,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [844149252] [2022-12-13 19:49:23,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:23,937 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:23,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:23,937 INFO L85 PathProgramCache]: Analyzing trace with hash -1833998209, now seen corresponding path program 1 times [2022-12-13 19:49:23,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:23,937 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403710416] [2022-12-13 19:49:23,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:23,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:23,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:23,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:23,971 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:23,971 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403710416] [2022-12-13 19:49:23,971 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403710416] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:23,971 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:23,971 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:23,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928735924] [2022-12-13 19:49:23,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:23,972 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:23,972 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:23,972 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:23,972 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:23,972 INFO L87 Difference]: Start difference. First operand 5099 states and 7292 transitions. cyclomatic complexity: 2197 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:24,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:24,034 INFO L93 Difference]: Finished difference Result 9538 states and 13577 transitions. [2022-12-13 19:49:24,034 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9538 states and 13577 transitions. [2022-12-13 19:49:24,063 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9400 [2022-12-13 19:49:24,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9538 states to 9538 states and 13577 transitions. [2022-12-13 19:49:24,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9538 [2022-12-13 19:49:24,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9538 [2022-12-13 19:49:24,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9538 states and 13577 transitions. [2022-12-13 19:49:24,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:24,100 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9538 states and 13577 transitions. [2022-12-13 19:49:24,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9538 states and 13577 transitions. [2022-12-13 19:49:24,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9538 to 9522. [2022-12-13 19:49:24,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9522 states, 9522 states have (on average 1.424175593362739) internal successors, (13561), 9521 states have internal predecessors, (13561), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:24,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9522 states to 9522 states and 13561 transitions. [2022-12-13 19:49:24,230 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9522 states and 13561 transitions. [2022-12-13 19:49:24,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:24,231 INFO L428 stractBuchiCegarLoop]: Abstraction has 9522 states and 13561 transitions. [2022-12-13 19:49:24,231 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 19:49:24,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9522 states and 13561 transitions. [2022-12-13 19:49:24,255 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9384 [2022-12-13 19:49:24,255 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:24,255 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:24,256 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:24,256 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:24,256 INFO L748 eck$LassoCheckResult]: Stem: 54474#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 54475#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 54651#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54652#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54808#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 54734#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54735#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54689#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54578#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54579#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54567#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54568#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54522#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54523#L754 assume !(0 == ~M_E~0); 54851#L754-2 assume !(0 == ~T1_E~0); 54452#L759-1 assume !(0 == ~T2_E~0); 54453#L764-1 assume !(0 == ~T3_E~0); 54908#L769-1 assume !(0 == ~T4_E~0); 54909#L774-1 assume !(0 == ~T5_E~0); 54777#L779-1 assume !(0 == ~T6_E~0); 54486#L784-1 assume !(0 == ~T7_E~0); 54487#L789-1 assume !(0 == ~E_1~0); 54168#L794-1 assume !(0 == ~E_2~0); 54169#L799-1 assume !(0 == ~E_3~0); 54915#L804-1 assume !(0 == ~E_4~0); 54916#L809-1 assume !(0 == ~E_5~0); 54582#L814-1 assume !(0 == ~E_6~0); 54082#L819-1 assume !(0 == ~E_7~0); 54083#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54563#L361 assume !(1 == ~m_pc~0); 54564#L361-2 is_master_triggered_~__retres1~0#1 := 0; 54617#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54417#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54418#L930 assume !(0 != activate_threads_~tmp~1#1); 54771#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54556#L380 assume !(1 == ~t1_pc~0); 54222#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54940#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54136#L938 assume !(0 != activate_threads_~tmp___0~0#1); 54298#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54223#L399 assume !(1 == ~t2_pc~0); 54224#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 54423#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54656#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54646#L946 assume !(0 != activate_threads_~tmp___1~0#1); 54116#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54091#L418 assume !(1 == ~t3_pc~0); 54051#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54052#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54076#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54077#L954 assume !(0 != activate_threads_~tmp___2~0#1); 54929#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54854#L437 assume !(1 == ~t4_pc~0); 54737#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54392#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54263#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54264#L962 assume !(0 != activate_threads_~tmp___3~0#1); 54705#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54353#L456 assume !(1 == ~t5_pc~0); 54354#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54450#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54429#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54106#L970 assume !(0 != activate_threads_~tmp___4~0#1); 54107#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54241#L475 assume 1 == ~t6_pc~0; 54242#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54318#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54319#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54070#L978 assume !(0 != activate_threads_~tmp___5~0#1); 54071#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54570#L494 assume !(1 == ~t7_pc~0); 54572#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 54627#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54887#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54910#L986 assume !(0 != activate_threads_~tmp___6~0#1); 54938#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54827#L837 assume !(1 == ~M_E~0); 54650#L837-2 assume !(1 == ~T1_E~0); 54203#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54204#L847-1 assume !(1 == ~T3_E~0); 54730#L852-1 assume !(1 == ~T4_E~0); 54821#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 60124#L862-1 assume !(1 == ~T6_E~0); 54662#L867-1 assume !(1 == ~T7_E~0); 54775#L872-1 assume !(1 == ~E_1~0); 54776#L877-1 assume !(1 == ~E_2~0); 54671#L882-1 assume !(1 == ~E_3~0); 54672#L887-1 assume !(1 == ~E_4~0); 54268#L892-1 assume !(1 == ~E_5~0); 54269#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 54698#L902-1 assume !(1 == ~E_7~0); 54699#L907-1 assume { :end_inline_reset_delta_events } true; 60059#L1148-2 [2022-12-13 19:49:24,256 INFO L750 eck$LassoCheckResult]: Loop: 60059#L1148-2 assume !false; 56932#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56930#L729 assume !false; 56927#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 56672#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 56662#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 56656#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 56649#L626 assume !(0 != eval_~tmp~0#1); 56650#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 62415#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 62414#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 62412#L754-5 assume !(0 == ~T1_E~0); 61363#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 61364#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61645#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61644#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61643#L779-3 assume !(0 == ~T6_E~0); 61642#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 61639#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61638#L794-3 assume !(0 == ~E_2~0); 61637#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61633#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 61631#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 61630#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54505#L819-3 assume !(0 == ~E_7~0); 54376#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54377#L361-24 assume !(1 == ~m_pc~0); 54518#L361-26 is_master_triggered_~__retres1~0#1 := 0; 54519#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61097#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 61096#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61095#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61094#L380-24 assume 1 == ~t1_pc~0; 61092#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 61089#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61086#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 61084#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 61083#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60763#L399-24 assume !(1 == ~t2_pc~0); 60762#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 60761#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60760#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 60759#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60758#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60757#L418-24 assume !(1 == ~t3_pc~0); 60755#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 60754#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60753#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 60752#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60751#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60750#L437-24 assume !(1 == ~t4_pc~0); 60749#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 60748#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60747#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 60746#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60745#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57094#L456-24 assume 1 == ~t5_pc~0; 57095#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 60744#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60743#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 60742#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 60741#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57079#L475-24 assume !(1 == ~t6_pc~0); 57080#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 60740#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60739#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60738#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 60737#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57065#L494-24 assume !(1 == ~t7_pc~0); 57062#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 57059#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57057#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57055#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 57053#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57051#L837-3 assume !(1 == ~M_E~0); 57048#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57046#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57044#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57042#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57040#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57038#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57036#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57034#L872-3 assume !(1 == ~E_1~0); 57031#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57029#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57027#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57025#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57022#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57020#L902-3 assume !(1 == ~E_7~0); 57017#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 57018#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 60089#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 60087#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 60084#L1167 assume !(0 == start_simulation_~tmp~3#1); 60081#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 60070#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 60065#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 60064#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 60063#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60062#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60061#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 60060#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 60059#L1148-2 [2022-12-13 19:49:24,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:24,257 INFO L85 PathProgramCache]: Analyzing trace with hash -1707940763, now seen corresponding path program 1 times [2022-12-13 19:49:24,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:24,257 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976190347] [2022-12-13 19:49:24,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:24,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:24,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:24,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:24,298 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:24,298 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [976190347] [2022-12-13 19:49:24,298 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [976190347] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:24,299 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:24,299 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:24,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [398188267] [2022-12-13 19:49:24,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:24,299 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:24,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:24,300 INFO L85 PathProgramCache]: Analyzing trace with hash -2135575235, now seen corresponding path program 1 times [2022-12-13 19:49:24,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:24,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974034179] [2022-12-13 19:49:24,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:24,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:24,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:24,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:24,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:24,356 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [974034179] [2022-12-13 19:49:24,356 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [974034179] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:24,356 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:24,356 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:24,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204990722] [2022-12-13 19:49:24,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:24,357 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:24,357 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:24,357 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:49:24,358 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:49:24,358 INFO L87 Difference]: Start difference. First operand 9522 states and 13561 transitions. cyclomatic complexity: 4047 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:24,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:24,581 INFO L93 Difference]: Finished difference Result 22429 states and 31670 transitions. [2022-12-13 19:49:24,581 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22429 states and 31670 transitions. [2022-12-13 19:49:24,677 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21732 [2022-12-13 19:49:24,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22429 states to 22429 states and 31670 transitions. [2022-12-13 19:49:24,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22429 [2022-12-13 19:49:24,763 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22429 [2022-12-13 19:49:24,763 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22429 states and 31670 transitions. [2022-12-13 19:49:24,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:24,779 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22429 states and 31670 transitions. [2022-12-13 19:49:24,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22429 states and 31670 transitions. [2022-12-13 19:49:24,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22429 to 17825. [2022-12-13 19:49:24,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17825 states, 17825 states have (on average 1.418569424964937) internal successors, (25286), 17824 states have internal predecessors, (25286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:25,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17825 states to 17825 states and 25286 transitions. [2022-12-13 19:49:25,025 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17825 states and 25286 transitions. [2022-12-13 19:49:25,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:49:25,026 INFO L428 stractBuchiCegarLoop]: Abstraction has 17825 states and 25286 transitions. [2022-12-13 19:49:25,026 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 19:49:25,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17825 states and 25286 transitions. [2022-12-13 19:49:25,082 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17664 [2022-12-13 19:49:25,082 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:25,082 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:25,084 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:25,084 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:25,084 INFO L748 eck$LassoCheckResult]: Stem: 86433#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 86434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 86608#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86609#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86762#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 86693#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86694#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86644#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86537#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86538#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86526#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86527#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86482#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86483#L754 assume !(0 == ~M_E~0); 86807#L754-2 assume !(0 == ~T1_E~0); 86413#L759-1 assume !(0 == ~T2_E~0); 86414#L764-1 assume !(0 == ~T3_E~0); 86866#L769-1 assume !(0 == ~T4_E~0); 86867#L774-1 assume !(0 == ~T5_E~0); 86731#L779-1 assume !(0 == ~T6_E~0); 86447#L784-1 assume !(0 == ~T7_E~0); 86448#L789-1 assume !(0 == ~E_1~0); 86130#L794-1 assume !(0 == ~E_2~0); 86131#L799-1 assume !(0 == ~E_3~0); 86869#L804-1 assume !(0 == ~E_4~0); 86870#L809-1 assume !(0 == ~E_5~0); 86541#L814-1 assume !(0 == ~E_6~0); 86044#L819-1 assume !(0 == ~E_7~0); 86045#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86522#L361 assume !(1 == ~m_pc~0); 86523#L361-2 is_master_triggered_~__retres1~0#1 := 0; 86575#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86380#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 86381#L930 assume !(0 != activate_threads_~tmp~1#1); 86727#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86515#L380 assume !(1 == ~t1_pc~0); 86184#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86894#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86098#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 86099#L938 assume !(0 != activate_threads_~tmp___0~0#1); 86260#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86185#L399 assume !(1 == ~t2_pc~0); 86186#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 86386#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86613#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 86604#L946 assume !(0 != activate_threads_~tmp___1~0#1); 86078#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86053#L418 assume !(1 == ~t3_pc~0); 86012#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86013#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86038#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 86039#L954 assume !(0 != activate_threads_~tmp___2~0#1); 86883#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86814#L437 assume !(1 == ~t4_pc~0); 86697#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 86356#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86224#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 86225#L962 assume !(0 != activate_threads_~tmp___3~0#1); 86663#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86313#L456 assume !(1 == ~t5_pc~0); 86314#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 86411#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86392#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 86068#L970 assume !(0 != activate_threads_~tmp___4~0#1); 86069#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86203#L475 assume !(1 == ~t6_pc~0); 86204#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 86279#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86280#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 86031#L978 assume !(0 != activate_threads_~tmp___5~0#1); 86032#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86529#L494 assume !(1 == ~t7_pc~0); 86531#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 86585#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86840#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 86868#L986 assume !(0 != activate_threads_~tmp___6~0#1); 86892#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86789#L837 assume !(1 == ~M_E~0); 86607#L837-2 assume !(1 == ~T1_E~0); 86165#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86166#L847-1 assume !(1 == ~T3_E~0); 86781#L852-1 assume !(1 == ~T4_E~0); 86782#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86617#L862-1 assume !(1 == ~T6_E~0); 86618#L867-1 assume !(1 == ~T7_E~0); 86729#L872-1 assume !(1 == ~E_1~0); 86730#L877-1 assume !(1 == ~E_2~0); 86625#L882-1 assume !(1 == ~E_3~0); 86626#L887-1 assume !(1 == ~E_4~0); 86229#L892-1 assume !(1 == ~E_5~0); 86230#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 86654#L902-1 assume !(1 == ~E_7~0); 86655#L907-1 assume { :end_inline_reset_delta_events } true; 100794#L1148-2 [2022-12-13 19:49:25,084 INFO L750 eck$LassoCheckResult]: Loop: 100794#L1148-2 assume !false; 100651#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 100649#L729 assume !false; 100647#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 100638#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 100632#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 100466#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 100464#L626 assume !(0 != eval_~tmp~0#1); 100465#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 101915#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 101913#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 101911#L754-5 assume !(0 == ~T1_E~0); 101909#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 101906#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 101904#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 101902#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 101900#L779-3 assume !(0 == ~T6_E~0); 101898#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 101896#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 101894#L794-3 assume !(0 == ~E_2~0); 101892#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 101888#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 101886#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 101884#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 101882#L819-3 assume !(0 == ~E_7~0); 101879#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101877#L361-24 assume !(1 == ~m_pc~0); 101875#L361-26 is_master_triggered_~__retres1~0#1 := 0; 101873#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 101871#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 101869#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 101784#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101783#L380-24 assume !(1 == ~t1_pc~0); 101781#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 101779#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101777#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 101776#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 101774#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101773#L399-24 assume !(1 == ~t2_pc~0); 101197#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 101770#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101768#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 101766#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 101764#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101762#L418-24 assume 1 == ~t3_pc~0; 101760#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 101757#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101755#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 101753#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 101741#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101736#L437-24 assume !(1 == ~t4_pc~0); 101732#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 101728#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 101413#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 101410#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 101408#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101406#L456-24 assume !(1 == ~t5_pc~0); 101403#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 101401#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101399#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 101375#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 101368#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101359#L475-24 assume !(1 == ~t6_pc~0); 90717#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 101345#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 101337#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 101332#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 101326#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101137#L494-24 assume !(1 == ~t7_pc~0); 101134#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 101132#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 101130#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 101128#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 101126#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101124#L837-3 assume !(1 == ~M_E~0); 101122#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101119#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 101115#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101113#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101111#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101109#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 101105#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 101104#L872-3 assume !(1 == ~E_1~0); 101090#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 101084#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 101079#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 101074#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 101070#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 101065#L902-3 assume !(1 == ~E_7~0); 101060#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 101053#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 101042#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 101040#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 101035#L1167 assume !(0 == start_simulation_~tmp~3#1); 101032#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 100944#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 100936#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 100931#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 100926#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 100920#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 100918#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 100796#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 100794#L1148-2 [2022-12-13 19:49:25,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:25,085 INFO L85 PathProgramCache]: Analyzing trace with hash -2016379772, now seen corresponding path program 1 times [2022-12-13 19:49:25,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:25,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234770164] [2022-12-13 19:49:25,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:25,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:25,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:25,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:25,133 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:25,134 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [234770164] [2022-12-13 19:49:25,134 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [234770164] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:25,134 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:25,134 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:49:25,134 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [272087390] [2022-12-13 19:49:25,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:25,135 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:25,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:25,135 INFO L85 PathProgramCache]: Analyzing trace with hash -2127143590, now seen corresponding path program 1 times [2022-12-13 19:49:25,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:25,135 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1731277847] [2022-12-13 19:49:25,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:25,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:25,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:25,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:25,179 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:25,179 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1731277847] [2022-12-13 19:49:25,179 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1731277847] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:25,180 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:25,180 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:25,180 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [378149294] [2022-12-13 19:49:25,180 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:25,180 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:25,180 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:25,181 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:25,181 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:25,181 INFO L87 Difference]: Start difference. First operand 17825 states and 25286 transitions. cyclomatic complexity: 7469 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:25,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:25,241 INFO L93 Difference]: Finished difference Result 17821 states and 25197 transitions. [2022-12-13 19:49:25,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17821 states and 25197 transitions. [2022-12-13 19:49:25,305 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17664 [2022-12-13 19:49:25,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17821 states to 17821 states and 25197 transitions. [2022-12-13 19:49:25,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17821 [2022-12-13 19:49:25,378 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17821 [2022-12-13 19:49:25,378 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17821 states and 25197 transitions. [2022-12-13 19:49:25,386 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:25,387 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17821 states and 25197 transitions. [2022-12-13 19:49:25,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17821 states and 25197 transitions. [2022-12-13 19:49:25,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17821 to 8956. [2022-12-13 19:49:25,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8956 states, 8956 states have (on average 1.4136891469405986) internal successors, (12661), 8955 states have internal predecessors, (12661), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:25,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8956 states to 8956 states and 12661 transitions. [2022-12-13 19:49:25,486 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8956 states and 12661 transitions. [2022-12-13 19:49:25,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:25,487 INFO L428 stractBuchiCegarLoop]: Abstraction has 8956 states and 12661 transitions. [2022-12-13 19:49:25,487 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 19:49:25,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8956 states and 12661 transitions. [2022-12-13 19:49:25,505 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2022-12-13 19:49:25,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:25,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:25,507 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:25,507 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:25,507 INFO L748 eck$LassoCheckResult]: Stem: 122085#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 122086#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 122263#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122264#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 122403#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 122338#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 122339#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122294#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 122189#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 122190#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 122178#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 122179#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 122133#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 122134#L754 assume !(0 == ~M_E~0); 122445#L754-2 assume !(0 == ~T1_E~0); 122060#L759-1 assume !(0 == ~T2_E~0); 122061#L764-1 assume !(0 == ~T3_E~0); 122497#L769-1 assume !(0 == ~T4_E~0); 122498#L774-1 assume !(0 == ~T5_E~0); 122379#L779-1 assume !(0 == ~T6_E~0); 122099#L784-1 assume !(0 == ~T7_E~0); 122100#L789-1 assume !(0 == ~E_1~0); 121778#L794-1 assume !(0 == ~E_2~0); 121779#L799-1 assume !(0 == ~E_3~0); 122502#L804-1 assume !(0 == ~E_4~0); 122503#L809-1 assume !(0 == ~E_5~0); 122193#L814-1 assume !(0 == ~E_6~0); 121692#L819-1 assume !(0 == ~E_7~0); 121693#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 122176#L361 assume !(1 == ~m_pc~0); 122177#L361-2 is_master_triggered_~__retres1~0#1 := 0; 122228#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122028#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 122029#L930 assume !(0 != activate_threads_~tmp~1#1); 122376#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122168#L380 assume !(1 == ~t1_pc~0); 121835#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 122528#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121747#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 121748#L938 assume !(0 != activate_threads_~tmp___0~0#1); 121909#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121836#L399 assume !(1 == ~t2_pc~0); 121837#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 122034#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 122268#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 122259#L946 assume !(0 != activate_threads_~tmp___1~0#1); 121730#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 121700#L418 assume !(1 == ~t3_pc~0); 121665#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 121666#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 121690#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 121691#L954 assume !(0 != activate_threads_~tmp___2~0#1); 122518#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122447#L437 assume !(1 == ~t4_pc~0); 122342#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 122003#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121873#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 121874#L962 assume !(0 != activate_threads_~tmp___3~0#1); 122310#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 121957#L456 assume !(1 == ~t5_pc~0); 121958#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 122059#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 122040#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 121717#L970 assume !(0 != activate_threads_~tmp___4~0#1); 121718#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 121849#L475 assume !(1 == ~t6_pc~0); 121850#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 121927#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 121928#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 121684#L978 assume !(0 != activate_threads_~tmp___5~0#1); 121685#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 122183#L494 assume !(1 == ~t7_pc~0); 122185#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 122238#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 122475#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122499#L986 assume !(0 != activate_threads_~tmp___6~0#1); 122525#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122424#L837 assume !(1 == ~M_E~0); 122262#L837-2 assume !(1 == ~T1_E~0); 121817#L842-1 assume !(1 == ~T2_E~0); 121818#L847-1 assume !(1 == ~T3_E~0); 122334#L852-1 assume !(1 == ~T4_E~0); 122417#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 122273#L862-1 assume !(1 == ~T6_E~0); 122274#L867-1 assume !(1 == ~T7_E~0); 122283#L872-1 assume !(1 == ~E_1~0); 122378#L877-1 assume !(1 == ~E_2~0); 122280#L882-1 assume !(1 == ~E_3~0); 122281#L887-1 assume !(1 == ~E_4~0); 121878#L892-1 assume !(1 == ~E_5~0); 121879#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 122301#L902-1 assume !(1 == ~E_7~0); 121954#L907-1 assume { :end_inline_reset_delta_events } true; 121955#L1148-2 [2022-12-13 19:49:25,507 INFO L750 eck$LassoCheckResult]: Loop: 121955#L1148-2 assume !false; 126390#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 126388#L729 assume !false; 126386#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 126283#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 126277#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 126275#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 126273#L626 assume !(0 != eval_~tmp~0#1); 121884#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 121885#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 122201#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 121731#L754-5 assume !(0 == ~T1_E~0); 121732#L759-3 assume !(0 == ~T2_E~0); 122126#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 122346#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 122347#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 122045#L779-3 assume !(0 == ~T6_E~0); 121709#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 121710#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 121696#L794-3 assume !(0 == ~E_2~0); 121697#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 121799#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 122209#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 121792#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 121793#L819-3 assume !(0 == ~E_7~0); 121988#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121989#L361-24 assume !(1 == ~m_pc~0); 122129#L361-26 is_master_triggered_~__retres1~0#1 := 0; 122130#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121903#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 121904#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 122200#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122290#L380-24 assume 1 == ~t1_pc~0; 122292#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 122293#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130433#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 130432#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 121838#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121839#L399-24 assume !(1 == ~t2_pc~0); 127845#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 127843#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 127841#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 127839#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 127837#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127835#L418-24 assume 1 == ~t3_pc~0; 127833#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 127831#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 127830#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 127828#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 127826#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127824#L437-24 assume !(1 == ~t4_pc~0); 127822#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 127820#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 127818#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 127816#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 127813#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 127811#L456-24 assume 1 == ~t5_pc~0; 127809#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 127799#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 127794#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 127787#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 127729#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 126594#L475-24 assume !(1 == ~t6_pc~0); 126591#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 126589#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 126587#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 126585#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 126583#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 126581#L494-24 assume !(1 == ~t7_pc~0); 126578#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 126576#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 126574#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 126572#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 126570#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126568#L837-3 assume !(1 == ~M_E~0); 126565#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 126563#L842-3 assume !(1 == ~T2_E~0); 126561#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 126559#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 126557#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 126555#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 126553#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 126551#L872-3 assume !(1 == ~E_1~0); 126549#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 126547#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 126545#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 126543#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 126541#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 126539#L902-3 assume !(1 == ~E_7~0); 126537#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 126531#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 126523#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 126521#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 126519#L1167 assume !(0 == start_simulation_~tmp~3#1); 126517#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 126513#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 126508#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 126507#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 126506#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 126505#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 126504#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 126502#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 121955#L1148-2 [2022-12-13 19:49:25,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:25,507 INFO L85 PathProgramCache]: Analyzing trace with hash 1267470274, now seen corresponding path program 1 times [2022-12-13 19:49:25,507 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:25,508 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1087986232] [2022-12-13 19:49:25,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:25,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:25,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:25,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:25,543 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:25,543 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1087986232] [2022-12-13 19:49:25,543 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1087986232] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:25,543 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:25,543 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:49:25,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [755144604] [2022-12-13 19:49:25,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:25,544 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:25,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:25,544 INFO L85 PathProgramCache]: Analyzing trace with hash 945175002, now seen corresponding path program 1 times [2022-12-13 19:49:25,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:25,544 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1356363302] [2022-12-13 19:49:25,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:25,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:25,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:25,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:25,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:25,598 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1356363302] [2022-12-13 19:49:25,598 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1356363302] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:25,598 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:25,598 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:25,598 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040338856] [2022-12-13 19:49:25,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:25,599 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:25,599 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:25,599 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:25,599 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:25,599 INFO L87 Difference]: Start difference. First operand 8956 states and 12661 transitions. cyclomatic complexity: 3709 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:25,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:25,625 INFO L93 Difference]: Finished difference Result 8956 states and 12611 transitions. [2022-12-13 19:49:25,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8956 states and 12611 transitions. [2022-12-13 19:49:25,649 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2022-12-13 19:49:25,666 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8956 states to 8956 states and 12611 transitions. [2022-12-13 19:49:25,666 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8956 [2022-12-13 19:49:25,670 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8956 [2022-12-13 19:49:25,670 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8956 states and 12611 transitions. [2022-12-13 19:49:25,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:25,675 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8956 states and 12611 transitions. [2022-12-13 19:49:25,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8956 states and 12611 transitions. [2022-12-13 19:49:25,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8956 to 8956. [2022-12-13 19:49:25,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8956 states, 8956 states have (on average 1.4081062974542207) internal successors, (12611), 8955 states have internal predecessors, (12611), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:25,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8956 states to 8956 states and 12611 transitions. [2022-12-13 19:49:25,768 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8956 states and 12611 transitions. [2022-12-13 19:49:25,772 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:25,772 INFO L428 stractBuchiCegarLoop]: Abstraction has 8956 states and 12611 transitions. [2022-12-13 19:49:25,772 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 19:49:25,772 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8956 states and 12611 transitions. [2022-12-13 19:49:25,786 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2022-12-13 19:49:25,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:25,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:25,788 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:25,788 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:25,788 INFO L748 eck$LassoCheckResult]: Stem: 140000#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 140001#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 140179#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 140180#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 140324#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 140258#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 140259#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 140214#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 140105#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 140106#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 140094#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 140095#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 140051#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 140052#L754 assume !(0 == ~M_E~0); 140377#L754-2 assume !(0 == ~T1_E~0); 139977#L759-1 assume !(0 == ~T2_E~0); 139978#L764-1 assume !(0 == ~T3_E~0); 140445#L769-1 assume !(0 == ~T4_E~0); 140446#L774-1 assume !(0 == ~T5_E~0); 140300#L779-1 assume !(0 == ~T6_E~0); 140014#L784-1 assume !(0 == ~T7_E~0); 140015#L789-1 assume !(0 == ~E_1~0); 139700#L794-1 assume !(0 == ~E_2~0); 139701#L799-1 assume !(0 == ~E_3~0); 140451#L804-1 assume !(0 == ~E_4~0); 140452#L809-1 assume !(0 == ~E_5~0); 140110#L814-1 assume !(0 == ~E_6~0); 139615#L819-1 assume !(0 == ~E_7~0); 139616#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 140090#L361 assume !(1 == ~m_pc~0); 140091#L361-2 is_master_triggered_~__retres1~0#1 := 0; 140146#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 139946#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 139947#L930 assume !(0 != activate_threads_~tmp~1#1); 140297#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 140083#L380 assume !(1 == ~t1_pc~0); 139753#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 140313#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 140314#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 140486#L938 assume !(0 != activate_threads_~tmp___0~0#1); 139828#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 139754#L399 assume !(1 == ~t2_pc~0); 139755#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 139952#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 140185#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 140175#L946 assume !(0 != activate_threads_~tmp___1~0#1); 139649#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 139624#L418 assume !(1 == ~t3_pc~0); 139584#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 139585#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 139609#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 139610#L954 assume !(0 != activate_threads_~tmp___2~0#1); 140468#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 140383#L437 assume !(1 == ~t4_pc~0); 140262#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 139923#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 139793#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 139794#L962 assume !(0 != activate_threads_~tmp___3~0#1); 140228#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 139882#L456 assume !(1 == ~t5_pc~0); 139883#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 139975#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 139958#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 139639#L970 assume !(0 != activate_threads_~tmp___4~0#1); 139640#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 139772#L475 assume !(1 == ~t6_pc~0); 139773#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 139847#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 139848#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 139603#L978 assume !(0 != activate_threads_~tmp___5~0#1); 139604#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 140097#L494 assume !(1 == ~t7_pc~0); 140099#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 140156#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 140417#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 140447#L986 assume !(0 != activate_threads_~tmp___6~0#1); 140481#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 140351#L837 assume !(1 == ~M_E~0); 140178#L837-2 assume !(1 == ~T1_E~0); 139735#L842-1 assume !(1 == ~T2_E~0); 139736#L847-1 assume !(1 == ~T3_E~0); 140254#L852-1 assume !(1 == ~T4_E~0); 140345#L857-1 assume !(1 == ~T5_E~0); 140189#L862-1 assume !(1 == ~T6_E~0); 140190#L867-1 assume !(1 == ~T7_E~0); 140204#L872-1 assume !(1 == ~E_1~0); 140299#L877-1 assume !(1 == ~E_2~0); 140199#L882-1 assume !(1 == ~E_3~0); 140200#L887-1 assume !(1 == ~E_4~0); 139798#L892-1 assume !(1 == ~E_5~0); 139799#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 140223#L902-1 assume !(1 == ~E_7~0); 139874#L907-1 assume { :end_inline_reset_delta_events } true; 139875#L1148-2 [2022-12-13 19:49:25,788 INFO L750 eck$LassoCheckResult]: Loop: 139875#L1148-2 assume !false; 143790#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 143788#L729 assume !false; 143786#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 143676#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 143670#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 143668#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 143665#L626 assume !(0 != eval_~tmp~0#1); 143666#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 144156#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 144153#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 144151#L754-5 assume !(0 == ~T1_E~0); 144149#L759-3 assume !(0 == ~T2_E~0); 144147#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 144145#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 144142#L774-3 assume !(0 == ~T5_E~0); 144140#L779-3 assume !(0 == ~T6_E~0); 144138#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 144136#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 144134#L794-3 assume !(0 == ~E_2~0); 144132#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 144131#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 144130#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 144127#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 144125#L819-3 assume !(0 == ~E_7~0); 144123#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144122#L361-24 assume !(1 == ~m_pc~0); 144121#L361-26 is_master_triggered_~__retres1~0#1 := 0; 144120#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144119#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 144118#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 144117#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144116#L380-24 assume !(1 == ~t1_pc~0); 144114#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 144112#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144110#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 144109#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 144107#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 144106#L399-24 assume !(1 == ~t2_pc~0); 142235#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 144105#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 144104#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 144103#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 144102#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144101#L418-24 assume !(1 == ~t3_pc~0); 144098#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 144096#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144094#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144092#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 144090#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 144088#L437-24 assume !(1 == ~t4_pc~0); 144086#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 144083#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 144081#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 144079#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 144077#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144075#L456-24 assume !(1 == ~t5_pc~0); 144072#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 144070#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144068#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 144066#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 144064#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 144062#L475-24 assume !(1 == ~t6_pc~0); 141903#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 144058#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 144056#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 144054#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 144052#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 144050#L494-24 assume !(1 == ~t7_pc~0); 144047#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 144046#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 144044#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 144042#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 144040#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144038#L837-3 assume !(1 == ~M_E~0); 144035#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 144033#L842-3 assume !(1 == ~T2_E~0); 144031#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 144029#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 144027#L857-3 assume !(1 == ~T5_E~0); 144025#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 144023#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 144021#L872-3 assume !(1 == ~E_1~0); 144019#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 144017#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 144015#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 144013#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 144011#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 144009#L902-3 assume !(1 == ~E_7~0); 144007#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 144001#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 143993#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 143991#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 143989#L1167 assume !(0 == start_simulation_~tmp~3#1); 143987#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 143839#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 143833#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 143831#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 143829#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 143827#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 143824#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 143822#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 139875#L1148-2 [2022-12-13 19:49:25,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:25,788 INFO L85 PathProgramCache]: Analyzing trace with hash 1968534852, now seen corresponding path program 1 times [2022-12-13 19:49:25,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:25,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336461580] [2022-12-13 19:49:25,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:25,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:25,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:25,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:25,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:25,830 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1336461580] [2022-12-13 19:49:25,830 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1336461580] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:25,831 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:25,831 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:25,831 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2094092610] [2022-12-13 19:49:25,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:25,831 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:25,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:25,831 INFO L85 PathProgramCache]: Analyzing trace with hash 573564601, now seen corresponding path program 1 times [2022-12-13 19:49:25,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:25,831 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [630128898] [2022-12-13 19:49:25,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:25,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:25,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:25,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:25,857 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:25,857 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [630128898] [2022-12-13 19:49:25,857 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [630128898] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:25,857 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:25,857 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:25,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2081022990] [2022-12-13 19:49:25,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:25,857 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:25,857 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:25,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:49:25,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:49:25,858 INFO L87 Difference]: Start difference. First operand 8956 states and 12611 transitions. cyclomatic complexity: 3659 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:25,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:25,965 INFO L93 Difference]: Finished difference Result 18213 states and 25558 transitions. [2022-12-13 19:49:25,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18213 states and 25558 transitions. [2022-12-13 19:49:26,061 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17976 [2022-12-13 19:49:26,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18213 states to 18213 states and 25558 transitions. [2022-12-13 19:49:26,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18213 [2022-12-13 19:49:26,111 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18213 [2022-12-13 19:49:26,111 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18213 states and 25558 transitions. [2022-12-13 19:49:26,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:26,121 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18213 states and 25558 transitions. [2022-12-13 19:49:26,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18213 states and 25558 transitions. [2022-12-13 19:49:26,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18213 to 10187. [2022-12-13 19:49:26,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10187 states, 10187 states have (on average 1.4017865907529203) internal successors, (14280), 10186 states have internal predecessors, (14280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:26,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10187 states to 10187 states and 14280 transitions. [2022-12-13 19:49:26,256 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10187 states and 14280 transitions. [2022-12-13 19:49:26,256 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:49:26,257 INFO L428 stractBuchiCegarLoop]: Abstraction has 10187 states and 14280 transitions. [2022-12-13 19:49:26,257 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 19:49:26,257 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10187 states and 14280 transitions. [2022-12-13 19:49:26,285 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9992 [2022-12-13 19:49:26,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:26,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:26,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:26,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:26,287 INFO L748 eck$LassoCheckResult]: Stem: 167189#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 167190#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 167376#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 167377#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 167536#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 167465#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 167466#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 167414#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 167295#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 167296#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 167283#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 167284#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 167236#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 167237#L754 assume !(0 == ~M_E~0); 167587#L754-2 assume !(0 == ~T1_E~0); 167164#L759-1 assume !(0 == ~T2_E~0); 167165#L764-1 assume !(0 == ~T3_E~0); 167653#L769-1 assume !(0 == ~T4_E~0); 167654#L774-1 assume !(0 == ~T5_E~0); 167513#L779-1 assume !(0 == ~T6_E~0); 167203#L784-1 assume !(0 == ~T7_E~0); 167204#L789-1 assume !(0 == ~E_1~0); 166878#L794-1 assume !(0 == ~E_2~0); 166879#L799-1 assume !(0 == ~E_3~0); 167664#L804-1 assume !(0 == ~E_4~0); 167665#L809-1 assume !(0 == ~E_5~0); 167299#L814-1 assume 0 == ~E_6~0;~E_6~0 := 1; 167300#L819-1 assume !(0 == ~E_7~0); 167365#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 167366#L361 assume !(1 == ~m_pc~0); 167338#L361-2 is_master_triggered_~__retres1~0#1 := 0; 167339#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 167128#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 167129#L930 assume !(0 != activate_threads_~tmp~1#1); 167566#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 167567#L380 assume !(1 == ~t1_pc~0); 166936#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 167701#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 167738#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 167735#L938 assume !(0 != activate_threads_~tmp___0~0#1); 167734#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 166937#L399 assume !(1 == ~t2_pc~0); 166938#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 167733#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 167381#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 167382#L946 assume !(0 != activate_threads_~tmp___1~0#1); 166829#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 166830#L418 assume !(1 == ~t3_pc~0); 166763#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 166764#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 167732#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 167712#L954 assume !(0 != activate_threads_~tmp___2~0#1); 167713#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 167589#L437 assume !(1 == ~t4_pc~0); 167469#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 167470#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 167730#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 167729#L962 assume !(0 != activate_threads_~tmp___3~0#1); 167428#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 167429#L456 assume !(1 == ~t5_pc~0); 167163#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 167162#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 167142#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 166820#L970 assume !(0 != activate_threads_~tmp___4~0#1); 166821#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 166950#L475 assume !(1 == ~t6_pc~0); 166951#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 167028#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 167029#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 167727#L978 assume !(0 != activate_threads_~tmp___5~0#1); 167672#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 167673#L494 assume !(1 == ~t7_pc~0); 167349#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 167350#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 167655#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 167656#L986 assume !(0 != activate_threads_~tmp___6~0#1); 167697#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 167698#L837 assume !(1 == ~M_E~0); 167374#L837-2 assume !(1 == ~T1_E~0); 167375#L842-1 assume !(1 == ~T2_E~0); 167725#L847-1 assume !(1 == ~T3_E~0); 167556#L852-1 assume !(1 == ~T4_E~0); 167557#L857-1 assume !(1 == ~T5_E~0); 167388#L862-1 assume !(1 == ~T6_E~0); 167389#L867-1 assume !(1 == ~T7_E~0); 167724#L872-1 assume !(1 == ~E_1~0); 167716#L877-1 assume !(1 == ~E_2~0); 167717#L882-1 assume !(1 == ~E_3~0); 167621#L887-1 assume !(1 == ~E_4~0); 166977#L892-1 assume !(1 == ~E_5~0); 166978#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 167419#L902-1 assume !(1 == ~E_7~0); 167055#L907-1 assume { :end_inline_reset_delta_events } true; 167056#L1148-2 [2022-12-13 19:49:26,287 INFO L750 eck$LassoCheckResult]: Loop: 167056#L1148-2 assume !false; 173577#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 173573#L729 assume !false; 173569#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 173561#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 173553#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 173549#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 173544#L626 assume !(0 != eval_~tmp~0#1); 173545#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 176482#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 176480#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 176478#L754-5 assume !(0 == ~T1_E~0); 176476#L759-3 assume !(0 == ~T2_E~0); 176473#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 176471#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 176469#L774-3 assume !(0 == ~T5_E~0); 176467#L779-3 assume !(0 == ~T6_E~0); 176432#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 176209#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 176195#L794-3 assume !(0 == ~E_2~0); 176194#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 176193#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 176192#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 174014#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 174008#L819-3 assume !(0 == ~E_7~0); 174003#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 173997#L361-24 assume !(1 == ~m_pc~0); 173992#L361-26 is_master_triggered_~__retres1~0#1 := 0; 173985#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 173986#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 174783#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 174781#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173957#L380-24 assume 1 == ~t1_pc~0; 173947#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 173937#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 173938#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 174770#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 174769#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174768#L399-24 assume !(1 == ~t2_pc~0); 172163#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 174767#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 174766#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 174765#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 174764#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 174763#L418-24 assume 1 == ~t3_pc~0; 174762#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 174760#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 174759#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 174758#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 174757#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 174756#L437-24 assume !(1 == ~t4_pc~0); 174755#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 174754#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 174753#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 174752#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 174751#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 174750#L456-24 assume !(1 == ~t5_pc~0); 174748#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 173796#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 173797#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 173780#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 173781#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 173765#L475-24 assume !(1 == ~t6_pc~0); 173764#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 173763#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 173762#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 173761#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 173760#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 173759#L494-24 assume !(1 == ~t7_pc~0); 173757#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 173756#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 173755#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 173754#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 173753#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 173752#L837-3 assume !(1 == ~M_E~0); 173751#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 173750#L842-3 assume !(1 == ~T2_E~0); 173749#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 173748#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 173747#L857-3 assume !(1 == ~T5_E~0); 173746#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 173745#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 173744#L872-3 assume !(1 == ~E_1~0); 173743#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 173742#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 173741#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 173740#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 173738#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 173732#L902-3 assume !(1 == ~E_7~0); 173726#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 173719#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 173633#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 173631#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 173628#L1167 assume !(0 == start_simulation_~tmp~3#1); 173626#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 173614#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 173607#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 173605#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 173603#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 173601#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 173599#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 173597#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 167056#L1148-2 [2022-12-13 19:49:26,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:26,288 INFO L85 PathProgramCache]: Analyzing trace with hash -1110278718, now seen corresponding path program 1 times [2022-12-13 19:49:26,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:26,288 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266741946] [2022-12-13 19:49:26,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:26,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:26,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:26,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:26,338 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:26,339 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266741946] [2022-12-13 19:49:26,339 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266741946] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:26,339 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:26,339 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:26,339 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [622562343] [2022-12-13 19:49:26,339 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:26,339 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:26,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:26,340 INFO L85 PathProgramCache]: Analyzing trace with hash 1540422973, now seen corresponding path program 1 times [2022-12-13 19:49:26,340 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:26,340 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683981248] [2022-12-13 19:49:26,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:26,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:26,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:26,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:26,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:26,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683981248] [2022-12-13 19:49:26,373 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [683981248] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:26,373 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:26,374 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:26,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1167986722] [2022-12-13 19:49:26,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:26,374 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:26,374 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:26,375 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:49:26,375 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:49:26,375 INFO L87 Difference]: Start difference. First operand 10187 states and 14280 transitions. cyclomatic complexity: 4097 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:26,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:26,483 INFO L93 Difference]: Finished difference Result 16884 states and 23649 transitions. [2022-12-13 19:49:26,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16884 states and 23649 transitions. [2022-12-13 19:49:26,545 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 16720 [2022-12-13 19:49:26,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16884 states to 16884 states and 23649 transitions. [2022-12-13 19:49:26,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16884 [2022-12-13 19:49:26,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16884 [2022-12-13 19:49:26,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16884 states and 23649 transitions. [2022-12-13 19:49:26,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:26,632 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16884 states and 23649 transitions. [2022-12-13 19:49:26,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16884 states and 23649 transitions. [2022-12-13 19:49:26,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16884 to 8956. [2022-12-13 19:49:26,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8956 states, 8956 states have (on average 1.3967172845020097) internal successors, (12509), 8955 states have internal predecessors, (12509), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:26,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8956 states to 8956 states and 12509 transitions. [2022-12-13 19:49:26,722 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8956 states and 12509 transitions. [2022-12-13 19:49:26,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:49:26,723 INFO L428 stractBuchiCegarLoop]: Abstraction has 8956 states and 12509 transitions. [2022-12-13 19:49:26,723 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 19:49:26,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8956 states and 12509 transitions. [2022-12-13 19:49:26,743 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2022-12-13 19:49:26,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:26,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:26,744 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:26,744 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:26,744 INFO L748 eck$LassoCheckResult]: Stem: 194258#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 194259#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 194433#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 194434#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 194588#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 194514#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 194515#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 194466#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 194358#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 194359#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 194347#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 194348#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 194305#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 194306#L754 assume !(0 == ~M_E~0); 194636#L754-2 assume !(0 == ~T1_E~0); 194237#L759-1 assume !(0 == ~T2_E~0); 194238#L764-1 assume !(0 == ~T3_E~0); 194691#L769-1 assume !(0 == ~T4_E~0); 194692#L774-1 assume !(0 == ~T5_E~0); 194560#L779-1 assume !(0 == ~T6_E~0); 194270#L784-1 assume !(0 == ~T7_E~0); 194271#L789-1 assume !(0 == ~E_1~0); 193954#L794-1 assume !(0 == ~E_2~0); 193955#L799-1 assume !(0 == ~E_3~0); 194700#L804-1 assume !(0 == ~E_4~0); 194701#L809-1 assume !(0 == ~E_5~0); 194362#L814-1 assume !(0 == ~E_6~0); 193872#L819-1 assume !(0 == ~E_7~0); 193873#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 194345#L361 assume !(1 == ~m_pc~0); 194346#L361-2 is_master_triggered_~__retres1~0#1 := 0; 194400#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 194205#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 194206#L930 assume !(0 != activate_threads_~tmp~1#1); 194555#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 194338#L380 assume !(1 == ~t1_pc~0); 194012#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 194576#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 194577#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 194727#L938 assume !(0 != activate_threads_~tmp___0~0#1); 194085#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 194013#L399 assume !(1 == ~t2_pc~0); 194014#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 194211#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 194438#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 194429#L946 assume !(0 != activate_threads_~tmp___1~0#1); 193909#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 193880#L418 assume !(1 == ~t3_pc~0); 193844#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 193845#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 193870#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 193871#L954 assume !(0 != activate_threads_~tmp___2~0#1); 194717#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 194640#L437 assume !(1 == ~t4_pc~0); 194518#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 194178#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 194049#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 194050#L962 assume !(0 != activate_threads_~tmp___3~0#1); 194483#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 194134#L456 assume !(1 == ~t5_pc~0); 194135#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 194236#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 194217#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 193897#L970 assume !(0 != activate_threads_~tmp___4~0#1); 193898#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 194026#L475 assume !(1 == ~t6_pc~0); 194027#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 194104#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 194105#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 193863#L978 assume !(0 != activate_threads_~tmp___5~0#1); 193864#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 194352#L494 assume !(1 == ~t7_pc~0); 194354#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 194410#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 194672#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 194693#L986 assume !(0 != activate_threads_~tmp___6~0#1); 194724#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 194611#L837 assume !(1 == ~M_E~0); 194432#L837-2 assume !(1 == ~T1_E~0); 193994#L842-1 assume !(1 == ~T2_E~0); 193995#L847-1 assume !(1 == ~T3_E~0); 194509#L852-1 assume !(1 == ~T4_E~0); 194603#L857-1 assume !(1 == ~T5_E~0); 194444#L862-1 assume !(1 == ~T6_E~0); 194445#L867-1 assume !(1 == ~T7_E~0); 194455#L872-1 assume !(1 == ~E_1~0); 194559#L877-1 assume !(1 == ~E_2~0); 194452#L882-1 assume !(1 == ~E_3~0); 194453#L887-1 assume !(1 == ~E_4~0); 194054#L892-1 assume !(1 == ~E_5~0); 194055#L897-1 assume !(1 == ~E_6~0); 194473#L902-1 assume !(1 == ~E_7~0); 194131#L907-1 assume { :end_inline_reset_delta_events } true; 194132#L1148-2 [2022-12-13 19:49:26,745 INFO L750 eck$LassoCheckResult]: Loop: 194132#L1148-2 assume !false; 200020#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 200018#L729 assume !false; 200016#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 200002#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 199996#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 199994#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 199991#L626 assume !(0 != eval_~tmp~0#1); 199992#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 202781#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 202779#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 202777#L754-5 assume !(0 == ~T1_E~0); 202775#L759-3 assume !(0 == ~T2_E~0); 202774#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 202773#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 202771#L774-3 assume !(0 == ~T5_E~0); 202769#L779-3 assume !(0 == ~T6_E~0); 202768#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 202766#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 202765#L794-3 assume !(0 == ~E_2~0); 202706#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 202705#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 202704#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 202703#L814-3 assume !(0 == ~E_6~0); 202702#L819-3 assume !(0 == ~E_7~0); 202701#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 202699#L361-24 assume !(1 == ~m_pc~0); 202698#L361-26 is_master_triggered_~__retres1~0#1 := 0; 202697#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 202696#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 202694#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 202692#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 202690#L380-24 assume 1 == ~t1_pc~0; 202688#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 202689#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 202700#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 202679#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 202677#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 202675#L399-24 assume !(1 == ~t2_pc~0); 199882#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 202672#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 202670#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 202668#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 202666#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 202664#L418-24 assume 1 == ~t3_pc~0; 202662#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 202630#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 194481#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 194482#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 202588#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 202587#L437-24 assume !(1 == ~t4_pc~0); 202586#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 202584#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 202582#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 202580#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 202579#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 202578#L456-24 assume 1 == ~t5_pc~0; 202576#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 202573#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 202564#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 194442#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 194443#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 194617#L475-24 assume !(1 == ~t6_pc~0); 194467#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 194468#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 194195#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 194196#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 201436#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 201435#L494-24 assume !(1 == ~t7_pc~0); 201433#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 201432#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 201431#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 201430#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 201429#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 201427#L837-3 assume !(1 == ~M_E~0); 201425#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 201423#L842-3 assume !(1 == ~T2_E~0); 201421#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 201419#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 201417#L857-3 assume !(1 == ~T5_E~0); 201415#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 201413#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 201411#L872-3 assume !(1 == ~E_1~0); 201409#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 201407#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 201405#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 201403#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 201401#L897-3 assume !(1 == ~E_6~0); 201399#L902-3 assume !(1 == ~E_7~0); 201397#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 201389#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 201381#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 201367#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 201343#L1167 assume !(0 == start_simulation_~tmp~3#1); 201339#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 201326#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 201318#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 201267#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 201258#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 201252#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 201245#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 201239#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 194132#L1148-2 [2022-12-13 19:49:26,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:26,745 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 1 times [2022-12-13 19:49:26,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:26,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745239408] [2022-12-13 19:49:26,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:26,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:26,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:26,755 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:26,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:26,789 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:26,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:26,790 INFO L85 PathProgramCache]: Analyzing trace with hash 1808803810, now seen corresponding path program 1 times [2022-12-13 19:49:26,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:26,790 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557664391] [2022-12-13 19:49:26,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:26,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:26,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:26,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:26,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:26,815 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557664391] [2022-12-13 19:49:26,815 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557664391] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:26,815 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:26,815 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:26,815 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523929462] [2022-12-13 19:49:26,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:26,815 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:26,816 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:26,816 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:26,816 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:26,816 INFO L87 Difference]: Start difference. First operand 8956 states and 12509 transitions. cyclomatic complexity: 3557 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:26,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:26,895 INFO L93 Difference]: Finished difference Result 13391 states and 18516 transitions. [2022-12-13 19:49:26,895 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13391 states and 18516 transitions. [2022-12-13 19:49:26,935 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13188 [2022-12-13 19:49:26,959 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13391 states to 13391 states and 18516 transitions. [2022-12-13 19:49:26,960 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13391 [2022-12-13 19:49:26,965 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13391 [2022-12-13 19:49:26,966 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13391 states and 18516 transitions. [2022-12-13 19:49:26,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:26,974 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13391 states and 18516 transitions. [2022-12-13 19:49:26,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13391 states and 18516 transitions. [2022-12-13 19:49:27,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13391 to 13391. [2022-12-13 19:49:27,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13391 states, 13391 states have (on average 1.382719737136883) internal successors, (18516), 13390 states have internal predecessors, (18516), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:27,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13391 states to 13391 states and 18516 transitions. [2022-12-13 19:49:27,086 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13391 states and 18516 transitions. [2022-12-13 19:49:27,086 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:27,087 INFO L428 stractBuchiCegarLoop]: Abstraction has 13391 states and 18516 transitions. [2022-12-13 19:49:27,087 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 19:49:27,087 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13391 states and 18516 transitions. [2022-12-13 19:49:27,124 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13188 [2022-12-13 19:49:27,124 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:27,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:27,126 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:27,126 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:27,127 INFO L748 eck$LassoCheckResult]: Stem: 216617#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 216618#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 216798#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 216799#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 216944#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 216877#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 216878#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 216832#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 216718#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 216719#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 216707#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 216708#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 216664#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 216665#L754 assume 0 == ~M_E~0;~M_E~0 := 1; 216988#L754-2 assume !(0 == ~T1_E~0); 216593#L759-1 assume !(0 == ~T2_E~0); 216594#L764-1 assume !(0 == ~T3_E~0); 217048#L769-1 assume !(0 == ~T4_E~0); 217049#L774-1 assume !(0 == ~T5_E~0); 216916#L779-1 assume !(0 == ~T6_E~0); 216917#L784-1 assume !(0 == ~T7_E~0); 217046#L789-1 assume !(0 == ~E_1~0); 217047#L794-1 assume !(0 == ~E_2~0); 217089#L799-1 assume !(0 == ~E_3~0); 217090#L804-1 assume !(0 == ~E_4~0); 217082#L809-1 assume !(0 == ~E_5~0); 217083#L814-1 assume !(0 == ~E_6~0); 216224#L819-1 assume !(0 == ~E_7~0); 216225#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216705#L361 assume !(1 == ~m_pc~0); 216706#L361-2 is_master_triggered_~__retres1~0#1 := 0; 217022#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 217023#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 216911#L930 assume !(0 != activate_threads_~tmp~1#1); 216912#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216698#L380 assume !(1 == ~t1_pc~0); 216366#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 217126#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 217124#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 217095#L938 assume !(0 != activate_threads_~tmp___0~0#1); 216440#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 216441#L399 assume !(1 == ~t2_pc~0); 217120#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 217119#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 216803#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 216804#L946 assume !(0 != activate_threads_~tmp___1~0#1); 216262#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216263#L418 assume !(1 == ~t3_pc~0); 216197#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 216198#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 217118#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 217100#L954 assume !(0 != activate_threads_~tmp___2~0#1); 217101#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 216994#L437 assume !(1 == ~t4_pc~0); 216881#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 216882#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 217116#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 217115#L962 assume !(0 != activate_threads_~tmp___3~0#1); 217114#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 216490#L456 assume !(1 == ~t5_pc~0); 216491#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 216980#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216572#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 216250#L970 assume !(0 != activate_threads_~tmp___4~0#1); 216251#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 216380#L475 assume !(1 == ~t6_pc~0); 216381#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 216460#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 216461#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 217111#L978 assume !(0 != activate_threads_~tmp___5~0#1); 217061#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 217062#L494 assume !(1 == ~t7_pc~0); 216770#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 216771#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 217024#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 217050#L986 assume !(0 != activate_threads_~tmp___6~0#1); 217084#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 216966#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 216797#L837-2 assume !(1 == ~T1_E~0); 216347#L842-1 assume !(1 == ~T2_E~0); 216348#L847-1 assume !(1 == ~T3_E~0); 216873#L852-1 assume !(1 == ~T4_E~0); 216959#L857-1 assume !(1 == ~T5_E~0); 216808#L862-1 assume !(1 == ~T6_E~0); 216809#L867-1 assume !(1 == ~T7_E~0); 216820#L872-1 assume !(1 == ~E_1~0); 216915#L877-1 assume !(1 == ~E_2~0); 216816#L882-1 assume !(1 == ~E_3~0); 216817#L887-1 assume !(1 == ~E_4~0); 216408#L892-1 assume !(1 == ~E_5~0); 216409#L897-1 assume !(1 == ~E_6~0); 216839#L902-1 assume !(1 == ~E_7~0); 216487#L907-1 assume { :end_inline_reset_delta_events } true; 216488#L1148-2 [2022-12-13 19:49:27,127 INFO L750 eck$LassoCheckResult]: Loop: 216488#L1148-2 assume !false; 223480#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 223478#L729 assume !false; 223475#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 223461#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 223456#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 223455#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 223453#L626 assume !(0 != eval_~tmp~0#1); 223454#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 224708#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 224706#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 224707#L754-5 assume !(0 == ~T1_E~0); 224892#L759-3 assume !(0 == ~T2_E~0); 224890#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 224888#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 224887#L774-3 assume !(0 == ~T5_E~0); 224886#L779-3 assume !(0 == ~T6_E~0); 224882#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 224880#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 224765#L794-3 assume !(0 == ~E_2~0); 224757#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 224756#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 224755#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 224753#L814-3 assume !(0 == ~E_6~0); 224751#L819-3 assume !(0 == ~E_7~0); 224749#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 224748#L361-24 assume !(1 == ~m_pc~0); 224747#L361-26 is_master_triggered_~__retres1~0#1 := 0; 224746#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 224742#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 224740#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 224738#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 224719#L380-24 assume !(1 == ~t1_pc~0); 224714#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 224720#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 224715#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 224521#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 224509#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 223649#L399-24 assume !(1 == ~t2_pc~0); 223647#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 223645#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223643#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 223641#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 223638#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 223636#L418-24 assume 1 == ~t3_pc~0; 223634#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 223631#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 223629#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 223627#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 223625#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223623#L437-24 assume !(1 == ~t4_pc~0); 223621#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 223619#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 223617#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 223615#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 223612#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 223610#L456-24 assume !(1 == ~t5_pc~0); 223607#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 223605#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 223603#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 223601#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 223600#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 223598#L475-24 assume !(1 == ~t6_pc~0); 222666#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 223595#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 223593#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 223590#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 223588#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 223586#L494-24 assume !(1 == ~t7_pc~0); 223583#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 223581#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 223579#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 223578#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 223577#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 223575#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 223572#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 223571#L842-3 assume !(1 == ~T2_E~0); 223570#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 223568#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 223566#L857-3 assume !(1 == ~T5_E~0); 223564#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 223562#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 223560#L872-3 assume !(1 == ~E_1~0); 223558#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 223556#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 223553#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 223551#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 223549#L897-3 assume !(1 == ~E_6~0); 223546#L902-3 assume !(1 == ~E_7~0); 223544#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 223539#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 223531#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 223529#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 223526#L1167 assume !(0 == start_simulation_~tmp~3#1); 223522#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 223512#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 223506#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 223504#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 223502#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 223500#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 223498#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 223495#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 216488#L1148-2 [2022-12-13 19:49:27,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:27,127 INFO L85 PathProgramCache]: Analyzing trace with hash -162859702, now seen corresponding path program 1 times [2022-12-13 19:49:27,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:27,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725392069] [2022-12-13 19:49:27,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:27,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:27,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:27,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:27,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:27,157 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725392069] [2022-12-13 19:49:27,158 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1725392069] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:27,158 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:27,158 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:49:27,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777096420] [2022-12-13 19:49:27,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:27,158 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:27,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:27,159 INFO L85 PathProgramCache]: Analyzing trace with hash 1185061152, now seen corresponding path program 1 times [2022-12-13 19:49:27,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:27,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565860784] [2022-12-13 19:49:27,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:27,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:27,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:27,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:27,189 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:27,190 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565860784] [2022-12-13 19:49:27,190 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565860784] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:27,190 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:27,190 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:27,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1534237777] [2022-12-13 19:49:27,190 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:27,190 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:27,191 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:27,191 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:27,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:27,191 INFO L87 Difference]: Start difference. First operand 13391 states and 18516 transitions. cyclomatic complexity: 5129 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:27,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:27,270 INFO L93 Difference]: Finished difference Result 8956 states and 12399 transitions. [2022-12-13 19:49:27,270 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8956 states and 12399 transitions. [2022-12-13 19:49:27,292 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2022-12-13 19:49:27,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8956 states to 8956 states and 12399 transitions. [2022-12-13 19:49:27,304 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8956 [2022-12-13 19:49:27,308 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8956 [2022-12-13 19:49:27,308 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8956 states and 12399 transitions. [2022-12-13 19:49:27,312 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:27,312 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8956 states and 12399 transitions. [2022-12-13 19:49:27,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8956 states and 12399 transitions. [2022-12-13 19:49:27,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8956 to 8956. [2022-12-13 19:49:27,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8956 states, 8956 states have (on average 1.3844350156319785) internal successors, (12399), 8955 states have internal predecessors, (12399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:27,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8956 states to 8956 states and 12399 transitions. [2022-12-13 19:49:27,374 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8956 states and 12399 transitions. [2022-12-13 19:49:27,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:27,374 INFO L428 stractBuchiCegarLoop]: Abstraction has 8956 states and 12399 transitions. [2022-12-13 19:49:27,374 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 19:49:27,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8956 states and 12399 transitions. [2022-12-13 19:49:27,392 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2022-12-13 19:49:27,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:27,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:27,393 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:27,393 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:27,393 INFO L748 eck$LassoCheckResult]: Stem: 238968#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 238969#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 239139#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 239140#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 239283#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 239216#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 239217#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 239173#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 239068#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 239069#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 239057#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 239058#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 239013#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 239014#L754 assume !(0 == ~M_E~0); 239324#L754-2 assume !(0 == ~T1_E~0); 238943#L759-1 assume !(0 == ~T2_E~0); 238944#L764-1 assume !(0 == ~T3_E~0); 239378#L769-1 assume !(0 == ~T4_E~0); 239379#L774-1 assume !(0 == ~T5_E~0); 239257#L779-1 assume !(0 == ~T6_E~0); 238980#L784-1 assume !(0 == ~T7_E~0); 238981#L789-1 assume !(0 == ~E_1~0); 238660#L794-1 assume !(0 == ~E_2~0); 238661#L799-1 assume !(0 == ~E_3~0); 239382#L804-1 assume !(0 == ~E_4~0); 239383#L809-1 assume !(0 == ~E_5~0); 239072#L814-1 assume !(0 == ~E_6~0); 238578#L819-1 assume !(0 == ~E_7~0); 238579#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 239055#L361 assume !(1 == ~m_pc~0); 239056#L361-2 is_master_triggered_~__retres1~0#1 := 0; 239108#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 238911#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 238912#L930 assume !(0 != activate_threads_~tmp~1#1); 239254#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 239048#L380 assume !(1 == ~t1_pc~0); 238719#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 239271#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 239272#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 239410#L938 assume !(0 != activate_threads_~tmp___0~0#1); 238792#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 238720#L399 assume !(1 == ~t2_pc~0); 238721#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 238917#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 239144#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 239134#L946 assume !(0 != activate_threads_~tmp___1~0#1); 238614#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238586#L418 assume !(1 == ~t3_pc~0); 238551#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 238552#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 238576#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 238577#L954 assume !(0 != activate_threads_~tmp___2~0#1); 239398#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 239325#L437 assume !(1 == ~t4_pc~0); 239220#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 238886#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 238756#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 238757#L962 assume !(0 != activate_threads_~tmp___3~0#1); 239187#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 238840#L456 assume !(1 == ~t5_pc~0); 238841#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 238942#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 238923#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 238602#L970 assume !(0 != activate_threads_~tmp___4~0#1); 238603#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 238733#L475 assume !(1 == ~t6_pc~0); 238734#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 238811#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 238812#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 238570#L978 assume !(0 != activate_threads_~tmp___5~0#1); 238571#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 239062#L494 assume !(1 == ~t7_pc~0); 239064#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 239116#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 239355#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 239380#L986 assume !(0 != activate_threads_~tmp___6~0#1); 239408#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 239303#L837 assume !(1 == ~M_E~0); 239138#L837-2 assume !(1 == ~T1_E~0); 238699#L842-1 assume !(1 == ~T2_E~0); 238700#L847-1 assume !(1 == ~T3_E~0); 239212#L852-1 assume !(1 == ~T4_E~0); 239296#L857-1 assume !(1 == ~T5_E~0); 239150#L862-1 assume !(1 == ~T6_E~0); 239151#L867-1 assume !(1 == ~T7_E~0); 239162#L872-1 assume !(1 == ~E_1~0); 239256#L877-1 assume !(1 == ~E_2~0); 239159#L882-1 assume !(1 == ~E_3~0); 239160#L887-1 assume !(1 == ~E_4~0); 238761#L892-1 assume !(1 == ~E_5~0); 238762#L897-1 assume !(1 == ~E_6~0); 239180#L902-1 assume !(1 == ~E_7~0); 238837#L907-1 assume { :end_inline_reset_delta_events } true; 238838#L1148-2 [2022-12-13 19:49:27,393 INFO L750 eck$LassoCheckResult]: Loop: 238838#L1148-2 assume !false; 245540#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 245535#L729 assume !false; 245531#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 245473#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 245467#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 245464#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 245461#L626 assume !(0 != eval_~tmp~0#1); 245462#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 247036#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 247035#L754-3 assume !(0 == ~M_E~0); 247034#L754-5 assume !(0 == ~T1_E~0); 247032#L759-3 assume !(0 == ~T2_E~0); 247030#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 247029#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 247028#L774-3 assume !(0 == ~T5_E~0); 247027#L779-3 assume !(0 == ~T6_E~0); 247025#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 247023#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 247021#L794-3 assume !(0 == ~E_2~0); 247019#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 247017#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 247015#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 247013#L814-3 assume !(0 == ~E_6~0); 247010#L819-3 assume !(0 == ~E_7~0); 247008#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247006#L361-24 assume !(1 == ~m_pc~0); 246685#L361-26 is_master_triggered_~__retres1~0#1 := 0; 246684#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 246683#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 246682#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 246681#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 246679#L380-24 assume 1 == ~t1_pc~0; 246677#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 246678#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 246680#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 246670#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 246563#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 245904#L399-24 assume !(1 == ~t2_pc~0); 245902#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 245899#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 245896#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 245890#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 245885#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 245880#L418-24 assume 1 == ~t3_pc~0; 245875#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 245869#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 245863#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 245857#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 245850#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 245844#L437-24 assume !(1 == ~t4_pc~0); 245838#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 245834#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 245829#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 245824#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 245819#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 245814#L456-24 assume 1 == ~t5_pc~0; 245808#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 245800#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 245793#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 245787#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 245782#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 245777#L475-24 assume !(1 == ~t6_pc~0); 242188#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 245767#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 245763#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 245757#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 245752#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 245747#L494-24 assume !(1 == ~t7_pc~0); 245741#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 245737#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 245732#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 245728#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 245724#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 245719#L837-3 assume !(1 == ~M_E~0); 245715#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 245711#L842-3 assume !(1 == ~T2_E~0); 245707#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 245703#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 245699#L857-3 assume !(1 == ~T5_E~0); 245695#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 245689#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 245684#L872-3 assume !(1 == ~E_1~0); 245680#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 245676#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 245670#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 245664#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 245659#L897-3 assume !(1 == ~E_6~0); 245653#L902-3 assume !(1 == ~E_7~0); 245650#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 245643#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 245632#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 245626#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 245619#L1167 assume !(0 == start_simulation_~tmp~3#1); 245616#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 245583#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 245574#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 245570#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 245563#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 245558#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 245553#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 245549#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 238838#L1148-2 [2022-12-13 19:49:27,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:27,394 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 2 times [2022-12-13 19:49:27,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:27,394 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1172836439] [2022-12-13 19:49:27,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:27,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:27,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:27,403 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:27,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:27,421 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:27,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:27,422 INFO L85 PathProgramCache]: Analyzing trace with hash 1780303520, now seen corresponding path program 1 times [2022-12-13 19:49:27,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:27,422 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927057048] [2022-12-13 19:49:27,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:27,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:27,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:27,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:27,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:27,445 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [927057048] [2022-12-13 19:49:27,445 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [927057048] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:27,446 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:27,446 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:27,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814048198] [2022-12-13 19:49:27,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:27,446 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:27,446 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:27,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:27,447 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:27,447 INFO L87 Difference]: Start difference. First operand 8956 states and 12399 transitions. cyclomatic complexity: 3447 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:27,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:27,532 INFO L93 Difference]: Finished difference Result 16204 states and 22209 transitions. [2022-12-13 19:49:27,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16204 states and 22209 transitions. [2022-12-13 19:49:27,575 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15988 [2022-12-13 19:49:27,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16204 states to 16204 states and 22209 transitions. [2022-12-13 19:49:27,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16204 [2022-12-13 19:49:27,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16204 [2022-12-13 19:49:27,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16204 states and 22209 transitions. [2022-12-13 19:49:27,617 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:27,617 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16204 states and 22209 transitions. [2022-12-13 19:49:27,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16204 states and 22209 transitions. [2022-12-13 19:49:27,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16204 to 16164. [2022-12-13 19:49:27,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16164 states, 16164 states have (on average 1.371504578074734) internal successors, (22169), 16163 states have internal predecessors, (22169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:27,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16164 states to 16164 states and 22169 transitions. [2022-12-13 19:49:27,735 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16164 states and 22169 transitions. [2022-12-13 19:49:27,735 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:27,735 INFO L428 stractBuchiCegarLoop]: Abstraction has 16164 states and 22169 transitions. [2022-12-13 19:49:27,736 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 19:49:27,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16164 states and 22169 transitions. [2022-12-13 19:49:27,768 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15956 [2022-12-13 19:49:27,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:27,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:27,770 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:27,770 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:27,770 INFO L748 eck$LassoCheckResult]: Stem: 264138#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 264139#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 264327#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 264328#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 264496#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 264418#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 264419#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 264369#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 264241#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 264242#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 264230#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 264231#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 264183#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 264184#L754 assume !(0 == ~M_E~0); 264547#L754-2 assume !(0 == ~T1_E~0); 264114#L759-1 assume !(0 == ~T2_E~0); 264115#L764-1 assume !(0 == ~T3_E~0); 264610#L769-1 assume !(0 == ~T4_E~0); 264611#L774-1 assume !(0 == ~T5_E~0); 264463#L779-1 assume !(0 == ~T6_E~0); 264150#L784-1 assume !(0 == ~T7_E~0); 264151#L789-1 assume 0 == ~E_1~0;~E_1~0 := 1; 263829#L794-1 assume !(0 == ~E_2~0); 263830#L799-1 assume !(0 == ~E_3~0); 264620#L804-1 assume !(0 == ~E_4~0); 264621#L809-1 assume !(0 == ~E_5~0); 264245#L814-1 assume !(0 == ~E_6~0); 264246#L819-1 assume !(0 == ~E_7~0); 264315#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264316#L361 assume !(1 == ~m_pc~0); 264285#L361-2 is_master_triggered_~__retres1~0#1 := 0; 264286#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 264685#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 264683#L930 assume !(0 != activate_threads_~tmp~1#1); 264523#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 264524#L380 assume !(1 == ~t1_pc~0); 264661#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 264481#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 264482#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 264664#L938 assume !(0 != activate_threads_~tmp___0~0#1); 263958#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 263959#L399 assume !(1 == ~t2_pc~0); 264085#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 264086#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 264497#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264321#L946 assume !(0 != activate_threads_~tmp___1~0#1); 264322#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 263752#L418 assume !(1 == ~t3_pc~0); 263753#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 264253#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 263742#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 263743#L954 assume !(0 != activate_threads_~tmp___2~0#1); 264643#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 264644#L437 assume !(1 == ~t4_pc~0); 264690#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 264054#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 263924#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 263925#L962 assume !(0 != activate_threads_~tmp___3~0#1); 264387#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 264388#L456 assume !(1 == ~t5_pc~0); 264113#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 264112#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264686#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 264684#L970 assume !(0 != activate_threads_~tmp___4~0#1); 264615#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 264616#L475 assume !(1 == ~t6_pc~0); 264577#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 264578#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 264312#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 263736#L978 assume !(0 != activate_threads_~tmp___5~0#1); 263737#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 264235#L494 assume !(1 == ~t7_pc~0); 264237#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 264586#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 264587#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 264680#L986 assume !(0 != activate_threads_~tmp___6~0#1); 264657#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 264658#L837 assume !(1 == ~M_E~0); 264325#L837-2 assume !(1 == ~T1_E~0); 264326#L842-1 assume !(1 == ~T2_E~0); 264679#L847-1 assume !(1 == ~T3_E~0); 264511#L852-1 assume !(1 == ~T4_E~0); 264512#L857-1 assume !(1 == ~T5_E~0); 264341#L862-1 assume !(1 == ~T6_E~0); 264342#L867-1 assume !(1 == ~T7_E~0); 264358#L872-1 assume 1 == ~E_1~0;~E_1~0 := 2; 264462#L877-1 assume !(1 == ~E_2~0); 264352#L882-1 assume !(1 == ~E_3~0); 264353#L887-1 assume !(1 == ~E_4~0); 263927#L892-1 assume !(1 == ~E_5~0); 263928#L897-1 assume !(1 == ~E_6~0); 264378#L902-1 assume !(1 == ~E_7~0); 264004#L907-1 assume { :end_inline_reset_delta_events } true; 264005#L1148-2 [2022-12-13 19:49:27,770 INFO L750 eck$LassoCheckResult]: Loop: 264005#L1148-2 assume !false; 263744#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 263745#L729 assume !false; 264146#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 264141#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 264090#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 264169#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 278808#L626 assume !(0 != eval_~tmp~0#1); 278809#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 279309#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 279308#L754-3 assume !(0 == ~M_E~0); 279307#L754-5 assume !(0 == ~T1_E~0); 279306#L759-3 assume !(0 == ~T2_E~0); 279305#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 279304#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 279303#L774-3 assume !(0 == ~T5_E~0); 279302#L779-3 assume !(0 == ~T6_E~0); 279301#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 279300#L789-3 assume !(0 == ~E_1~0); 279299#L794-3 assume !(0 == ~E_2~0); 279298#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 279297#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 279296#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 279295#L814-3 assume !(0 == ~E_6~0); 279294#L819-3 assume !(0 == ~E_7~0); 279293#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 279292#L361-24 assume !(1 == ~m_pc~0); 279291#L361-26 is_master_triggered_~__retres1~0#1 := 0; 279290#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 279289#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 279288#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 279287#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 279286#L380-24 assume !(1 == ~t1_pc~0); 278980#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 278979#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 278977#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 278973#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 278969#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 264099#L399-24 assume !(1 == ~t2_pc~0); 264100#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 264148#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 264149#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264508#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 264243#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 264244#L418-24 assume 1 == ~t3_pc~0; 279644#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 279641#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 279639#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 279637#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 279635#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 279633#L437-24 assume !(1 == ~t4_pc~0); 279631#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 279629#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 279626#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 279624#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 264627#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 264483#L456-24 assume 1 == ~t5_pc~0; 264484#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 264575#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264185#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 264186#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 264340#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 264527#L475-24 assume !(1 == ~t6_pc~0); 264370#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 264371#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 278688#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 264623#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 264624#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 278682#L494-24 assume !(1 == ~t7_pc~0); 264351#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 264317#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 264318#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 264234#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 264046#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 264047#L837-3 assume !(1 == ~M_E~0); 264131#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 264518#L842-3 assume !(1 == ~T2_E~0); 264412#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 263766#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 263767#L857-3 assume !(1 == ~T5_E~0); 264582#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 264636#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 278652#L872-3 assume !(1 == ~E_1~0); 264478#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 264572#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 264603#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 264135#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 264127#L897-3 assume !(1 == ~E_6~0); 264128#L902-3 assume !(1 == ~E_7~0); 264372#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 264360#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 263751#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 264272#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 264273#L1167 assume !(0 == start_simulation_~tmp~3#1); 264413#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 264452#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 264159#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 263798#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 263799#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 264429#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 264430#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 264182#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 264005#L1148-2 [2022-12-13 19:49:27,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:27,771 INFO L85 PathProgramCache]: Analyzing trace with hash -1593984694, now seen corresponding path program 1 times [2022-12-13 19:49:27,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:27,771 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [893782327] [2022-12-13 19:49:27,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:27,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:27,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:27,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:27,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:27,827 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [893782327] [2022-12-13 19:49:27,827 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [893782327] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:27,827 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:27,827 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:27,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [67029172] [2022-12-13 19:49:27,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:27,828 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:27,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:27,828 INFO L85 PathProgramCache]: Analyzing trace with hash 75961595, now seen corresponding path program 1 times [2022-12-13 19:49:27,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:27,828 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752038004] [2022-12-13 19:49:27,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:27,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:27,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:27,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:27,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:27,862 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1752038004] [2022-12-13 19:49:27,862 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1752038004] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:27,862 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:27,862 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:49:27,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728591693] [2022-12-13 19:49:27,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:27,863 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:27,863 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:27,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:49:27,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:49:27,864 INFO L87 Difference]: Start difference. First operand 16164 states and 22169 transitions. cyclomatic complexity: 6009 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:27,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:27,982 INFO L93 Difference]: Finished difference Result 23828 states and 32646 transitions. [2022-12-13 19:49:27,982 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23828 states and 32646 transitions. [2022-12-13 19:49:28,042 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22496 [2022-12-13 19:49:28,081 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23828 states to 23828 states and 32646 transitions. [2022-12-13 19:49:28,081 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23828 [2022-12-13 19:49:28,091 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23828 [2022-12-13 19:49:28,091 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23828 states and 32646 transitions. [2022-12-13 19:49:28,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:28,101 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23828 states and 32646 transitions. [2022-12-13 19:49:28,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23828 states and 32646 transitions. [2022-12-13 19:49:28,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23828 to 16145. [2022-12-13 19:49:28,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16145 states, 16145 states have (on average 1.370517187983896) internal successors, (22127), 16144 states have internal predecessors, (22127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:28,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16145 states to 16145 states and 22127 transitions. [2022-12-13 19:49:28,239 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16145 states and 22127 transitions. [2022-12-13 19:49:28,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:49:28,239 INFO L428 stractBuchiCegarLoop]: Abstraction has 16145 states and 22127 transitions. [2022-12-13 19:49:28,239 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 19:49:28,239 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16145 states and 22127 transitions. [2022-12-13 19:49:28,271 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15956 [2022-12-13 19:49:28,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:28,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:28,272 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:28,272 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:28,272 INFO L748 eck$LassoCheckResult]: Stem: 304137#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 304138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 304325#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 304326#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 304478#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 304409#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 304410#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 304363#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 304246#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 304247#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 304235#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 304236#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 304191#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 304192#L754 assume !(0 == ~M_E~0); 304528#L754-2 assume !(0 == ~T1_E~0); 304117#L759-1 assume !(0 == ~T2_E~0); 304118#L764-1 assume !(0 == ~T3_E~0); 304585#L769-1 assume !(0 == ~T4_E~0); 304586#L774-1 assume !(0 == ~T5_E~0); 304449#L779-1 assume !(0 == ~T6_E~0); 304152#L784-1 assume !(0 == ~T7_E~0); 304153#L789-1 assume !(0 == ~E_1~0); 303838#L794-1 assume !(0 == ~E_2~0); 303839#L799-1 assume !(0 == ~E_3~0); 304592#L804-1 assume !(0 == ~E_4~0); 304593#L809-1 assume !(0 == ~E_5~0); 304251#L814-1 assume !(0 == ~E_6~0); 303753#L819-1 assume !(0 == ~E_7~0); 303754#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 304231#L361 assume !(1 == ~m_pc~0); 304232#L361-2 is_master_triggered_~__retres1~0#1 := 0; 304285#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 304083#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 304084#L930 assume !(0 != activate_threads_~tmp~1#1); 304446#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 304224#L380 assume !(1 == ~t1_pc~0); 303891#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 304629#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 303807#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 303808#L938 assume !(0 != activate_threads_~tmp___0~0#1); 304654#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 303892#L399 assume !(1 == ~t2_pc~0); 303893#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 304089#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 304480#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 304319#L946 assume !(0 != activate_threads_~tmp___1~0#1); 304320#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 303761#L418 assume !(1 == ~t3_pc~0); 303762#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 304255#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 303747#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 303748#L954 assume !(0 != activate_threads_~tmp___2~0#1); 304615#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 304616#L437 assume !(1 == ~t4_pc~0); 304650#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 304060#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 303930#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 303931#L962 assume !(0 != activate_threads_~tmp___3~0#1); 304378#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 304379#L456 assume !(1 == ~t5_pc~0); 304115#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 304114#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 304095#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 303778#L970 assume !(0 != activate_threads_~tmp___4~0#1); 303779#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 303909#L475 assume !(1 == ~t6_pc~0); 303910#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 303983#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 303984#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 304645#L978 assume !(0 != activate_threads_~tmp___5~0#1); 304599#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 304600#L494 assume !(1 == ~t7_pc~0); 304294#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 304295#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 304587#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 304588#L986 assume !(0 != activate_threads_~tmp___6~0#1); 304625#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 304626#L837 assume !(1 == ~M_E~0); 304323#L837-2 assume !(1 == ~T1_E~0); 304324#L842-1 assume !(1 == ~T2_E~0); 304643#L847-1 assume !(1 == ~T3_E~0); 304493#L852-1 assume !(1 == ~T4_E~0); 304494#L857-1 assume !(1 == ~T5_E~0); 304336#L862-1 assume !(1 == ~T6_E~0); 304337#L867-1 assume !(1 == ~T7_E~0); 304642#L872-1 assume !(1 == ~E_1~0); 304448#L877-1 assume !(1 == ~E_2~0); 304345#L882-1 assume !(1 == ~E_3~0); 304346#L887-1 assume !(1 == ~E_4~0); 303935#L892-1 assume !(1 == ~E_5~0); 303936#L897-1 assume !(1 == ~E_6~0); 304373#L902-1 assume !(1 == ~E_7~0); 304009#L907-1 assume { :end_inline_reset_delta_events } true; 304010#L1148-2 [2022-12-13 19:49:28,272 INFO L750 eck$LassoCheckResult]: Loop: 304010#L1148-2 assume !false; 312828#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 312827#L729 assume !false; 312826#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 312822#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 312818#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 314862#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 314859#L626 assume !(0 != eval_~tmp~0#1); 314860#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 319391#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 319390#L754-3 assume !(0 == ~M_E~0); 319389#L754-5 assume !(0 == ~T1_E~0); 319388#L759-3 assume !(0 == ~T2_E~0); 319386#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 319384#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 319382#L774-3 assume !(0 == ~T5_E~0); 319380#L779-3 assume !(0 == ~T6_E~0); 319378#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 319376#L789-3 assume !(0 == ~E_1~0); 319373#L794-3 assume !(0 == ~E_2~0); 319372#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 319370#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 319368#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 319366#L814-3 assume !(0 == ~E_6~0); 319364#L819-3 assume !(0 == ~E_7~0); 319362#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 319360#L361-24 assume !(1 == ~m_pc~0); 319358#L361-26 is_master_triggered_~__retres1~0#1 := 0; 319356#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 319353#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 319351#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 319349#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 319347#L380-24 assume !(1 == ~t1_pc~0); 319344#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 319342#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 319341#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 319269#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 319268#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 316692#L399-24 assume !(1 == ~t2_pc~0); 315024#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 316689#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 316687#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 316685#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 316101#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 316099#L418-24 assume !(1 == ~t3_pc~0); 316096#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 316094#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 316092#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 316090#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 316088#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 316086#L437-24 assume !(1 == ~t4_pc~0); 316084#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 316082#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 316080#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 316078#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 316076#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 315934#L456-24 assume 1 == ~t5_pc~0; 315884#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 315878#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 315869#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 315868#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 315819#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 314855#L475-24 assume !(1 == ~t6_pc~0); 314854#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 314853#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 314852#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 314849#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 314847#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 314845#L494-24 assume !(1 == ~t7_pc~0); 314842#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 314839#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 314837#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 314835#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 314833#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 314831#L837-3 assume !(1 == ~M_E~0); 314829#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 314827#L842-3 assume !(1 == ~T2_E~0); 314824#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 314822#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 314820#L857-3 assume !(1 == ~T5_E~0); 314818#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 314816#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 314809#L872-3 assume !(1 == ~E_1~0); 314805#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 314803#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 314801#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 314787#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 314781#L897-3 assume !(1 == ~E_6~0); 314770#L902-3 assume !(1 == ~E_7~0); 314769#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 314693#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 314681#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 314676#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 314668#L1167 assume !(0 == start_simulation_~tmp~3#1); 314664#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 314619#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 314611#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 314608#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 314605#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 314600#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 314593#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 314588#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 304010#L1148-2 [2022-12-13 19:49:28,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:28,273 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 3 times [2022-12-13 19:49:28,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:28,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032305605] [2022-12-13 19:49:28,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:28,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:28,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:28,279 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:28,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:28,294 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:28,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:28,295 INFO L85 PathProgramCache]: Analyzing trace with hash -1065685798, now seen corresponding path program 1 times [2022-12-13 19:49:28,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:28,295 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [900515324] [2022-12-13 19:49:28,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:28,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:28,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:28,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:28,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:28,326 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [900515324] [2022-12-13 19:49:28,326 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [900515324] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:28,326 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:28,326 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:49:28,326 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636344830] [2022-12-13 19:49:28,326 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:28,326 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:28,326 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:28,327 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:49:28,327 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:49:28,327 INFO L87 Difference]: Start difference. First operand 16145 states and 22127 transitions. cyclomatic complexity: 5986 Second operand has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:28,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:28,464 INFO L93 Difference]: Finished difference Result 29293 states and 39879 transitions. [2022-12-13 19:49:28,464 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29293 states and 39879 transitions. [2022-12-13 19:49:28,561 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 29064 [2022-12-13 19:49:28,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29293 states to 29293 states and 39879 transitions. [2022-12-13 19:49:28,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29293 [2022-12-13 19:49:28,691 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29293 [2022-12-13 19:49:28,691 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29293 states and 39879 transitions. [2022-12-13 19:49:28,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:28,703 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29293 states and 39879 transitions. [2022-12-13 19:49:28,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29293 states and 39879 transitions. [2022-12-13 19:49:28,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29293 to 16241. [2022-12-13 19:49:28,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16241 states, 16241 states have (on average 1.368327073456068) internal successors, (22223), 16240 states have internal predecessors, (22223), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:28,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16241 states to 16241 states and 22223 transitions. [2022-12-13 19:49:28,882 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16241 states and 22223 transitions. [2022-12-13 19:49:28,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 19:49:28,883 INFO L428 stractBuchiCegarLoop]: Abstraction has 16241 states and 22223 transitions. [2022-12-13 19:49:28,883 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 19:49:28,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16241 states and 22223 transitions. [2022-12-13 19:49:28,926 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 16052 [2022-12-13 19:49:28,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:28,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:28,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:28,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:28,928 INFO L748 eck$LassoCheckResult]: Stem: 349600#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 349601#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 349785#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 349786#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 349937#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 349868#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 349869#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 349823#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 349709#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 349710#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 349697#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 349698#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 349652#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 349653#L754 assume !(0 == ~M_E~0); 349990#L754-2 assume !(0 == ~T1_E~0); 349571#L759-1 assume !(0 == ~T2_E~0); 349572#L764-1 assume !(0 == ~T3_E~0); 350057#L769-1 assume !(0 == ~T4_E~0); 350058#L774-1 assume !(0 == ~T5_E~0); 349911#L779-1 assume !(0 == ~T6_E~0); 349616#L784-1 assume !(0 == ~T7_E~0); 349617#L789-1 assume !(0 == ~E_1~0); 349291#L794-1 assume !(0 == ~E_2~0); 349292#L799-1 assume !(0 == ~E_3~0); 350065#L804-1 assume !(0 == ~E_4~0); 350066#L809-1 assume !(0 == ~E_5~0); 349713#L814-1 assume !(0 == ~E_6~0); 349206#L819-1 assume !(0 == ~E_7~0); 349207#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 349693#L361 assume !(1 == ~m_pc~0); 349694#L361-2 is_master_triggered_~__retres1~0#1 := 0; 349750#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 349535#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 349536#L930 assume !(0 != activate_threads_~tmp~1#1); 349907#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 349685#L380 assume !(1 == ~t1_pc~0); 349344#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 350102#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 349260#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 349261#L938 assume !(0 != activate_threads_~tmp___0~0#1); 350138#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 349345#L399 assume !(1 == ~t2_pc~0); 349346#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 350137#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 349790#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 349791#L946 assume !(0 != activate_threads_~tmp___1~0#1); 349240#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 349241#L418 assume !(1 == ~t3_pc~0); 349175#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 349176#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 350136#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 350115#L954 assume !(0 != activate_threads_~tmp___2~0#1); 350116#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 349995#L437 assume !(1 == ~t4_pc~0); 349872#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 349873#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 350134#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 350133#L962 assume !(0 != activate_threads_~tmp___3~0#1); 350132#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 349469#L456 assume !(1 == ~t5_pc~0); 349470#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 349980#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 349549#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 349231#L970 assume !(0 != activate_threads_~tmp___4~0#1); 349232#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 349362#L475 assume !(1 == ~t6_pc~0); 349363#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 349434#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 349435#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 350129#L978 assume !(0 != activate_threads_~tmp___5~0#1); 350071#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 350072#L494 assume !(1 == ~t7_pc~0); 349758#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 349759#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 350059#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 350060#L986 assume !(0 != activate_threads_~tmp___6~0#1); 350105#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 349962#L837 assume !(1 == ~M_E~0); 349963#L837-2 assume !(1 == ~T1_E~0); 349326#L842-1 assume !(1 == ~T2_E~0); 349327#L847-1 assume !(1 == ~T3_E~0); 349863#L852-1 assume !(1 == ~T4_E~0); 350125#L857-1 assume !(1 == ~T5_E~0); 349796#L862-1 assume !(1 == ~T6_E~0); 349797#L867-1 assume !(1 == ~T7_E~0); 350124#L872-1 assume !(1 == ~E_1~0); 349910#L877-1 assume !(1 == ~E_2~0); 349804#L882-1 assume !(1 == ~E_3~0); 349805#L887-1 assume !(1 == ~E_4~0); 349387#L892-1 assume !(1 == ~E_5~0); 349388#L897-1 assume !(1 == ~E_6~0); 349835#L902-1 assume !(1 == ~E_7~0); 349461#L907-1 assume { :end_inline_reset_delta_events } true; 349462#L1148-2 [2022-12-13 19:49:28,928 INFO L750 eck$LassoCheckResult]: Loop: 349462#L1148-2 assume !false; 357018#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 357016#L729 assume !false; 356947#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 356801#L569 assume !(0 == ~m_st~0); 356802#L573 assume !(0 == ~t1_st~0); 356805#L577 assume !(0 == ~t2_st~0); 356799#L581 assume !(0 == ~t3_st~0); 356800#L585 assume !(0 == ~t4_st~0); 356804#L589 assume !(0 == ~t5_st~0); 356797#L593 assume !(0 == ~t6_st~0); 356798#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 356803#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 355210#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 355211#L626 assume !(0 != eval_~tmp~0#1); 357219#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 357217#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 357215#L754-3 assume !(0 == ~M_E~0); 357213#L754-5 assume !(0 == ~T1_E~0); 357211#L759-3 assume !(0 == ~T2_E~0); 357209#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 357207#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 357205#L774-3 assume !(0 == ~T5_E~0); 357203#L779-3 assume !(0 == ~T6_E~0); 357201#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 357199#L789-3 assume !(0 == ~E_1~0); 357197#L794-3 assume !(0 == ~E_2~0); 357195#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 357193#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 357191#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 357189#L814-3 assume !(0 == ~E_6~0); 357187#L819-3 assume !(0 == ~E_7~0); 357185#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 357183#L361-24 assume !(1 == ~m_pc~0); 357181#L361-26 is_master_triggered_~__retres1~0#1 := 0; 357179#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 357177#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 357175#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 357173#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 357170#L380-24 assume !(1 == ~t1_pc~0); 357166#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 357163#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 357160#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 357157#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 357155#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 357153#L399-24 assume !(1 == ~t2_pc~0); 354366#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 357151#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 357149#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 357147#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 357145#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 357143#L418-24 assume 1 == ~t3_pc~0; 357140#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 357137#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 357135#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 357133#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 357131#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 357129#L437-24 assume !(1 == ~t4_pc~0); 357127#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 357125#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 357123#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 357121#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 357119#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 357117#L456-24 assume !(1 == ~t5_pc~0); 357113#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 357111#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 357109#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 357107#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 357105#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 357103#L475-24 assume !(1 == ~t6_pc~0); 355385#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 357101#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 357099#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 357097#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 357095#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 357092#L494-24 assume !(1 == ~t7_pc~0); 357089#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 357087#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 357085#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 357083#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 357081#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 357079#L837-3 assume !(1 == ~M_E~0); 357077#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 357075#L842-3 assume !(1 == ~T2_E~0); 357073#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 357071#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 357069#L857-3 assume !(1 == ~T5_E~0); 357067#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 357065#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 357063#L872-3 assume !(1 == ~E_1~0); 357062#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 357061#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 357060#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 357059#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 357058#L897-3 assume !(1 == ~E_6~0); 357057#L902-3 assume !(1 == ~E_7~0); 357056#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 357054#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 357046#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 357044#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 357041#L1167 assume !(0 == start_simulation_~tmp~3#1); 357039#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 357035#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 357030#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 357029#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 357028#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 357027#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 357025#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 357023#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 349462#L1148-2 [2022-12-13 19:49:28,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:28,929 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 4 times [2022-12-13 19:49:28,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:28,929 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791608393] [2022-12-13 19:49:28,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:28,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:28,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:28,938 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:28,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:28,955 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:28,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:28,956 INFO L85 PathProgramCache]: Analyzing trace with hash -544398754, now seen corresponding path program 1 times [2022-12-13 19:49:28,956 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:28,956 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403570256] [2022-12-13 19:49:28,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:28,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:28,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:29,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:29,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:29,031 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1403570256] [2022-12-13 19:49:29,031 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1403570256] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:29,031 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:29,031 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:49:29,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1503639715] [2022-12-13 19:49:29,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:29,032 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:29,032 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:29,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:49:29,032 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:49:29,032 INFO L87 Difference]: Start difference. First operand 16241 states and 22223 transitions. cyclomatic complexity: 5986 Second operand has 5 states, 5 states have (on average 21.8) internal successors, (109), 5 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:29,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:29,202 INFO L93 Difference]: Finished difference Result 19929 states and 27326 transitions. [2022-12-13 19:49:29,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19929 states and 27326 transitions. [2022-12-13 19:49:29,267 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 19724 [2022-12-13 19:49:29,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19929 states to 19929 states and 27326 transitions. [2022-12-13 19:49:29,309 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19929 [2022-12-13 19:49:29,318 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19929 [2022-12-13 19:49:29,318 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19929 states and 27326 transitions. [2022-12-13 19:49:29,329 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:29,329 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19929 states and 27326 transitions. [2022-12-13 19:49:29,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19929 states and 27326 transitions. [2022-12-13 19:49:29,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19929 to 16265. [2022-12-13 19:49:29,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16265 states, 16265 states have (on average 1.3559176145096834) internal successors, (22054), 16264 states have internal predecessors, (22054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:29,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16265 states to 16265 states and 22054 transitions. [2022-12-13 19:49:29,494 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16265 states and 22054 transitions. [2022-12-13 19:49:29,495 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 19:49:29,495 INFO L428 stractBuchiCegarLoop]: Abstraction has 16265 states and 22054 transitions. [2022-12-13 19:49:29,495 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 19:49:29,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16265 states and 22054 transitions. [2022-12-13 19:49:29,536 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 16076 [2022-12-13 19:49:29,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:29,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:29,537 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:29,538 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:29,538 INFO L748 eck$LassoCheckResult]: Stem: 385792#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 385793#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 385986#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 385987#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 386161#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 386081#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 386082#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 386024#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 385899#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 385900#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 385887#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 385888#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 385842#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 385843#L754 assume !(0 == ~M_E~0); 386220#L754-2 assume !(0 == ~T1_E~0); 385766#L759-1 assume !(0 == ~T2_E~0); 385767#L764-1 assume !(0 == ~T3_E~0); 386304#L769-1 assume !(0 == ~T4_E~0); 386305#L774-1 assume !(0 == ~T5_E~0); 386133#L779-1 assume !(0 == ~T6_E~0); 385804#L784-1 assume !(0 == ~T7_E~0); 385805#L789-1 assume !(0 == ~E_1~0); 385470#L794-1 assume !(0 == ~E_2~0); 385471#L799-1 assume !(0 == ~E_3~0); 386318#L804-1 assume !(0 == ~E_4~0); 386319#L809-1 assume !(0 == ~E_5~0); 385903#L814-1 assume !(0 == ~E_6~0); 385385#L819-1 assume !(0 == ~E_7~0); 385386#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 385885#L361 assume !(1 == ~m_pc~0); 385886#L361-2 is_master_triggered_~__retres1~0#1 := 0; 385943#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 385726#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 385727#L930 assume !(0 != activate_threads_~tmp~1#1); 386129#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 385877#L380 assume !(1 == ~t1_pc~0); 385529#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 386150#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 386151#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 386371#L938 assume !(0 != activate_threads_~tmp___0~0#1); 385604#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 385605#L399 assume !(1 == ~t2_pc~0); 385732#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 385733#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 386166#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 385978#L946 assume !(0 != activate_threads_~tmp___1~0#1); 385979#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 385393#L418 assume !(1 == ~t3_pc~0); 385394#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 385909#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 385383#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 385384#L954 assume !(0 != activate_threads_~tmp___2~0#1); 386342#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 386343#L437 assume !(1 == ~t4_pc~0); 386406#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 385699#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 385566#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 385567#L962 assume !(0 != activate_threads_~tmp___3~0#1); 386045#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 386046#L456 assume !(1 == ~t5_pc~0); 385765#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 385764#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 386402#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 386401#L970 assume !(0 != activate_threads_~tmp___4~0#1); 386312#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 386313#L475 assume !(1 == ~t6_pc~0); 386261#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 386262#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 385967#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 385377#L978 assume !(0 != activate_threads_~tmp___5~0#1); 385378#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 385893#L494 assume !(1 == ~t7_pc~0); 385895#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 386271#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 386272#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 386368#L986 assume !(0 != activate_threads_~tmp___6~0#1); 386369#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 386193#L837 assume !(1 == ~M_E~0); 386194#L837-2 assume !(1 == ~T1_E~0); 385510#L842-1 assume !(1 == ~T2_E~0); 385511#L847-1 assume !(1 == ~T3_E~0); 386077#L852-1 assume !(1 == ~T4_E~0); 386397#L857-1 assume !(1 == ~T5_E~0); 385997#L862-1 assume !(1 == ~T6_E~0); 385998#L867-1 assume !(1 == ~T7_E~0); 386396#L872-1 assume !(1 == ~E_1~0); 386132#L877-1 assume !(1 == ~E_2~0); 386005#L882-1 assume !(1 == ~E_3~0); 386006#L887-1 assume !(1 == ~E_4~0); 385571#L892-1 assume !(1 == ~E_5~0); 385572#L897-1 assume !(1 == ~E_6~0); 386037#L902-1 assume !(1 == ~E_7~0); 385651#L907-1 assume { :end_inline_reset_delta_events } true; 385652#L1148-2 [2022-12-13 19:49:29,538 INFO L750 eck$LassoCheckResult]: Loop: 385652#L1148-2 assume !false; 392927#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 392925#L729 assume !false; 392922#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 392910#L569 assume !(0 == ~m_st~0); 392911#L573 assume !(0 == ~t1_st~0); 392914#L577 assume !(0 == ~t2_st~0); 392908#L581 assume !(0 == ~t3_st~0); 392909#L585 assume !(0 == ~t4_st~0); 392913#L589 assume !(0 == ~t5_st~0); 392906#L593 assume !(0 == ~t6_st~0); 392907#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 392912#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 392843#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 392844#L626 assume !(0 != eval_~tmp~0#1); 394014#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 394008#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 394002#L754-3 assume !(0 == ~M_E~0); 393996#L754-5 assume !(0 == ~T1_E~0); 393990#L759-3 assume !(0 == ~T2_E~0); 393984#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 393978#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 393971#L774-3 assume !(0 == ~T5_E~0); 393965#L779-3 assume !(0 == ~T6_E~0); 393957#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 393950#L789-3 assume !(0 == ~E_1~0); 393943#L794-3 assume !(0 == ~E_2~0); 393936#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 393928#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 393917#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 393867#L814-3 assume !(0 == ~E_6~0); 393863#L819-3 assume !(0 == ~E_7~0); 393838#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 393832#L361-24 assume !(1 == ~m_pc~0); 393825#L361-26 is_master_triggered_~__retres1~0#1 := 0; 393818#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 393811#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 393804#L930-24 assume !(0 != activate_threads_~tmp~1#1); 393797#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 393790#L380-24 assume !(1 == ~t1_pc~0); 393781#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 393774#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 393767#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 393759#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 393751#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 393744#L399-24 assume !(1 == ~t2_pc~0); 393694#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 393729#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 393532#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 393529#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 393527#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 393525#L418-24 assume !(1 == ~t3_pc~0); 393522#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 393520#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 393518#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 393515#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 393513#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 393511#L437-24 assume !(1 == ~t4_pc~0); 393509#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 393507#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 393505#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 393503#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 393501#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 393499#L456-24 assume !(1 == ~t5_pc~0); 393496#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 393494#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 393492#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 393489#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 393487#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 393485#L475-24 assume !(1 == ~t6_pc~0); 393481#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 393482#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 393479#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 393477#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 393475#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 393473#L494-24 assume !(1 == ~t7_pc~0); 393470#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 393468#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 393466#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 393463#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 393461#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 393459#L837-3 assume !(1 == ~M_E~0); 393457#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 393455#L842-3 assume !(1 == ~T2_E~0); 393453#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 393451#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 393449#L857-3 assume !(1 == ~T5_E~0); 393447#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 393445#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 393407#L872-3 assume !(1 == ~E_1~0); 393405#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 393403#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 393401#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 393398#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 393396#L897-3 assume !(1 == ~E_6~0); 393394#L902-3 assume !(1 == ~E_7~0); 393392#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 393386#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 393378#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 393376#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 393373#L1167 assume !(0 == start_simulation_~tmp~3#1); 393370#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 393361#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 393167#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 393000#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 392997#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 392995#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 392993#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 392992#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 385652#L1148-2 [2022-12-13 19:49:29,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:29,539 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 5 times [2022-12-13 19:49:29,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:29,539 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [43987403] [2022-12-13 19:49:29,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:29,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:29,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:29,549 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:29,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:29,566 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:29,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:29,566 INFO L85 PathProgramCache]: Analyzing trace with hash -1609145349, now seen corresponding path program 1 times [2022-12-13 19:49:29,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:29,566 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314351132] [2022-12-13 19:49:29,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:29,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:29,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:29,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:29,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:29,598 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1314351132] [2022-12-13 19:49:29,598 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1314351132] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:29,598 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:29,598 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:29,598 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336910520] [2022-12-13 19:49:29,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:29,599 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:49:29,599 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:29,599 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:29,599 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:29,599 INFO L87 Difference]: Start difference. First operand 16265 states and 22054 transitions. cyclomatic complexity: 5793 Second operand has 3 states, 3 states have (on average 36.333333333333336) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:29,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:29,702 INFO L93 Difference]: Finished difference Result 27243 states and 36568 transitions. [2022-12-13 19:49:29,702 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27243 states and 36568 transitions. [2022-12-13 19:49:29,797 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 27020 [2022-12-13 19:49:29,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27243 states to 27243 states and 36568 transitions. [2022-12-13 19:49:29,860 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27243 [2022-12-13 19:49:29,874 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27243 [2022-12-13 19:49:29,874 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27243 states and 36568 transitions. [2022-12-13 19:49:29,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:29,889 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27243 states and 36568 transitions. [2022-12-13 19:49:29,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27243 states and 36568 transitions. [2022-12-13 19:49:30,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27243 to 27243. [2022-12-13 19:49:30,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27243 states, 27243 states have (on average 1.3422897625078) internal successors, (36568), 27242 states have internal predecessors, (36568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:30,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27243 states to 27243 states and 36568 transitions. [2022-12-13 19:49:30,165 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27243 states and 36568 transitions. [2022-12-13 19:49:30,166 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:30,166 INFO L428 stractBuchiCegarLoop]: Abstraction has 27243 states and 36568 transitions. [2022-12-13 19:49:30,166 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 19:49:30,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27243 states and 36568 transitions. [2022-12-13 19:49:30,242 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 27020 [2022-12-13 19:49:30,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:30,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:30,243 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:30,243 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:30,244 INFO L748 eck$LassoCheckResult]: Stem: 429297#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 429298#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 429481#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 429482#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 429631#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 429563#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 429564#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 429517#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 429401#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 429402#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 429390#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 429391#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 429345#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 429346#L754 assume !(0 == ~M_E~0); 429681#L754-2 assume !(0 == ~T1_E~0); 429270#L759-1 assume !(0 == ~T2_E~0); 429271#L764-1 assume !(0 == ~T3_E~0); 429740#L769-1 assume !(0 == ~T4_E~0); 429741#L774-1 assume !(0 == ~T5_E~0); 429606#L779-1 assume !(0 == ~T6_E~0); 429311#L784-1 assume !(0 == ~T7_E~0); 429312#L789-1 assume !(0 == ~E_1~0); 428984#L794-1 assume !(0 == ~E_2~0); 428985#L799-1 assume !(0 == ~E_3~0); 429747#L804-1 assume !(0 == ~E_4~0); 429748#L809-1 assume !(0 == ~E_5~0); 429405#L814-1 assume !(0 == ~E_6~0); 428899#L819-1 assume !(0 == ~E_7~0); 428900#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 429388#L361 assume !(1 == ~m_pc~0); 429389#L361-2 is_master_triggered_~__retres1~0#1 := 0; 429445#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 429234#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 429235#L930 assume !(0 != activate_threads_~tmp~1#1); 429602#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 429380#L380 assume !(1 == ~t1_pc~0); 429040#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 429620#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 429621#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 429789#L938 assume !(0 != activate_threads_~tmp___0~0#1); 429113#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 429114#L399 assume !(1 == ~t2_pc~0); 429241#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 429242#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 429634#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 429475#L946 assume !(0 != activate_threads_~tmp___1~0#1); 429476#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 428907#L418 assume !(1 == ~t3_pc~0); 428908#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 429410#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 428897#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 428898#L954 assume !(0 != activate_threads_~tmp___2~0#1); 429765#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 429766#L437 assume !(1 == ~t4_pc~0); 429808#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 429208#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 429077#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 429078#L962 assume !(0 != activate_threads_~tmp___3~0#1); 429534#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 429535#L456 assume !(1 == ~t5_pc~0); 429269#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 429268#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 429804#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 429803#L970 assume !(0 != activate_threads_~tmp___4~0#1); 429744#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 429745#L475 assume !(1 == ~t6_pc~0); 429709#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 429710#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 429468#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 428891#L978 assume !(0 != activate_threads_~tmp___5~0#1); 428892#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 429395#L494 assume !(1 == ~t7_pc~0); 429397#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 429716#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 429717#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 429784#L986 assume !(0 != activate_threads_~tmp___6~0#1); 429785#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 429657#L837 assume !(1 == ~M_E~0); 429658#L837-2 assume !(1 == ~T1_E~0); 429022#L842-1 assume !(1 == ~T2_E~0); 429023#L847-1 assume !(1 == ~T3_E~0); 429559#L852-1 assume !(1 == ~T4_E~0); 429799#L857-1 assume !(1 == ~T5_E~0); 429491#L862-1 assume !(1 == ~T6_E~0); 429492#L867-1 assume !(1 == ~T7_E~0); 429798#L872-1 assume !(1 == ~E_1~0); 429605#L877-1 assume !(1 == ~E_2~0); 429501#L882-1 assume !(1 == ~E_3~0); 429502#L887-1 assume !(1 == ~E_4~0); 429082#L892-1 assume !(1 == ~E_5~0); 429083#L897-1 assume !(1 == ~E_6~0); 429527#L902-1 assume !(1 == ~E_7~0); 429159#L907-1 assume { :end_inline_reset_delta_events } true; 429160#L1148-2 assume !false; 433406#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 433404#L729 [2022-12-13 19:49:30,244 INFO L750 eck$LassoCheckResult]: Loop: 433404#L729 assume !false; 433402#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 433399#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 433397#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 433395#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 433393#L626 assume 0 != eval_~tmp~0#1; 433390#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 433388#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 433355#L631 assume !(0 == ~t1_st~0); 433348#L645 assume !(0 == ~t2_st~0); 433343#L659 assume !(0 == ~t3_st~0); 433566#L673 assume !(0 == ~t4_st~0); 433562#L687 assume !(0 == ~t5_st~0); 433554#L701 assume !(0 == ~t6_st~0); 433410#L715 assume !(0 == ~t7_st~0); 433404#L729 [2022-12-13 19:49:30,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:30,244 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 1 times [2022-12-13 19:49:30,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:30,244 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196877856] [2022-12-13 19:49:30,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:30,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:30,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:30,254 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:30,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:30,271 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:30,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:30,272 INFO L85 PathProgramCache]: Analyzing trace with hash -1503391009, now seen corresponding path program 1 times [2022-12-13 19:49:30,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:30,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668203937] [2022-12-13 19:49:30,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:30,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:30,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:30,275 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:30,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:30,277 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:30,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:30,278 INFO L85 PathProgramCache]: Analyzing trace with hash -1562289544, now seen corresponding path program 1 times [2022-12-13 19:49:30,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:30,278 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920582543] [2022-12-13 19:49:30,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:30,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:30,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:30,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:30,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:30,312 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1920582543] [2022-12-13 19:49:30,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1920582543] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:30,312 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:30,312 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:30,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [344225560] [2022-12-13 19:49:30,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:30,404 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:30,404 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:30,404 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:30,405 INFO L87 Difference]: Start difference. First operand 27243 states and 36568 transitions. cyclomatic complexity: 9333 Second operand has 3 states, 3 states have (on average 36.666666666666664) internal successors, (110), 3 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:30,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:30,576 INFO L93 Difference]: Finished difference Result 49528 states and 66201 transitions. [2022-12-13 19:49:30,576 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49528 states and 66201 transitions. [2022-12-13 19:49:30,778 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 49088 [2022-12-13 19:49:30,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49528 states to 49528 states and 66201 transitions. [2022-12-13 19:49:30,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49528 [2022-12-13 19:49:30,924 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49528 [2022-12-13 19:49:30,924 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49528 states and 66201 transitions. [2022-12-13 19:49:30,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:30,950 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49528 states and 66201 transitions. [2022-12-13 19:49:30,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49528 states and 66201 transitions. [2022-12-13 19:49:31,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49528 to 48104. [2022-12-13 19:49:31,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48104 states, 48104 states have (on average 1.3376226509230003) internal successors, (64345), 48103 states have internal predecessors, (64345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:31,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48104 states to 48104 states and 64345 transitions. [2022-12-13 19:49:31,453 INFO L240 hiAutomatonCegarLoop]: Abstraction has 48104 states and 64345 transitions. [2022-12-13 19:49:31,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:31,455 INFO L428 stractBuchiCegarLoop]: Abstraction has 48104 states and 64345 transitions. [2022-12-13 19:49:31,455 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-12-13 19:49:31,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48104 states and 64345 transitions. [2022-12-13 19:49:31,535 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 47664 [2022-12-13 19:49:31,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:31,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:31,536 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:31,536 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:31,536 INFO L748 eck$LassoCheckResult]: Stem: 506078#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 506079#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 506266#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 506267#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 506447#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 506370#L521-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 506371#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 523146#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 523145#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 523144#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 523143#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 523142#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 523141#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 523140#L754 assume !(0 == ~M_E~0); 523139#L754-2 assume !(0 == ~T1_E~0); 523138#L759-1 assume !(0 == ~T2_E~0); 523137#L764-1 assume !(0 == ~T3_E~0); 506579#L769-1 assume !(0 == ~T4_E~0); 506580#L774-1 assume !(0 == ~T5_E~0); 506418#L779-1 assume !(0 == ~T6_E~0); 506094#L784-1 assume !(0 == ~T7_E~0); 506095#L789-1 assume !(0 == ~E_1~0); 505763#L794-1 assume !(0 == ~E_2~0); 505764#L799-1 assume !(0 == ~E_3~0); 506588#L804-1 assume !(0 == ~E_4~0); 506589#L809-1 assume !(0 == ~E_5~0); 506187#L814-1 assume !(0 == ~E_6~0); 505678#L819-1 assume !(0 == ~E_7~0); 505679#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 523091#L361 assume !(1 == ~m_pc~0); 506225#L361-2 is_master_triggered_~__retres1~0#1 := 0; 506226#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 506017#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 506018#L930 assume !(0 != activate_threads_~tmp~1#1); 506413#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 506163#L380 assume !(1 == ~t1_pc~0); 505821#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 506638#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 505734#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 505735#L938 assume !(0 != activate_threads_~tmp___0~0#1); 506709#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 505822#L399 assume !(1 == ~t2_pc~0); 505823#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 506708#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 506271#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 506272#L946 assume !(0 != activate_threads_~tmp___1~0#1); 505716#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 505717#L418 assume !(1 == ~t3_pc~0); 505651#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 505652#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 506706#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 506654#L954 assume !(0 != activate_threads_~tmp___2~0#1); 506655#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 506505#L437 assume !(1 == ~t4_pc~0); 506375#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 506376#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 506704#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 506703#L962 assume !(0 != activate_threads_~tmp___3~0#1); 506702#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 505944#L456 assume !(1 == ~t5_pc~0); 505945#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 506490#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 506030#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 505704#L970 assume !(0 != activate_threads_~tmp___4~0#1); 505705#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 505835#L475 assume !(1 == ~t6_pc~0); 505836#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 505915#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 505916#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 506697#L978 assume !(0 != activate_threads_~tmp___5~0#1); 506594#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 506595#L494 assume !(1 == ~t7_pc~0); 506694#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 506689#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 506690#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 506639#L986 assume !(0 != activate_threads_~tmp___6~0#1); 506640#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 506472#L837 assume !(1 == ~M_E~0); 506473#L837-2 assume !(1 == ~T1_E~0); 505802#L842-1 assume !(1 == ~T2_E~0); 505803#L847-1 assume !(1 == ~T3_E~0); 506673#L852-1 assume !(1 == ~T4_E~0); 506674#L857-1 assume !(1 == ~T5_E~0); 506280#L862-1 assume !(1 == ~T6_E~0); 506281#L867-1 assume !(1 == ~T7_E~0); 506666#L872-1 assume !(1 == ~E_1~0); 506417#L877-1 assume !(1 == ~E_2~0); 506292#L882-1 assume !(1 == ~E_3~0); 506293#L887-1 assume !(1 == ~E_4~0); 505863#L892-1 assume !(1 == ~E_5~0); 505864#L897-1 assume !(1 == ~E_6~0); 506322#L902-1 assume !(1 == ~E_7~0); 506323#L907-1 assume { :end_inline_reset_delta_events } true; 523021#L1148-2 assume !false; 523010#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 523008#L729 [2022-12-13 19:49:31,536 INFO L750 eck$LassoCheckResult]: Loop: 523008#L729 assume !false; 523006#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 523003#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 523001#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 522998#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 522996#L626 assume 0 != eval_~tmp~0#1; 522993#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 522989#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 522990#L631 assume !(0 == ~t1_st~0); 524265#L645 assume !(0 == ~t2_st~0); 524258#L659 assume !(0 == ~t3_st~0); 524252#L673 assume !(0 == ~t4_st~0); 524251#L687 assume !(0 == ~t5_st~0); 524237#L701 assume !(0 == ~t6_st~0); 524238#L715 assume !(0 == ~t7_st~0); 523008#L729 [2022-12-13 19:49:31,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:31,536 INFO L85 PathProgramCache]: Analyzing trace with hash -439660602, now seen corresponding path program 1 times [2022-12-13 19:49:31,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:31,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040104942] [2022-12-13 19:49:31,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:31,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:31,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:31,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:31,555 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:31,555 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040104942] [2022-12-13 19:49:31,555 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040104942] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:31,555 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:31,555 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:31,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2054315114] [2022-12-13 19:49:31,556 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:31,556 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:49:31,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:31,556 INFO L85 PathProgramCache]: Analyzing trace with hash -1503391009, now seen corresponding path program 2 times [2022-12-13 19:49:31,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:31,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1614915561] [2022-12-13 19:49:31,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:31,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:31,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:31,559 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:31,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:31,562 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:31,643 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:31,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:31,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:31,643 INFO L87 Difference]: Start difference. First operand 48104 states and 64345 transitions. cyclomatic complexity: 16249 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:31,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:31,731 INFO L93 Difference]: Finished difference Result 47959 states and 64151 transitions. [2022-12-13 19:49:31,731 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47959 states and 64151 transitions. [2022-12-13 19:49:31,861 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 47664 [2022-12-13 19:49:31,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47959 states to 47959 states and 64151 transitions. [2022-12-13 19:49:31,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 47959 [2022-12-13 19:49:31,960 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 47959 [2022-12-13 19:49:31,960 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47959 states and 64151 transitions. [2022-12-13 19:49:31,980 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:31,980 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47959 states and 64151 transitions. [2022-12-13 19:49:32,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47959 states and 64151 transitions. [2022-12-13 19:49:32,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47959 to 47959. [2022-12-13 19:49:32,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47959 states, 47959 states have (on average 1.3376217185512624) internal successors, (64151), 47958 states have internal predecessors, (64151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:32,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47959 states to 47959 states and 64151 transitions. [2022-12-13 19:49:32,423 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47959 states and 64151 transitions. [2022-12-13 19:49:32,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:32,424 INFO L428 stractBuchiCegarLoop]: Abstraction has 47959 states and 64151 transitions. [2022-12-13 19:49:32,424 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-12-13 19:49:32,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47959 states and 64151 transitions. [2022-12-13 19:49:32,530 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 47664 [2022-12-13 19:49:32,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:32,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:32,531 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:32,531 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:32,531 INFO L748 eck$LassoCheckResult]: Stem: 602144#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 602145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 602325#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 602326#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 602501#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 602429#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 602430#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 602373#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 602248#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 602249#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 602239#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 602240#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 602195#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 602196#L754 assume !(0 == ~M_E~0); 602549#L754-2 assume !(0 == ~T1_E~0); 602118#L759-1 assume !(0 == ~T2_E~0); 602119#L764-1 assume !(0 == ~T3_E~0); 602623#L769-1 assume !(0 == ~T4_E~0); 602624#L774-1 assume !(0 == ~T5_E~0); 602474#L779-1 assume !(0 == ~T6_E~0); 602158#L784-1 assume !(0 == ~T7_E~0); 602159#L789-1 assume !(0 == ~E_1~0); 601836#L794-1 assume !(0 == ~E_2~0); 601837#L799-1 assume !(0 == ~E_3~0); 602633#L804-1 assume !(0 == ~E_4~0); 602634#L809-1 assume !(0 == ~E_5~0); 602253#L814-1 assume !(0 == ~E_6~0); 601749#L819-1 assume !(0 == ~E_7~0); 601750#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 602235#L361 assume !(1 == ~m_pc~0); 602236#L361-2 is_master_triggered_~__retres1~0#1 := 0; 602288#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 602083#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 602084#L930 assume !(0 != activate_threads_~tmp~1#1); 602471#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 602227#L380 assume !(1 == ~t1_pc~0); 601895#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 602678#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 601805#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 601806#L938 assume !(0 != activate_threads_~tmp___0~0#1); 601964#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 601965#L399 assume !(1 == ~t2_pc~0); 602089#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 602090#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 602503#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 602319#L946 assume !(0 != activate_threads_~tmp___1~0#1); 602320#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 601759#L418 assume !(1 == ~t3_pc~0); 601760#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 602258#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 601745#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 601746#L954 assume !(0 != activate_threads_~tmp___2~0#1); 602660#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 602661#L437 assume !(1 == ~t4_pc~0); 602705#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 602060#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 601931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 601932#L962 assume !(0 != activate_threads_~tmp___3~0#1); 602393#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 602394#L456 assume !(1 == ~t5_pc~0); 602116#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 602115#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 602701#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 602700#L970 assume !(0 != activate_threads_~tmp___4~0#1); 602627#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 602628#L475 assume !(1 == ~t6_pc~0); 602585#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 602586#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 602313#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 601739#L978 assume !(0 != activate_threads_~tmp___5~0#1); 601740#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 602242#L494 assume !(1 == ~t7_pc~0); 602244#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 602595#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 602596#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 602679#L986 assume !(0 != activate_threads_~tmp___6~0#1); 602680#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 602525#L837 assume !(1 == ~M_E~0); 602526#L837-2 assume !(1 == ~T1_E~0); 601871#L842-1 assume !(1 == ~T2_E~0); 601872#L847-1 assume !(1 == ~T3_E~0); 602424#L852-1 assume !(1 == ~T4_E~0); 602696#L857-1 assume !(1 == ~T5_E~0); 602340#L862-1 assume !(1 == ~T6_E~0); 602341#L867-1 assume !(1 == ~T7_E~0); 602695#L872-1 assume !(1 == ~E_1~0); 602473#L877-1 assume !(1 == ~E_2~0); 602348#L882-1 assume !(1 == ~E_3~0); 602349#L887-1 assume !(1 == ~E_4~0); 601936#L892-1 assume !(1 == ~E_5~0); 601937#L897-1 assume !(1 == ~E_6~0); 602388#L902-1 assume !(1 == ~E_7~0); 602009#L907-1 assume { :end_inline_reset_delta_events } true; 602010#L1148-2 assume !false; 630911#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 630910#L729 [2022-12-13 19:49:32,531 INFO L750 eck$LassoCheckResult]: Loop: 630910#L729 assume !false; 630909#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 630907#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 630906#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 630905#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 630904#L626 assume 0 != eval_~tmp~0#1; 630902#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 630900#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 623713#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 623709#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 623546#L645 assume !(0 == ~t2_st~0); 623542#L659 assume !(0 == ~t3_st~0); 623537#L673 assume !(0 == ~t4_st~0); 623533#L687 assume !(0 == ~t5_st~0); 623528#L701 assume !(0 == ~t6_st~0); 623526#L715 assume !(0 == ~t7_st~0); 630910#L729 [2022-12-13 19:49:32,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:32,532 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 2 times [2022-12-13 19:49:32,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:32,532 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562159994] [2022-12-13 19:49:32,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:32,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:32,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:32,539 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:32,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:32,556 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:32,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:32,557 INFO L85 PathProgramCache]: Analyzing trace with hash -1848014684, now seen corresponding path program 1 times [2022-12-13 19:49:32,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:32,557 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136120729] [2022-12-13 19:49:32,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:32,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:32,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:32,559 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:32,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:32,562 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:32,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:32,562 INFO L85 PathProgramCache]: Analyzing trace with hash 621098027, now seen corresponding path program 1 times [2022-12-13 19:49:32,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:32,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004501608] [2022-12-13 19:49:32,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:32,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:32,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:32,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:32,586 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:32,586 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1004501608] [2022-12-13 19:49:32,586 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1004501608] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:32,586 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:32,586 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:32,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [540291751] [2022-12-13 19:49:32,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:32,676 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:32,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:32,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:32,677 INFO L87 Difference]: Start difference. First operand 47959 states and 64151 transitions. cyclomatic complexity: 16200 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:32,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:32,932 INFO L93 Difference]: Finished difference Result 92159 states and 122847 transitions. [2022-12-13 19:49:32,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 92159 states and 122847 transitions. [2022-12-13 19:49:33,218 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 91720 [2022-12-13 19:49:33,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 92159 states to 92159 states and 122847 transitions. [2022-12-13 19:49:33,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 92159 [2022-12-13 19:49:33,521 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 92159 [2022-12-13 19:49:33,521 INFO L73 IsDeterministic]: Start isDeterministic. Operand 92159 states and 122847 transitions. [2022-12-13 19:49:33,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:33,552 INFO L218 hiAutomatonCegarLoop]: Abstraction has 92159 states and 122847 transitions. [2022-12-13 19:49:33,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92159 states and 122847 transitions. [2022-12-13 19:49:34,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92159 to 89727. [2022-12-13 19:49:34,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89727 states, 89727 states have (on average 1.3338125647798322) internal successors, (119679), 89726 states have internal predecessors, (119679), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:34,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89727 states to 89727 states and 119679 transitions. [2022-12-13 19:49:34,355 INFO L240 hiAutomatonCegarLoop]: Abstraction has 89727 states and 119679 transitions. [2022-12-13 19:49:34,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:34,356 INFO L428 stractBuchiCegarLoop]: Abstraction has 89727 states and 119679 transitions. [2022-12-13 19:49:34,356 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-12-13 19:49:34,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89727 states and 119679 transitions. [2022-12-13 19:49:34,587 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 89288 [2022-12-13 19:49:34,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:34,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:34,587 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:34,588 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:34,588 INFO L748 eck$LassoCheckResult]: Stem: 742270#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 742271#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 742457#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 742458#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 742644#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 742564#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 742565#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 742508#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 742379#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 742380#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 742368#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 742369#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 742323#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 742324#L754 assume !(0 == ~M_E~0); 742694#L754-2 assume !(0 == ~T1_E~0); 742245#L759-1 assume !(0 == ~T2_E~0); 742246#L764-1 assume !(0 == ~T3_E~0); 742767#L769-1 assume !(0 == ~T4_E~0); 742768#L774-1 assume !(0 == ~T5_E~0); 742611#L779-1 assume !(0 == ~T6_E~0); 742284#L784-1 assume !(0 == ~T7_E~0); 742285#L789-1 assume !(0 == ~E_1~0); 741962#L794-1 assume !(0 == ~E_2~0); 741963#L799-1 assume !(0 == ~E_3~0); 742776#L804-1 assume !(0 == ~E_4~0); 742777#L809-1 assume !(0 == ~E_5~0); 742384#L814-1 assume !(0 == ~E_6~0); 741877#L819-1 assume !(0 == ~E_7~0); 741878#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 742364#L361 assume !(1 == ~m_pc~0); 742365#L361-2 is_master_triggered_~__retres1~0#1 := 0; 742420#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 742208#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 742209#L930 assume !(0 != activate_threads_~tmp~1#1); 742608#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 742356#L380 assume !(1 == ~t1_pc~0); 742016#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 742820#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 741931#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 741932#L938 assume !(0 != activate_threads_~tmp___0~0#1); 742853#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 742017#L399 assume !(1 == ~t2_pc~0); 742018#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 742852#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 742463#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 742464#L946 assume !(0 != activate_threads_~tmp___1~0#1); 741911#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 741912#L418 assume !(1 == ~t3_pc~0); 741846#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 741847#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 742851#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 742832#L954 assume !(0 != activate_threads_~tmp___2~0#1); 742833#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 742698#L437 assume !(1 == ~t4_pc~0); 742568#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 742569#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 742849#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 742848#L962 assume !(0 != activate_threads_~tmp___3~0#1); 742847#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 742144#L456 assume !(1 == ~t5_pc~0); 742145#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 742682#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 742223#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 741902#L970 assume !(0 != activate_threads_~tmp___4~0#1); 741903#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 742034#L475 assume !(1 == ~t6_pc~0); 742035#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 742109#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 742110#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 742844#L978 assume !(0 != activate_threads_~tmp___5~0#1); 742781#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 742782#L494 assume !(1 == ~t7_pc~0); 742429#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 742430#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 742769#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 742770#L986 assume !(0 != activate_threads_~tmp___6~0#1); 742821#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 742669#L837 assume !(1 == ~M_E~0); 742670#L837-2 assume !(1 == ~T1_E~0); 741997#L842-1 assume !(1 == ~T2_E~0); 741998#L847-1 assume !(1 == ~T3_E~0); 742560#L852-1 assume !(1 == ~T4_E~0); 742840#L857-1 assume !(1 == ~T5_E~0); 742471#L862-1 assume !(1 == ~T6_E~0); 742472#L867-1 assume !(1 == ~T7_E~0); 742839#L872-1 assume !(1 == ~E_1~0); 742610#L877-1 assume !(1 == ~E_2~0); 742483#L882-1 assume !(1 == ~E_3~0); 742484#L887-1 assume !(1 == ~E_4~0); 742060#L892-1 assume !(1 == ~E_5~0); 742061#L897-1 assume !(1 == ~E_6~0); 742521#L902-1 assume !(1 == ~E_7~0); 742136#L907-1 assume { :end_inline_reset_delta_events } true; 742137#L1148-2 assume !false; 771832#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 771830#L729 [2022-12-13 19:49:34,588 INFO L750 eck$LassoCheckResult]: Loop: 771830#L729 assume !false; 771828#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 771825#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 771821#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 771819#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 771817#L626 assume 0 != eval_~tmp~0#1; 771814#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 771434#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 766926#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 763952#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 763951#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 763746#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 763950#L659 assume !(0 == ~t3_st~0); 771850#L673 assume !(0 == ~t4_st~0); 771847#L687 assume !(0 == ~t5_st~0); 771838#L701 assume !(0 == ~t6_st~0); 771836#L715 assume !(0 == ~t7_st~0); 771830#L729 [2022-12-13 19:49:34,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:34,588 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 3 times [2022-12-13 19:49:34,589 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:34,589 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990213785] [2022-12-13 19:49:34,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:34,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:34,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:34,598 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:34,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:34,615 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:34,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:34,615 INFO L85 PathProgramCache]: Analyzing trace with hash -10094934, now seen corresponding path program 1 times [2022-12-13 19:49:34,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:34,615 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988998519] [2022-12-13 19:49:34,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:34,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:34,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:34,618 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:34,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:34,621 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:34,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:34,622 INFO L85 PathProgramCache]: Analyzing trace with hash -777012221, now seen corresponding path program 1 times [2022-12-13 19:49:34,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:34,622 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088432424] [2022-12-13 19:49:34,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:34,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:34,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:34,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:34,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:34,654 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088432424] [2022-12-13 19:49:34,654 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2088432424] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:34,654 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:34,654 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:34,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [307613008] [2022-12-13 19:49:34,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:34,752 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:34,752 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:34,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:34,753 INFO L87 Difference]: Start difference. First operand 89727 states and 119679 transitions. cyclomatic complexity: 29960 Second operand has 3 states, 3 states have (on average 37.333333333333336) internal successors, (112), 3 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:35,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:35,215 INFO L93 Difference]: Finished difference Result 168623 states and 224463 transitions. [2022-12-13 19:49:35,215 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 168623 states and 224463 transitions. [2022-12-13 19:49:35,920 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 167896 [2022-12-13 19:49:36,145 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 168623 states to 168623 states and 224463 transitions. [2022-12-13 19:49:36,145 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 168623 [2022-12-13 19:49:36,197 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 168623 [2022-12-13 19:49:36,197 INFO L73 IsDeterministic]: Start isDeterministic. Operand 168623 states and 224463 transitions. [2022-12-13 19:49:36,250 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:36,250 INFO L218 hiAutomatonCegarLoop]: Abstraction has 168623 states and 224463 transitions. [2022-12-13 19:49:36,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168623 states and 224463 transitions. [2022-12-13 19:49:37,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168623 to 160687. [2022-12-13 19:49:37,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 160687 states, 160687 states have (on average 1.3339660333443277) internal successors, (214351), 160686 states have internal predecessors, (214351), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:37,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160687 states to 160687 states and 214351 transitions. [2022-12-13 19:49:37,711 INFO L240 hiAutomatonCegarLoop]: Abstraction has 160687 states and 214351 transitions. [2022-12-13 19:49:37,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:37,712 INFO L428 stractBuchiCegarLoop]: Abstraction has 160687 states and 214351 transitions. [2022-12-13 19:49:37,712 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-12-13 19:49:37,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 160687 states and 214351 transitions. [2022-12-13 19:49:38,012 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 159960 [2022-12-13 19:49:38,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:38,012 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:38,013 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:38,013 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:38,013 INFO L748 eck$LassoCheckResult]: Stem: 1000638#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1000639#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1000831#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1000832#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1001017#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1000930#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1000931#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1000875#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1000749#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1000750#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1000737#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1000738#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1000691#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1000692#L754 assume !(0 == ~M_E~0); 1001085#L754-2 assume !(0 == ~T1_E~0); 1000609#L759-1 assume !(0 == ~T2_E~0); 1000610#L764-1 assume !(0 == ~T3_E~0); 1001173#L769-1 assume !(0 == ~T4_E~0); 1001174#L774-1 assume !(0 == ~T5_E~0); 1000987#L779-1 assume !(0 == ~T6_E~0); 1000651#L784-1 assume !(0 == ~T7_E~0); 1000652#L789-1 assume !(0 == ~E_1~0); 1000316#L794-1 assume !(0 == ~E_2~0); 1000317#L799-1 assume !(0 == ~E_3~0); 1001185#L804-1 assume !(0 == ~E_4~0); 1001186#L809-1 assume !(0 == ~E_5~0); 1000753#L814-1 assume !(0 == ~E_6~0); 1000231#L819-1 assume !(0 == ~E_7~0); 1000232#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1000735#L361 assume !(1 == ~m_pc~0); 1000736#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1000793#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1000572#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1000573#L930 assume !(0 != activate_threads_~tmp~1#1); 1000979#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1000726#L380 assume !(1 == ~t1_pc~0); 1000373#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1001002#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1001003#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1001240#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1000447#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1000448#L399 assume !(1 == ~t2_pc~0); 1000578#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1000579#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1001021#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1000825#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1000826#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1000239#L418 assume !(1 == ~t3_pc~0); 1000240#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1000759#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1000229#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1000230#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1001215#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1001216#L437 assume !(1 == ~t4_pc~0); 1001261#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1000548#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1000410#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1000411#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1000895#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1000896#L456 assume !(1 == ~t5_pc~0); 1000608#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1000607#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1001257#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1001256#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1001181#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1001182#L475 assume !(1 == ~t6_pc~0); 1001133#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1001134#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1000818#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1000223#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1000224#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1000742#L494 assume !(1 == ~t7_pc~0); 1000744#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1001144#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1001145#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1001236#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1001237#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1001048#L837 assume !(1 == ~M_E~0); 1001049#L837-2 assume !(1 == ~T1_E~0); 1000355#L842-1 assume !(1 == ~T2_E~0); 1000356#L847-1 assume !(1 == ~T3_E~0); 1000925#L852-1 assume !(1 == ~T4_E~0); 1001252#L857-1 assume !(1 == ~T5_E~0); 1000845#L862-1 assume !(1 == ~T6_E~0); 1000846#L867-1 assume !(1 == ~T7_E~0); 1001251#L872-1 assume !(1 == ~E_1~0); 1000986#L877-1 assume !(1 == ~E_2~0); 1000856#L882-1 assume !(1 == ~E_3~0); 1000857#L887-1 assume !(1 == ~E_4~0); 1000415#L892-1 assume !(1 == ~E_5~0); 1000416#L897-1 assume !(1 == ~E_6~0); 1000885#L902-1 assume !(1 == ~E_7~0); 1000496#L907-1 assume { :end_inline_reset_delta_events } true; 1000497#L1148-2 assume !false; 1046865#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1046866#L729 [2022-12-13 19:49:38,013 INFO L750 eck$LassoCheckResult]: Loop: 1046866#L729 assume !false; 1047053#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1047051#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1047050#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1047049#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1047048#L626 assume 0 != eval_~tmp~0#1; 1047046#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1047047#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1046775#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1046773#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1046772#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1018885#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 1021208#L659 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1021206#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 1021205#L673 assume !(0 == ~t4_st~0); 1021202#L687 assume !(0 == ~t5_st~0); 1021016#L701 assume !(0 == ~t6_st~0); 1021015#L715 assume !(0 == ~t7_st~0); 1046866#L729 [2022-12-13 19:49:38,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:38,013 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 4 times [2022-12-13 19:49:38,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:38,014 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [972503141] [2022-12-13 19:49:38,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:38,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:38,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:38,020 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:38,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:38,038 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:38,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:38,039 INFO L85 PathProgramCache]: Analyzing trace with hash 1673301209, now seen corresponding path program 1 times [2022-12-13 19:49:38,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:38,039 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [714176959] [2022-12-13 19:49:38,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:38,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:38,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:38,042 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:38,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:38,045 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:38,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:38,046 INFO L85 PathProgramCache]: Analyzing trace with hash -626298208, now seen corresponding path program 1 times [2022-12-13 19:49:38,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:38,046 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845646050] [2022-12-13 19:49:38,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:38,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:38,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:38,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:38,081 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:38,081 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1845646050] [2022-12-13 19:49:38,081 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1845646050] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:38,081 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:38,081 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:38,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [171044715] [2022-12-13 19:49:38,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:38,190 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:38,191 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:38,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:38,191 INFO L87 Difference]: Start difference. First operand 160687 states and 214351 transitions. cyclomatic complexity: 53672 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:38,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:38,843 INFO L93 Difference]: Finished difference Result 205811 states and 274019 transitions. [2022-12-13 19:49:38,843 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 205811 states and 274019 transitions. [2022-12-13 19:49:39,719 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 203196 [2022-12-13 19:49:40,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 205811 states to 205811 states and 274019 transitions. [2022-12-13 19:49:40,282 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 205811 [2022-12-13 19:49:40,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 205811 [2022-12-13 19:49:40,370 INFO L73 IsDeterministic]: Start isDeterministic. Operand 205811 states and 274019 transitions. [2022-12-13 19:49:40,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:40,444 INFO L218 hiAutomatonCegarLoop]: Abstraction has 205811 states and 274019 transitions. [2022-12-13 19:49:40,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205811 states and 274019 transitions. [2022-12-13 19:49:41,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205811 to 199539. [2022-12-13 19:49:42,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 199539 states, 199539 states have (on average 1.3334886914337547) internal successors, (266083), 199538 states have internal predecessors, (266083), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:42,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199539 states to 199539 states and 266083 transitions. [2022-12-13 19:49:42,332 INFO L240 hiAutomatonCegarLoop]: Abstraction has 199539 states and 266083 transitions. [2022-12-13 19:49:42,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:42,333 INFO L428 stractBuchiCegarLoop]: Abstraction has 199539 states and 266083 transitions. [2022-12-13 19:49:42,333 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-12-13 19:49:42,333 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 199539 states and 266083 transitions. [2022-12-13 19:49:43,066 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 196924 [2022-12-13 19:49:43,067 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:43,067 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:43,068 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:43,068 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:43,068 INFO L748 eck$LassoCheckResult]: Stem: 1367147#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1367148#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1367345#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1367346#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1367531#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1367443#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1367444#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1367391#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1367263#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1367264#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1367252#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1367253#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1367202#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1367203#L754 assume !(0 == ~M_E~0); 1367599#L754-2 assume !(0 == ~T1_E~0); 1367118#L759-1 assume !(0 == ~T2_E~0); 1367119#L764-1 assume !(0 == ~T3_E~0); 1367697#L769-1 assume !(0 == ~T4_E~0); 1367698#L774-1 assume !(0 == ~T5_E~0); 1367497#L779-1 assume !(0 == ~T6_E~0); 1367163#L784-1 assume !(0 == ~T7_E~0); 1367164#L789-1 assume !(0 == ~E_1~0); 1366823#L794-1 assume !(0 == ~E_2~0); 1366824#L799-1 assume !(0 == ~E_3~0); 1367710#L804-1 assume !(0 == ~E_4~0); 1367711#L809-1 assume !(0 == ~E_5~0); 1367267#L814-1 assume !(0 == ~E_6~0); 1366738#L819-1 assume !(0 == ~E_7~0); 1366739#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1367250#L361 assume !(1 == ~m_pc~0); 1367251#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1367306#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1367082#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1367083#L930 assume !(0 != activate_threads_~tmp~1#1); 1367491#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1367242#L380 assume !(1 == ~t1_pc~0); 1366885#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1367517#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1367518#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1367764#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1366958#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1366959#L399 assume !(1 == ~t2_pc~0); 1367088#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1367089#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1367533#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1367338#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1367339#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1366746#L418 assume !(1 == ~t3_pc~0); 1366747#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1367272#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1366736#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1366737#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1367735#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1367736#L437 assume !(1 == ~t4_pc~0); 1367787#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1367055#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1366922#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1366923#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1367410#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1367411#L456 assume !(1 == ~t5_pc~0); 1367117#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1367116#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1367783#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1367782#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1367705#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1367706#L475 assume !(1 == ~t6_pc~0); 1367648#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1367649#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1367331#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1366729#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1366730#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1367257#L494 assume !(1 == ~t7_pc~0); 1367259#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1367662#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1367663#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1367758#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1367759#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1367561#L837 assume !(1 == ~M_E~0); 1367562#L837-2 assume !(1 == ~T1_E~0); 1366864#L842-1 assume !(1 == ~T2_E~0); 1366865#L847-1 assume !(1 == ~T3_E~0); 1367439#L852-1 assume !(1 == ~T4_E~0); 1367778#L857-1 assume !(1 == ~T5_E~0); 1367361#L862-1 assume !(1 == ~T6_E~0); 1367362#L867-1 assume !(1 == ~T7_E~0); 1367777#L872-1 assume !(1 == ~E_1~0); 1367496#L877-1 assume !(1 == ~E_2~0); 1367370#L882-1 assume !(1 == ~E_3~0); 1367371#L887-1 assume !(1 == ~E_4~0); 1366927#L892-1 assume !(1 == ~E_5~0); 1366928#L897-1 assume !(1 == ~E_6~0); 1367401#L902-1 assume !(1 == ~E_7~0); 1367005#L907-1 assume { :end_inline_reset_delta_events } true; 1367006#L1148-2 assume !false; 1430052#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1430049#L729 [2022-12-13 19:49:43,069 INFO L750 eck$LassoCheckResult]: Loop: 1430049#L729 assume !false; 1430045#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1430002#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1429985#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1429986#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1429959#L626 assume 0 != eval_~tmp~0#1; 1429960#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1433445#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1382916#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1382917#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1382468#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1382424#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 1382425#L659 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1412970#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 1413002#L673 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1414367#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 1414369#L687 assume !(0 == ~t5_st~0); 1430115#L701 assume !(0 == ~t6_st~0); 1430056#L715 assume !(0 == ~t7_st~0); 1430049#L729 [2022-12-13 19:49:43,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:43,069 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 5 times [2022-12-13 19:49:43,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:43,069 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614281225] [2022-12-13 19:49:43,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:43,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:43,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:43,083 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:43,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:43,107 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:43,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:43,107 INFO L85 PathProgramCache]: Analyzing trace with hash 119715445, now seen corresponding path program 1 times [2022-12-13 19:49:43,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:43,108 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842616619] [2022-12-13 19:49:43,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:43,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:43,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:43,112 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:43,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:43,116 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:43,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:43,116 INFO L85 PathProgramCache]: Analyzing trace with hash 1846577550, now seen corresponding path program 1 times [2022-12-13 19:49:43,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:43,117 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176997296] [2022-12-13 19:49:43,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:43,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:43,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:43,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:43,149 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:43,149 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [176997296] [2022-12-13 19:49:43,149 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [176997296] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:43,149 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:43,149 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:43,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1604382799] [2022-12-13 19:49:43,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:43,279 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:43,280 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:43,280 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:43,280 INFO L87 Difference]: Start difference. First operand 199539 states and 266083 transitions. cyclomatic complexity: 66554 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:44,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:44,205 INFO L93 Difference]: Finished difference Result 363283 states and 483083 transitions. [2022-12-13 19:49:44,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 363283 states and 483083 transitions. [2022-12-13 19:49:45,507 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 358204 [2022-12-13 19:49:46,023 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 363283 states to 363283 states and 483083 transitions. [2022-12-13 19:49:46,023 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 363283 [2022-12-13 19:49:46,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 363283 [2022-12-13 19:49:46,144 INFO L73 IsDeterministic]: Start isDeterministic. Operand 363283 states and 483083 transitions. [2022-12-13 19:49:46,390 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:46,390 INFO L218 hiAutomatonCegarLoop]: Abstraction has 363283 states and 483083 transitions. [2022-12-13 19:49:46,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 363283 states and 483083 transitions. [2022-12-13 19:49:48,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 363283 to 350963. [2022-12-13 19:49:49,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 350963 states, 350963 states have (on average 1.333322885888256) internal successors, (467947), 350962 states have internal predecessors, (467947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:49,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 350963 states to 350963 states and 467947 transitions. [2022-12-13 19:49:49,534 INFO L240 hiAutomatonCegarLoop]: Abstraction has 350963 states and 467947 transitions. [2022-12-13 19:49:49,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:49:49,535 INFO L428 stractBuchiCegarLoop]: Abstraction has 350963 states and 467947 transitions. [2022-12-13 19:49:49,535 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-12-13 19:49:49,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 350963 states and 467947 transitions. [2022-12-13 19:49:50,394 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 345884 [2022-12-13 19:49:50,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:49:50,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:49:50,395 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:50,395 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:49:50,395 INFO L748 eck$LassoCheckResult]: Stem: 1929976#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1929977#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1930170#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1930171#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1930361#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1930275#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1930276#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1930219#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1930091#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1930092#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1930079#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1930080#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1930029#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1930030#L754 assume !(0 == ~M_E~0); 1930423#L754-2 assume !(0 == ~T1_E~0); 1929951#L759-1 assume !(0 == ~T2_E~0); 1929952#L764-1 assume !(0 == ~T3_E~0); 1930502#L769-1 assume !(0 == ~T4_E~0); 1930503#L774-1 assume !(0 == ~T5_E~0); 1930330#L779-1 assume !(0 == ~T6_E~0); 1929989#L784-1 assume !(0 == ~T7_E~0); 1929990#L789-1 assume !(0 == ~E_1~0); 1929656#L794-1 assume !(0 == ~E_2~0); 1929657#L799-1 assume !(0 == ~E_3~0); 1930514#L804-1 assume !(0 == ~E_4~0); 1930515#L809-1 assume !(0 == ~E_5~0); 1930096#L814-1 assume !(0 == ~E_6~0); 1929571#L819-1 assume !(0 == ~E_7~0); 1929572#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1930075#L361 assume !(1 == ~m_pc~0); 1930076#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1930133#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1929911#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1929912#L930 assume !(0 != activate_threads_~tmp~1#1); 1930324#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1930068#L380 assume !(1 == ~t1_pc~0); 1929709#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1930561#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1929625#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1929626#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1930591#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1929710#L399 assume !(1 == ~t2_pc~0); 1929711#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1930590#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1930176#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1930177#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1929605#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1929606#L418 assume !(1 == ~t3_pc~0); 1929540#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1929541#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1930589#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1930570#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1930571#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1930427#L437 assume !(1 == ~t4_pc~0); 1930279#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1930280#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1930587#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1930586#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1930585#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1929839#L456 assume !(1 == ~t5_pc~0); 1929840#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1930408#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1929925#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1929596#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1929597#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1929727#L475 assume !(1 == ~t6_pc~0); 1929728#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1929802#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1929803#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1930582#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1930524#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1930525#L494 assume !(1 == ~t7_pc~0); 1930141#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1930142#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1930504#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1930505#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1930564#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1930389#L837 assume !(1 == ~M_E~0); 1930390#L837-2 assume !(1 == ~T1_E~0); 1929690#L842-1 assume !(1 == ~T2_E~0); 1929691#L847-1 assume !(1 == ~T3_E~0); 1930271#L852-1 assume !(1 == ~T4_E~0); 1930578#L857-1 assume !(1 == ~T5_E~0); 1930185#L862-1 assume !(1 == ~T6_E~0); 1930186#L867-1 assume !(1 == ~T7_E~0); 1930577#L872-1 assume !(1 == ~E_1~0); 1930329#L877-1 assume !(1 == ~E_2~0); 1930197#L882-1 assume !(1 == ~E_3~0); 1930198#L887-1 assume !(1 == ~E_4~0); 1929752#L892-1 assume !(1 == ~E_5~0); 1929753#L897-1 assume !(1 == ~E_6~0); 1930229#L902-1 assume !(1 == ~E_7~0); 1929830#L907-1 assume { :end_inline_reset_delta_events } true; 1929831#L1148-2 assume !false; 2102742#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2102743#L729 [2022-12-13 19:49:50,395 INFO L750 eck$LassoCheckResult]: Loop: 2102743#L729 assume !false; 2162094#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2162092#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2162091#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2162090#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2162089#L626 assume 0 != eval_~tmp~0#1; 2162087#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 2162086#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1960751#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1960718#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1941986#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1941692#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 1941693#L659 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2033111#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 2033108#L673 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 2033103#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 2033100#L687 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 2033061#L704 assume !(0 != eval_~tmp_ndt_6~0#1); 2033097#L701 assume !(0 == ~t6_st~0); 2072402#L715 assume !(0 == ~t7_st~0); 2102743#L729 [2022-12-13 19:49:50,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:50,395 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 6 times [2022-12-13 19:49:50,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:50,395 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [917344883] [2022-12-13 19:49:50,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:50,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:50,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:50,401 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:50,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:50,413 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:50,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:50,414 INFO L85 PathProgramCache]: Analyzing trace with hash -590652146, now seen corresponding path program 1 times [2022-12-13 19:49:50,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:50,414 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394220086] [2022-12-13 19:49:50,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:50,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:50,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:50,416 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:49:50,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:49:50,418 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:49:50,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:49:50,419 INFO L85 PathProgramCache]: Analyzing trace with hash 1402465557, now seen corresponding path program 1 times [2022-12-13 19:49:50,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:49:50,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726862766] [2022-12-13 19:49:50,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:49:50,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:49:50,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:49:50,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:49:50,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:49:50,440 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [726862766] [2022-12-13 19:49:50,440 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [726862766] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:49:50,440 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:49:50,441 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:49:50,441 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2002358751] [2022-12-13 19:49:50,441 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:49:50,605 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:49:50,606 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:49:50,606 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:49:50,606 INFO L87 Difference]: Start difference. First operand 350963 states and 467947 transitions. cyclomatic complexity: 116994 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:49:52,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:49:52,502 INFO L93 Difference]: Finished difference Result 656627 states and 873243 transitions. [2022-12-13 19:49:52,502 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 656627 states and 873243 transitions. [2022-12-13 19:49:54,870 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 646620 [2022-12-13 19:49:56,250 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 656627 states to 656627 states and 873243 transitions. [2022-12-13 19:49:56,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 656627 [2022-12-13 19:49:56,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 656627 [2022-12-13 19:49:56,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 656627 states and 873243 transitions. [2022-12-13 19:49:56,920 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:49:56,921 INFO L218 hiAutomatonCegarLoop]: Abstraction has 656627 states and 873243 transitions. [2022-12-13 19:49:57,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 656627 states and 873243 transitions. [2022-12-13 19:50:01,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 656627 to 648883. [2022-12-13 19:50:01,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 648883 states, 648883 states have (on average 1.3305742329510868) internal successors, (863387), 648882 states have internal predecessors, (863387), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:50:03,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 648883 states to 648883 states and 863387 transitions. [2022-12-13 19:50:03,266 INFO L240 hiAutomatonCegarLoop]: Abstraction has 648883 states and 863387 transitions. [2022-12-13 19:50:03,266 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:50:03,267 INFO L428 stractBuchiCegarLoop]: Abstraction has 648883 states and 863387 transitions. [2022-12-13 19:50:03,267 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2022-12-13 19:50:03,267 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 648883 states and 863387 transitions. [2022-12-13 19:50:04,776 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 638876 [2022-12-13 19:50:04,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:50:04,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:50:04,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:50:04,777 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:50:04,777 INFO L748 eck$LassoCheckResult]: Stem: 2937581#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 2937582#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2937775#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2937776#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2937962#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 2937876#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2937877#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2937826#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2937692#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2937693#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2937680#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2937681#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2937633#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2937634#L754 assume !(0 == ~M_E~0); 2938038#L754-2 assume !(0 == ~T1_E~0); 2937552#L759-1 assume !(0 == ~T2_E~0); 2937553#L764-1 assume !(0 == ~T3_E~0); 2938121#L769-1 assume !(0 == ~T4_E~0); 2938122#L774-1 assume !(0 == ~T5_E~0); 2937930#L779-1 assume !(0 == ~T6_E~0); 2937593#L784-1 assume !(0 == ~T7_E~0); 2937594#L789-1 assume !(0 == ~E_1~0); 2937251#L794-1 assume !(0 == ~E_2~0); 2937252#L799-1 assume !(0 == ~E_3~0); 2938139#L804-1 assume !(0 == ~E_4~0); 2938140#L809-1 assume !(0 == ~E_5~0); 2937696#L814-1 assume !(0 == ~E_6~0); 2937166#L819-1 assume !(0 == ~E_7~0); 2937167#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2937678#L361 assume !(1 == ~m_pc~0); 2937679#L361-2 is_master_triggered_~__retres1~0#1 := 0; 2937735#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2937516#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2937517#L930 assume !(0 != activate_threads_~tmp~1#1); 2937924#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2937671#L380 assume !(1 == ~t1_pc~0); 2937312#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2937949#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2937950#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2938193#L938 assume !(0 != activate_threads_~tmp___0~0#1); 2937384#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2937385#L399 assume !(1 == ~t2_pc~0); 2937522#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2937523#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2937967#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2937767#L946 assume !(0 != activate_threads_~tmp___1~0#1); 2937768#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2937174#L418 assume !(1 == ~t3_pc~0); 2937175#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2937702#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2937164#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2937165#L954 assume !(0 != activate_threads_~tmp___2~0#1); 2938165#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2938166#L437 assume !(1 == ~t4_pc~0); 2938220#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2937489#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2937347#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2937348#L962 assume !(0 != activate_threads_~tmp___3~0#1); 2937846#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2937847#L456 assume !(1 == ~t5_pc~0); 2937551#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2937550#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2938216#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2938215#L970 assume !(0 != activate_threads_~tmp___4~0#1); 2938132#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2938133#L475 assume !(1 == ~t6_pc~0); 2938075#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2938076#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2937760#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2937157#L978 assume !(0 != activate_threads_~tmp___5~0#1); 2937158#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2937686#L494 assume !(1 == ~t7_pc~0); 2937688#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2938084#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2938085#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2938189#L986 assume !(0 != activate_threads_~tmp___6~0#1); 2938190#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2937998#L837 assume !(1 == ~M_E~0); 2937999#L837-2 assume !(1 == ~T1_E~0); 2937289#L842-1 assume !(1 == ~T2_E~0); 2937290#L847-1 assume !(1 == ~T3_E~0); 2937872#L852-1 assume !(1 == ~T4_E~0); 2938211#L857-1 assume !(1 == ~T5_E~0); 2937791#L862-1 assume !(1 == ~T6_E~0); 2937792#L867-1 assume !(1 == ~T7_E~0); 2938210#L872-1 assume !(1 == ~E_1~0); 2937929#L877-1 assume !(1 == ~E_2~0); 2937800#L882-1 assume !(1 == ~E_3~0); 2937801#L887-1 assume !(1 == ~E_4~0); 2937352#L892-1 assume !(1 == ~E_5~0); 2937353#L897-1 assume !(1 == ~E_6~0); 2937837#L902-1 assume !(1 == ~E_7~0); 2937435#L907-1 assume { :end_inline_reset_delta_events } true; 2937436#L1148-2 assume !false; 3222571#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3222569#L729 [2022-12-13 19:50:04,777 INFO L750 eck$LassoCheckResult]: Loop: 3222569#L729 assume !false; 3222567#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3222564#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3222562#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3222560#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3222557#L626 assume 0 != eval_~tmp~0#1; 3222554#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 3222551#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 3222547#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 3222533#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 3222545#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 3198483#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 3202271#L659 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 3222122#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 3201511#L673 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 3201508#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 3201505#L687 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 3201502#L704 assume !(0 != eval_~tmp_ndt_6~0#1); 3201500#L701 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 3141708#L718 assume !(0 != eval_~tmp_ndt_7~0#1); 3198970#L715 assume !(0 == ~t7_st~0); 3222569#L729 [2022-12-13 19:50:04,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:50:04,778 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 7 times [2022-12-13 19:50:04,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:50:04,778 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179191703] [2022-12-13 19:50:04,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:50:04,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:50:04,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:50:04,784 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:50:04,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:50:04,798 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:50:04,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:50:04,799 INFO L85 PathProgramCache]: Analyzing trace with hash -1130560960, now seen corresponding path program 1 times [2022-12-13 19:50:04,799 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:50:04,799 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219144642] [2022-12-13 19:50:04,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:50:04,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:50:04,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:50:04,802 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:50:04,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:50:04,804 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:50:04,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:50:04,805 INFO L85 PathProgramCache]: Analyzing trace with hash 526545689, now seen corresponding path program 1 times [2022-12-13 19:50:04,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:50:04,805 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133847637] [2022-12-13 19:50:04,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:50:04,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:50:04,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:50:04,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:50:04,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:50:04,828 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133847637] [2022-12-13 19:50:04,828 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133847637] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:50:04,828 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:50:04,828 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:50:04,828 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [359454069] [2022-12-13 19:50:04,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:50:04,983 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:50:04,983 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:50:04,983 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:50:04,983 INFO L87 Difference]: Start difference. First operand 648883 states and 863387 transitions. cyclomatic complexity: 214514 Second operand has 3 states, 2 states have (on average 58.0) internal successors, (116), 3 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:50:08,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:50:08,446 INFO L93 Difference]: Finished difference Result 1269731 states and 1686859 transitions. [2022-12-13 19:50:08,446 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1269731 states and 1686859 transitions. [2022-12-13 19:50:13,590 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 1249868 [2022-12-13 19:50:15,964 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1269731 states to 1269731 states and 1686859 transitions. [2022-12-13 19:50:15,964 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1269731 [2022-12-13 19:50:16,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1269731 [2022-12-13 19:50:16,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1269731 states and 1686859 transitions. [2022-12-13 19:50:16,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:50:16,876 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1269731 states and 1686859 transitions. [2022-12-13 19:50:17,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1269731 states and 1686859 transitions. [2022-12-13 19:50:26,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1269731 to 1269731. [2022-12-13 19:50:26,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1269731 states, 1269731 states have (on average 1.328516827580015) internal successors, (1686859), 1269730 states have internal predecessors, (1686859), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:50:29,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1269731 states to 1269731 states and 1686859 transitions. [2022-12-13 19:50:29,880 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1269731 states and 1686859 transitions. [2022-12-13 19:50:29,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:50:29,880 INFO L428 stractBuchiCegarLoop]: Abstraction has 1269731 states and 1686859 transitions. [2022-12-13 19:50:29,881 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2022-12-13 19:50:29,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1269731 states and 1686859 transitions. [2022-12-13 19:50:33,160 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 1249868 [2022-12-13 19:50:33,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:50:33,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:50:33,161 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:50:33,161 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:50:33,161 INFO L748 eck$LassoCheckResult]: Stem: 4856195#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 4856196#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4856388#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4856389#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4856566#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 4856491#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4856492#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4856437#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4856305#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4856306#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4856292#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4856293#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4856247#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4856248#L754 assume !(0 == ~M_E~0); 4856622#L754-2 assume !(0 == ~T1_E~0); 4856172#L759-1 assume !(0 == ~T2_E~0); 4856173#L764-1 assume !(0 == ~T3_E~0); 4856695#L769-1 assume !(0 == ~T4_E~0); 4856696#L774-1 assume !(0 == ~T5_E~0); 4856534#L779-1 assume !(0 == ~T6_E~0); 4856208#L784-1 assume !(0 == ~T7_E~0); 4856209#L789-1 assume !(0 == ~E_1~0); 4855877#L794-1 assume !(0 == ~E_2~0); 4855878#L799-1 assume !(0 == ~E_3~0); 4856709#L804-1 assume !(0 == ~E_4~0); 4856710#L809-1 assume !(0 == ~E_5~0); 4856309#L814-1 assume !(0 == ~E_6~0); 4855792#L819-1 assume !(0 == ~E_7~0); 4855793#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4856288#L361 assume !(1 == ~m_pc~0); 4856289#L361-2 is_master_triggered_~__retres1~0#1 := 0; 4856346#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4856134#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4856135#L930 assume !(0 != activate_threads_~tmp~1#1); 4856530#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4856280#L380 assume !(1 == ~t1_pc~0); 4855931#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4856754#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4855846#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4855847#L938 assume !(0 != activate_threads_~tmp___0~0#1); 4856790#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4855927#L399 assume !(1 == ~t2_pc~0); 4855928#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4856789#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4856396#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4856397#L946 assume !(0 != activate_threads_~tmp___1~0#1); 4855826#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4855827#L418 assume !(1 == ~t3_pc~0); 4855760#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4855761#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4856788#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4856768#L954 assume !(0 != activate_threads_~tmp___2~0#1); 4856769#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4856627#L437 assume !(1 == ~t4_pc~0); 4856495#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4856496#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4856786#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4856785#L962 assume !(0 != activate_threads_~tmp___3~0#1); 4856784#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4856061#L456 assume !(1 == ~t5_pc~0); 4856062#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4856608#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4856147#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4855817#L970 assume !(0 != activate_threads_~tmp___4~0#1); 4855818#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4855947#L475 assume !(1 == ~t6_pc~0); 4855948#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4856024#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4856025#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4856781#L978 assume !(0 != activate_threads_~tmp___5~0#1); 4856719#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4856720#L494 assume !(1 == ~t7_pc~0); 4856355#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4856356#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4856697#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4856698#L986 assume !(0 != activate_threads_~tmp___6~0#1); 4856757#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4856593#L837 assume !(1 == ~M_E~0); 4856594#L837-2 assume !(1 == ~T1_E~0); 4855911#L842-1 assume !(1 == ~T2_E~0); 4855912#L847-1 assume !(1 == ~T3_E~0); 4856486#L852-1 assume !(1 == ~T4_E~0); 4856777#L857-1 assume !(1 == ~T5_E~0); 4856406#L862-1 assume !(1 == ~T6_E~0); 4856407#L867-1 assume !(1 == ~T7_E~0); 4856776#L872-1 assume !(1 == ~E_1~0); 4856533#L877-1 assume !(1 == ~E_2~0); 4856415#L882-1 assume !(1 == ~E_3~0); 4856416#L887-1 assume !(1 == ~E_4~0); 4855973#L892-1 assume !(1 == ~E_5~0); 4855974#L897-1 assume !(1 == ~E_6~0); 4856448#L902-1 assume !(1 == ~E_7~0); 4856052#L907-1 assume { :end_inline_reset_delta_events } true; 4856053#L1148-2 assume !false; 5698155#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5486710#L729 [2022-12-13 19:50:33,161 INFO L750 eck$LassoCheckResult]: Loop: 5486710#L729 assume !false; 5698152#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5698150#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5698148#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5698146#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5698144#L626 assume 0 != eval_~tmp~0#1; 5698142#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 5698139#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 5226430#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 5226426#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 5226384#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5226381#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 5226382#L659 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 5262313#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 5302244#L673 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 5302241#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 5302238#L687 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 5302224#L704 assume !(0 != eval_~tmp_ndt_6~0#1); 5302236#L701 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 5205768#L718 assume !(0 != eval_~tmp_ndt_7~0#1); 5486713#L715 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0#1;eval_~tmp_ndt_8~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 5486703#L732 assume !(0 != eval_~tmp_ndt_8~0#1); 5486710#L729 [2022-12-13 19:50:33,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:50:33,162 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 8 times [2022-12-13 19:50:33,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:50:33,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1656566945] [2022-12-13 19:50:33,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:50:33,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:50:33,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:50:33,168 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:50:33,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:50:33,185 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:50:33,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:50:33,186 INFO L85 PathProgramCache]: Analyzing trace with hash -687650493, now seen corresponding path program 1 times [2022-12-13 19:50:33,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:50:33,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945573821] [2022-12-13 19:50:33,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:50:33,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:50:33,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:50:33,189 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:50:33,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:50:33,191 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:50:33,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:50:33,192 INFO L85 PathProgramCache]: Analyzing trace with hash -856951926, now seen corresponding path program 1 times [2022-12-13 19:50:33,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:50:33,192 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109788358] [2022-12-13 19:50:33,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:50:33,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:50:33,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:50:33,198 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:50:33,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:50:33,213 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:50:34,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:50:34,826 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:50:34,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:50:34,975 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 07:50:34 BoogieIcfgContainer [2022-12-13 19:50:34,975 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 19:50:34,975 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 19:50:34,976 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 19:50:34,976 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 19:50:34,976 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:49:21" (3/4) ... [2022-12-13 19:50:34,978 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 19:50:35,031 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 19:50:35,032 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 19:50:35,032 INFO L158 Benchmark]: Toolchain (without parser) took 75225.04ms. Allocated memory was 130.0MB in the beginning and 14.6GB in the end (delta: 14.4GB). Free memory was 95.6MB in the beginning and 1.6GB in the end (delta: -1.5GB). Peak memory consumption was 12.9GB. Max. memory is 16.1GB. [2022-12-13 19:50:35,032 INFO L158 Benchmark]: CDTParser took 0.13ms. Allocated memory is still 130.0MB. Free memory was 91.4MB in the beginning and 91.4MB in the end (delta: 27.0kB). There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 19:50:35,032 INFO L158 Benchmark]: CACSL2BoogieTranslator took 282.56ms. Allocated memory is still 130.0MB. Free memory was 95.0MB in the beginning and 77.3MB in the end (delta: 17.7MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2022-12-13 19:50:35,032 INFO L158 Benchmark]: Boogie Procedure Inliner took 69.24ms. Allocated memory is still 130.0MB. Free memory was 77.3MB in the beginning and 71.0MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-12-13 19:50:35,033 INFO L158 Benchmark]: Boogie Preprocessor took 64.98ms. Allocated memory is still 130.0MB. Free memory was 71.0MB in the beginning and 65.3MB in the end (delta: 5.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 19:50:35,033 INFO L158 Benchmark]: RCFGBuilder took 1072.63ms. Allocated memory was 130.0MB in the beginning and 161.5MB in the end (delta: 31.5MB). Free memory was 64.8MB in the beginning and 75.4MB in the end (delta: -10.7MB). Peak memory consumption was 35.0MB. Max. memory is 16.1GB. [2022-12-13 19:50:35,033 INFO L158 Benchmark]: BuchiAutomizer took 73675.14ms. Allocated memory was 161.5MB in the beginning and 14.6GB in the end (delta: 14.4GB). Free memory was 75.4MB in the beginning and 1.6GB in the end (delta: -1.6GB). Peak memory consumption was 12.9GB. Max. memory is 16.1GB. [2022-12-13 19:50:35,033 INFO L158 Benchmark]: Witness Printer took 56.13ms. Allocated memory is still 14.6GB. Free memory was 1.6GB in the beginning and 1.6GB in the end (delta: 14.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2022-12-13 19:50:35,034 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13ms. Allocated memory is still 130.0MB. Free memory was 91.4MB in the beginning and 91.4MB in the end (delta: 27.0kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 282.56ms. Allocated memory is still 130.0MB. Free memory was 95.0MB in the beginning and 77.3MB in the end (delta: 17.7MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 69.24ms. Allocated memory is still 130.0MB. Free memory was 77.3MB in the beginning and 71.0MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 64.98ms. Allocated memory is still 130.0MB. Free memory was 71.0MB in the beginning and 65.3MB in the end (delta: 5.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1072.63ms. Allocated memory was 130.0MB in the beginning and 161.5MB in the end (delta: 31.5MB). Free memory was 64.8MB in the beginning and 75.4MB in the end (delta: -10.7MB). Peak memory consumption was 35.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 73675.14ms. Allocated memory was 161.5MB in the beginning and 14.6GB in the end (delta: 14.4GB). Free memory was 75.4MB in the beginning and 1.6GB in the end (delta: -1.6GB). Peak memory consumption was 12.9GB. Max. memory is 16.1GB. * Witness Printer took 56.13ms. Allocated memory is still 14.6GB. Free memory was 1.6GB in the beginning and 1.6GB in the end (delta: 14.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 33 terminating modules (33 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.33 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1269731 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 73.5s and 34 iterations. TraceHistogramMax:1. Analysis of lassos took 5.2s. Construction of modules took 0.8s. Büchi inclusion checks took 59.7s. Highest rank in rank-based complementation 0. Minimization of det autom 33. Minimization of nondet autom 0. Automata minimization 29.7s AutomataMinimizationTime, 33 MinimizatonAttempts, 98096 StatesRemovedByMinimization, 18 NontrivialMinimizations. Non-live state removal took 18.1s Buchi closure took 1.3s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 46818 SdHoareTripleChecker+Valid, 1.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 46818 mSDsluCounter, 71189 SdHoareTripleChecker+Invalid, 0.8s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 29646 mSDsCounter, 481 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 954 IncrementalHoareTripleChecker+Invalid, 1435 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 481 mSolverCounterUnsat, 41543 mSDtfsCounter, 954 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc7 concLT0 SILN1 SILU0 SILI20 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 621]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int m_st ; [L34] int t1_st ; [L35] int t2_st ; [L36] int t3_st ; [L37] int t4_st ; [L38] int t5_st ; [L39] int t6_st ; [L40] int t7_st ; [L41] int m_i ; [L42] int t1_i ; [L43] int t2_i ; [L44] int t3_i ; [L45] int t4_i ; [L46] int t5_i ; [L47] int t6_i ; [L48] int t7_i ; [L49] int M_E = 2; [L50] int T1_E = 2; [L51] int T2_E = 2; [L52] int T3_E = 2; [L53] int T4_E = 2; [L54] int T5_E = 2; [L55] int T6_E = 2; [L56] int T7_E = 2; [L57] int E_1 = 2; [L58] int E_2 = 2; [L59] int E_3 = 2; [L60] int E_4 = 2; [L61] int E_5 = 2; [L62] int E_6 = 2; [L63] int E_7 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0, T7_E=2, t7_i=0, t7_pc=0, t7_st=0] [L1193] int __retres1 ; [L1197] CALL init_model() [L1102] m_i = 1 [L1103] t1_i = 1 [L1104] t2_i = 1 [L1105] t3_i = 1 [L1106] t4_i = 1 [L1107] t5_i = 1 [L1108] t6_i = 1 [L1109] t7_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L1197] RET init_model() [L1198] CALL start_simulation() [L1134] int kernel_st ; [L1135] int tmp ; [L1136] int tmp___0 ; [L1140] kernel_st = 0 [L1141] FCALL update_channels() [L1142] CALL init_threads() [L521] COND TRUE m_i == 1 [L522] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L526] COND TRUE t1_i == 1 [L527] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L531] COND TRUE t2_i == 1 [L532] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L536] COND TRUE t3_i == 1 [L537] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L541] COND TRUE t4_i == 1 [L542] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L546] COND TRUE t5_i == 1 [L547] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L551] COND TRUE t6_i == 1 [L552] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L556] COND TRUE t7_i == 1 [L557] t7_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L1142] RET init_threads() [L1143] CALL fire_delta_events() [L754] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L759] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L764] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L769] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L774] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L779] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L784] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L789] COND FALSE !(T7_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L794] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L799] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L804] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L809] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L814] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L819] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L824] COND FALSE !(E_7 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L1143] RET fire_delta_events() [L1144] CALL activate_threads() [L917] int tmp ; [L918] int tmp___0 ; [L919] int tmp___1 ; [L920] int tmp___2 ; [L921] int tmp___3 ; [L922] int tmp___4 ; [L923] int tmp___5 ; [L924] int tmp___6 ; [L928] CALL, EXPR is_master_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L361] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L371] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L373] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L928] RET, EXPR is_master_triggered() [L928] tmp = is_master_triggered() [L930] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0] [L936] CALL, EXPR is_transmit1_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L380] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L390] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L392] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L936] RET, EXPR is_transmit1_triggered() [L936] tmp___0 = is_transmit1_triggered() [L938] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0] [L944] CALL, EXPR is_transmit2_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L399] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L409] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L411] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L944] RET, EXPR is_transmit2_triggered() [L944] tmp___1 = is_transmit2_triggered() [L946] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0] [L952] CALL, EXPR is_transmit3_triggered() [L415] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L418] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L428] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L430] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L952] RET, EXPR is_transmit3_triggered() [L952] tmp___2 = is_transmit3_triggered() [L954] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L960] CALL, EXPR is_transmit4_triggered() [L434] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L437] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L447] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L449] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L960] RET, EXPR is_transmit4_triggered() [L960] tmp___3 = is_transmit4_triggered() [L962] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L968] CALL, EXPR is_transmit5_triggered() [L453] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L456] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L466] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L468] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L968] RET, EXPR is_transmit5_triggered() [L968] tmp___4 = is_transmit5_triggered() [L970] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L976] CALL, EXPR is_transmit6_triggered() [L472] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L475] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L485] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L487] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L976] RET, EXPR is_transmit6_triggered() [L976] tmp___5 = is_transmit6_triggered() [L978] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L984] CALL, EXPR is_transmit7_triggered() [L491] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L494] COND FALSE !(t7_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L504] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L506] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L984] RET, EXPR is_transmit7_triggered() [L984] tmp___6 = is_transmit7_triggered() [L986] COND FALSE !(\read(tmp___6)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0, tmp___6=0] [L1144] RET activate_threads() [L1145] CALL reset_delta_events() [L837] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L842] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L847] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L852] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L857] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L862] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L867] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L872] COND FALSE !(T7_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L877] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L882] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L887] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L892] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L897] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L902] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L907] COND FALSE !(E_7 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L1145] RET reset_delta_events() [L1148] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L1151] kernel_st = 1 [L1152] CALL eval() [L617] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] Loop: [L621] COND TRUE 1 [L624] CALL, EXPR exists_runnable_thread() [L566] int __retres1 ; [L569] COND TRUE m_st == 0 [L570] __retres1 = 1 [L612] return (__retres1); [L624] RET, EXPR exists_runnable_thread() [L624] tmp = exists_runnable_thread() [L626] COND TRUE \read(tmp) [L631] COND TRUE m_st == 0 [L632] int tmp_ndt_1; [L633] tmp_ndt_1 = __VERIFIER_nondet_int() [L634] COND FALSE !(\read(tmp_ndt_1)) [L645] COND TRUE t1_st == 0 [L646] int tmp_ndt_2; [L647] tmp_ndt_2 = __VERIFIER_nondet_int() [L648] COND FALSE !(\read(tmp_ndt_2)) [L659] COND TRUE t2_st == 0 [L660] int tmp_ndt_3; [L661] tmp_ndt_3 = __VERIFIER_nondet_int() [L662] COND FALSE !(\read(tmp_ndt_3)) [L673] COND TRUE t3_st == 0 [L674] int tmp_ndt_4; [L675] tmp_ndt_4 = __VERIFIER_nondet_int() [L676] COND FALSE !(\read(tmp_ndt_4)) [L687] COND TRUE t4_st == 0 [L688] int tmp_ndt_5; [L689] tmp_ndt_5 = __VERIFIER_nondet_int() [L690] COND FALSE !(\read(tmp_ndt_5)) [L701] COND TRUE t5_st == 0 [L702] int tmp_ndt_6; [L703] tmp_ndt_6 = __VERIFIER_nondet_int() [L704] COND FALSE !(\read(tmp_ndt_6)) [L715] COND TRUE t6_st == 0 [L716] int tmp_ndt_7; [L717] tmp_ndt_7 = __VERIFIER_nondet_int() [L718] COND FALSE !(\read(tmp_ndt_7)) [L729] COND TRUE t7_st == 0 [L730] int tmp_ndt_8; [L731] tmp_ndt_8 = __VERIFIER_nondet_int() [L732] COND FALSE !(\read(tmp_ndt_8)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 621]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int m_st ; [L34] int t1_st ; [L35] int t2_st ; [L36] int t3_st ; [L37] int t4_st ; [L38] int t5_st ; [L39] int t6_st ; [L40] int t7_st ; [L41] int m_i ; [L42] int t1_i ; [L43] int t2_i ; [L44] int t3_i ; [L45] int t4_i ; [L46] int t5_i ; [L47] int t6_i ; [L48] int t7_i ; [L49] int M_E = 2; [L50] int T1_E = 2; [L51] int T2_E = 2; [L52] int T3_E = 2; [L53] int T4_E = 2; [L54] int T5_E = 2; [L55] int T6_E = 2; [L56] int T7_E = 2; [L57] int E_1 = 2; [L58] int E_2 = 2; [L59] int E_3 = 2; [L60] int E_4 = 2; [L61] int E_5 = 2; [L62] int E_6 = 2; [L63] int E_7 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0, T7_E=2, t7_i=0, t7_pc=0, t7_st=0] [L1193] int __retres1 ; [L1197] CALL init_model() [L1102] m_i = 1 [L1103] t1_i = 1 [L1104] t2_i = 1 [L1105] t3_i = 1 [L1106] t4_i = 1 [L1107] t5_i = 1 [L1108] t6_i = 1 [L1109] t7_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L1197] RET init_model() [L1198] CALL start_simulation() [L1134] int kernel_st ; [L1135] int tmp ; [L1136] int tmp___0 ; [L1140] kernel_st = 0 [L1141] FCALL update_channels() [L1142] CALL init_threads() [L521] COND TRUE m_i == 1 [L522] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L526] COND TRUE t1_i == 1 [L527] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L531] COND TRUE t2_i == 1 [L532] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L536] COND TRUE t3_i == 1 [L537] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L541] COND TRUE t4_i == 1 [L542] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L546] COND TRUE t5_i == 1 [L547] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L551] COND TRUE t6_i == 1 [L552] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L556] COND TRUE t7_i == 1 [L557] t7_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L1142] RET init_threads() [L1143] CALL fire_delta_events() [L754] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L759] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L764] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L769] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L774] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L779] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L784] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L789] COND FALSE !(T7_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L794] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L799] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L804] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L809] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L814] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L819] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L824] COND FALSE !(E_7 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L1143] RET fire_delta_events() [L1144] CALL activate_threads() [L917] int tmp ; [L918] int tmp___0 ; [L919] int tmp___1 ; [L920] int tmp___2 ; [L921] int tmp___3 ; [L922] int tmp___4 ; [L923] int tmp___5 ; [L924] int tmp___6 ; [L928] CALL, EXPR is_master_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L361] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L371] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L373] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L928] RET, EXPR is_master_triggered() [L928] tmp = is_master_triggered() [L930] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0] [L936] CALL, EXPR is_transmit1_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L380] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L390] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L392] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L936] RET, EXPR is_transmit1_triggered() [L936] tmp___0 = is_transmit1_triggered() [L938] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0] [L944] CALL, EXPR is_transmit2_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L399] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L409] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L411] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L944] RET, EXPR is_transmit2_triggered() [L944] tmp___1 = is_transmit2_triggered() [L946] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0] [L952] CALL, EXPR is_transmit3_triggered() [L415] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L418] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L428] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L430] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L952] RET, EXPR is_transmit3_triggered() [L952] tmp___2 = is_transmit3_triggered() [L954] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L960] CALL, EXPR is_transmit4_triggered() [L434] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L437] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L447] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L449] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L960] RET, EXPR is_transmit4_triggered() [L960] tmp___3 = is_transmit4_triggered() [L962] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L968] CALL, EXPR is_transmit5_triggered() [L453] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L456] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L466] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L468] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L968] RET, EXPR is_transmit5_triggered() [L968] tmp___4 = is_transmit5_triggered() [L970] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L976] CALL, EXPR is_transmit6_triggered() [L472] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L475] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L485] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L487] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L976] RET, EXPR is_transmit6_triggered() [L976] tmp___5 = is_transmit6_triggered() [L978] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L984] CALL, EXPR is_transmit7_triggered() [L491] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L494] COND FALSE !(t7_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L504] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L506] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L984] RET, EXPR is_transmit7_triggered() [L984] tmp___6 = is_transmit7_triggered() [L986] COND FALSE !(\read(tmp___6)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0, tmp___6=0] [L1144] RET activate_threads() [L1145] CALL reset_delta_events() [L837] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L842] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L847] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L852] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L857] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L862] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L867] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L872] COND FALSE !(T7_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L877] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L882] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L887] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L892] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L897] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L902] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L907] COND FALSE !(E_7 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L1145] RET reset_delta_events() [L1148] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] [L1151] kernel_st = 1 [L1152] CALL eval() [L617] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0] Loop: [L621] COND TRUE 1 [L624] CALL, EXPR exists_runnable_thread() [L566] int __retres1 ; [L569] COND TRUE m_st == 0 [L570] __retres1 = 1 [L612] return (__retres1); [L624] RET, EXPR exists_runnable_thread() [L624] tmp = exists_runnable_thread() [L626] COND TRUE \read(tmp) [L631] COND TRUE m_st == 0 [L632] int tmp_ndt_1; [L633] tmp_ndt_1 = __VERIFIER_nondet_int() [L634] COND FALSE !(\read(tmp_ndt_1)) [L645] COND TRUE t1_st == 0 [L646] int tmp_ndt_2; [L647] tmp_ndt_2 = __VERIFIER_nondet_int() [L648] COND FALSE !(\read(tmp_ndt_2)) [L659] COND TRUE t2_st == 0 [L660] int tmp_ndt_3; [L661] tmp_ndt_3 = __VERIFIER_nondet_int() [L662] COND FALSE !(\read(tmp_ndt_3)) [L673] COND TRUE t3_st == 0 [L674] int tmp_ndt_4; [L675] tmp_ndt_4 = __VERIFIER_nondet_int() [L676] COND FALSE !(\read(tmp_ndt_4)) [L687] COND TRUE t4_st == 0 [L688] int tmp_ndt_5; [L689] tmp_ndt_5 = __VERIFIER_nondet_int() [L690] COND FALSE !(\read(tmp_ndt_5)) [L701] COND TRUE t5_st == 0 [L702] int tmp_ndt_6; [L703] tmp_ndt_6 = __VERIFIER_nondet_int() [L704] COND FALSE !(\read(tmp_ndt_6)) [L715] COND TRUE t6_st == 0 [L716] int tmp_ndt_7; [L717] tmp_ndt_7 = __VERIFIER_nondet_int() [L718] COND FALSE !(\read(tmp_ndt_7)) [L729] COND TRUE t7_st == 0 [L730] int tmp_ndt_8; [L731] tmp_ndt_8 = __VERIFIER_nondet_int() [L732] COND FALSE !(\read(tmp_ndt_8)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 19:50:35,117 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e66b6e45-012c-4937-b941-0383a60c1f42/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)