./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.12.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.12.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 19:05:19,727 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 19:05:19,729 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 19:05:19,748 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 19:05:19,749 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 19:05:19,750 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 19:05:19,751 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 19:05:19,752 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 19:05:19,754 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 19:05:19,755 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 19:05:19,755 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 19:05:19,756 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 19:05:19,757 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 19:05:19,758 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 19:05:19,759 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 19:05:19,760 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 19:05:19,761 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 19:05:19,762 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 19:05:19,763 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 19:05:19,765 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 19:05:19,766 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 19:05:19,767 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 19:05:19,768 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 19:05:19,769 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 19:05:19,773 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 19:05:19,773 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 19:05:19,773 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 19:05:19,774 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 19:05:19,775 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 19:05:19,775 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 19:05:19,776 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 19:05:19,776 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 19:05:19,777 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 19:05:19,778 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 19:05:19,779 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 19:05:19,779 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 19:05:19,780 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 19:05:19,780 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 19:05:19,780 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 19:05:19,781 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 19:05:19,781 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 19:05:19,782 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 19:05:19,811 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 19:05:19,812 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 19:05:19,819 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 19:05:19,820 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 19:05:19,821 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 19:05:19,821 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 19:05:19,821 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 19:05:19,821 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 19:05:19,822 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 19:05:19,822 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 19:05:19,822 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 19:05:19,822 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 19:05:19,822 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 19:05:19,822 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 19:05:19,823 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 19:05:19,823 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 19:05:19,823 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 19:05:19,823 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 19:05:19,823 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 19:05:19,823 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 19:05:19,824 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 19:05:19,824 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 19:05:19,824 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 19:05:19,824 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 19:05:19,824 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 19:05:19,824 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 19:05:19,824 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 19:05:19,825 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 19:05:19,825 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 19:05:19,825 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 19:05:19,825 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 19:05:19,826 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 19:05:19,826 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 [2022-12-13 19:05:20,015 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 19:05:20,034 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 19:05:20,036 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 19:05:20,037 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 19:05:20,038 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 19:05:20,039 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/transmitter.12.cil.c [2022-12-13 19:05:22,697 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 19:05:22,858 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 19:05:22,858 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/sv-benchmarks/c/systemc/transmitter.12.cil.c [2022-12-13 19:05:22,867 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8/data/ef1381fcf/030cd47e84aa4da8a3ac26d4d5ff38b5/FLAGa98b29751 [2022-12-13 19:05:22,881 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8/data/ef1381fcf/030cd47e84aa4da8a3ac26d4d5ff38b5 [2022-12-13 19:05:22,883 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 19:05:22,884 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 19:05:22,886 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 19:05:22,886 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 19:05:22,889 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 19:05:22,889 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 07:05:22" (1/1) ... [2022-12-13 19:05:22,890 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1785ac89 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:22, skipping insertion in model container [2022-12-13 19:05:22,891 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 07:05:22" (1/1) ... [2022-12-13 19:05:22,897 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 19:05:22,936 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 19:05:23,053 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/sv-benchmarks/c/systemc/transmitter.12.cil.c[706,719] [2022-12-13 19:05:23,157 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 19:05:23,171 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 19:05:23,179 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/sv-benchmarks/c/systemc/transmitter.12.cil.c[706,719] [2022-12-13 19:05:23,230 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 19:05:23,248 INFO L208 MainTranslator]: Completed translation [2022-12-13 19:05:23,249 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:23 WrapperNode [2022-12-13 19:05:23,249 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 19:05:23,250 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 19:05:23,250 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 19:05:23,250 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 19:05:23,255 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:23" (1/1) ... [2022-12-13 19:05:23,266 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:23" (1/1) ... [2022-12-13 19:05:23,339 INFO L138 Inliner]: procedures = 52, calls = 66, calls flagged for inlining = 61, calls inlined = 254, statements flattened = 3910 [2022-12-13 19:05:23,339 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 19:05:23,340 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 19:05:23,340 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 19:05:23,340 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 19:05:23,348 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:23" (1/1) ... [2022-12-13 19:05:23,349 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:23" (1/1) ... [2022-12-13 19:05:23,355 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:23" (1/1) ... [2022-12-13 19:05:23,355 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:23" (1/1) ... [2022-12-13 19:05:23,379 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:23" (1/1) ... [2022-12-13 19:05:23,424 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:23" (1/1) ... [2022-12-13 19:05:23,430 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:23" (1/1) ... [2022-12-13 19:05:23,440 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:23" (1/1) ... [2022-12-13 19:05:23,453 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 19:05:23,454 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 19:05:23,454 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 19:05:23,454 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 19:05:23,455 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:23" (1/1) ... [2022-12-13 19:05:23,461 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 19:05:23,471 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 19:05:23,481 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 19:05:23,483 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a366f98d-94d6-4c87-a156-2e49efa250fe/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 19:05:23,516 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 19:05:23,517 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 19:05:23,517 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 19:05:23,517 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 19:05:23,608 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 19:05:23,609 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 19:05:25,018 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 19:05:25,035 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 19:05:25,035 INFO L300 CfgBuilder]: Removed 16 assume(true) statements. [2022-12-13 19:05:25,039 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:05:25 BoogieIcfgContainer [2022-12-13 19:05:25,039 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 19:05:25,040 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 19:05:25,040 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 19:05:25,043 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 19:05:25,044 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:05:25,044 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 07:05:22" (1/3) ... [2022-12-13 19:05:25,045 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@775bbe77 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 07:05:25, skipping insertion in model container [2022-12-13 19:05:25,045 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:05:25,045 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:05:23" (2/3) ... [2022-12-13 19:05:25,046 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@775bbe77 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 07:05:25, skipping insertion in model container [2022-12-13 19:05:25,046 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:05:25,046 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:05:25" (3/3) ... [2022-12-13 19:05:25,047 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.12.cil.c [2022-12-13 19:05:25,112 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 19:05:25,112 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 19:05:25,112 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 19:05:25,112 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 19:05:25,112 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 19:05:25,112 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 19:05:25,112 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 19:05:25,112 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 19:05:25,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:25,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1530 [2022-12-13 19:05:25,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:25,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:25,176 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:25,176 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:25,176 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 19:05:25,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:25,189 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1530 [2022-12-13 19:05:25,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:25,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:25,194 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:25,194 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:25,201 INFO L748 eck$LassoCheckResult]: Stem: 127#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1607#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 622#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1602#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 518#L821true assume !(1 == ~m_i~0);~m_st~0 := 2; 592#L821-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 863#L826-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1175#L831-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1017#L836-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1321#L841-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 116#L846-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1621#L851-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 932#L856-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 445#L861-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 471#L866-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 387#L871-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 697#L876-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 692#L881-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 237#L1174true assume !(0 == ~M_E~0); 1344#L1174-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 160#L1179-1true assume !(0 == ~T2_E~0); 115#L1184-1true assume !(0 == ~T3_E~0); 135#L1189-1true assume !(0 == ~T4_E~0); 181#L1194-1true assume !(0 == ~T5_E~0); 803#L1199-1true assume !(0 == ~T6_E~0); 966#L1204-1true assume !(0 == ~T7_E~0); 731#L1209-1true assume !(0 == ~T8_E~0); 1237#L1214-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1636#L1219-1true assume !(0 == ~T10_E~0); 1555#L1224-1true assume !(0 == ~T11_E~0); 302#L1229-1true assume !(0 == ~T12_E~0); 83#L1234-1true assume !(0 == ~E_1~0); 483#L1239-1true assume !(0 == ~E_2~0); 97#L1244-1true assume !(0 == ~E_3~0); 1327#L1249-1true assume !(0 == ~E_4~0); 460#L1254-1true assume 0 == ~E_5~0;~E_5~0 := 1; 49#L1259-1true assume !(0 == ~E_6~0); 29#L1264-1true assume !(0 == ~E_7~0); 1688#L1269-1true assume !(0 == ~E_8~0); 1610#L1274-1true assume !(0 == ~E_9~0); 1315#L1279-1true assume !(0 == ~E_10~0); 137#L1284-1true assume !(0 == ~E_11~0); 1457#L1289-1true assume !(0 == ~E_12~0); 497#L1294-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1331#L566true assume 1 == ~m_pc~0; 36#L567true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 959#L577true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 532#is_master_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1182#L1455true assume !(0 != activate_threads_~tmp~1#1); 249#L1455-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 775#L585true assume 1 == ~t1_pc~0; 82#L586true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1613#L596true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 854#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1530#L1463true assume !(0 != activate_threads_~tmp___0~0#1); 1399#L1463-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1391#L604true assume !(1 == ~t2_pc~0); 768#L604-2true is_transmit2_triggered_~__retres1~2#1 := 0; 1353#L615true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1191#L1471true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 973#L1471-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1455#L623true assume 1 == ~t3_pc~0; 352#L624true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1661#L634true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 827#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1010#L1479true assume !(0 != activate_threads_~tmp___2~0#1); 1235#L1479-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35#L642true assume !(1 == ~t4_pc~0); 662#L642-2true is_transmit4_triggered_~__retres1~4#1 := 0; 256#L653true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71#L1487true assume !(0 != activate_threads_~tmp___3~0#1); 780#L1487-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1116#L661true assume 1 == ~t5_pc~0; 144#L662true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 705#L672true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1359#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1093#L1495true assume !(0 != activate_threads_~tmp___4~0#1); 810#L1495-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1689#L680true assume !(1 == ~t6_pc~0); 1691#L680-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1484#L691true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 215#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1108#L1503true assume !(0 != activate_threads_~tmp___5~0#1); 1396#L1503-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1387#L699true assume 1 == ~t7_pc~0; 673#L700true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 882#L710true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1622#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 581#L1511true assume !(0 != activate_threads_~tmp___6~0#1); 788#L1511-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 498#L718true assume !(1 == ~t8_pc~0); 1243#L718-2true is_transmit8_triggered_~__retres1~8#1 := 0; 134#L729true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1309#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 152#L1519true assume !(0 != activate_threads_~tmp___7~0#1); 218#L1519-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 841#L737true assume 1 == ~t9_pc~0; 1496#L738true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1278#L748true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 241#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1637#L1527true assume !(0 != activate_threads_~tmp___8~0#1); 400#L1527-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1087#L756true assume 1 == ~t10_pc~0; 874#L757true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 798#L767true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1109#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 525#L1535true assume !(0 != activate_threads_~tmp___9~0#1); 281#L1535-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 742#L775true assume !(1 == ~t11_pc~0); 440#L775-2true is_transmit11_triggered_~__retres1~11#1 := 0; 1257#L786true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1223#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 102#L1543true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 834#L1543-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 192#L794true assume 1 == ~t12_pc~0; 113#L795true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1094#L805true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 174#L1551true assume !(0 != activate_threads_~tmp___11~0#1); 689#L1551-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 449#L1307true assume !(1 == ~M_E~0); 529#L1307-2true assume !(1 == ~T1_E~0); 1437#L1312-1true assume !(1 == ~T2_E~0); 469#L1317-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 635#L1322-1true assume !(1 == ~T4_E~0); 288#L1327-1true assume !(1 == ~T5_E~0); 677#L1332-1true assume !(1 == ~T6_E~0); 1412#L1337-1true assume !(1 == ~T7_E~0); 630#L1342-1true assume !(1 == ~T8_E~0); 1313#L1347-1true assume !(1 == ~T9_E~0); 1056#L1352-1true assume !(1 == ~T10_E~0); 883#L1357-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 386#L1362-1true assume !(1 == ~T12_E~0); 1127#L1367-1true assume !(1 == ~E_1~0); 182#L1372-1true assume !(1 == ~E_2~0); 478#L1377-1true assume !(1 == ~E_3~0); 345#L1382-1true assume !(1 == ~E_4~0); 769#L1387-1true assume !(1 == ~E_5~0); 1252#L1392-1true assume !(1 == ~E_6~0); 356#L1397-1true assume 1 == ~E_7~0;~E_7~0 := 2; 1381#L1402-1true assume !(1 == ~E_8~0); 190#L1407-1true assume !(1 == ~E_9~0); 1513#L1412-1true assume !(1 == ~E_10~0); 962#L1417-1true assume !(1 == ~E_11~0); 1695#L1422-1true assume !(1 == ~E_12~0); 1377#L1427-1true assume { :end_inline_reset_delta_events } true; 95#L1768-2true [2022-12-13 19:05:25,202 INFO L750 eck$LassoCheckResult]: Loop: 95#L1768-2true assume !false; 514#L1769true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 830#L1149true assume false; 492#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 314#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 986#L1174-3true assume !(0 == ~M_E~0); 978#L1174-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 713#L1179-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1392#L1184-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 884#L1189-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 569#L1194-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 170#L1199-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 807#L1204-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 298#L1209-3true assume !(0 == ~T8_E~0); 11#L1214-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 620#L1219-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 408#L1224-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1693#L1229-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 419#L1234-3true assume 0 == ~E_1~0;~E_1~0 := 1; 99#L1239-3true assume 0 == ~E_2~0;~E_2~0 := 1; 332#L1244-3true assume 0 == ~E_3~0;~E_3~0 := 1; 660#L1249-3true assume !(0 == ~E_4~0); 1438#L1254-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1230#L1259-3true assume 0 == ~E_6~0;~E_6~0 := 1; 755#L1264-3true assume 0 == ~E_7~0;~E_7~0 := 1; 101#L1269-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1497#L1274-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1312#L1279-3true assume 0 == ~E_10~0;~E_10~0 := 1; 407#L1284-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1369#L1289-3true assume !(0 == ~E_12~0); 398#L1294-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 210#L566-39true assume 1 == ~m_pc~0; 738#L567-13true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 600#L577-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 642#is_master_triggered_returnLabel#14true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1244#L1455-39true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 820#L1455-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1288#L585-39true assume !(1 == ~t1_pc~0); 214#L585-41true is_transmit1_triggered_~__retres1~1#1 := 0; 328#L596-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1471#is_transmit1_triggered_returnLabel#14true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1218#L1463-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 857#L1463-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 585#L604-39true assume 1 == ~t2_pc~0; 687#L605-13true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 334#L615-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 448#is_transmit2_triggered_returnLabel#14true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 624#L1471-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 994#L1471-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 320#L623-39true assume !(1 == ~t3_pc~0); 649#L623-41true is_transmit3_triggered_~__retres1~3#1 := 0; 837#L634-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1667#is_transmit3_triggered_returnLabel#14true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 238#L1479-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 787#L1479-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1294#L642-39true assume 1 == ~t4_pc~0; 442#L643-13true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 741#L653-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 566#is_transmit4_triggered_returnLabel#14true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1030#L1487-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1172#L1487-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 196#L661-39true assume 1 == ~t5_pc~0; 1041#L662-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1626#L672-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 589#is_transmit5_triggered_returnLabel#14true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1143#L1495-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 839#L1495-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1165#L680-39true assume !(1 == ~t6_pc~0); 964#L680-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1136#L691-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1560#is_transmit6_triggered_returnLabel#14true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 280#L1503-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1485#L1503-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1241#L699-39true assume 1 == ~t7_pc~0; 571#L700-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 376#L710-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 842#is_transmit7_triggered_returnLabel#14true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1263#L1511-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1133#L1511-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1131#L718-39true assume 1 == ~t8_pc~0; 501#L719-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1380#L729-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 943#is_transmit8_triggered_returnLabel#14true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1145#L1519-39true assume !(0 != activate_threads_~tmp___7~0#1); 704#L1519-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 683#L737-39true assume !(1 == ~t9_pc~0); 1447#L737-41true is_transmit9_triggered_~__retres1~9#1 := 0; 446#L748-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65#is_transmit9_triggered_returnLabel#14true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1440#L1527-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1092#L1527-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1012#L756-39true assume !(1 == ~t10_pc~0); 509#L756-41true is_transmit10_triggered_~__retres1~10#1 := 0; 1508#L767-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1217#is_transmit10_triggered_returnLabel#14true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 430#L1535-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 555#L1535-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76#L775-39true assume 1 == ~t11_pc~0; 1260#L776-13true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 426#L786-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 610#is_transmit11_triggered_returnLabel#14true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1540#L1543-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 749#L1543-41true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 459#L794-39true assume !(1 == ~t12_pc~0); 265#L794-41true is_transmit12_triggered_~__retres1~12#1 := 0; 904#L805-13true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 318#is_transmit12_triggered_returnLabel#14true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 793#L1551-39true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47#L1551-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1296#L1307-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1192#L1307-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1608#L1312-3true assume !(1 == ~T2_E~0); 1599#L1317-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 811#L1322-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1673#L1327-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 108#L1332-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 98#L1337-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 522#L1342-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 944#L1347-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 626#L1352-3true assume !(1 == ~T10_E~0); 1104#L1357-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1683#L1362-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1535#L1367-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1502#L1372-3true assume 1 == ~E_2~0;~E_2~0 := 2; 17#L1377-3true assume 1 == ~E_3~0;~E_3~0 := 2; 422#L1382-3true assume 1 == ~E_4~0;~E_4~0 := 2; 336#L1387-3true assume 1 == ~E_5~0;~E_5~0 := 2; 917#L1392-3true assume !(1 == ~E_6~0); 1590#L1397-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1363#L1402-3true assume 1 == ~E_8~0;~E_8~0 := 2; 599#L1407-3true assume 1 == ~E_9~0;~E_9~0 := 2; 150#L1412-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1141#L1417-3true assume 1 == ~E_11~0;~E_11~0 := 2; 536#L1422-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1097#L1427-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 154#L894-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1650#L961-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 188#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 602#L1787true assume !(0 == start_simulation_~tmp~3#1); 1426#L1787-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1207#L894-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 997#L961-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1307#L1742true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 324#L1749true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1138#stop_simulation_returnLabel#1true start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1586#L1800true assume !(0 != start_simulation_~tmp___0~1#1); 95#L1768-2true [2022-12-13 19:05:25,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:25,207 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 1 times [2022-12-13 19:05:25,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:25,214 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116922630] [2022-12-13 19:05:25,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:25,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:25,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:25,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:25,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:25,423 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116922630] [2022-12-13 19:05:25,424 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [116922630] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:25,424 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:25,425 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:25,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732729] [2022-12-13 19:05:25,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:25,431 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:25,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:25,432 INFO L85 PathProgramCache]: Analyzing trace with hash -1533874250, now seen corresponding path program 1 times [2022-12-13 19:05:25,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:25,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288012137] [2022-12-13 19:05:25,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:25,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:25,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:25,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:25,482 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:25,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1288012137] [2022-12-13 19:05:25,482 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1288012137] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:25,482 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:25,483 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:05:25,483 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1902205407] [2022-12-13 19:05:25,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:25,484 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:25,485 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:25,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 19:05:25,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 19:05:25,512 INFO L87 Difference]: Start difference. First operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 73.5) internal successors, (147), 2 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:25,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:25,558 INFO L93 Difference]: Finished difference Result 1694 states and 2510 transitions. [2022-12-13 19:05:25,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1694 states and 2510 transitions. [2022-12-13 19:05:25,568 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:25,578 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1694 states to 1688 states and 2504 transitions. [2022-12-13 19:05:25,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-12-13 19:05:25,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-12-13 19:05:25,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2504 transitions. [2022-12-13 19:05:25,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:25,586 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2022-12-13 19:05:25,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2504 transitions. [2022-12-13 19:05:25,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-12-13 19:05:25,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4834123222748816) internal successors, (2504), 1687 states have internal predecessors, (2504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:25,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2504 transitions. [2022-12-13 19:05:25,655 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2022-12-13 19:05:25,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 19:05:25,659 INFO L428 stractBuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2022-12-13 19:05:25,660 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 19:05:25,660 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2504 transitions. [2022-12-13 19:05:25,668 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:25,668 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:25,668 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:25,671 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:25,671 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:25,672 INFO L748 eck$LassoCheckResult]: Stem: 3668#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 3669#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4455#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4456#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4325#L821 assume !(1 == ~m_i~0);~m_st~0 := 2; 4326#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4418#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4718#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4849#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4850#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3645#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3646#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4782#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4225#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4226#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4135#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4136#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4525#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3881#L1174 assume !(0 == ~M_E~0); 3882#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3735#L1179-1 assume !(0 == ~T2_E~0); 3643#L1184-1 assume !(0 == ~T3_E~0); 3644#L1189-1 assume !(0 == ~T4_E~0); 3684#L1194-1 assume !(0 == ~T5_E~0); 3775#L1199-1 assume !(0 == ~T6_E~0); 4651#L1204-1 assume !(0 == ~T7_E~0); 4570#L1209-1 assume !(0 == ~T8_E~0); 4571#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4994#L1219-1 assume !(0 == ~T10_E~0); 5080#L1224-1 assume !(0 == ~T11_E~0); 4000#L1229-1 assume !(0 == ~T12_E~0); 3575#L1234-1 assume !(0 == ~E_1~0); 3576#L1239-1 assume !(0 == ~E_2~0); 3608#L1244-1 assume !(0 == ~E_3~0); 3609#L1249-1 assume !(0 == ~E_4~0); 4245#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3505#L1259-1 assume !(0 == ~E_6~0); 3458#L1264-1 assume !(0 == ~E_7~0); 3459#L1269-1 assume !(0 == ~E_8~0); 5083#L1274-1 assume !(0 == ~E_9~0); 5021#L1279-1 assume !(0 == ~E_10~0); 3688#L1284-1 assume !(0 == ~E_11~0); 3689#L1289-1 assume !(0 == ~E_12~0); 4294#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4295#L566 assume 1 == ~m_pc~0; 3475#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3476#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4339#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4340#L1455 assume !(0 != activate_threads_~tmp~1#1); 3908#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3909#L585 assume 1 == ~t1_pc~0; 3572#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3573#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4709#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4710#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 5050#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5046#L604 assume !(1 == ~t2_pc~0); 4613#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4614#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3851#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3852#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4809#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4810#L623 assume 1 == ~t3_pc~0; 4084#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3437#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4682#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4683#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 4843#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3472#L642 assume !(1 == ~t4_pc~0); 3473#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3921#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3527#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3528#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 3549#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4627#L661 assume 1 == ~t5_pc~0; 3701#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3702#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4542#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4908#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 4658#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4659#L680 assume !(1 == ~t6_pc~0); 4117#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4118#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3842#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3843#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 4919#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5043#L699 assume 1 == ~t7_pc~0; 4506#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4507#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4741#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4400#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 4401#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4296#L718 assume !(1 == ~t8_pc~0); 4297#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3682#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3683#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3717#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 3718#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3848#L737 assume 1 == ~t9_pc~0; 4697#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3981#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3888#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3889#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 4155#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4156#L756 assume 1 == ~t10_pc~0; 4731#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4391#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4646#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4332#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 3960#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3961#L775 assume !(1 == ~t11_pc~0); 4214#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4215#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4987#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3618#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3619#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3796#L794 assume 1 == ~t12_pc~0; 3641#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3621#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3478#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3479#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 3761#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4229#L1307 assume !(1 == ~M_E~0); 4230#L1307-2 assume !(1 == ~T1_E~0); 4336#L1312-1 assume !(1 == ~T2_E~0); 4258#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4259#L1322-1 assume !(1 == ~T4_E~0); 3971#L1327-1 assume !(1 == ~T5_E~0); 3972#L1332-1 assume !(1 == ~T6_E~0); 4511#L1337-1 assume !(1 == ~T7_E~0); 4468#L1342-1 assume !(1 == ~T8_E~0); 4469#L1347-1 assume !(1 == ~T9_E~0); 4880#L1352-1 assume !(1 == ~T10_E~0); 4742#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4133#L1362-1 assume !(1 == ~T12_E~0); 4134#L1367-1 assume !(1 == ~E_1~0); 3776#L1372-1 assume !(1 == ~E_2~0); 3777#L1377-1 assume !(1 == ~E_3~0); 4069#L1382-1 assume !(1 == ~E_4~0); 4070#L1387-1 assume !(1 == ~E_5~0); 4615#L1392-1 assume !(1 == ~E_6~0); 4087#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4088#L1402-1 assume !(1 == ~E_8~0); 3791#L1407-1 assume !(1 == ~E_9~0); 3792#L1412-1 assume !(1 == ~E_10~0); 4804#L1417-1 assume !(1 == ~E_11~0); 4805#L1422-1 assume !(1 == ~E_12~0); 5040#L1427-1 assume { :end_inline_reset_delta_events } true; 3604#L1768-2 [2022-12-13 19:05:25,673 INFO L750 eck$LassoCheckResult]: Loop: 3604#L1768-2 assume !false; 3605#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4320#L1149 assume !false; 4687#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4861#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3978#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4787#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4856#L976 assume !(0 != eval_~tmp~0#1); 4287#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4021#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4022#L1174-3 assume !(0 == ~M_E~0); 4814#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4553#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4554#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4743#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4386#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3752#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3753#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3991#L1209-3 assume !(0 == ~T8_E~0); 3421#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3422#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4166#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4167#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4181#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3612#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3613#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4046#L1249-3 assume !(0 == ~E_4~0); 4498#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4990#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4598#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3616#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3617#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5020#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4164#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4165#L1289-3 assume !(0 == ~E_12~0); 4152#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3832#L566-39 assume 1 == ~m_pc~0; 3833#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4429#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4430#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4481#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4673#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4674#L585-39 assume !(1 == ~t1_pc~0); 3840#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 3841#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4043#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4984#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4713#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4406#L604-39 assume 1 == ~t2_pc~0; 4407#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4050#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4051#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4228#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4458#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4032#L623-39 assume 1 == ~t3_pc~0; 3438#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3440#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4692#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3883#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3884#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4634#L642-39 assume 1 == ~t4_pc~0; 4219#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4220#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4381#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4382#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4860#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3802#L661-39 assume !(1 == ~t5_pc~0); 3446#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 3447#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4413#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4414#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4694#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4695#L680-39 assume 1 == ~t6_pc~0; 3510#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3511#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4941#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3958#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3959#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4996#L699-39 assume 1 == ~t7_pc~0; 4388#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4120#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4121#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4699#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4937#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4934#L718-39 assume 1 == ~t8_pc~0; 4300#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4301#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4792#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4793#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 4541#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4519#L737-39 assume 1 == ~t9_pc~0; 3939#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3940#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3538#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3539#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4907#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4844#L756-39 assume !(1 == ~t10_pc~0); 4314#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 4315#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4983#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4199#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4200#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3559#L775-39 assume 1 == ~t11_pc~0; 3560#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4190#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4191#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4441#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4591#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4244#L794-39 assume 1 == ~t12_pc~0; 3942#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3936#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4029#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4030#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3501#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3502#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4967#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4968#L1312-3 assume !(1 == ~T2_E~0); 5082#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4660#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4661#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3633#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3610#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3611#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4330#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4461#L1352-3 assume !(1 == ~T10_E~0); 4462#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4916#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5077#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5068#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3434#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3435#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4053#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4054#L1392-3 assume !(1 == ~E_6~0); 4768#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5034#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4428#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3713#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3714#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4344#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4345#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3721#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3722#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3787#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 3788#L1787 assume !(0 == start_simulation_~tmp~3#1); 4432#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4976#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3698#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3450#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 3451#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4039#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4040#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4944#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 3604#L1768-2 [2022-12-13 19:05:25,674 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:25,674 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 2 times [2022-12-13 19:05:25,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:25,674 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535429824] [2022-12-13 19:05:25,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:25,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:25,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:25,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:25,757 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:25,757 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535429824] [2022-12-13 19:05:25,757 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535429824] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:25,758 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:25,758 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:25,758 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140892028] [2022-12-13 19:05:25,758 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:25,758 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:25,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:25,759 INFO L85 PathProgramCache]: Analyzing trace with hash -1994635518, now seen corresponding path program 1 times [2022-12-13 19:05:25,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:25,760 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090536084] [2022-12-13 19:05:25,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:25,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:25,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:25,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:25,863 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:25,863 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090536084] [2022-12-13 19:05:25,863 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1090536084] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:25,864 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:25,864 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:25,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [914493921] [2022-12-13 19:05:25,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:25,864 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:25,865 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:25,865 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:25,865 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:25,865 INFO L87 Difference]: Start difference. First operand 1688 states and 2504 transitions. cyclomatic complexity: 817 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:25,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:25,912 INFO L93 Difference]: Finished difference Result 1688 states and 2503 transitions. [2022-12-13 19:05:25,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2503 transitions. [2022-12-13 19:05:25,917 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:25,922 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2503 transitions. [2022-12-13 19:05:25,922 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-12-13 19:05:25,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-12-13 19:05:25,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2503 transitions. [2022-12-13 19:05:25,925 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:25,925 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2022-12-13 19:05:25,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2503 transitions. [2022-12-13 19:05:25,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-12-13 19:05:25,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4828199052132702) internal successors, (2503), 1687 states have internal predecessors, (2503), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:25,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2503 transitions. [2022-12-13 19:05:25,943 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2022-12-13 19:05:25,943 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:25,944 INFO L428 stractBuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2022-12-13 19:05:25,944 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 19:05:25,944 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2503 transitions. [2022-12-13 19:05:25,949 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:25,949 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:25,949 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:25,951 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:25,952 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:25,952 INFO L748 eck$LassoCheckResult]: Stem: 7051#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 7052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 7838#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7839#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7708#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 7709#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7801#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8101#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8232#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8233#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7028#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7029#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8165#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7608#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7609#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7518#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7519#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 7908#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7264#L1174 assume !(0 == ~M_E~0); 7265#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7118#L1179-1 assume !(0 == ~T2_E~0); 7026#L1184-1 assume !(0 == ~T3_E~0); 7027#L1189-1 assume !(0 == ~T4_E~0); 7067#L1194-1 assume !(0 == ~T5_E~0); 7158#L1199-1 assume !(0 == ~T6_E~0); 8034#L1204-1 assume !(0 == ~T7_E~0); 7953#L1209-1 assume !(0 == ~T8_E~0); 7954#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8377#L1219-1 assume !(0 == ~T10_E~0); 8463#L1224-1 assume !(0 == ~T11_E~0); 7383#L1229-1 assume !(0 == ~T12_E~0); 6958#L1234-1 assume !(0 == ~E_1~0); 6959#L1239-1 assume !(0 == ~E_2~0); 6991#L1244-1 assume !(0 == ~E_3~0); 6992#L1249-1 assume !(0 == ~E_4~0); 7628#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6888#L1259-1 assume !(0 == ~E_6~0); 6841#L1264-1 assume !(0 == ~E_7~0); 6842#L1269-1 assume !(0 == ~E_8~0); 8466#L1274-1 assume !(0 == ~E_9~0); 8404#L1279-1 assume !(0 == ~E_10~0); 7071#L1284-1 assume !(0 == ~E_11~0); 7072#L1289-1 assume !(0 == ~E_12~0); 7677#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7678#L566 assume 1 == ~m_pc~0; 6858#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6859#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7722#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7723#L1455 assume !(0 != activate_threads_~tmp~1#1); 7291#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7292#L585 assume 1 == ~t1_pc~0; 6955#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6956#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8092#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8093#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 8433#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8429#L604 assume !(1 == ~t2_pc~0); 7996#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7997#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7234#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7235#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8192#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8193#L623 assume 1 == ~t3_pc~0; 7467#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6820#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8065#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8066#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 8226#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6855#L642 assume !(1 == ~t4_pc~0); 6856#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7304#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6910#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6911#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 6932#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8010#L661 assume 1 == ~t5_pc~0; 7084#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7085#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7925#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8291#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 8041#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8042#L680 assume !(1 == ~t6_pc~0); 7500#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7501#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7225#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7226#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 8302#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8426#L699 assume 1 == ~t7_pc~0; 7889#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7890#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8124#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7783#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 7784#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7679#L718 assume !(1 == ~t8_pc~0); 7680#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7065#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7066#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7100#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 7101#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7231#L737 assume 1 == ~t9_pc~0; 8080#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7364#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7271#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7272#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 7538#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7539#L756 assume 1 == ~t10_pc~0; 8114#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7774#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8029#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7715#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 7343#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7344#L775 assume !(1 == ~t11_pc~0); 7597#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 7598#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8370#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7001#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7002#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7179#L794 assume 1 == ~t12_pc~0; 7024#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7004#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 6861#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6862#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 7144#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7612#L1307 assume !(1 == ~M_E~0); 7613#L1307-2 assume !(1 == ~T1_E~0); 7719#L1312-1 assume !(1 == ~T2_E~0); 7641#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7642#L1322-1 assume !(1 == ~T4_E~0); 7354#L1327-1 assume !(1 == ~T5_E~0); 7355#L1332-1 assume !(1 == ~T6_E~0); 7894#L1337-1 assume !(1 == ~T7_E~0); 7851#L1342-1 assume !(1 == ~T8_E~0); 7852#L1347-1 assume !(1 == ~T9_E~0); 8263#L1352-1 assume !(1 == ~T10_E~0); 8125#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7516#L1362-1 assume !(1 == ~T12_E~0); 7517#L1367-1 assume !(1 == ~E_1~0); 7159#L1372-1 assume !(1 == ~E_2~0); 7160#L1377-1 assume !(1 == ~E_3~0); 7452#L1382-1 assume !(1 == ~E_4~0); 7453#L1387-1 assume !(1 == ~E_5~0); 7998#L1392-1 assume !(1 == ~E_6~0); 7470#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7471#L1402-1 assume !(1 == ~E_8~0); 7174#L1407-1 assume !(1 == ~E_9~0); 7175#L1412-1 assume !(1 == ~E_10~0); 8187#L1417-1 assume !(1 == ~E_11~0); 8188#L1422-1 assume !(1 == ~E_12~0); 8423#L1427-1 assume { :end_inline_reset_delta_events } true; 6987#L1768-2 [2022-12-13 19:05:25,953 INFO L750 eck$LassoCheckResult]: Loop: 6987#L1768-2 assume !false; 6988#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7703#L1149 assume !false; 8070#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8244#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7361#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8170#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8239#L976 assume !(0 != eval_~tmp~0#1); 7670#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7404#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7405#L1174-3 assume !(0 == ~M_E~0); 8197#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7936#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7937#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8126#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7769#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7135#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7136#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7374#L1209-3 assume !(0 == ~T8_E~0); 6804#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6805#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7549#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7550#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7564#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6995#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6996#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7429#L1249-3 assume !(0 == ~E_4~0); 7881#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8373#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7981#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6999#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7000#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8403#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7547#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7548#L1289-3 assume !(0 == ~E_12~0); 7535#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7215#L566-39 assume 1 == ~m_pc~0; 7216#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7812#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7813#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7864#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8056#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8057#L585-39 assume !(1 == ~t1_pc~0); 7223#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 7224#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7426#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8367#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8096#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7789#L604-39 assume 1 == ~t2_pc~0; 7790#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7433#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7434#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7611#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7841#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7415#L623-39 assume 1 == ~t3_pc~0; 6821#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6823#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8075#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7266#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7267#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8017#L642-39 assume 1 == ~t4_pc~0; 7602#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7603#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7764#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7765#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8243#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7185#L661-39 assume 1 == ~t5_pc~0; 7186#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6830#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7796#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7797#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8077#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8078#L680-39 assume 1 == ~t6_pc~0; 6893#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6894#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8324#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7341#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7342#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8379#L699-39 assume 1 == ~t7_pc~0; 7771#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7503#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7504#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8082#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8320#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8317#L718-39 assume 1 == ~t8_pc~0; 7683#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7684#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8175#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8176#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 7924#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7902#L737-39 assume 1 == ~t9_pc~0; 7322#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7323#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6921#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6922#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8290#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8227#L756-39 assume !(1 == ~t10_pc~0); 7697#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 7698#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8366#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7582#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7583#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6942#L775-39 assume !(1 == ~t11_pc~0); 6944#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 7573#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7574#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7824#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7974#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7627#L794-39 assume !(1 == ~t12_pc~0); 7318#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 7319#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7412#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7413#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 6884#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6885#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8350#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8351#L1312-3 assume !(1 == ~T2_E~0); 8465#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8043#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8044#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7016#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6993#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6994#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7713#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7844#L1352-3 assume !(1 == ~T10_E~0); 7845#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8299#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8460#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8451#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6817#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6818#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7436#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7437#L1392-3 assume !(1 == ~E_6~0); 8151#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8417#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7811#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7096#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7097#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7727#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7728#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7104#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7105#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7170#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7171#L1787 assume !(0 == start_simulation_~tmp~3#1); 7815#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8359#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7081#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 6833#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 6834#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7422#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7423#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 8327#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 6987#L1768-2 [2022-12-13 19:05:25,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:25,953 INFO L85 PathProgramCache]: Analyzing trace with hash -1760586097, now seen corresponding path program 1 times [2022-12-13 19:05:25,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:25,954 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1555761935] [2022-12-13 19:05:25,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:25,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:25,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:26,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:26,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:26,005 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1555761935] [2022-12-13 19:05:26,005 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1555761935] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:26,006 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:26,006 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:26,006 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [862902627] [2022-12-13 19:05:26,006 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:26,007 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:26,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:26,007 INFO L85 PathProgramCache]: Analyzing trace with hash -1627028319, now seen corresponding path program 1 times [2022-12-13 19:05:26,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:26,007 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415393396] [2022-12-13 19:05:26,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:26,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:26,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:26,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:26,069 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:26,069 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415393396] [2022-12-13 19:05:26,069 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1415393396] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:26,069 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:26,069 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:26,069 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1657478022] [2022-12-13 19:05:26,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:26,070 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:26,070 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:26,071 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:26,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:26,071 INFO L87 Difference]: Start difference. First operand 1688 states and 2503 transitions. cyclomatic complexity: 816 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:26,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:26,097 INFO L93 Difference]: Finished difference Result 1688 states and 2502 transitions. [2022-12-13 19:05:26,097 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2502 transitions. [2022-12-13 19:05:26,103 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:26,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2502 transitions. [2022-12-13 19:05:26,107 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-12-13 19:05:26,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-12-13 19:05:26,108 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2502 transitions. [2022-12-13 19:05:26,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:26,110 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2022-12-13 19:05:26,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2502 transitions. [2022-12-13 19:05:26,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-12-13 19:05:26,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4822274881516588) internal successors, (2502), 1687 states have internal predecessors, (2502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:26,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2502 transitions. [2022-12-13 19:05:26,128 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2022-12-13 19:05:26,128 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:26,129 INFO L428 stractBuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2022-12-13 19:05:26,129 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 19:05:26,129 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2502 transitions. [2022-12-13 19:05:26,134 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:26,134 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:26,134 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:26,136 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:26,136 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:26,136 INFO L748 eck$LassoCheckResult]: Stem: 10434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 10435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11221#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11222#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11091#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 11092#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11184#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11484#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 11615#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11616#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10411#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10412#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11548#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10991#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10992#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10901#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10902#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11291#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10647#L1174 assume !(0 == ~M_E~0); 10648#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10501#L1179-1 assume !(0 == ~T2_E~0); 10409#L1184-1 assume !(0 == ~T3_E~0); 10410#L1189-1 assume !(0 == ~T4_E~0); 10450#L1194-1 assume !(0 == ~T5_E~0); 10541#L1199-1 assume !(0 == ~T6_E~0); 11417#L1204-1 assume !(0 == ~T7_E~0); 11336#L1209-1 assume !(0 == ~T8_E~0); 11337#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11760#L1219-1 assume !(0 == ~T10_E~0); 11846#L1224-1 assume !(0 == ~T11_E~0); 10766#L1229-1 assume !(0 == ~T12_E~0); 10341#L1234-1 assume !(0 == ~E_1~0); 10342#L1239-1 assume !(0 == ~E_2~0); 10374#L1244-1 assume !(0 == ~E_3~0); 10375#L1249-1 assume !(0 == ~E_4~0); 11011#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10271#L1259-1 assume !(0 == ~E_6~0); 10224#L1264-1 assume !(0 == ~E_7~0); 10225#L1269-1 assume !(0 == ~E_8~0); 11849#L1274-1 assume !(0 == ~E_9~0); 11787#L1279-1 assume !(0 == ~E_10~0); 10454#L1284-1 assume !(0 == ~E_11~0); 10455#L1289-1 assume !(0 == ~E_12~0); 11060#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11061#L566 assume 1 == ~m_pc~0; 10241#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10242#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11105#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11106#L1455 assume !(0 != activate_threads_~tmp~1#1); 10674#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10675#L585 assume 1 == ~t1_pc~0; 10338#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10339#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11475#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11476#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 11816#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11812#L604 assume !(1 == ~t2_pc~0); 11379#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11380#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10617#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10618#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11575#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11576#L623 assume 1 == ~t3_pc~0; 10850#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10203#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11448#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11449#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 11609#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10238#L642 assume !(1 == ~t4_pc~0); 10239#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10687#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10293#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10294#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 10315#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11393#L661 assume 1 == ~t5_pc~0; 10467#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10468#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11308#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11674#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 11424#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11425#L680 assume !(1 == ~t6_pc~0); 10883#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10884#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10608#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10609#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 11685#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11809#L699 assume 1 == ~t7_pc~0; 11272#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11273#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11507#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11166#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 11167#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11062#L718 assume !(1 == ~t8_pc~0); 11063#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10448#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10449#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10483#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 10484#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10614#L737 assume 1 == ~t9_pc~0; 11463#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10747#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10654#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10655#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 10921#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10922#L756 assume 1 == ~t10_pc~0; 11497#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11157#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11412#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11098#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 10726#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10727#L775 assume !(1 == ~t11_pc~0); 10980#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 10981#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11753#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10384#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10385#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 10562#L794 assume 1 == ~t12_pc~0; 10407#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10387#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10244#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10245#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 10527#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10995#L1307 assume !(1 == ~M_E~0); 10996#L1307-2 assume !(1 == ~T1_E~0); 11102#L1312-1 assume !(1 == ~T2_E~0); 11024#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11025#L1322-1 assume !(1 == ~T4_E~0); 10737#L1327-1 assume !(1 == ~T5_E~0); 10738#L1332-1 assume !(1 == ~T6_E~0); 11277#L1337-1 assume !(1 == ~T7_E~0); 11234#L1342-1 assume !(1 == ~T8_E~0); 11235#L1347-1 assume !(1 == ~T9_E~0); 11646#L1352-1 assume !(1 == ~T10_E~0); 11508#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10899#L1362-1 assume !(1 == ~T12_E~0); 10900#L1367-1 assume !(1 == ~E_1~0); 10542#L1372-1 assume !(1 == ~E_2~0); 10543#L1377-1 assume !(1 == ~E_3~0); 10835#L1382-1 assume !(1 == ~E_4~0); 10836#L1387-1 assume !(1 == ~E_5~0); 11381#L1392-1 assume !(1 == ~E_6~0); 10853#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10854#L1402-1 assume !(1 == ~E_8~0); 10557#L1407-1 assume !(1 == ~E_9~0); 10558#L1412-1 assume !(1 == ~E_10~0); 11570#L1417-1 assume !(1 == ~E_11~0); 11571#L1422-1 assume !(1 == ~E_12~0); 11806#L1427-1 assume { :end_inline_reset_delta_events } true; 10370#L1768-2 [2022-12-13 19:05:26,136 INFO L750 eck$LassoCheckResult]: Loop: 10370#L1768-2 assume !false; 10371#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11086#L1149 assume !false; 11453#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11627#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10744#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11553#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11622#L976 assume !(0 != eval_~tmp~0#1); 11053#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10787#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10788#L1174-3 assume !(0 == ~M_E~0); 11580#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11319#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11320#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11509#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11152#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10518#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10519#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10757#L1209-3 assume !(0 == ~T8_E~0); 10187#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10188#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10932#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 10933#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 10947#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10378#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10379#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10812#L1249-3 assume !(0 == ~E_4~0); 11264#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11756#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11364#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10382#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10383#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11786#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10930#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10931#L1289-3 assume !(0 == ~E_12~0); 10918#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10598#L566-39 assume 1 == ~m_pc~0; 10599#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11195#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11196#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11247#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11439#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11440#L585-39 assume !(1 == ~t1_pc~0); 10606#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 10607#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10809#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11750#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11479#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11172#L604-39 assume 1 == ~t2_pc~0; 11173#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10816#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10817#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10994#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11224#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10798#L623-39 assume 1 == ~t3_pc~0; 10204#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10206#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11458#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10649#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10650#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11400#L642-39 assume 1 == ~t4_pc~0; 10985#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10986#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11147#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11148#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11626#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10568#L661-39 assume !(1 == ~t5_pc~0); 10212#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 10213#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11179#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11180#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11460#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11461#L680-39 assume 1 == ~t6_pc~0; 10276#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10277#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11707#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10724#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10725#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11762#L699-39 assume 1 == ~t7_pc~0; 11154#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10886#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10887#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11465#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11703#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11700#L718-39 assume 1 == ~t8_pc~0; 11066#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11067#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11558#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11559#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 11307#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11285#L737-39 assume 1 == ~t9_pc~0; 10705#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10706#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10304#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10305#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11673#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11610#L756-39 assume !(1 == ~t10_pc~0); 11080#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 11081#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11749#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10965#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10966#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10325#L775-39 assume 1 == ~t11_pc~0; 10326#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10956#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10957#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11207#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11357#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11010#L794-39 assume 1 == ~t12_pc~0; 10708#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10702#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10795#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10796#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10267#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10268#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11733#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11734#L1312-3 assume !(1 == ~T2_E~0); 11848#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11426#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11427#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10399#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10376#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10377#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11096#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11227#L1352-3 assume !(1 == ~T10_E~0); 11228#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11682#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11843#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11834#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10200#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10201#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10819#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10820#L1392-3 assume !(1 == ~E_6~0); 11534#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11800#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11194#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10479#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10480#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 11110#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 11111#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10487#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10488#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10553#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10554#L1787 assume !(0 == start_simulation_~tmp~3#1); 11198#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11742#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10464#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10216#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 10217#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10805#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10806#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 11710#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 10370#L1768-2 [2022-12-13 19:05:26,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:26,137 INFO L85 PathProgramCache]: Analyzing trace with hash -1220156591, now seen corresponding path program 1 times [2022-12-13 19:05:26,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:26,137 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396768717] [2022-12-13 19:05:26,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:26,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:26,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:26,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:26,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:26,175 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396768717] [2022-12-13 19:05:26,175 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1396768717] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:26,175 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:26,175 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:26,175 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101361370] [2022-12-13 19:05:26,175 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:26,176 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:26,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:26,176 INFO L85 PathProgramCache]: Analyzing trace with hash -1994635518, now seen corresponding path program 2 times [2022-12-13 19:05:26,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:26,177 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893442183] [2022-12-13 19:05:26,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:26,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:26,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:26,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:26,240 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:26,240 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893442183] [2022-12-13 19:05:26,240 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1893442183] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:26,240 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:26,240 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:26,241 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1159827785] [2022-12-13 19:05:26,241 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:26,241 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:26,241 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:26,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:26,242 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:26,242 INFO L87 Difference]: Start difference. First operand 1688 states and 2502 transitions. cyclomatic complexity: 815 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:26,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:26,267 INFO L93 Difference]: Finished difference Result 1688 states and 2501 transitions. [2022-12-13 19:05:26,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2501 transitions. [2022-12-13 19:05:26,272 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:26,276 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2501 transitions. [2022-12-13 19:05:26,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-12-13 19:05:26,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-12-13 19:05:26,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2501 transitions. [2022-12-13 19:05:26,279 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:26,279 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2022-12-13 19:05:26,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2501 transitions. [2022-12-13 19:05:26,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-12-13 19:05:26,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4816350710900474) internal successors, (2501), 1687 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:26,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2501 transitions. [2022-12-13 19:05:26,298 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2022-12-13 19:05:26,299 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:26,299 INFO L428 stractBuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2022-12-13 19:05:26,299 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 19:05:26,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2501 transitions. [2022-12-13 19:05:26,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:26,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:26,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:26,306 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:26,306 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:26,306 INFO L748 eck$LassoCheckResult]: Stem: 13817#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 13818#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 14605#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14606#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14474#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 14475#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14567#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14869#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14998#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14999#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13794#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13795#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14931#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14374#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14375#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14284#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14285#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 14674#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14030#L1174 assume !(0 == ~M_E~0); 14031#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13886#L1179-1 assume !(0 == ~T2_E~0); 13792#L1184-1 assume !(0 == ~T3_E~0); 13793#L1189-1 assume !(0 == ~T4_E~0); 13833#L1194-1 assume !(0 == ~T5_E~0); 13926#L1199-1 assume !(0 == ~T6_E~0); 14800#L1204-1 assume !(0 == ~T7_E~0); 14719#L1209-1 assume !(0 == ~T8_E~0); 14720#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15143#L1219-1 assume !(0 == ~T10_E~0); 15229#L1224-1 assume !(0 == ~T11_E~0); 14151#L1229-1 assume !(0 == ~T12_E~0); 13724#L1234-1 assume !(0 == ~E_1~0); 13725#L1239-1 assume !(0 == ~E_2~0); 13759#L1244-1 assume !(0 == ~E_3~0); 13760#L1249-1 assume !(0 == ~E_4~0); 14394#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13654#L1259-1 assume !(0 == ~E_6~0); 13607#L1264-1 assume !(0 == ~E_7~0); 13608#L1269-1 assume !(0 == ~E_8~0); 15232#L1274-1 assume !(0 == ~E_9~0); 15171#L1279-1 assume !(0 == ~E_10~0); 13837#L1284-1 assume !(0 == ~E_11~0); 13838#L1289-1 assume !(0 == ~E_12~0); 14443#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14444#L566 assume 1 == ~m_pc~0; 13624#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13625#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14488#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14489#L1455 assume !(0 != activate_threads_~tmp~1#1); 14057#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14058#L585 assume 1 == ~t1_pc~0; 13721#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13722#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14858#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14859#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 15199#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15195#L604 assume !(1 == ~t2_pc~0); 14762#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14763#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14005#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14006#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14960#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14961#L623 assume 1 == ~t3_pc~0; 14233#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13586#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14834#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14835#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 14992#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13621#L642 assume !(1 == ~t4_pc~0); 13622#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14070#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13682#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13683#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 13698#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14776#L661 assume 1 == ~t5_pc~0; 13850#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13851#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14691#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15057#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 14809#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14810#L680 assume !(1 == ~t6_pc~0); 14266#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14267#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13994#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13995#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 15068#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15193#L699 assume 1 == ~t7_pc~0; 14655#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14656#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14890#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14549#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 14550#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14445#L718 assume !(1 == ~t8_pc~0); 14446#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13831#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13832#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13866#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 13867#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13997#L737 assume 1 == ~t9_pc~0; 14848#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14132#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14037#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14038#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 14304#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14305#L756 assume 1 == ~t10_pc~0; 14880#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14541#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14795#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14481#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 14109#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14110#L775 assume !(1 == ~t11_pc~0); 14363#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 14364#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15136#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13767#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13768#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13945#L794 assume 1 == ~t12_pc~0; 13791#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13770#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13629#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13630#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 13912#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14378#L1307 assume !(1 == ~M_E~0); 14379#L1307-2 assume !(1 == ~T1_E~0); 14485#L1312-1 assume !(1 == ~T2_E~0); 14407#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14408#L1322-1 assume !(1 == ~T4_E~0); 14120#L1327-1 assume !(1 == ~T5_E~0); 14121#L1332-1 assume !(1 == ~T6_E~0); 14660#L1337-1 assume !(1 == ~T7_E~0); 14618#L1342-1 assume !(1 == ~T8_E~0); 14619#L1347-1 assume !(1 == ~T9_E~0); 15029#L1352-1 assume !(1 == ~T10_E~0); 14891#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14282#L1362-1 assume !(1 == ~T12_E~0); 14283#L1367-1 assume !(1 == ~E_1~0); 13927#L1372-1 assume !(1 == ~E_2~0); 13928#L1377-1 assume !(1 == ~E_3~0); 14218#L1382-1 assume !(1 == ~E_4~0); 14219#L1387-1 assume !(1 == ~E_5~0); 14764#L1392-1 assume !(1 == ~E_6~0); 14238#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14239#L1402-1 assume !(1 == ~E_8~0); 13943#L1407-1 assume !(1 == ~E_9~0); 13944#L1412-1 assume !(1 == ~E_10~0); 14953#L1417-1 assume !(1 == ~E_11~0); 14954#L1422-1 assume !(1 == ~E_12~0); 15189#L1427-1 assume { :end_inline_reset_delta_events } true; 13753#L1768-2 [2022-12-13 19:05:26,307 INFO L750 eck$LassoCheckResult]: Loop: 13753#L1768-2 assume !false; 13754#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14469#L1149 assume !false; 14837#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15010#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14127#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14936#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15005#L976 assume !(0 != eval_~tmp~0#1); 14436#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14170#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14171#L1174-3 assume !(0 == ~M_E~0); 14963#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14702#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14703#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14893#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14535#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13904#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13905#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14140#L1209-3 assume !(0 == ~T8_E~0); 13570#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13571#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14315#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14316#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14331#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13761#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13762#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14198#L1249-3 assume !(0 == ~E_4~0); 14647#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15139#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14747#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13765#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13766#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15169#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14313#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14314#L1289-3 assume !(0 == ~E_12~0); 14301#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13978#L566-39 assume 1 == ~m_pc~0; 13979#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14578#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14579#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14630#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14822#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14823#L585-39 assume !(1 == ~t1_pc~0); 13989#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 13990#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14192#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15133#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14862#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14555#L604-39 assume 1 == ~t2_pc~0; 14556#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14199#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14200#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14377#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14607#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14181#L623-39 assume 1 == ~t3_pc~0; 13587#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13589#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14841#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14032#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14033#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14783#L642-39 assume 1 == ~t4_pc~0; 14368#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14369#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14530#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14531#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15009#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13951#L661-39 assume 1 == ~t5_pc~0; 13952#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13596#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14562#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14563#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14843#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14844#L680-39 assume 1 == ~t6_pc~0; 13659#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13660#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15090#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14107#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14108#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15145#L699-39 assume 1 == ~t7_pc~0; 14537#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14269#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14270#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14847#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15086#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15083#L718-39 assume 1 == ~t8_pc~0; 14449#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14450#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14941#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14942#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 14690#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14668#L737-39 assume 1 == ~t9_pc~0; 14088#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14089#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13687#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13688#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15056#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14993#L756-39 assume 1 == ~t10_pc~0; 14994#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14464#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15132#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14348#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14349#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13708#L775-39 assume 1 == ~t11_pc~0; 13709#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14339#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14340#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14590#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14740#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14393#L794-39 assume !(1 == ~t12_pc~0); 14084#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 14085#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14178#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14179#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13650#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13651#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15116#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15117#L1312-3 assume !(1 == ~T2_E~0); 15231#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14807#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14808#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13782#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13757#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13758#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14479#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14610#L1352-3 assume !(1 == ~T10_E~0); 14611#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15065#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15226#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15217#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13580#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13581#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14202#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14203#L1392-3 assume !(1 == ~E_6~0); 14917#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15183#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14577#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13862#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13863#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14493#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 14494#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 13870#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13871#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 13936#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 13937#L1787 assume !(0 == start_simulation_~tmp~3#1); 14580#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15125#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13847#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 13599#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 13600#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14188#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14189#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 15093#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 13753#L1768-2 [2022-12-13 19:05:26,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:26,307 INFO L85 PathProgramCache]: Analyzing trace with hash -1064176049, now seen corresponding path program 1 times [2022-12-13 19:05:26,307 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:26,307 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049387712] [2022-12-13 19:05:26,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:26,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:26,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:26,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:26,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:26,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049387712] [2022-12-13 19:05:26,345 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049387712] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:26,345 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:26,345 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:26,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043882289] [2022-12-13 19:05:26,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:26,346 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:26,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:26,346 INFO L85 PathProgramCache]: Analyzing trace with hash 95558179, now seen corresponding path program 1 times [2022-12-13 19:05:26,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:26,346 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738006058] [2022-12-13 19:05:26,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:26,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:26,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:26,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:26,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:26,394 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1738006058] [2022-12-13 19:05:26,394 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1738006058] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:26,395 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:26,395 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:26,395 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1868463580] [2022-12-13 19:05:26,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:26,395 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:26,395 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:26,396 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:26,396 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:26,396 INFO L87 Difference]: Start difference. First operand 1688 states and 2501 transitions. cyclomatic complexity: 814 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:26,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:26,420 INFO L93 Difference]: Finished difference Result 1688 states and 2500 transitions. [2022-12-13 19:05:26,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2500 transitions. [2022-12-13 19:05:26,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:26,431 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2500 transitions. [2022-12-13 19:05:26,431 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-12-13 19:05:26,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-12-13 19:05:26,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2500 transitions. [2022-12-13 19:05:26,434 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:26,434 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2022-12-13 19:05:26,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2500 transitions. [2022-12-13 19:05:26,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-12-13 19:05:26,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.481042654028436) internal successors, (2500), 1687 states have internal predecessors, (2500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:26,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2500 transitions. [2022-12-13 19:05:26,452 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2022-12-13 19:05:26,452 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:26,453 INFO L428 stractBuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2022-12-13 19:05:26,453 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 19:05:26,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2500 transitions. [2022-12-13 19:05:26,458 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:26,458 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:26,458 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:26,459 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:26,459 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:26,460 INFO L748 eck$LassoCheckResult]: Stem: 17200#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 17201#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 17987#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17988#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17857#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 17858#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17950#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18250#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18381#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18382#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17177#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17178#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18314#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17757#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17758#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17667#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17668#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18057#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17413#L1174 assume !(0 == ~M_E~0); 17414#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17269#L1179-1 assume !(0 == ~T2_E~0); 17175#L1184-1 assume !(0 == ~T3_E~0); 17176#L1189-1 assume !(0 == ~T4_E~0); 17216#L1194-1 assume !(0 == ~T5_E~0); 17307#L1199-1 assume !(0 == ~T6_E~0); 18183#L1204-1 assume !(0 == ~T7_E~0); 18102#L1209-1 assume !(0 == ~T8_E~0); 18103#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18526#L1219-1 assume !(0 == ~T10_E~0); 18612#L1224-1 assume !(0 == ~T11_E~0); 17532#L1229-1 assume !(0 == ~T12_E~0); 17107#L1234-1 assume !(0 == ~E_1~0); 17108#L1239-1 assume !(0 == ~E_2~0); 17142#L1244-1 assume !(0 == ~E_3~0); 17143#L1249-1 assume !(0 == ~E_4~0); 17777#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17037#L1259-1 assume !(0 == ~E_6~0); 16990#L1264-1 assume !(0 == ~E_7~0); 16991#L1269-1 assume !(0 == ~E_8~0); 18615#L1274-1 assume !(0 == ~E_9~0); 18554#L1279-1 assume !(0 == ~E_10~0); 17220#L1284-1 assume !(0 == ~E_11~0); 17221#L1289-1 assume !(0 == ~E_12~0); 17826#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17827#L566 assume 1 == ~m_pc~0; 17007#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17008#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17871#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17872#L1455 assume !(0 != activate_threads_~tmp~1#1); 17440#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17441#L585 assume 1 == ~t1_pc~0; 17104#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17105#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18241#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18242#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 18582#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18578#L604 assume !(1 == ~t2_pc~0); 18145#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18146#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17388#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17389#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18343#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18344#L623 assume 1 == ~t3_pc~0; 17616#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16969#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18217#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18218#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 18375#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17004#L642 assume !(1 == ~t4_pc~0); 17005#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17453#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17062#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17063#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 17081#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18159#L661 assume 1 == ~t5_pc~0; 17233#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17234#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18074#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18440#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 18192#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18193#L680 assume !(1 == ~t6_pc~0); 17649#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17650#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17374#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17375#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 18451#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18575#L699 assume 1 == ~t7_pc~0; 18038#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18039#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18273#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17932#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 17933#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17828#L718 assume !(1 == ~t8_pc~0); 17829#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17214#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17215#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17249#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 17250#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17380#L737 assume 1 == ~t9_pc~0; 18231#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17513#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17420#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17421#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 17687#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17688#L756 assume 1 == ~t10_pc~0; 18263#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17923#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18178#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17864#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 17492#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17493#L775 assume !(1 == ~t11_pc~0); 17746#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 17747#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18519#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17150#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17151#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17328#L794 assume 1 == ~t12_pc~0; 17174#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17153#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17012#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17013#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 17295#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17761#L1307 assume !(1 == ~M_E~0); 17762#L1307-2 assume !(1 == ~T1_E~0); 17868#L1312-1 assume !(1 == ~T2_E~0); 17790#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17791#L1322-1 assume !(1 == ~T4_E~0); 17503#L1327-1 assume !(1 == ~T5_E~0); 17504#L1332-1 assume !(1 == ~T6_E~0); 18043#L1337-1 assume !(1 == ~T7_E~0); 18000#L1342-1 assume !(1 == ~T8_E~0); 18001#L1347-1 assume !(1 == ~T9_E~0); 18412#L1352-1 assume !(1 == ~T10_E~0); 18274#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17665#L1362-1 assume !(1 == ~T12_E~0); 17666#L1367-1 assume !(1 == ~E_1~0); 17308#L1372-1 assume !(1 == ~E_2~0); 17309#L1377-1 assume !(1 == ~E_3~0); 17601#L1382-1 assume !(1 == ~E_4~0); 17602#L1387-1 assume !(1 == ~E_5~0); 18147#L1392-1 assume !(1 == ~E_6~0); 17621#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17622#L1402-1 assume !(1 == ~E_8~0); 17323#L1407-1 assume !(1 == ~E_9~0); 17324#L1412-1 assume !(1 == ~E_10~0); 18336#L1417-1 assume !(1 == ~E_11~0); 18337#L1422-1 assume !(1 == ~E_12~0); 18572#L1427-1 assume { :end_inline_reset_delta_events } true; 17136#L1768-2 [2022-12-13 19:05:26,460 INFO L750 eck$LassoCheckResult]: Loop: 17136#L1768-2 assume !false; 17137#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17852#L1149 assume !false; 18219#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18393#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17510#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18319#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18388#L976 assume !(0 != eval_~tmp~0#1); 17819#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17553#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17554#L1174-3 assume !(0 == ~M_E~0); 18346#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18085#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18086#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18275#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17918#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17287#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17288#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17523#L1209-3 assume !(0 == ~T8_E~0); 16953#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16954#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17698#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17699#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17713#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17144#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17145#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17578#L1249-3 assume !(0 == ~E_4~0); 18030#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18522#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18130#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17148#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17149#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18552#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17696#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 17697#L1289-3 assume !(0 == ~E_12~0); 17684#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17364#L566-39 assume 1 == ~m_pc~0; 17365#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17961#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17962#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18013#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18205#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18206#L585-39 assume !(1 == ~t1_pc~0); 17372#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 17373#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17575#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18516#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18245#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17938#L604-39 assume 1 == ~t2_pc~0; 17939#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17582#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17583#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17760#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17992#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17564#L623-39 assume 1 == ~t3_pc~0; 16972#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16974#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18224#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17415#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17416#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18166#L642-39 assume 1 == ~t4_pc~0; 17753#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17754#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17913#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17914#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18392#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17336#L661-39 assume !(1 == ~t5_pc~0); 16978#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 16979#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17945#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17946#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18227#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18228#L680-39 assume 1 == ~t6_pc~0; 17044#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17045#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18473#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17490#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17491#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18528#L699-39 assume 1 == ~t7_pc~0; 17920#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17652#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17653#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18230#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18467#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18465#L718-39 assume 1 == ~t8_pc~0; 17832#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17833#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18323#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18324#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 18073#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18051#L737-39 assume !(1 == ~t9_pc~0); 17473#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 17472#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17069#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17070#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18439#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18376#L756-39 assume !(1 == ~t10_pc~0); 17846#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 17847#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18515#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17731#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17732#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17091#L775-39 assume 1 == ~t11_pc~0; 17092#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17722#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17723#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17973#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18123#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17776#L794-39 assume 1 == ~t12_pc~0; 17474#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17468#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17559#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17560#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17033#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17034#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18499#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18500#L1312-3 assume !(1 == ~T2_E~0); 18614#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18190#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18191#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17163#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17140#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17141#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17862#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17990#L1352-3 assume !(1 == ~T10_E~0); 17991#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18448#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18609#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18600#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16963#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16964#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17585#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17586#L1392-3 assume !(1 == ~E_6~0); 18300#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18566#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17960#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17245#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17246#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17875#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17876#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 17253#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17254#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 17318#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 17319#L1787 assume !(0 == start_simulation_~tmp~3#1); 17963#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18508#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17230#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 16982#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 16983#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17571#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17572#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 18476#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 17136#L1768-2 [2022-12-13 19:05:26,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:26,460 INFO L85 PathProgramCache]: Analyzing trace with hash -1474786415, now seen corresponding path program 1 times [2022-12-13 19:05:26,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:26,461 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396434223] [2022-12-13 19:05:26,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:26,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:26,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:26,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:26,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:26,509 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396434223] [2022-12-13 19:05:26,509 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1396434223] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:26,509 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:26,510 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:26,510 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1438911431] [2022-12-13 19:05:26,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:26,510 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:26,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:26,511 INFO L85 PathProgramCache]: Analyzing trace with hash -174909599, now seen corresponding path program 1 times [2022-12-13 19:05:26,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:26,511 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935656310] [2022-12-13 19:05:26,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:26,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:26,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:26,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:26,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:26,557 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [935656310] [2022-12-13 19:05:26,557 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [935656310] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:26,557 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:26,557 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:26,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [127884837] [2022-12-13 19:05:26,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:26,558 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:26,558 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:26,558 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:26,558 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:26,559 INFO L87 Difference]: Start difference. First operand 1688 states and 2500 transitions. cyclomatic complexity: 813 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:26,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:26,591 INFO L93 Difference]: Finished difference Result 1688 states and 2499 transitions. [2022-12-13 19:05:26,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2499 transitions. [2022-12-13 19:05:26,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:26,605 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2499 transitions. [2022-12-13 19:05:26,605 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-12-13 19:05:26,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-12-13 19:05:26,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2499 transitions. [2022-12-13 19:05:26,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:26,607 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2022-12-13 19:05:26,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2499 transitions. [2022-12-13 19:05:26,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-12-13 19:05:26,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4804502369668247) internal successors, (2499), 1687 states have internal predecessors, (2499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:26,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2499 transitions. [2022-12-13 19:05:26,625 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2022-12-13 19:05:26,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:26,626 INFO L428 stractBuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2022-12-13 19:05:26,626 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 19:05:26,626 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2499 transitions. [2022-12-13 19:05:26,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:26,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:26,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:26,634 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:26,634 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:26,635 INFO L748 eck$LassoCheckResult]: Stem: 20583#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 20584#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21370#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21371#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21240#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 21241#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21333#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21633#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21764#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21765#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20560#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20561#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21697#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21140#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21141#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21050#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21051#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21440#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20796#L1174 assume !(0 == ~M_E~0); 20797#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20650#L1179-1 assume !(0 == ~T2_E~0); 20558#L1184-1 assume !(0 == ~T3_E~0); 20559#L1189-1 assume !(0 == ~T4_E~0); 20599#L1194-1 assume !(0 == ~T5_E~0); 20690#L1199-1 assume !(0 == ~T6_E~0); 21566#L1204-1 assume !(0 == ~T7_E~0); 21485#L1209-1 assume !(0 == ~T8_E~0); 21486#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21909#L1219-1 assume !(0 == ~T10_E~0); 21995#L1224-1 assume !(0 == ~T11_E~0); 20915#L1229-1 assume !(0 == ~T12_E~0); 20490#L1234-1 assume !(0 == ~E_1~0); 20491#L1239-1 assume !(0 == ~E_2~0); 20523#L1244-1 assume !(0 == ~E_3~0); 20524#L1249-1 assume !(0 == ~E_4~0); 21160#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 20420#L1259-1 assume !(0 == ~E_6~0); 20373#L1264-1 assume !(0 == ~E_7~0); 20374#L1269-1 assume !(0 == ~E_8~0); 21998#L1274-1 assume !(0 == ~E_9~0); 21936#L1279-1 assume !(0 == ~E_10~0); 20603#L1284-1 assume !(0 == ~E_11~0); 20604#L1289-1 assume !(0 == ~E_12~0); 21209#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21210#L566 assume 1 == ~m_pc~0; 20390#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20391#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21254#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21255#L1455 assume !(0 != activate_threads_~tmp~1#1); 20823#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20824#L585 assume 1 == ~t1_pc~0; 20487#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20488#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21624#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21625#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 21965#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21961#L604 assume !(1 == ~t2_pc~0); 21528#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21529#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20766#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20767#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21724#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21725#L623 assume 1 == ~t3_pc~0; 20999#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20352#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21597#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21598#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 21758#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20387#L642 assume !(1 == ~t4_pc~0); 20388#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20836#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20442#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20443#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 20464#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21542#L661 assume 1 == ~t5_pc~0; 20616#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20617#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21457#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21823#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 21573#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21574#L680 assume !(1 == ~t6_pc~0); 21032#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21033#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20757#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20758#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 21834#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21958#L699 assume 1 == ~t7_pc~0; 21421#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21422#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21656#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21315#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 21316#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21211#L718 assume !(1 == ~t8_pc~0); 21212#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20597#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20598#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20632#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 20633#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20763#L737 assume 1 == ~t9_pc~0; 21612#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20896#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20803#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20804#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 21070#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21071#L756 assume 1 == ~t10_pc~0; 21646#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21306#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21561#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21247#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 20875#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20876#L775 assume !(1 == ~t11_pc~0); 21129#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21130#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21902#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20533#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20534#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20711#L794 assume 1 == ~t12_pc~0; 20556#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20536#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20393#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20394#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 20676#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21144#L1307 assume !(1 == ~M_E~0); 21145#L1307-2 assume !(1 == ~T1_E~0); 21251#L1312-1 assume !(1 == ~T2_E~0); 21173#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21174#L1322-1 assume !(1 == ~T4_E~0); 20886#L1327-1 assume !(1 == ~T5_E~0); 20887#L1332-1 assume !(1 == ~T6_E~0); 21426#L1337-1 assume !(1 == ~T7_E~0); 21383#L1342-1 assume !(1 == ~T8_E~0); 21384#L1347-1 assume !(1 == ~T9_E~0); 21795#L1352-1 assume !(1 == ~T10_E~0); 21657#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21048#L1362-1 assume !(1 == ~T12_E~0); 21049#L1367-1 assume !(1 == ~E_1~0); 20691#L1372-1 assume !(1 == ~E_2~0); 20692#L1377-1 assume !(1 == ~E_3~0); 20984#L1382-1 assume !(1 == ~E_4~0); 20985#L1387-1 assume !(1 == ~E_5~0); 21530#L1392-1 assume !(1 == ~E_6~0); 21002#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 21003#L1402-1 assume !(1 == ~E_8~0); 20706#L1407-1 assume !(1 == ~E_9~0); 20707#L1412-1 assume !(1 == ~E_10~0); 21719#L1417-1 assume !(1 == ~E_11~0); 21720#L1422-1 assume !(1 == ~E_12~0); 21955#L1427-1 assume { :end_inline_reset_delta_events } true; 20519#L1768-2 [2022-12-13 19:05:26,635 INFO L750 eck$LassoCheckResult]: Loop: 20519#L1768-2 assume !false; 20520#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21235#L1149 assume !false; 21602#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21776#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20893#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21702#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21771#L976 assume !(0 != eval_~tmp~0#1); 21202#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20936#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20937#L1174-3 assume !(0 == ~M_E~0); 21729#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21468#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21469#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21658#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21301#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20667#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20668#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20906#L1209-3 assume !(0 == ~T8_E~0); 20336#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20337#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21081#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21082#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21096#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20527#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20528#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20961#L1249-3 assume !(0 == ~E_4~0); 21413#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21905#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21513#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20531#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20532#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21935#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21079#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21080#L1289-3 assume !(0 == ~E_12~0); 21067#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20747#L566-39 assume 1 == ~m_pc~0; 20748#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21344#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21345#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21396#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21588#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21589#L585-39 assume !(1 == ~t1_pc~0); 20755#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 20756#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20958#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21899#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21628#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21321#L604-39 assume 1 == ~t2_pc~0; 21322#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20965#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20966#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21143#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21373#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20947#L623-39 assume 1 == ~t3_pc~0; 20353#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20355#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21607#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20798#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20799#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21549#L642-39 assume !(1 == ~t4_pc~0); 21136#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 21135#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21296#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21297#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21775#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20717#L661-39 assume !(1 == ~t5_pc~0); 20361#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 20362#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21328#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21329#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21609#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21610#L680-39 assume 1 == ~t6_pc~0; 20425#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20426#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21856#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20873#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20874#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21911#L699-39 assume 1 == ~t7_pc~0; 21303#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21035#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21036#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21614#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21852#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21849#L718-39 assume !(1 == ~t8_pc~0); 21217#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 21216#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21707#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21708#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 21456#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21434#L737-39 assume 1 == ~t9_pc~0; 20854#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20855#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20453#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20454#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21822#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21759#L756-39 assume 1 == ~t10_pc~0; 21760#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21230#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21898#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21114#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21115#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20474#L775-39 assume 1 == ~t11_pc~0; 20475#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21105#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21106#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21356#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21506#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21159#L794-39 assume !(1 == ~t12_pc~0); 20850#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 20851#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20944#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20945#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20416#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20417#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21882#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21883#L1312-3 assume !(1 == ~T2_E~0); 21997#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21575#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21576#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20548#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20525#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20526#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21245#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21376#L1352-3 assume !(1 == ~T10_E~0); 21377#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21831#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 21992#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21983#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20349#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20350#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20968#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20969#L1392-3 assume !(1 == ~E_6~0); 21683#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21949#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21343#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20628#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20629#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21259#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21260#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 20636#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20637#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20702#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 20703#L1787 assume !(0 == start_simulation_~tmp~3#1); 21347#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21891#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20613#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20365#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 20366#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20954#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20955#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 21859#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 20519#L1768-2 [2022-12-13 19:05:26,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:26,636 INFO L85 PathProgramCache]: Analyzing trace with hash 313083407, now seen corresponding path program 1 times [2022-12-13 19:05:26,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:26,636 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532587221] [2022-12-13 19:05:26,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:26,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:26,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:26,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:26,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:26,683 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1532587221] [2022-12-13 19:05:26,683 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1532587221] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:26,683 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:26,684 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:26,684 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1119832426] [2022-12-13 19:05:26,684 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:26,684 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:26,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:26,685 INFO L85 PathProgramCache]: Analyzing trace with hash 1228761792, now seen corresponding path program 1 times [2022-12-13 19:05:26,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:26,685 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109487074] [2022-12-13 19:05:26,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:26,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:26,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:26,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:26,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:26,737 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [109487074] [2022-12-13 19:05:26,737 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [109487074] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:26,737 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:26,737 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:26,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [169441539] [2022-12-13 19:05:26,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:26,738 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:26,738 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:26,738 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:26,739 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:26,739 INFO L87 Difference]: Start difference. First operand 1688 states and 2499 transitions. cyclomatic complexity: 812 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:26,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:26,766 INFO L93 Difference]: Finished difference Result 1688 states and 2498 transitions. [2022-12-13 19:05:26,766 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2498 transitions. [2022-12-13 19:05:26,773 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:26,780 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2498 transitions. [2022-12-13 19:05:26,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-12-13 19:05:26,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-12-13 19:05:26,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2498 transitions. [2022-12-13 19:05:26,785 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:26,785 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2022-12-13 19:05:26,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2498 transitions. [2022-12-13 19:05:26,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-12-13 19:05:26,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4798578199052133) internal successors, (2498), 1687 states have internal predecessors, (2498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:26,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2498 transitions. [2022-12-13 19:05:26,813 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2022-12-13 19:05:26,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:26,814 INFO L428 stractBuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2022-12-13 19:05:26,814 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 19:05:26,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2498 transitions. [2022-12-13 19:05:26,842 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:26,842 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:26,842 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:26,843 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:26,843 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:26,843 INFO L748 eck$LassoCheckResult]: Stem: 23966#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 23967#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 24753#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24754#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24623#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 24624#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24716#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25016#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25147#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25148#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23943#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23944#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25080#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24523#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24524#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24433#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24434#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24823#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24179#L1174 assume !(0 == ~M_E~0); 24180#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24033#L1179-1 assume !(0 == ~T2_E~0); 23941#L1184-1 assume !(0 == ~T3_E~0); 23942#L1189-1 assume !(0 == ~T4_E~0); 23982#L1194-1 assume !(0 == ~T5_E~0); 24073#L1199-1 assume !(0 == ~T6_E~0); 24949#L1204-1 assume !(0 == ~T7_E~0); 24868#L1209-1 assume !(0 == ~T8_E~0); 24869#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25292#L1219-1 assume !(0 == ~T10_E~0); 25378#L1224-1 assume !(0 == ~T11_E~0); 24298#L1229-1 assume !(0 == ~T12_E~0); 23873#L1234-1 assume !(0 == ~E_1~0); 23874#L1239-1 assume !(0 == ~E_2~0); 23906#L1244-1 assume !(0 == ~E_3~0); 23907#L1249-1 assume !(0 == ~E_4~0); 24543#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 23803#L1259-1 assume !(0 == ~E_6~0); 23756#L1264-1 assume !(0 == ~E_7~0); 23757#L1269-1 assume !(0 == ~E_8~0); 25381#L1274-1 assume !(0 == ~E_9~0); 25319#L1279-1 assume !(0 == ~E_10~0); 23986#L1284-1 assume !(0 == ~E_11~0); 23987#L1289-1 assume !(0 == ~E_12~0); 24592#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24593#L566 assume 1 == ~m_pc~0; 23773#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23774#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24637#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24638#L1455 assume !(0 != activate_threads_~tmp~1#1); 24206#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24207#L585 assume 1 == ~t1_pc~0; 23870#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23871#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25007#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25008#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 25348#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25344#L604 assume !(1 == ~t2_pc~0); 24911#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24912#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24149#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24150#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25107#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25108#L623 assume 1 == ~t3_pc~0; 24382#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23735#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24980#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24981#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 25141#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23770#L642 assume !(1 == ~t4_pc~0); 23771#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24219#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23825#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23826#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 23847#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24925#L661 assume 1 == ~t5_pc~0; 23999#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24000#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24840#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25206#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 24956#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24957#L680 assume !(1 == ~t6_pc~0); 24415#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24416#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24140#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24141#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 25217#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25341#L699 assume 1 == ~t7_pc~0; 24804#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24805#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25039#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24698#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 24699#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24594#L718 assume !(1 == ~t8_pc~0); 24595#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23980#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23981#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24015#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 24016#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24146#L737 assume 1 == ~t9_pc~0; 24995#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24279#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24186#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24187#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 24453#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24454#L756 assume 1 == ~t10_pc~0; 25029#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24689#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24944#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24630#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 24258#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24259#L775 assume !(1 == ~t11_pc~0); 24512#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24513#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25285#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23916#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23917#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24094#L794 assume 1 == ~t12_pc~0; 23939#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23919#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23776#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23777#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 24059#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24527#L1307 assume !(1 == ~M_E~0); 24528#L1307-2 assume !(1 == ~T1_E~0); 24634#L1312-1 assume !(1 == ~T2_E~0); 24556#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24557#L1322-1 assume !(1 == ~T4_E~0); 24269#L1327-1 assume !(1 == ~T5_E~0); 24270#L1332-1 assume !(1 == ~T6_E~0); 24809#L1337-1 assume !(1 == ~T7_E~0); 24766#L1342-1 assume !(1 == ~T8_E~0); 24767#L1347-1 assume !(1 == ~T9_E~0); 25178#L1352-1 assume !(1 == ~T10_E~0); 25040#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24431#L1362-1 assume !(1 == ~T12_E~0); 24432#L1367-1 assume !(1 == ~E_1~0); 24074#L1372-1 assume !(1 == ~E_2~0); 24075#L1377-1 assume !(1 == ~E_3~0); 24367#L1382-1 assume !(1 == ~E_4~0); 24368#L1387-1 assume !(1 == ~E_5~0); 24913#L1392-1 assume !(1 == ~E_6~0); 24385#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 24386#L1402-1 assume !(1 == ~E_8~0); 24089#L1407-1 assume !(1 == ~E_9~0); 24090#L1412-1 assume !(1 == ~E_10~0); 25102#L1417-1 assume !(1 == ~E_11~0); 25103#L1422-1 assume !(1 == ~E_12~0); 25338#L1427-1 assume { :end_inline_reset_delta_events } true; 23902#L1768-2 [2022-12-13 19:05:26,844 INFO L750 eck$LassoCheckResult]: Loop: 23902#L1768-2 assume !false; 23903#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24618#L1149 assume !false; 24985#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25159#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24276#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25085#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 25154#L976 assume !(0 != eval_~tmp~0#1); 24585#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24319#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24320#L1174-3 assume !(0 == ~M_E~0); 25112#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24851#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24852#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25041#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24684#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24050#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24051#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24289#L1209-3 assume !(0 == ~T8_E~0); 23719#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23720#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24464#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24465#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24479#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23910#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23911#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24344#L1249-3 assume !(0 == ~E_4~0); 24796#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25288#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24896#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23914#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23915#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25318#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24462#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24463#L1289-3 assume !(0 == ~E_12~0); 24450#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24130#L566-39 assume 1 == ~m_pc~0; 24131#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24727#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24728#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24779#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24971#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24972#L585-39 assume !(1 == ~t1_pc~0); 24138#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 24139#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24341#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25282#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25011#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24704#L604-39 assume 1 == ~t2_pc~0; 24705#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24348#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24349#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24526#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24756#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24330#L623-39 assume 1 == ~t3_pc~0; 23736#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23738#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24990#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24181#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24182#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24932#L642-39 assume 1 == ~t4_pc~0; 24517#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24518#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24679#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24680#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25158#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24100#L661-39 assume !(1 == ~t5_pc~0); 23744#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 23745#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24711#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24712#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24992#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24993#L680-39 assume 1 == ~t6_pc~0; 23808#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23809#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25239#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24256#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24257#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25294#L699-39 assume 1 == ~t7_pc~0; 24686#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24418#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24419#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24997#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25235#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25232#L718-39 assume 1 == ~t8_pc~0; 24598#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24599#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25090#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25091#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 24839#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24817#L737-39 assume 1 == ~t9_pc~0; 24237#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24238#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23836#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23837#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25205#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25142#L756-39 assume !(1 == ~t10_pc~0); 24612#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 24613#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25281#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24497#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24498#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23857#L775-39 assume 1 == ~t11_pc~0; 23858#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24488#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24489#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24739#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24889#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24542#L794-39 assume 1 == ~t12_pc~0; 24240#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24234#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24327#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24328#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 23799#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23800#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25265#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25266#L1312-3 assume !(1 == ~T2_E~0); 25380#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24958#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24959#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23931#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23908#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23909#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24628#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24759#L1352-3 assume !(1 == ~T10_E~0); 24760#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25214#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25375#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25366#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23732#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23733#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24351#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24352#L1392-3 assume !(1 == ~E_6~0); 25066#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25332#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24726#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24011#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24012#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24642#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24643#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 24019#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24020#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24085#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 24086#L1787 assume !(0 == start_simulation_~tmp~3#1); 24730#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25274#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 23996#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 23748#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 23749#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24337#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24338#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 25242#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 23902#L1768-2 [2022-12-13 19:05:26,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:26,844 INFO L85 PathProgramCache]: Analyzing trace with hash -1846000687, now seen corresponding path program 1 times [2022-12-13 19:05:26,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:26,844 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679607207] [2022-12-13 19:05:26,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:26,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:26,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:26,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:26,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:26,878 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1679607207] [2022-12-13 19:05:26,879 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1679607207] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:26,879 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:26,879 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:26,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767893519] [2022-12-13 19:05:26,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:26,879 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:26,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:26,880 INFO L85 PathProgramCache]: Analyzing trace with hash -1994635518, now seen corresponding path program 3 times [2022-12-13 19:05:26,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:26,880 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013485072] [2022-12-13 19:05:26,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:26,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:26,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:26,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:26,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:26,935 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013485072] [2022-12-13 19:05:26,935 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2013485072] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:26,935 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:26,935 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:26,935 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257939625] [2022-12-13 19:05:26,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:26,936 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:26,936 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:26,936 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:26,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:26,937 INFO L87 Difference]: Start difference. First operand 1688 states and 2498 transitions. cyclomatic complexity: 811 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:26,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:26,965 INFO L93 Difference]: Finished difference Result 1688 states and 2497 transitions. [2022-12-13 19:05:26,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2497 transitions. [2022-12-13 19:05:26,972 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:26,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2497 transitions. [2022-12-13 19:05:26,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-12-13 19:05:26,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-12-13 19:05:26,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2497 transitions. [2022-12-13 19:05:26,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:26,981 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2022-12-13 19:05:26,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2497 transitions. [2022-12-13 19:05:26,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-12-13 19:05:26,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4792654028436019) internal successors, (2497), 1687 states have internal predecessors, (2497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:27,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2497 transitions. [2022-12-13 19:05:27,000 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2022-12-13 19:05:27,000 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:27,001 INFO L428 stractBuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2022-12-13 19:05:27,001 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 19:05:27,001 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2497 transitions. [2022-12-13 19:05:27,006 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:27,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:27,006 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:27,008 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:27,008 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:27,009 INFO L748 eck$LassoCheckResult]: Stem: 27349#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 27350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28136#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28137#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28006#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 28007#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28099#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28399#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28530#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28531#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27326#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27327#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28463#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27906#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27907#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27816#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27817#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28206#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27562#L1174 assume !(0 == ~M_E~0); 27563#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27416#L1179-1 assume !(0 == ~T2_E~0); 27324#L1184-1 assume !(0 == ~T3_E~0); 27325#L1189-1 assume !(0 == ~T4_E~0); 27365#L1194-1 assume !(0 == ~T5_E~0); 27456#L1199-1 assume !(0 == ~T6_E~0); 28332#L1204-1 assume !(0 == ~T7_E~0); 28251#L1209-1 assume !(0 == ~T8_E~0); 28252#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28675#L1219-1 assume !(0 == ~T10_E~0); 28761#L1224-1 assume !(0 == ~T11_E~0); 27681#L1229-1 assume !(0 == ~T12_E~0); 27256#L1234-1 assume !(0 == ~E_1~0); 27257#L1239-1 assume !(0 == ~E_2~0); 27289#L1244-1 assume !(0 == ~E_3~0); 27290#L1249-1 assume !(0 == ~E_4~0); 27926#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 27186#L1259-1 assume !(0 == ~E_6~0); 27139#L1264-1 assume !(0 == ~E_7~0); 27140#L1269-1 assume !(0 == ~E_8~0); 28764#L1274-1 assume !(0 == ~E_9~0); 28702#L1279-1 assume !(0 == ~E_10~0); 27369#L1284-1 assume !(0 == ~E_11~0); 27370#L1289-1 assume !(0 == ~E_12~0); 27975#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27976#L566 assume 1 == ~m_pc~0; 27156#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27157#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28020#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28021#L1455 assume !(0 != activate_threads_~tmp~1#1); 27589#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27590#L585 assume 1 == ~t1_pc~0; 27253#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27254#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28390#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28391#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 28731#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28727#L604 assume !(1 == ~t2_pc~0); 28294#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28295#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27532#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27533#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28490#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28491#L623 assume 1 == ~t3_pc~0; 27765#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27118#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28363#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28364#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 28524#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27153#L642 assume !(1 == ~t4_pc~0); 27154#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27602#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27208#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27209#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 27230#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28308#L661 assume 1 == ~t5_pc~0; 27382#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27383#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28223#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28589#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 28339#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28340#L680 assume !(1 == ~t6_pc~0); 27798#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27799#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27523#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27524#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 28600#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28724#L699 assume 1 == ~t7_pc~0; 28187#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28188#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28422#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28081#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 28082#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27977#L718 assume !(1 == ~t8_pc~0); 27978#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27363#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27364#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27398#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 27399#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27529#L737 assume 1 == ~t9_pc~0; 28378#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27662#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27569#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27570#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 27836#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27837#L756 assume 1 == ~t10_pc~0; 28412#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28072#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28327#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28013#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 27641#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27642#L775 assume !(1 == ~t11_pc~0); 27895#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27896#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28668#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27299#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27300#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27477#L794 assume 1 == ~t12_pc~0; 27322#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27302#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27159#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27160#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 27442#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27910#L1307 assume !(1 == ~M_E~0); 27911#L1307-2 assume !(1 == ~T1_E~0); 28017#L1312-1 assume !(1 == ~T2_E~0); 27939#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27940#L1322-1 assume !(1 == ~T4_E~0); 27652#L1327-1 assume !(1 == ~T5_E~0); 27653#L1332-1 assume !(1 == ~T6_E~0); 28192#L1337-1 assume !(1 == ~T7_E~0); 28149#L1342-1 assume !(1 == ~T8_E~0); 28150#L1347-1 assume !(1 == ~T9_E~0); 28561#L1352-1 assume !(1 == ~T10_E~0); 28423#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27814#L1362-1 assume !(1 == ~T12_E~0); 27815#L1367-1 assume !(1 == ~E_1~0); 27457#L1372-1 assume !(1 == ~E_2~0); 27458#L1377-1 assume !(1 == ~E_3~0); 27750#L1382-1 assume !(1 == ~E_4~0); 27751#L1387-1 assume !(1 == ~E_5~0); 28296#L1392-1 assume !(1 == ~E_6~0); 27768#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27769#L1402-1 assume !(1 == ~E_8~0); 27472#L1407-1 assume !(1 == ~E_9~0); 27473#L1412-1 assume !(1 == ~E_10~0); 28485#L1417-1 assume !(1 == ~E_11~0); 28486#L1422-1 assume !(1 == ~E_12~0); 28721#L1427-1 assume { :end_inline_reset_delta_events } true; 27285#L1768-2 [2022-12-13 19:05:27,009 INFO L750 eck$LassoCheckResult]: Loop: 27285#L1768-2 assume !false; 27286#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28001#L1149 assume !false; 28368#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28542#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27659#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28468#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28537#L976 assume !(0 != eval_~tmp~0#1); 27968#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27702#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27703#L1174-3 assume !(0 == ~M_E~0); 28495#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28234#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28235#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28424#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28067#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27433#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27434#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27672#L1209-3 assume !(0 == ~T8_E~0); 27102#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27103#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27847#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 27848#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 27862#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27293#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27294#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27727#L1249-3 assume !(0 == ~E_4~0); 28179#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28671#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28279#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27297#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27298#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28701#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27845#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 27846#L1289-3 assume !(0 == ~E_12~0); 27833#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27513#L566-39 assume 1 == ~m_pc~0; 27514#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28110#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28111#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28162#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28354#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28355#L585-39 assume !(1 == ~t1_pc~0); 27521#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 27522#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27724#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28665#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28394#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28087#L604-39 assume 1 == ~t2_pc~0; 28088#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27731#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27732#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27909#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28139#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27713#L623-39 assume !(1 == ~t3_pc~0); 27120#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 27121#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28373#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27564#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27565#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28315#L642-39 assume 1 == ~t4_pc~0; 27900#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27901#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28062#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28063#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28541#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27483#L661-39 assume !(1 == ~t5_pc~0); 27127#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 27128#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28094#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28095#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28375#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28376#L680-39 assume 1 == ~t6_pc~0; 27191#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27192#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28622#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27639#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27640#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28677#L699-39 assume 1 == ~t7_pc~0; 28069#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27801#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27802#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28380#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28618#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28615#L718-39 assume 1 == ~t8_pc~0; 27981#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27982#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28473#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28474#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 28222#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28200#L737-39 assume 1 == ~t9_pc~0; 27620#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27621#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27219#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27220#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28588#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28525#L756-39 assume !(1 == ~t10_pc~0); 27995#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 27996#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28664#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27880#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 27881#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27240#L775-39 assume 1 == ~t11_pc~0; 27241#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 27871#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27872#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28122#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28272#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27925#L794-39 assume !(1 == ~t12_pc~0); 27616#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 27617#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27710#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27711#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 27182#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27183#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28648#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28649#L1312-3 assume !(1 == ~T2_E~0); 28763#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28341#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28342#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27314#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27291#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27292#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28011#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28142#L1352-3 assume !(1 == ~T10_E~0); 28143#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28597#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28758#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28749#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27115#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27116#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27734#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27735#L1392-3 assume !(1 == ~E_6~0); 28449#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28715#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28109#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27394#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27395#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28025#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28026#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 27402#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27403#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 27468#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 27469#L1787 assume !(0 == start_simulation_~tmp~3#1); 28113#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28657#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27379#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 27131#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 27132#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27720#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27721#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 28625#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 27285#L1768-2 [2022-12-13 19:05:27,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:27,009 INFO L85 PathProgramCache]: Analyzing trace with hash -1915648561, now seen corresponding path program 1 times [2022-12-13 19:05:27,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:27,010 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029467773] [2022-12-13 19:05:27,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:27,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:27,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:27,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:27,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:27,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2029467773] [2022-12-13 19:05:27,053 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2029467773] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:27,053 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:27,053 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:27,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1334668263] [2022-12-13 19:05:27,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:27,054 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:27,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:27,054 INFO L85 PathProgramCache]: Analyzing trace with hash -843969024, now seen corresponding path program 1 times [2022-12-13 19:05:27,055 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:27,055 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687256247] [2022-12-13 19:05:27,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:27,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:27,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:27,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:27,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:27,110 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687256247] [2022-12-13 19:05:27,110 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1687256247] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:27,110 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:27,110 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:27,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382470298] [2022-12-13 19:05:27,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:27,111 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:27,111 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:27,111 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:27,111 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:27,111 INFO L87 Difference]: Start difference. First operand 1688 states and 2497 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:27,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:27,139 INFO L93 Difference]: Finished difference Result 1688 states and 2496 transitions. [2022-12-13 19:05:27,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2496 transitions. [2022-12-13 19:05:27,147 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:27,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2496 transitions. [2022-12-13 19:05:27,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-12-13 19:05:27,156 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-12-13 19:05:27,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2496 transitions. [2022-12-13 19:05:27,158 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:27,158 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2022-12-13 19:05:27,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2496 transitions. [2022-12-13 19:05:27,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-12-13 19:05:27,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4786729857819905) internal successors, (2496), 1687 states have internal predecessors, (2496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:27,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2496 transitions. [2022-12-13 19:05:27,195 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2022-12-13 19:05:27,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:27,196 INFO L428 stractBuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2022-12-13 19:05:27,196 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 19:05:27,196 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2496 transitions. [2022-12-13 19:05:27,203 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:27,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:27,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:27,206 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:27,206 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:27,207 INFO L748 eck$LassoCheckResult]: Stem: 30732#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 30733#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 31519#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31520#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31389#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 31390#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31482#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31782#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31913#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31914#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30709#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30710#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31846#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31289#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31290#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31199#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31200#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 31589#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30945#L1174 assume !(0 == ~M_E~0); 30946#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30799#L1179-1 assume !(0 == ~T2_E~0); 30707#L1184-1 assume !(0 == ~T3_E~0); 30708#L1189-1 assume !(0 == ~T4_E~0); 30748#L1194-1 assume !(0 == ~T5_E~0); 30839#L1199-1 assume !(0 == ~T6_E~0); 31715#L1204-1 assume !(0 == ~T7_E~0); 31634#L1209-1 assume !(0 == ~T8_E~0); 31635#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32058#L1219-1 assume !(0 == ~T10_E~0); 32144#L1224-1 assume !(0 == ~T11_E~0); 31064#L1229-1 assume !(0 == ~T12_E~0); 30639#L1234-1 assume !(0 == ~E_1~0); 30640#L1239-1 assume !(0 == ~E_2~0); 30672#L1244-1 assume !(0 == ~E_3~0); 30673#L1249-1 assume !(0 == ~E_4~0); 31309#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 30569#L1259-1 assume !(0 == ~E_6~0); 30522#L1264-1 assume !(0 == ~E_7~0); 30523#L1269-1 assume !(0 == ~E_8~0); 32147#L1274-1 assume !(0 == ~E_9~0); 32085#L1279-1 assume !(0 == ~E_10~0); 30752#L1284-1 assume !(0 == ~E_11~0); 30753#L1289-1 assume !(0 == ~E_12~0); 31358#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31359#L566 assume 1 == ~m_pc~0; 30539#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30540#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31403#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31404#L1455 assume !(0 != activate_threads_~tmp~1#1); 30972#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30973#L585 assume 1 == ~t1_pc~0; 30636#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30637#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31773#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31774#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 32114#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32110#L604 assume !(1 == ~t2_pc~0); 31677#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31678#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30915#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30916#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31873#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31874#L623 assume 1 == ~t3_pc~0; 31148#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30501#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31746#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31747#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 31907#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30536#L642 assume !(1 == ~t4_pc~0); 30537#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30985#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30591#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30592#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 30613#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31691#L661 assume 1 == ~t5_pc~0; 30765#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30766#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31606#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31972#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 31722#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31723#L680 assume !(1 == ~t6_pc~0); 31181#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31182#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30906#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30907#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 31983#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32107#L699 assume 1 == ~t7_pc~0; 31570#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31571#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31805#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31464#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 31465#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31360#L718 assume !(1 == ~t8_pc~0); 31361#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30746#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30747#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30781#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 30782#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30912#L737 assume 1 == ~t9_pc~0; 31761#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31045#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30952#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30953#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 31219#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31220#L756 assume 1 == ~t10_pc~0; 31795#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31455#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31710#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31396#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 31024#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31025#L775 assume !(1 == ~t11_pc~0); 31278#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 31279#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32051#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30682#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30683#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30860#L794 assume 1 == ~t12_pc~0; 30705#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30685#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30542#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30543#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 30825#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31293#L1307 assume !(1 == ~M_E~0); 31294#L1307-2 assume !(1 == ~T1_E~0); 31400#L1312-1 assume !(1 == ~T2_E~0); 31322#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31323#L1322-1 assume !(1 == ~T4_E~0); 31035#L1327-1 assume !(1 == ~T5_E~0); 31036#L1332-1 assume !(1 == ~T6_E~0); 31575#L1337-1 assume !(1 == ~T7_E~0); 31532#L1342-1 assume !(1 == ~T8_E~0); 31533#L1347-1 assume !(1 == ~T9_E~0); 31944#L1352-1 assume !(1 == ~T10_E~0); 31806#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31197#L1362-1 assume !(1 == ~T12_E~0); 31198#L1367-1 assume !(1 == ~E_1~0); 30840#L1372-1 assume !(1 == ~E_2~0); 30841#L1377-1 assume !(1 == ~E_3~0); 31133#L1382-1 assume !(1 == ~E_4~0); 31134#L1387-1 assume !(1 == ~E_5~0); 31679#L1392-1 assume !(1 == ~E_6~0); 31151#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 31152#L1402-1 assume !(1 == ~E_8~0); 30855#L1407-1 assume !(1 == ~E_9~0); 30856#L1412-1 assume !(1 == ~E_10~0); 31868#L1417-1 assume !(1 == ~E_11~0); 31869#L1422-1 assume !(1 == ~E_12~0); 32104#L1427-1 assume { :end_inline_reset_delta_events } true; 30668#L1768-2 [2022-12-13 19:05:27,207 INFO L750 eck$LassoCheckResult]: Loop: 30668#L1768-2 assume !false; 30669#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31384#L1149 assume !false; 31751#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 31925#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31042#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31851#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31920#L976 assume !(0 != eval_~tmp~0#1); 31351#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31085#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31086#L1174-3 assume !(0 == ~M_E~0); 31878#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31617#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31618#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31807#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31450#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30816#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30817#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31055#L1209-3 assume !(0 == ~T8_E~0); 30485#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30486#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31230#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 31231#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31245#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30676#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30677#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31110#L1249-3 assume !(0 == ~E_4~0); 31562#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32054#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31662#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30680#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30681#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32084#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31228#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31229#L1289-3 assume !(0 == ~E_12~0); 31216#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30896#L566-39 assume 1 == ~m_pc~0; 30897#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31493#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31494#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31545#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31737#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31738#L585-39 assume !(1 == ~t1_pc~0); 30904#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 30905#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31107#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32048#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31777#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31470#L604-39 assume !(1 == ~t2_pc~0); 31472#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 31114#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31115#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31292#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31522#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31096#L623-39 assume 1 == ~t3_pc~0; 30502#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30504#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31756#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30947#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30948#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31698#L642-39 assume 1 == ~t4_pc~0; 31283#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31284#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31445#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31446#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31924#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30866#L661-39 assume 1 == ~t5_pc~0; 30867#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30511#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31477#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31478#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31758#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31759#L680-39 assume !(1 == ~t6_pc~0); 30576#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 30575#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32005#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31022#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31023#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32060#L699-39 assume 1 == ~t7_pc~0; 31452#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31184#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31185#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31763#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32001#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31998#L718-39 assume 1 == ~t8_pc~0; 31364#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31365#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31856#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31857#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 31605#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31583#L737-39 assume 1 == ~t9_pc~0; 31003#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31004#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30602#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30603#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31971#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31908#L756-39 assume !(1 == ~t10_pc~0); 31378#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 31379#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32047#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31263#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31264#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30623#L775-39 assume 1 == ~t11_pc~0; 30624#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31254#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31255#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31505#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31655#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31308#L794-39 assume !(1 == ~t12_pc~0); 30999#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 31000#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31093#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31094#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30565#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30566#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32031#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32032#L1312-3 assume !(1 == ~T2_E~0); 32146#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31724#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31725#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30697#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30674#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30675#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31394#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31525#L1352-3 assume !(1 == ~T10_E~0); 31526#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31980#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32141#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32132#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30498#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30499#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31117#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31118#L1392-3 assume !(1 == ~E_6~0); 31832#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32098#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31492#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30777#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30778#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 31408#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31409#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30785#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 30786#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30851#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 30852#L1787 assume !(0 == start_simulation_~tmp~3#1); 31496#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32040#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 30762#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30514#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 30515#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31103#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31104#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 32008#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 30668#L1768-2 [2022-12-13 19:05:27,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:27,208 INFO L85 PathProgramCache]: Analyzing trace with hash 1961430033, now seen corresponding path program 1 times [2022-12-13 19:05:27,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:27,208 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [754213537] [2022-12-13 19:05:27,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:27,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:27,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:27,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:27,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:27,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [754213537] [2022-12-13 19:05:27,249 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [754213537] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:27,249 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:27,249 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:27,250 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1161495452] [2022-12-13 19:05:27,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:27,250 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:27,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:27,251 INFO L85 PathProgramCache]: Analyzing trace with hash -117416448, now seen corresponding path program 1 times [2022-12-13 19:05:27,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:27,251 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002934557] [2022-12-13 19:05:27,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:27,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:27,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:27,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:27,307 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:27,307 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1002934557] [2022-12-13 19:05:27,307 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1002934557] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:27,307 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:27,307 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:27,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1824029342] [2022-12-13 19:05:27,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:27,308 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:27,308 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:27,308 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:27,309 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:27,309 INFO L87 Difference]: Start difference. First operand 1688 states and 2496 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:27,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:27,338 INFO L93 Difference]: Finished difference Result 1688 states and 2495 transitions. [2022-12-13 19:05:27,339 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2495 transitions. [2022-12-13 19:05:27,344 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:27,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2495 transitions. [2022-12-13 19:05:27,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-12-13 19:05:27,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-12-13 19:05:27,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2495 transitions. [2022-12-13 19:05:27,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:27,355 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2022-12-13 19:05:27,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2495 transitions. [2022-12-13 19:05:27,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-12-13 19:05:27,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.478080568720379) internal successors, (2495), 1687 states have internal predecessors, (2495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:27,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2495 transitions. [2022-12-13 19:05:27,372 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2022-12-13 19:05:27,372 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:27,373 INFO L428 stractBuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2022-12-13 19:05:27,373 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 19:05:27,373 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2495 transitions. [2022-12-13 19:05:27,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:27,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:27,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:27,380 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:27,380 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:27,381 INFO L748 eck$LassoCheckResult]: Stem: 34115#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 34116#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 34902#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34903#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34772#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 34773#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34865#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35167#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35296#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35297#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34092#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34093#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35229#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34672#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34673#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34582#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 34583#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 34972#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34328#L1174 assume !(0 == ~M_E~0); 34329#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34184#L1179-1 assume !(0 == ~T2_E~0); 34090#L1184-1 assume !(0 == ~T3_E~0); 34091#L1189-1 assume !(0 == ~T4_E~0); 34131#L1194-1 assume !(0 == ~T5_E~0); 34224#L1199-1 assume !(0 == ~T6_E~0); 35098#L1204-1 assume !(0 == ~T7_E~0); 35017#L1209-1 assume !(0 == ~T8_E~0); 35018#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35441#L1219-1 assume !(0 == ~T10_E~0); 35527#L1224-1 assume !(0 == ~T11_E~0); 34449#L1229-1 assume !(0 == ~T12_E~0); 34022#L1234-1 assume !(0 == ~E_1~0); 34023#L1239-1 assume !(0 == ~E_2~0); 34057#L1244-1 assume !(0 == ~E_3~0); 34058#L1249-1 assume !(0 == ~E_4~0); 34692#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 33952#L1259-1 assume !(0 == ~E_6~0); 33905#L1264-1 assume !(0 == ~E_7~0); 33906#L1269-1 assume !(0 == ~E_8~0); 35530#L1274-1 assume !(0 == ~E_9~0); 35469#L1279-1 assume !(0 == ~E_10~0); 34135#L1284-1 assume !(0 == ~E_11~0); 34136#L1289-1 assume !(0 == ~E_12~0); 34741#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34742#L566 assume 1 == ~m_pc~0; 33922#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33923#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34786#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34787#L1455 assume !(0 != activate_threads_~tmp~1#1); 34355#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34356#L585 assume 1 == ~t1_pc~0; 34019#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34020#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35156#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35157#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 35497#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35493#L604 assume !(1 == ~t2_pc~0); 35060#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35061#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34303#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34304#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35258#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35259#L623 assume 1 == ~t3_pc~0; 34531#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33884#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35132#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35133#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 35290#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33919#L642 assume !(1 == ~t4_pc~0); 33920#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34368#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33980#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33981#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 33996#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35074#L661 assume 1 == ~t5_pc~0; 34148#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34149#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34989#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35355#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 35107#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35108#L680 assume !(1 == ~t6_pc~0); 34564#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34565#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34289#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34290#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 35366#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35491#L699 assume 1 == ~t7_pc~0; 34953#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34954#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35188#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34847#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 34848#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34743#L718 assume !(1 == ~t8_pc~0); 34744#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34129#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34130#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34164#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 34165#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34295#L737 assume 1 == ~t9_pc~0; 35146#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34428#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34335#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34336#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 34602#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34603#L756 assume 1 == ~t10_pc~0; 35178#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34838#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35093#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34779#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 34407#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34408#L775 assume !(1 == ~t11_pc~0); 34661#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 34662#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35434#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34065#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34066#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34243#L794 assume 1 == ~t12_pc~0; 34089#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34068#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33927#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33928#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 34210#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34676#L1307 assume !(1 == ~M_E~0); 34677#L1307-2 assume !(1 == ~T1_E~0); 34783#L1312-1 assume !(1 == ~T2_E~0); 34705#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34706#L1322-1 assume !(1 == ~T4_E~0); 34418#L1327-1 assume !(1 == ~T5_E~0); 34419#L1332-1 assume !(1 == ~T6_E~0); 34958#L1337-1 assume !(1 == ~T7_E~0); 34916#L1342-1 assume !(1 == ~T8_E~0); 34917#L1347-1 assume !(1 == ~T9_E~0); 35327#L1352-1 assume !(1 == ~T10_E~0); 35189#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34580#L1362-1 assume !(1 == ~T12_E~0); 34581#L1367-1 assume !(1 == ~E_1~0); 34225#L1372-1 assume !(1 == ~E_2~0); 34226#L1377-1 assume !(1 == ~E_3~0); 34516#L1382-1 assume !(1 == ~E_4~0); 34517#L1387-1 assume !(1 == ~E_5~0); 35062#L1392-1 assume !(1 == ~E_6~0); 34536#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34537#L1402-1 assume !(1 == ~E_8~0); 34238#L1407-1 assume !(1 == ~E_9~0); 34239#L1412-1 assume !(1 == ~E_10~0); 35251#L1417-1 assume !(1 == ~E_11~0); 35252#L1422-1 assume !(1 == ~E_12~0); 35487#L1427-1 assume { :end_inline_reset_delta_events } true; 34051#L1768-2 [2022-12-13 19:05:27,381 INFO L750 eck$LassoCheckResult]: Loop: 34051#L1768-2 assume !false; 34052#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34767#L1149 assume !false; 35135#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35308#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34425#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 35234#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35303#L976 assume !(0 != eval_~tmp~0#1); 34734#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34468#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34469#L1174-3 assume !(0 == ~M_E~0); 35261#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35000#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35001#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35191#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34833#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34202#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34203#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34438#L1209-3 assume !(0 == ~T8_E~0); 33868#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33869#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34613#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34614#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 34628#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34059#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34060#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34493#L1249-3 assume !(0 == ~E_4~0); 34945#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35437#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35045#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34063#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34064#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35467#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34611#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34612#L1289-3 assume !(0 == ~E_12~0); 34599#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34279#L566-39 assume 1 == ~m_pc~0; 34280#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34876#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34877#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34928#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35120#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35121#L585-39 assume !(1 == ~t1_pc~0); 34286#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 34287#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34490#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35431#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35160#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34852#L604-39 assume 1 == ~t2_pc~0; 34853#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34497#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34498#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34675#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34905#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34479#L623-39 assume 1 == ~t3_pc~0; 33885#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33887#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35139#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34330#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34331#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35081#L642-39 assume 1 == ~t4_pc~0; 34666#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34667#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34828#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34829#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35307#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34249#L661-39 assume !(1 == ~t5_pc~0); 33893#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 33894#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34860#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34861#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35141#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35142#L680-39 assume 1 == ~t6_pc~0; 33957#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33958#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35388#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34405#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34406#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35443#L699-39 assume 1 == ~t7_pc~0; 34835#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34567#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34568#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35145#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35384#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35381#L718-39 assume 1 == ~t8_pc~0; 34747#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34748#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35239#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35240#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 34988#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34966#L737-39 assume 1 == ~t9_pc~0; 34386#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34387#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33985#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33986#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35354#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35291#L756-39 assume !(1 == ~t10_pc~0); 34761#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 34762#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35430#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34646#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34647#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34006#L775-39 assume 1 == ~t11_pc~0; 34007#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34637#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34638#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34888#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35038#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34691#L794-39 assume 1 == ~t12_pc~0; 34389#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34383#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34476#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34477#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33948#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33949#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35414#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35415#L1312-3 assume !(1 == ~T2_E~0); 35529#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35105#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35106#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34080#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34055#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34056#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34777#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34908#L1352-3 assume !(1 == ~T10_E~0); 34909#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35363#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35524#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35515#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33878#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33879#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34500#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34501#L1392-3 assume !(1 == ~E_6~0); 35215#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35481#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34875#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34160#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 34161#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 34790#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 34791#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 34168#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34169#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34234#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 34235#L1787 assume !(0 == start_simulation_~tmp~3#1); 34878#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35423#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34145#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33897#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 33898#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34486#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34487#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 35391#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 34051#L1768-2 [2022-12-13 19:05:27,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:27,382 INFO L85 PathProgramCache]: Analyzing trace with hash -716096813, now seen corresponding path program 1 times [2022-12-13 19:05:27,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:27,382 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [34689200] [2022-12-13 19:05:27,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:27,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:27,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:27,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:27,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:27,421 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [34689200] [2022-12-13 19:05:27,421 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [34689200] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:27,421 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:27,421 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:27,421 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2039002963] [2022-12-13 19:05:27,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:27,422 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:27,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:27,422 INFO L85 PathProgramCache]: Analyzing trace with hash -1994635518, now seen corresponding path program 4 times [2022-12-13 19:05:27,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:27,422 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [130291190] [2022-12-13 19:05:27,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:27,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:27,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:27,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:27,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:27,457 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [130291190] [2022-12-13 19:05:27,457 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [130291190] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:27,457 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:27,458 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:27,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1303632123] [2022-12-13 19:05:27,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:27,458 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:27,458 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:27,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:27,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:27,459 INFO L87 Difference]: Start difference. First operand 1688 states and 2495 transitions. cyclomatic complexity: 808 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:27,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:27,484 INFO L93 Difference]: Finished difference Result 1688 states and 2494 transitions. [2022-12-13 19:05:27,484 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2494 transitions. [2022-12-13 19:05:27,490 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:27,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2494 transitions. [2022-12-13 19:05:27,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-12-13 19:05:27,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-12-13 19:05:27,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2494 transitions. [2022-12-13 19:05:27,501 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:27,501 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2022-12-13 19:05:27,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2494 transitions. [2022-12-13 19:05:27,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-12-13 19:05:27,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4774881516587677) internal successors, (2494), 1687 states have internal predecessors, (2494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:27,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2494 transitions. [2022-12-13 19:05:27,527 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2022-12-13 19:05:27,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:27,528 INFO L428 stractBuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2022-12-13 19:05:27,528 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 19:05:27,528 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2494 transitions. [2022-12-13 19:05:27,533 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:27,533 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:27,533 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:27,534 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:27,534 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:27,535 INFO L748 eck$LassoCheckResult]: Stem: 37498#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 37499#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 38285#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38286#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38155#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 38156#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38248#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38548#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38679#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38680#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37475#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37476#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38612#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38055#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38056#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 37965#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 37966#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38355#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37711#L1174 assume !(0 == ~M_E~0); 37712#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37565#L1179-1 assume !(0 == ~T2_E~0); 37473#L1184-1 assume !(0 == ~T3_E~0); 37474#L1189-1 assume !(0 == ~T4_E~0); 37514#L1194-1 assume !(0 == ~T5_E~0); 37605#L1199-1 assume !(0 == ~T6_E~0); 38481#L1204-1 assume !(0 == ~T7_E~0); 38400#L1209-1 assume !(0 == ~T8_E~0); 38401#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38824#L1219-1 assume !(0 == ~T10_E~0); 38910#L1224-1 assume !(0 == ~T11_E~0); 37830#L1229-1 assume !(0 == ~T12_E~0); 37405#L1234-1 assume !(0 == ~E_1~0); 37406#L1239-1 assume !(0 == ~E_2~0); 37440#L1244-1 assume !(0 == ~E_3~0); 37441#L1249-1 assume !(0 == ~E_4~0); 38075#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 37335#L1259-1 assume !(0 == ~E_6~0); 37288#L1264-1 assume !(0 == ~E_7~0); 37289#L1269-1 assume !(0 == ~E_8~0); 38913#L1274-1 assume !(0 == ~E_9~0); 38852#L1279-1 assume !(0 == ~E_10~0); 37518#L1284-1 assume !(0 == ~E_11~0); 37519#L1289-1 assume !(0 == ~E_12~0); 38124#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38125#L566 assume 1 == ~m_pc~0; 37305#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 37306#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38169#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38170#L1455 assume !(0 != activate_threads_~tmp~1#1); 37738#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37739#L585 assume 1 == ~t1_pc~0; 37402#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37403#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38539#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38540#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 38880#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38876#L604 assume !(1 == ~t2_pc~0); 38443#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38444#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37686#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37687#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38639#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38640#L623 assume 1 == ~t3_pc~0; 37914#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37267#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38514#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38515#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 38673#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37302#L642 assume !(1 == ~t4_pc~0); 37303#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37751#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37360#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37361#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 37379#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38457#L661 assume 1 == ~t5_pc~0; 37531#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37532#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38372#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38738#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 38490#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38491#L680 assume !(1 == ~t6_pc~0); 37947#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37948#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37672#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37673#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 38749#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38873#L699 assume 1 == ~t7_pc~0; 38336#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38337#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38571#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38230#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 38231#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38126#L718 assume !(1 == ~t8_pc~0); 38127#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37512#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37513#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37547#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 37548#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37678#L737 assume 1 == ~t9_pc~0; 38527#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37811#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37718#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37719#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 37985#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37986#L756 assume 1 == ~t10_pc~0; 38561#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38221#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38476#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38162#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 37790#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37791#L775 assume !(1 == ~t11_pc~0); 38044#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 38045#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38817#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37448#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 37449#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37626#L794 assume 1 == ~t12_pc~0; 37472#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37451#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37310#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37311#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 37591#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38059#L1307 assume !(1 == ~M_E~0); 38060#L1307-2 assume !(1 == ~T1_E~0); 38166#L1312-1 assume !(1 == ~T2_E~0); 38088#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38089#L1322-1 assume !(1 == ~T4_E~0); 37801#L1327-1 assume !(1 == ~T5_E~0); 37802#L1332-1 assume !(1 == ~T6_E~0); 38341#L1337-1 assume !(1 == ~T7_E~0); 38298#L1342-1 assume !(1 == ~T8_E~0); 38299#L1347-1 assume !(1 == ~T9_E~0); 38710#L1352-1 assume !(1 == ~T10_E~0); 38572#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37963#L1362-1 assume !(1 == ~T12_E~0); 37964#L1367-1 assume !(1 == ~E_1~0); 37606#L1372-1 assume !(1 == ~E_2~0); 37607#L1377-1 assume !(1 == ~E_3~0); 37899#L1382-1 assume !(1 == ~E_4~0); 37900#L1387-1 assume !(1 == ~E_5~0); 38445#L1392-1 assume !(1 == ~E_6~0); 37917#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 37918#L1402-1 assume !(1 == ~E_8~0); 37621#L1407-1 assume !(1 == ~E_9~0); 37622#L1412-1 assume !(1 == ~E_10~0); 38634#L1417-1 assume !(1 == ~E_11~0); 38635#L1422-1 assume !(1 == ~E_12~0); 38870#L1427-1 assume { :end_inline_reset_delta_events } true; 37434#L1768-2 [2022-12-13 19:05:27,535 INFO L750 eck$LassoCheckResult]: Loop: 37434#L1768-2 assume !false; 37435#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38150#L1149 assume !false; 38517#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38691#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37808#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38617#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38686#L976 assume !(0 != eval_~tmp~0#1); 38117#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37851#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37852#L1174-3 assume !(0 == ~M_E~0); 38644#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38383#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38384#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38573#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38216#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37585#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37586#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37821#L1209-3 assume !(0 == ~T8_E~0); 37251#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37252#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37996#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37997#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38011#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37442#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37443#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37876#L1249-3 assume !(0 == ~E_4~0); 38328#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38820#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38428#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37446#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37447#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38850#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37994#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 37995#L1289-3 assume !(0 == ~E_12~0); 37982#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37662#L566-39 assume !(1 == ~m_pc~0); 37664#L566-41 is_master_triggered_~__retres1~0#1 := 0; 38259#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38260#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38311#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38503#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38504#L585-39 assume !(1 == ~t1_pc~0); 37670#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 37671#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37873#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38814#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38543#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38236#L604-39 assume 1 == ~t2_pc~0; 38237#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37880#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37881#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38058#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38290#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37862#L623-39 assume 1 == ~t3_pc~0; 37270#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37272#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38522#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37713#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37714#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38464#L642-39 assume 1 == ~t4_pc~0; 38051#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38052#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38211#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38212#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38690#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37634#L661-39 assume 1 == ~t5_pc~0; 37635#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37277#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38243#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38244#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38524#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38525#L680-39 assume !(1 == ~t6_pc~0); 37344#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 37343#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38774#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37788#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37789#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38826#L699-39 assume 1 == ~t7_pc~0; 38218#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37950#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37951#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38529#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38767#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38764#L718-39 assume 1 == ~t8_pc~0; 38131#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38132#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38621#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38622#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 38371#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38348#L737-39 assume 1 == ~t9_pc~0; 37769#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37770#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37367#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37368#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38737#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38674#L756-39 assume 1 == ~t10_pc~0; 38675#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38142#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38813#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38029#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38030#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37389#L775-39 assume 1 == ~t11_pc~0; 37390#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38020#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38021#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38271#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38421#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38074#L794-39 assume !(1 == ~t12_pc~0); 37765#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 37766#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37857#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37858#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37331#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37332#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38797#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38798#L1312-3 assume !(1 == ~T2_E~0); 38912#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38488#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38489#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37461#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37438#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37439#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38160#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38288#L1352-3 assume !(1 == ~T10_E~0); 38289#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38746#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38907#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38898#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37261#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37262#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37883#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37884#L1392-3 assume !(1 == ~E_6~0); 38598#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38864#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38258#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37543#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37544#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 38173#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38174#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37551#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37552#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37616#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 37617#L1787 assume !(0 == start_simulation_~tmp~3#1); 38261#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38806#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37528#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37280#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 37281#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37869#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37870#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 38773#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 37434#L1768-2 [2022-12-13 19:05:27,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:27,535 INFO L85 PathProgramCache]: Analyzing trace with hash -1079563311, now seen corresponding path program 1 times [2022-12-13 19:05:27,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:27,536 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089469196] [2022-12-13 19:05:27,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:27,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:27,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:27,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:27,588 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:27,588 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089469196] [2022-12-13 19:05:27,588 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089469196] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:27,588 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:27,588 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:27,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832999442] [2022-12-13 19:05:27,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:27,589 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:27,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:27,589 INFO L85 PathProgramCache]: Analyzing trace with hash -707419167, now seen corresponding path program 1 times [2022-12-13 19:05:27,590 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:27,590 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829170869] [2022-12-13 19:05:27,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:27,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:27,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:27,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:27,643 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:27,643 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [829170869] [2022-12-13 19:05:27,643 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [829170869] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:27,643 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:27,643 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:27,643 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [298105567] [2022-12-13 19:05:27,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:27,644 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:27,644 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:27,644 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:27,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:27,644 INFO L87 Difference]: Start difference. First operand 1688 states and 2494 transitions. cyclomatic complexity: 807 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:27,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:27,670 INFO L93 Difference]: Finished difference Result 1688 states and 2493 transitions. [2022-12-13 19:05:27,670 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2493 transitions. [2022-12-13 19:05:27,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:27,682 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2493 transitions. [2022-12-13 19:05:27,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-12-13 19:05:27,684 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-12-13 19:05:27,684 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2493 transitions. [2022-12-13 19:05:27,686 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:27,686 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2022-12-13 19:05:27,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2493 transitions. [2022-12-13 19:05:27,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-12-13 19:05:27,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4768957345971565) internal successors, (2493), 1687 states have internal predecessors, (2493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:27,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2493 transitions. [2022-12-13 19:05:27,705 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2022-12-13 19:05:27,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:27,706 INFO L428 stractBuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2022-12-13 19:05:27,706 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 19:05:27,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2493 transitions. [2022-12-13 19:05:27,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:27,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:27,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:27,710 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:27,710 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:27,710 INFO L748 eck$LassoCheckResult]: Stem: 40881#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 40882#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 41668#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41669#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41538#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 41539#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41631#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41931#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42062#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42063#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40858#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40859#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41995#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41438#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41439#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41348#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 41349#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 41738#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41094#L1174 assume !(0 == ~M_E~0); 41095#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40948#L1179-1 assume !(0 == ~T2_E~0); 40856#L1184-1 assume !(0 == ~T3_E~0); 40857#L1189-1 assume !(0 == ~T4_E~0); 40897#L1194-1 assume !(0 == ~T5_E~0); 40988#L1199-1 assume !(0 == ~T6_E~0); 41864#L1204-1 assume !(0 == ~T7_E~0); 41783#L1209-1 assume !(0 == ~T8_E~0); 41784#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42207#L1219-1 assume !(0 == ~T10_E~0); 42293#L1224-1 assume !(0 == ~T11_E~0); 41213#L1229-1 assume !(0 == ~T12_E~0); 40788#L1234-1 assume !(0 == ~E_1~0); 40789#L1239-1 assume !(0 == ~E_2~0); 40821#L1244-1 assume !(0 == ~E_3~0); 40822#L1249-1 assume !(0 == ~E_4~0); 41458#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 40718#L1259-1 assume !(0 == ~E_6~0); 40671#L1264-1 assume !(0 == ~E_7~0); 40672#L1269-1 assume !(0 == ~E_8~0); 42296#L1274-1 assume !(0 == ~E_9~0); 42234#L1279-1 assume !(0 == ~E_10~0); 40901#L1284-1 assume !(0 == ~E_11~0); 40902#L1289-1 assume !(0 == ~E_12~0); 41507#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41508#L566 assume 1 == ~m_pc~0; 40688#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 40689#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41552#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41553#L1455 assume !(0 != activate_threads_~tmp~1#1); 41121#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41122#L585 assume 1 == ~t1_pc~0; 40785#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40786#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41922#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41923#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 42263#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42259#L604 assume !(1 == ~t2_pc~0); 41826#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41827#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41064#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41065#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42022#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42023#L623 assume 1 == ~t3_pc~0; 41297#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40650#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41895#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41896#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 42056#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40685#L642 assume !(1 == ~t4_pc~0); 40686#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41134#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40740#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40741#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 40762#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41840#L661 assume 1 == ~t5_pc~0; 40914#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40915#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41755#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42121#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 41871#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41872#L680 assume !(1 == ~t6_pc~0); 41330#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41331#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41055#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41056#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 42132#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42256#L699 assume 1 == ~t7_pc~0; 41719#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41720#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41954#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41613#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 41614#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41509#L718 assume !(1 == ~t8_pc~0); 41510#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40895#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40896#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40930#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 40931#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41061#L737 assume 1 == ~t9_pc~0; 41910#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41194#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41101#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41102#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 41368#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41369#L756 assume 1 == ~t10_pc~0; 41944#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41604#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41859#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41545#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 41173#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41174#L775 assume !(1 == ~t11_pc~0); 41427#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 41428#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42200#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40831#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40832#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41009#L794 assume 1 == ~t12_pc~0; 40854#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40834#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40691#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40692#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 40974#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41442#L1307 assume !(1 == ~M_E~0); 41443#L1307-2 assume !(1 == ~T1_E~0); 41549#L1312-1 assume !(1 == ~T2_E~0); 41471#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41472#L1322-1 assume !(1 == ~T4_E~0); 41184#L1327-1 assume !(1 == ~T5_E~0); 41185#L1332-1 assume !(1 == ~T6_E~0); 41724#L1337-1 assume !(1 == ~T7_E~0); 41681#L1342-1 assume !(1 == ~T8_E~0); 41682#L1347-1 assume !(1 == ~T9_E~0); 42093#L1352-1 assume !(1 == ~T10_E~0); 41955#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41346#L1362-1 assume !(1 == ~T12_E~0); 41347#L1367-1 assume !(1 == ~E_1~0); 40989#L1372-1 assume !(1 == ~E_2~0); 40990#L1377-1 assume !(1 == ~E_3~0); 41282#L1382-1 assume !(1 == ~E_4~0); 41283#L1387-1 assume !(1 == ~E_5~0); 41828#L1392-1 assume !(1 == ~E_6~0); 41300#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 41301#L1402-1 assume !(1 == ~E_8~0); 41004#L1407-1 assume !(1 == ~E_9~0); 41005#L1412-1 assume !(1 == ~E_10~0); 42017#L1417-1 assume !(1 == ~E_11~0); 42018#L1422-1 assume !(1 == ~E_12~0); 42253#L1427-1 assume { :end_inline_reset_delta_events } true; 40817#L1768-2 [2022-12-13 19:05:27,710 INFO L750 eck$LassoCheckResult]: Loop: 40817#L1768-2 assume !false; 40818#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41533#L1149 assume !false; 41900#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42074#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41191#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 42000#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42069#L976 assume !(0 != eval_~tmp~0#1); 41500#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41234#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41235#L1174-3 assume !(0 == ~M_E~0); 42027#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41766#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41767#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41956#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41599#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40965#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40966#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41204#L1209-3 assume !(0 == ~T8_E~0); 40634#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40635#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41379#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41380#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41394#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40825#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40826#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41259#L1249-3 assume !(0 == ~E_4~0); 41711#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42203#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41811#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40829#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40830#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42233#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41377#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41378#L1289-3 assume !(0 == ~E_12~0); 41365#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41045#L566-39 assume 1 == ~m_pc~0; 41046#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41642#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41643#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41694#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41886#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41887#L585-39 assume !(1 == ~t1_pc~0); 41053#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 41054#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41256#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42197#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41926#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41619#L604-39 assume 1 == ~t2_pc~0; 41620#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41263#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41264#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41441#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41671#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41245#L623-39 assume 1 == ~t3_pc~0; 40651#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40653#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41905#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41096#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41097#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41847#L642-39 assume 1 == ~t4_pc~0; 41432#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41433#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41594#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41595#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42073#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41015#L661-39 assume !(1 == ~t5_pc~0); 40659#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 40660#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41626#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41627#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41907#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41908#L680-39 assume 1 == ~t6_pc~0; 40723#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40724#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42154#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41171#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41172#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42209#L699-39 assume 1 == ~t7_pc~0; 41601#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41333#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41334#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41912#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42150#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42147#L718-39 assume 1 == ~t8_pc~0; 41513#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41514#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42005#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42006#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 41754#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41732#L737-39 assume 1 == ~t9_pc~0; 41152#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41153#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40751#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40752#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42120#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42057#L756-39 assume !(1 == ~t10_pc~0); 41527#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 41528#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42196#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41412#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41413#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40772#L775-39 assume 1 == ~t11_pc~0; 40773#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41403#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41404#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41654#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41804#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41457#L794-39 assume 1 == ~t12_pc~0; 41155#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 41149#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41242#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41243#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40714#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40715#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42180#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42181#L1312-3 assume !(1 == ~T2_E~0); 42295#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41873#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41874#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40846#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40823#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40824#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41543#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41674#L1352-3 assume !(1 == ~T10_E~0); 41675#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42129#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42290#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42281#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40647#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40648#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41266#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41267#L1392-3 assume !(1 == ~E_6~0); 41981#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42247#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41641#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40926#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40927#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41557#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41558#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40934#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40935#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41000#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 41001#L1787 assume !(0 == start_simulation_~tmp~3#1); 41645#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42189#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40911#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40663#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 40664#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41252#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41253#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 42157#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 40817#L1768-2 [2022-12-13 19:05:27,711 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:27,711 INFO L85 PathProgramCache]: Analyzing trace with hash -1368382701, now seen corresponding path program 1 times [2022-12-13 19:05:27,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:27,711 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523454736] [2022-12-13 19:05:27,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:27,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:27,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:27,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:27,748 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:27,748 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523454736] [2022-12-13 19:05:27,748 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [523454736] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:27,748 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:27,748 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:05:27,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [327038635] [2022-12-13 19:05:27,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:27,749 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:27,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:27,749 INFO L85 PathProgramCache]: Analyzing trace with hash -1994635518, now seen corresponding path program 5 times [2022-12-13 19:05:27,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:27,750 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [471209314] [2022-12-13 19:05:27,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:27,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:27,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:27,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:27,789 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:27,789 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [471209314] [2022-12-13 19:05:27,789 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [471209314] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:27,789 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:27,789 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:27,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [104417340] [2022-12-13 19:05:27,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:27,790 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:27,790 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:27,790 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:27,790 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:27,791 INFO L87 Difference]: Start difference. First operand 1688 states and 2493 transitions. cyclomatic complexity: 806 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:27,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:27,816 INFO L93 Difference]: Finished difference Result 1688 states and 2488 transitions. [2022-12-13 19:05:27,816 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2488 transitions. [2022-12-13 19:05:27,822 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:27,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2488 transitions. [2022-12-13 19:05:27,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-12-13 19:05:27,829 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-12-13 19:05:27,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2488 transitions. [2022-12-13 19:05:27,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:27,831 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2022-12-13 19:05:27,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2488 transitions. [2022-12-13 19:05:27,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-12-13 19:05:27,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4739336492890995) internal successors, (2488), 1687 states have internal predecessors, (2488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:27,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2488 transitions. [2022-12-13 19:05:27,847 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2022-12-13 19:05:27,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:27,847 INFO L428 stractBuchiCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2022-12-13 19:05:27,848 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 19:05:27,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2488 transitions. [2022-12-13 19:05:27,850 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-12-13 19:05:27,851 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:27,851 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:27,851 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:27,852 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:27,852 INFO L748 eck$LassoCheckResult]: Stem: 44264#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 44265#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 45051#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45052#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44921#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 44922#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45014#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45314#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45445#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45446#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44241#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44242#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45378#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44821#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44822#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44731#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44732#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 45121#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44477#L1174 assume !(0 == ~M_E~0); 44478#L1174-2 assume !(0 == ~T1_E~0); 44331#L1179-1 assume !(0 == ~T2_E~0); 44239#L1184-1 assume !(0 == ~T3_E~0); 44240#L1189-1 assume !(0 == ~T4_E~0); 44280#L1194-1 assume !(0 == ~T5_E~0); 44371#L1199-1 assume !(0 == ~T6_E~0); 45247#L1204-1 assume !(0 == ~T7_E~0); 45166#L1209-1 assume !(0 == ~T8_E~0); 45167#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45590#L1219-1 assume !(0 == ~T10_E~0); 45676#L1224-1 assume !(0 == ~T11_E~0); 44596#L1229-1 assume !(0 == ~T12_E~0); 44171#L1234-1 assume !(0 == ~E_1~0); 44172#L1239-1 assume !(0 == ~E_2~0); 44204#L1244-1 assume !(0 == ~E_3~0); 44205#L1249-1 assume !(0 == ~E_4~0); 44841#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 44101#L1259-1 assume !(0 == ~E_6~0); 44054#L1264-1 assume !(0 == ~E_7~0); 44055#L1269-1 assume !(0 == ~E_8~0); 45679#L1274-1 assume !(0 == ~E_9~0); 45617#L1279-1 assume !(0 == ~E_10~0); 44284#L1284-1 assume !(0 == ~E_11~0); 44285#L1289-1 assume !(0 == ~E_12~0); 44890#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44891#L566 assume 1 == ~m_pc~0; 44071#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 44072#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44935#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44936#L1455 assume !(0 != activate_threads_~tmp~1#1); 44504#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44505#L585 assume 1 == ~t1_pc~0; 44168#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44169#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45305#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45306#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 45646#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45642#L604 assume !(1 == ~t2_pc~0); 45209#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45210#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44447#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44448#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45405#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45406#L623 assume 1 == ~t3_pc~0; 44680#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44033#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45278#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45279#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 45439#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44068#L642 assume !(1 == ~t4_pc~0); 44069#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44517#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44123#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44124#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 44145#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45223#L661 assume 1 == ~t5_pc~0; 44297#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44298#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45138#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45504#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 45254#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45255#L680 assume !(1 == ~t6_pc~0); 44713#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 44714#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44438#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44439#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 45515#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45639#L699 assume 1 == ~t7_pc~0; 45102#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45103#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45337#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44996#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 44997#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44892#L718 assume !(1 == ~t8_pc~0); 44893#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44278#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44279#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44313#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 44314#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44444#L737 assume 1 == ~t9_pc~0; 45293#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44577#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44484#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44485#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 44751#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44752#L756 assume 1 == ~t10_pc~0; 45327#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44987#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45242#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44928#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 44556#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44557#L775 assume !(1 == ~t11_pc~0); 44810#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 44811#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45583#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44214#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44215#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44392#L794 assume 1 == ~t12_pc~0; 44237#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44217#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44074#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44075#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 44357#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44825#L1307 assume !(1 == ~M_E~0); 44826#L1307-2 assume !(1 == ~T1_E~0); 44932#L1312-1 assume !(1 == ~T2_E~0); 44854#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44855#L1322-1 assume !(1 == ~T4_E~0); 44567#L1327-1 assume !(1 == ~T5_E~0); 44568#L1332-1 assume !(1 == ~T6_E~0); 45107#L1337-1 assume !(1 == ~T7_E~0); 45064#L1342-1 assume !(1 == ~T8_E~0); 45065#L1347-1 assume !(1 == ~T9_E~0); 45476#L1352-1 assume !(1 == ~T10_E~0); 45338#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44729#L1362-1 assume !(1 == ~T12_E~0); 44730#L1367-1 assume !(1 == ~E_1~0); 44372#L1372-1 assume !(1 == ~E_2~0); 44373#L1377-1 assume !(1 == ~E_3~0); 44665#L1382-1 assume !(1 == ~E_4~0); 44666#L1387-1 assume !(1 == ~E_5~0); 45211#L1392-1 assume !(1 == ~E_6~0); 44683#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 44684#L1402-1 assume !(1 == ~E_8~0); 44387#L1407-1 assume !(1 == ~E_9~0); 44388#L1412-1 assume !(1 == ~E_10~0); 45400#L1417-1 assume !(1 == ~E_11~0); 45401#L1422-1 assume !(1 == ~E_12~0); 45636#L1427-1 assume { :end_inline_reset_delta_events } true; 44200#L1768-2 [2022-12-13 19:05:27,852 INFO L750 eck$LassoCheckResult]: Loop: 44200#L1768-2 assume !false; 44201#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44916#L1149 assume !false; 45283#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45457#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44574#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45383#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45452#L976 assume !(0 != eval_~tmp~0#1); 44883#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44617#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44618#L1174-3 assume !(0 == ~M_E~0); 45410#L1174-5 assume !(0 == ~T1_E~0); 45149#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45150#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45339#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44982#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44348#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44349#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44587#L1209-3 assume !(0 == ~T8_E~0); 44017#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44018#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44762#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44763#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44777#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44208#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44209#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44642#L1249-3 assume !(0 == ~E_4~0); 45094#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45586#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45194#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44212#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44213#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45616#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44760#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44761#L1289-3 assume !(0 == ~E_12~0); 44748#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44428#L566-39 assume 1 == ~m_pc~0; 44429#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 45025#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45026#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45077#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45269#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45270#L585-39 assume !(1 == ~t1_pc~0); 44436#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 44437#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44639#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45580#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45309#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45002#L604-39 assume 1 == ~t2_pc~0; 45003#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44646#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44647#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44824#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45054#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44628#L623-39 assume 1 == ~t3_pc~0; 44034#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44036#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45288#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44479#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44480#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45230#L642-39 assume !(1 == ~t4_pc~0); 44817#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 44816#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44977#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44978#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45456#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44398#L661-39 assume !(1 == ~t5_pc~0); 44042#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 44043#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45009#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45010#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45290#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45291#L680-39 assume 1 == ~t6_pc~0; 44106#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44107#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45537#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44554#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44555#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45592#L699-39 assume 1 == ~t7_pc~0; 44984#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44716#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44717#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45295#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45533#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45530#L718-39 assume 1 == ~t8_pc~0; 44896#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44897#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45388#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45389#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 45137#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45115#L737-39 assume 1 == ~t9_pc~0; 44535#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44536#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44134#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44135#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45503#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45440#L756-39 assume 1 == ~t10_pc~0; 45441#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44911#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45579#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44795#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44796#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44155#L775-39 assume 1 == ~t11_pc~0; 44156#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44786#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44787#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45037#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45187#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44840#L794-39 assume !(1 == ~t12_pc~0); 44531#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 44532#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44625#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44626#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44097#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44098#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45563#L1307-5 assume !(1 == ~T1_E~0); 45564#L1312-3 assume !(1 == ~T2_E~0); 45678#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45256#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45257#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44229#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44206#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44207#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44926#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45057#L1352-3 assume !(1 == ~T10_E~0); 45058#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45512#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45673#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45664#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44030#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44031#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44649#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44650#L1392-3 assume !(1 == ~E_6~0); 45364#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45630#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45024#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 44309#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44310#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44940#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44941#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44317#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44318#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44383#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 44384#L1787 assume !(0 == start_simulation_~tmp~3#1); 45028#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45572#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44294#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44046#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 44047#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44635#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44636#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 45540#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 44200#L1768-2 [2022-12-13 19:05:27,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:27,852 INFO L85 PathProgramCache]: Analyzing trace with hash 1978532629, now seen corresponding path program 1 times [2022-12-13 19:05:27,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:27,852 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [460867735] [2022-12-13 19:05:27,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:27,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:27,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:27,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:27,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:27,906 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [460867735] [2022-12-13 19:05:27,906 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [460867735] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:27,906 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:27,906 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:27,906 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293903568] [2022-12-13 19:05:27,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:27,907 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:27,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:27,907 INFO L85 PathProgramCache]: Analyzing trace with hash -105500251, now seen corresponding path program 1 times [2022-12-13 19:05:27,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:27,907 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1442894855] [2022-12-13 19:05:27,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:27,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:27,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:27,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:27,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:27,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1442894855] [2022-12-13 19:05:27,957 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1442894855] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:27,957 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:27,957 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:27,958 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [474688046] [2022-12-13 19:05:27,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:27,958 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:27,958 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:27,958 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:05:27,958 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:05:27,959 INFO L87 Difference]: Start difference. First operand 1688 states and 2488 transitions. cyclomatic complexity: 801 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:28,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:28,071 INFO L93 Difference]: Finished difference Result 3238 states and 4766 transitions. [2022-12-13 19:05:28,071 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3238 states and 4766 transitions. [2022-12-13 19:05:28,079 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3054 [2022-12-13 19:05:28,085 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3238 states to 3238 states and 4766 transitions. [2022-12-13 19:05:28,085 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3238 [2022-12-13 19:05:28,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3238 [2022-12-13 19:05:28,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3238 states and 4766 transitions. [2022-12-13 19:05:28,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:28,090 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3238 states and 4766 transitions. [2022-12-13 19:05:28,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3238 states and 4766 transitions. [2022-12-13 19:05:28,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3238 to 3238. [2022-12-13 19:05:28,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3238 states, 3238 states have (on average 1.4718962322421247) internal successors, (4766), 3237 states have internal predecessors, (4766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:28,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3238 states to 3238 states and 4766 transitions. [2022-12-13 19:05:28,125 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3238 states and 4766 transitions. [2022-12-13 19:05:28,125 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:05:28,125 INFO L428 stractBuchiCegarLoop]: Abstraction has 3238 states and 4766 transitions. [2022-12-13 19:05:28,126 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 19:05:28,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3238 states and 4766 transitions. [2022-12-13 19:05:28,135 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3054 [2022-12-13 19:05:28,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:28,135 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:28,136 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:28,136 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:28,137 INFO L748 eck$LassoCheckResult]: Stem: 49200#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 49201#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 49990#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49991#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49859#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 49860#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49953#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50259#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50399#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50400#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49177#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49178#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50328#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49759#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49760#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49669#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49670#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50064#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49413#L1174 assume !(0 == ~M_E~0); 49414#L1174-2 assume !(0 == ~T1_E~0); 49267#L1179-1 assume !(0 == ~T2_E~0); 49175#L1184-1 assume !(0 == ~T3_E~0); 49176#L1189-1 assume !(0 == ~T4_E~0); 49216#L1194-1 assume !(0 == ~T5_E~0); 49307#L1199-1 assume !(0 == ~T6_E~0); 50192#L1204-1 assume !(0 == ~T7_E~0); 50111#L1209-1 assume !(0 == ~T8_E~0); 50112#L1214-1 assume !(0 == ~T9_E~0); 50548#L1219-1 assume !(0 == ~T10_E~0); 50663#L1224-1 assume !(0 == ~T11_E~0); 49533#L1229-1 assume !(0 == ~T12_E~0); 49107#L1234-1 assume !(0 == ~E_1~0); 49108#L1239-1 assume !(0 == ~E_2~0); 49140#L1244-1 assume !(0 == ~E_3~0); 49141#L1249-1 assume !(0 == ~E_4~0); 49779#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 49037#L1259-1 assume !(0 == ~E_6~0); 48990#L1264-1 assume !(0 == ~E_7~0); 48991#L1269-1 assume !(0 == ~E_8~0); 50670#L1274-1 assume !(0 == ~E_9~0); 50577#L1279-1 assume !(0 == ~E_10~0); 49220#L1284-1 assume !(0 == ~E_11~0); 49221#L1289-1 assume !(0 == ~E_12~0); 49828#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49829#L566 assume 1 == ~m_pc~0; 49007#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49008#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49873#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49874#L1455 assume !(0 != activate_threads_~tmp~1#1); 49440#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49441#L585 assume 1 == ~t1_pc~0; 49104#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49105#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50250#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50251#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 50608#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50604#L604 assume !(1 == ~t2_pc~0); 50154#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 50155#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49383#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49384#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50356#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50357#L623 assume 1 == ~t3_pc~0; 49617#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48969#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50223#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50224#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 50393#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49004#L642 assume !(1 == ~t4_pc~0); 49005#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49453#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49059#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49060#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 49081#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50168#L661 assume 1 == ~t5_pc~0; 49233#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49234#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50081#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50459#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 50199#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50200#L680 assume !(1 == ~t6_pc~0); 49651#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49652#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49374#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49375#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 50471#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50601#L699 assume 1 == ~t7_pc~0; 50043#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50044#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50283#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49935#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 49936#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49830#L718 assume !(1 == ~t8_pc~0); 49831#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49214#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49215#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49249#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 49250#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49380#L737 assume 1 == ~t9_pc~0; 50238#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49514#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49420#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49421#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 49689#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49690#L756 assume 1 == ~t10_pc~0; 50273#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49926#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50187#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49866#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 49492#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49493#L775 assume !(1 == ~t11_pc~0); 49748#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 49749#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50541#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49150#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 49151#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49328#L794 assume 1 == ~t12_pc~0; 49173#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 49153#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49010#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49011#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 49293#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49763#L1307 assume !(1 == ~M_E~0); 49764#L1307-2 assume !(1 == ~T1_E~0); 49870#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49792#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49793#L1322-1 assume !(1 == ~T4_E~0); 49504#L1327-1 assume !(1 == ~T5_E~0); 49505#L1332-1 assume !(1 == ~T6_E~0); 50048#L1337-1 assume !(1 == ~T7_E~0); 51031#L1342-1 assume !(1 == ~T8_E~0); 51029#L1347-1 assume !(1 == ~T9_E~0); 50576#L1352-1 assume !(1 == ~T10_E~0); 51026#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 51024#L1362-1 assume !(1 == ~T12_E~0); 51022#L1367-1 assume !(1 == ~E_1~0); 50764#L1372-1 assume !(1 == ~E_2~0); 50763#L1377-1 assume !(1 == ~E_3~0); 50762#L1382-1 assume !(1 == ~E_4~0); 50760#L1387-1 assume !(1 == ~E_5~0); 50746#L1392-1 assume !(1 == ~E_6~0); 50744#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 50742#L1402-1 assume !(1 == ~E_8~0); 50740#L1407-1 assume !(1 == ~E_9~0); 50738#L1412-1 assume !(1 == ~E_10~0); 50736#L1417-1 assume !(1 == ~E_11~0); 50735#L1422-1 assume !(1 == ~E_12~0); 50722#L1427-1 assume { :end_inline_reset_delta_events } true; 50716#L1768-2 [2022-12-13 19:05:28,137 INFO L750 eck$LassoCheckResult]: Loop: 50716#L1768-2 assume !false; 50711#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50708#L1149 assume !false; 50707#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 50699#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 50693#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 50692#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 50690#L976 assume !(0 != eval_~tmp~0#1); 50689#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50688#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50687#L1174-3 assume !(0 == ~M_E~0); 50686#L1174-5 assume !(0 == ~T1_E~0); 50684#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50685#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51986#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49921#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49284#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49285#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49524#L1209-3 assume !(0 == ~T8_E~0); 48953#L1214-3 assume !(0 == ~T9_E~0); 48954#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49700#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49701#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 49715#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49144#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49145#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49579#L1249-3 assume !(0 == ~E_4~0); 50034#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50544#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50139#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49148#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49149#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50575#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49698#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 49699#L1289-3 assume !(0 == ~E_12~0); 49686#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49364#L566-39 assume 1 == ~m_pc~0; 49365#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49964#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49965#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50016#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50214#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50215#L585-39 assume 1 == ~t1_pc~0; 50347#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49373#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49576#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50538#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50254#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49941#L604-39 assume 1 == ~t2_pc~0; 49942#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49583#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49584#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49762#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49993#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49565#L623-39 assume 1 == ~t3_pc~0; 48970#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48972#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50233#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49415#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49416#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50175#L642-39 assume 1 == ~t4_pc~0; 49753#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49754#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49916#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49917#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50410#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49334#L661-39 assume !(1 == ~t5_pc~0); 48978#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 48979#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49948#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49949#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50235#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50236#L680-39 assume 1 == ~t6_pc~0; 49042#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49043#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50494#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49490#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49491#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50550#L699-39 assume 1 == ~t7_pc~0; 49923#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49654#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49655#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50240#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50490#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50487#L718-39 assume 1 == ~t8_pc~0; 49834#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49835#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50338#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50339#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 50080#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50056#L737-39 assume 1 == ~t9_pc~0; 50057#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51762#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51761#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51760#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50458#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50394#L756-39 assume !(1 == ~t10_pc~0); 49848#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 49849#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50537#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49733#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49734#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49091#L775-39 assume 1 == ~t11_pc~0; 49092#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49724#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49725#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49976#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50660#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50963#L794-39 assume !(1 == ~t12_pc~0); 50960#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 50958#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50956#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50954#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50951#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50949#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50947#L1307-5 assume !(1 == ~T1_E~0); 50945#L1312-3 assume !(1 == ~T2_E~0); 50669#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50942#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50939#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50937#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50935#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50933#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50931#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50340#L1352-3 assume !(1 == ~T10_E~0); 50927#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50925#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50923#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50921#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50919#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50917#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50914#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50912#L1392-3 assume !(1 == ~E_6~0); 50910#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50908#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50906#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50904#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 50901#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 50899#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50897#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 50890#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 50876#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 50873#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 50872#L1787 assume !(0 == start_simulation_~tmp~3#1); 50870#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 50753#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 50745#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 50743#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 50741#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50739#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50737#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 50723#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 50716#L1768-2 [2022-12-13 19:05:28,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:28,137 INFO L85 PathProgramCache]: Analyzing trace with hash -1694374055, now seen corresponding path program 1 times [2022-12-13 19:05:28,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:28,138 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247705339] [2022-12-13 19:05:28,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:28,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:28,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:28,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:28,202 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:28,202 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1247705339] [2022-12-13 19:05:28,203 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1247705339] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:28,203 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:28,203 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:28,203 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [522691108] [2022-12-13 19:05:28,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:28,203 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:28,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:28,204 INFO L85 PathProgramCache]: Analyzing trace with hash 1730309576, now seen corresponding path program 1 times [2022-12-13 19:05:28,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:28,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381245307] [2022-12-13 19:05:28,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:28,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:28,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:28,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:28,239 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:28,239 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381245307] [2022-12-13 19:05:28,239 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [381245307] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:28,239 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:28,239 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:28,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887019904] [2022-12-13 19:05:28,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:28,240 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:28,240 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:28,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:05:28,240 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:05:28,241 INFO L87 Difference]: Start difference. First operand 3238 states and 4766 transitions. cyclomatic complexity: 1530 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:28,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:28,412 INFO L93 Difference]: Finished difference Result 6132 states and 9017 transitions. [2022-12-13 19:05:28,412 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6132 states and 9017 transitions. [2022-12-13 19:05:28,435 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5922 [2022-12-13 19:05:28,477 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6132 states to 6132 states and 9017 transitions. [2022-12-13 19:05:28,477 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6132 [2022-12-13 19:05:28,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6132 [2022-12-13 19:05:28,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6132 states and 9017 transitions. [2022-12-13 19:05:28,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:28,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6132 states and 9017 transitions. [2022-12-13 19:05:28,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6132 states and 9017 transitions. [2022-12-13 19:05:28,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6132 to 6130. [2022-12-13 19:05:28,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6130 states, 6130 states have (on average 1.4706362153344208) internal successors, (9015), 6129 states have internal predecessors, (9015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:28,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6130 states to 6130 states and 9015 transitions. [2022-12-13 19:05:28,558 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6130 states and 9015 transitions. [2022-12-13 19:05:28,559 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:05:28,559 INFO L428 stractBuchiCegarLoop]: Abstraction has 6130 states and 9015 transitions. [2022-12-13 19:05:28,559 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 19:05:28,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6130 states and 9015 transitions. [2022-12-13 19:05:28,576 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5922 [2022-12-13 19:05:28,576 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:28,576 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:28,578 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:28,578 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:28,578 INFO L748 eck$LassoCheckResult]: Stem: 58581#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 58582#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 59376#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59377#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59246#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 59247#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59339#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59647#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59790#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59791#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58558#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58559#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59717#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59143#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59144#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59049#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59050#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59450#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58794#L1174 assume !(0 == ~M_E~0); 58795#L1174-2 assume !(0 == ~T1_E~0); 58648#L1179-1 assume !(0 == ~T2_E~0); 58556#L1184-1 assume !(0 == ~T3_E~0); 58557#L1189-1 assume !(0 == ~T4_E~0); 58597#L1194-1 assume !(0 == ~T5_E~0); 58688#L1199-1 assume !(0 == ~T6_E~0); 59580#L1204-1 assume !(0 == ~T7_E~0); 59497#L1209-1 assume !(0 == ~T8_E~0); 59498#L1214-1 assume !(0 == ~T9_E~0); 59952#L1219-1 assume !(0 == ~T10_E~0); 60071#L1224-1 assume !(0 == ~T11_E~0); 58914#L1229-1 assume !(0 == ~T12_E~0); 58488#L1234-1 assume !(0 == ~E_1~0); 58489#L1239-1 assume !(0 == ~E_2~0); 58523#L1244-1 assume !(0 == ~E_3~0); 58524#L1249-1 assume !(0 == ~E_4~0); 59163#L1254-1 assume !(0 == ~E_5~0); 58418#L1259-1 assume !(0 == ~E_6~0); 58370#L1264-1 assume !(0 == ~E_7~0); 58371#L1269-1 assume !(0 == ~E_8~0); 60078#L1274-1 assume !(0 == ~E_9~0); 59985#L1279-1 assume !(0 == ~E_10~0); 58601#L1284-1 assume !(0 == ~E_11~0); 58602#L1289-1 assume !(0 == ~E_12~0); 59215#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59216#L566 assume 1 == ~m_pc~0; 58387#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58388#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59260#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59261#L1455 assume !(0 != activate_threads_~tmp~1#1); 58821#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58822#L585 assume 1 == ~t1_pc~0; 58485#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58486#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59638#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59639#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 60023#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60018#L604 assume !(1 == ~t2_pc~0); 59540#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59541#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58766#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58767#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59748#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59749#L623 assume 1 == ~t3_pc~0; 58998#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58349#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59611#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59612#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 59784#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58384#L642 assume !(1 == ~t4_pc~0); 58385#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 58834#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58440#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58441#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 58462#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59556#L661 assume 1 == ~t5_pc~0; 58614#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58615#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59468#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59850#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 59589#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59590#L680 assume !(1 == ~t6_pc~0); 59031#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 59032#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58755#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58756#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 59863#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60015#L699 assume 1 == ~t7_pc~0; 59430#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59431#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59670#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59321#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 59322#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59217#L718 assume !(1 == ~t8_pc~0); 59218#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 58595#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58596#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58630#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 58631#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58761#L737 assume 1 == ~t9_pc~0; 59626#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58894#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58801#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58802#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 59069#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59070#L756 assume 1 == ~t10_pc~0; 59660#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59312#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59575#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59253#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 58873#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58874#L775 assume !(1 == ~t11_pc~0); 59132#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 59133#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59944#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58531#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58532#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58709#L794 assume 1 == ~t12_pc~0; 58555#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58534#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58393#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58394#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 58674#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59147#L1307 assume !(1 == ~M_E~0); 59148#L1307-2 assume !(1 == ~T1_E~0); 59257#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60037#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59397#L1322-1 assume !(1 == ~T4_E~0); 59398#L1327-1 assume !(1 == ~T5_E~0); 60527#L1332-1 assume !(1 == ~T6_E~0); 60028#L1337-1 assume !(1 == ~T7_E~0); 60029#L1342-1 assume !(1 == ~T8_E~0); 59983#L1347-1 assume !(1 == ~T9_E~0); 59822#L1352-1 assume !(1 == ~T10_E~0); 59671#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59047#L1362-1 assume !(1 == ~T12_E~0); 59048#L1367-1 assume !(1 == ~E_1~0); 59879#L1372-1 assume !(1 == ~E_2~0); 60187#L1377-1 assume !(1 == ~E_3~0); 60185#L1382-1 assume !(1 == ~E_4~0); 60184#L1387-1 assume !(1 == ~E_5~0); 60181#L1392-1 assume !(1 == ~E_6~0); 60167#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 60165#L1402-1 assume !(1 == ~E_8~0); 60163#L1407-1 assume !(1 == ~E_9~0); 60161#L1412-1 assume !(1 == ~E_10~0); 60159#L1417-1 assume !(1 == ~E_11~0); 60136#L1422-1 assume !(1 == ~E_12~0); 60127#L1427-1 assume { :end_inline_reset_delta_events } true; 60120#L1768-2 [2022-12-13 19:05:28,578 INFO L750 eck$LassoCheckResult]: Loop: 60120#L1768-2 assume !false; 60114#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60110#L1149 assume !false; 60109#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60101#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60095#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60094#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 60092#L976 assume !(0 != eval_~tmp~0#1); 60091#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60090#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60089#L1174-3 assume !(0 == ~M_E~0); 60088#L1174-5 assume !(0 == ~T1_E~0); 60087#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60020#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59672#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59307#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 58665#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 58666#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58904#L1209-3 assume !(0 == ~T8_E~0); 58333#L1214-3 assume !(0 == ~T9_E~0); 58334#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 59080#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 59081#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59095#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 58525#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58526#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58960#L1249-3 assume !(0 == ~E_4~0); 59422#L1254-3 assume !(0 == ~E_5~0); 59948#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59525#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 58529#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 58530#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 60051#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 61595#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 61593#L1289-3 assume !(0 == ~E_12~0); 61591#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61589#L566-39 assume 1 == ~m_pc~0; 61586#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 61583#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61581#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 61579#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61577#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61575#L585-39 assume 1 == ~t1_pc~0; 61571#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 61569#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61567#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61565#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 61563#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61562#L604-39 assume 1 == ~t2_pc~0; 61556#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61554#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61075#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61072#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 61070#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61068#L623-39 assume !(1 == ~t3_pc~0); 61065#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 61063#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61061#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61058#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61056#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61054#L642-39 assume 1 == ~t4_pc~0; 61050#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61048#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61045#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61043#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61041#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61039#L661-39 assume !(1 == ~t5_pc~0); 61036#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 61034#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61031#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61029#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 61027#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61025#L680-39 assume 1 == ~t6_pc~0; 61022#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61018#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61016#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61014#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 61013#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 61012#L699-39 assume !(1 == ~t7_pc~0); 61010#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 61006#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61001#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61000#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 60999#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60998#L718-39 assume 1 == ~t8_pc~0; 60996#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60995#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60994#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60993#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 60992#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60991#L737-39 assume 1 == ~t9_pc~0; 60989#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60987#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60985#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 60983#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 60981#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60978#L756-39 assume 1 == ~t10_pc~0; 60976#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 60973#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60971#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60969#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 60967#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60966#L775-39 assume 1 == ~t11_pc~0; 60964#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 60961#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60959#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60957#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 60955#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60953#L794-39 assume !(1 == ~t12_pc~0); 60950#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 60949#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60946#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60944#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 60942#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60940#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 60938#L1307-5 assume !(1 == ~T1_E~0); 60384#L1312-3 assume !(1 == ~T2_E~0); 60077#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60380#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60378#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 60376#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60374#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60372#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 60369#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60366#L1352-3 assume !(1 == ~T10_E~0); 60364#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 60362#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 60360#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 60358#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60357#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60354#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 60352#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 60348#L1392-3 assume !(1 == ~E_6~0); 60346#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 60344#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 60342#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 60339#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 60337#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 60335#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 60333#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60326#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60313#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60311#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 60308#L1787 assume !(0 == start_simulation_~tmp~3#1); 60305#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60174#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60166#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60164#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 60162#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60160#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60137#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 60128#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 60120#L1768-2 [2022-12-13 19:05:28,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:28,579 INFO L85 PathProgramCache]: Analyzing trace with hash 32770907, now seen corresponding path program 1 times [2022-12-13 19:05:28,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:28,579 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969429408] [2022-12-13 19:05:28,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:28,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:28,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:28,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:28,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:28,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969429408] [2022-12-13 19:05:28,641 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969429408] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:28,642 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:28,642 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:05:28,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1874224896] [2022-12-13 19:05:28,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:28,642 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:28,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:28,643 INFO L85 PathProgramCache]: Analyzing trace with hash 813883881, now seen corresponding path program 1 times [2022-12-13 19:05:28,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:28,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265190943] [2022-12-13 19:05:28,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:28,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:28,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:28,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:28,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:28,683 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [265190943] [2022-12-13 19:05:28,683 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [265190943] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:28,683 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:28,683 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:28,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059705520] [2022-12-13 19:05:28,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:28,683 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:28,683 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:28,684 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:28,684 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:28,684 INFO L87 Difference]: Start difference. First operand 6130 states and 9015 transitions. cyclomatic complexity: 2889 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:28,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:28,788 INFO L93 Difference]: Finished difference Result 11989 states and 17511 transitions. [2022-12-13 19:05:28,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11989 states and 17511 transitions. [2022-12-13 19:05:28,847 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11778 [2022-12-13 19:05:28,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11989 states to 11989 states and 17511 transitions. [2022-12-13 19:05:28,871 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11989 [2022-12-13 19:05:28,877 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11989 [2022-12-13 19:05:28,877 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11989 states and 17511 transitions. [2022-12-13 19:05:28,884 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:28,885 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11989 states and 17511 transitions. [2022-12-13 19:05:28,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11989 states and 17511 transitions. [2022-12-13 19:05:29,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11989 to 11621. [2022-12-13 19:05:29,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11621 states, 11621 states have (on average 1.4624386885810172) internal successors, (16995), 11620 states have internal predecessors, (16995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:29,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11621 states to 11621 states and 16995 transitions. [2022-12-13 19:05:29,032 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11621 states and 16995 transitions. [2022-12-13 19:05:29,032 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:29,033 INFO L428 stractBuchiCegarLoop]: Abstraction has 11621 states and 16995 transitions. [2022-12-13 19:05:29,033 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 19:05:29,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11621 states and 16995 transitions. [2022-12-13 19:05:29,056 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11410 [2022-12-13 19:05:29,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:29,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:29,057 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:29,057 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:29,057 INFO L748 eck$LassoCheckResult]: Stem: 76704#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 76705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 77512#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77513#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77374#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 77375#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77473#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77807#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77957#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77958#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76680#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76681#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 77880#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77269#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77270#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77180#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 77181#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 77586#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76919#L1174 assume !(0 == ~M_E~0); 76920#L1174-2 assume !(0 == ~T1_E~0); 76775#L1179-1 assume !(0 == ~T2_E~0); 76678#L1184-1 assume !(0 == ~T3_E~0); 76679#L1189-1 assume !(0 == ~T4_E~0); 76720#L1194-1 assume !(0 == ~T5_E~0); 76816#L1199-1 assume !(0 == ~T6_E~0); 77728#L1204-1 assume !(0 == ~T7_E~0); 77637#L1209-1 assume !(0 == ~T8_E~0); 77638#L1214-1 assume !(0 == ~T9_E~0); 78133#L1219-1 assume !(0 == ~T10_E~0); 78293#L1224-1 assume !(0 == ~T11_E~0); 77042#L1229-1 assume !(0 == ~T12_E~0); 76610#L1234-1 assume !(0 == ~E_1~0); 76611#L1239-1 assume !(0 == ~E_2~0); 76645#L1244-1 assume !(0 == ~E_3~0); 76646#L1249-1 assume !(0 == ~E_4~0); 77290#L1254-1 assume !(0 == ~E_5~0); 76540#L1259-1 assume !(0 == ~E_6~0); 76496#L1264-1 assume !(0 == ~E_7~0); 76497#L1269-1 assume !(0 == ~E_8~0); 78311#L1274-1 assume !(0 == ~E_9~0); 78183#L1279-1 assume !(0 == ~E_10~0); 76724#L1284-1 assume !(0 == ~E_11~0); 76725#L1289-1 assume !(0 == ~E_12~0); 77342#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77343#L566 assume !(1 == ~m_pc~0); 77799#L566-2 is_master_triggered_~__retres1~0#1 := 0; 77800#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77391#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77392#L1455 assume !(0 != activate_threads_~tmp~1#1); 76946#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76947#L585 assume 1 == ~t1_pc~0; 76607#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76608#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77790#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 77791#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 78223#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78218#L604 assume !(1 == ~t2_pc~0); 77683#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 77684#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76894#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76895#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77916#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77917#L623 assume 1 == ~t3_pc~0; 77125#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76475#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77764#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77765#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 77950#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76510#L642 assume !(1 == ~t4_pc~0); 76511#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76959#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76568#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76569#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 76584#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77700#L661 assume 1 == ~t5_pc~0; 76739#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 76740#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77605#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78023#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 77738#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77739#L680 assume !(1 == ~t6_pc~0); 77158#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 77159#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76883#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76884#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 78038#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78215#L699 assume 1 == ~t7_pc~0; 77566#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 77567#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77829#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77454#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 77455#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77344#L718 assume !(1 == ~t8_pc~0); 77345#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 76718#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76719#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76757#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 76758#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76886#L737 assume 1 == ~t9_pc~0; 77780#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77025#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76926#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76927#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 77198#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77199#L756 assume 1 == ~t10_pc~0; 77819#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 77446#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77723#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77381#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 77000#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77001#L775 assume !(1 == ~t11_pc~0); 77258#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 77259#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 78126#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76653#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 76654#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76836#L794 assume 1 == ~t12_pc~0; 76677#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 76656#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76515#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76516#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 76801#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77273#L1307 assume !(1 == ~M_E~0); 77274#L1307-2 assume !(1 == ~T1_E~0); 77385#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77303#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77304#L1322-1 assume !(1 == ~T4_E~0); 77013#L1327-1 assume !(1 == ~T5_E~0); 77014#L1332-1 assume !(1 == ~T6_E~0); 77572#L1337-1 assume !(1 == ~T7_E~0); 77526#L1342-1 assume !(1 == ~T8_E~0); 77527#L1347-1 assume !(1 == ~T9_E~0); 78180#L1352-1 assume !(1 == ~T10_E~0); 77830#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77831#L1362-1 assume !(1 == ~T12_E~0); 80138#L1367-1 assume !(1 == ~E_1~0); 80137#L1372-1 assume !(1 == ~E_2~0); 77314#L1377-1 assume !(1 == ~E_3~0); 77110#L1382-1 assume !(1 == ~E_4~0); 77111#L1387-1 assume !(1 == ~E_5~0); 80041#L1392-1 assume !(1 == ~E_6~0); 79333#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 79331#L1402-1 assume !(1 == ~E_8~0); 78952#L1407-1 assume !(1 == ~E_9~0); 78830#L1412-1 assume !(1 == ~E_10~0); 78826#L1417-1 assume !(1 == ~E_11~0); 78807#L1422-1 assume !(1 == ~E_12~0); 78798#L1427-1 assume { :end_inline_reset_delta_events } true; 78791#L1768-2 [2022-12-13 19:05:29,057 INFO L750 eck$LassoCheckResult]: Loop: 78791#L1768-2 assume !false; 78785#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 78781#L1149 assume !false; 78780#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 78772#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 78766#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 78765#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 78763#L976 assume !(0 != eval_~tmp~0#1); 78762#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78761#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78760#L1174-3 assume !(0 == ~M_E~0); 78759#L1174-5 assume !(0 == ~T1_E~0); 78756#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 78754#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78752#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 78750#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78748#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 78746#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 78743#L1209-3 assume !(0 == ~T8_E~0); 78741#L1214-3 assume !(0 == ~T9_E~0); 78739#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 78737#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 78735#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 78734#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 78732#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 78727#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78719#L1249-3 assume !(0 == ~E_4~0); 78645#L1254-3 assume !(0 == ~E_5~0); 78646#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 80993#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 80982#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 80966#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 80950#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 80941#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 80933#L1289-3 assume !(0 == ~E_12~0); 80926#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 80892#L566-39 assume !(1 == ~m_pc~0); 80888#L566-41 is_master_triggered_~__retres1~0#1 := 0; 80884#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80879#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 80875#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 80870#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80866#L585-39 assume !(1 == ~t1_pc~0); 80861#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 80854#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 80848#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 80842#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 80835#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80829#L604-39 assume !(1 == ~t2_pc~0); 80823#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 80815#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80810#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80803#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80761#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80723#L623-39 assume 1 == ~t3_pc~0; 80717#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 80710#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80702#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 80695#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 80689#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 80683#L642-39 assume !(1 == ~t4_pc~0); 80677#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 80670#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80663#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 80655#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 80649#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80642#L661-39 assume !(1 == ~t5_pc~0); 80635#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 80629#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80622#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 80614#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 80608#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80601#L680-39 assume !(1 == ~t6_pc~0); 80595#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 80587#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80580#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 80572#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 80566#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 80559#L699-39 assume 1 == ~t7_pc~0; 80553#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 80545#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 80538#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 80530#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 80524#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 80517#L718-39 assume !(1 == ~t8_pc~0); 80511#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 80503#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 80497#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 80489#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 80481#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 80472#L737-39 assume !(1 == ~t9_pc~0); 80464#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 80394#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 80391#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 80389#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 80387#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 80385#L756-39 assume 1 == ~t10_pc~0; 80383#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 80380#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 80377#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 80375#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 80373#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 80371#L775-39 assume !(1 == ~t11_pc~0); 80363#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 80360#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 80358#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 80356#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 80353#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 80351#L794-39 assume 1 == ~t12_pc~0; 80349#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 80346#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 80344#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 80342#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 80340#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 80338#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 80336#L1307-5 assume !(1 == ~T1_E~0); 80330#L1312-3 assume !(1 == ~T2_E~0); 80295#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 80326#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 80324#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 80239#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 80228#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 80219#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 80209#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 80198#L1352-3 assume !(1 == ~T10_E~0); 80191#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 80182#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 80174#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 80170#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 80163#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 80157#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 80152#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 80139#L1392-3 assume !(1 == ~E_6~0); 80079#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 80074#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 80069#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 80062#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 80056#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 80052#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 79612#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 79035#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 79022#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 79020#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 79017#L1787 assume !(0 == start_simulation_~tmp~3#1); 79014#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 78843#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 78835#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 78833#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 78832#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78831#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78808#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 78799#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 78791#L1768-2 [2022-12-13 19:05:29,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:29,057 INFO L85 PathProgramCache]: Analyzing trace with hash -1204882182, now seen corresponding path program 1 times [2022-12-13 19:05:29,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:29,058 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870481503] [2022-12-13 19:05:29,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:29,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:29,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:29,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:29,103 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:29,103 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870481503] [2022-12-13 19:05:29,103 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1870481503] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:29,103 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:29,103 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:29,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [725913707] [2022-12-13 19:05:29,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:29,104 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:29,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:29,104 INFO L85 PathProgramCache]: Analyzing trace with hash 713043780, now seen corresponding path program 1 times [2022-12-13 19:05:29,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:29,104 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997413934] [2022-12-13 19:05:29,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:29,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:29,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:29,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:29,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:29,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1997413934] [2022-12-13 19:05:29,136 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1997413934] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:29,136 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:29,136 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:29,137 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [729364094] [2022-12-13 19:05:29,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:29,137 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:29,137 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:29,137 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:05:29,137 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:05:29,138 INFO L87 Difference]: Start difference. First operand 11621 states and 16995 transitions. cyclomatic complexity: 5382 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:29,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:29,472 INFO L93 Difference]: Finished difference Result 28292 states and 41065 transitions. [2022-12-13 19:05:29,472 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28292 states and 41065 transitions. [2022-12-13 19:05:29,561 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 27682 [2022-12-13 19:05:29,617 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28292 states to 28292 states and 41065 transitions. [2022-12-13 19:05:29,617 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28292 [2022-12-13 19:05:29,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28292 [2022-12-13 19:05:29,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28292 states and 41065 transitions. [2022-12-13 19:05:29,647 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:29,648 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28292 states and 41065 transitions. [2022-12-13 19:05:29,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28292 states and 41065 transitions. [2022-12-13 19:05:29,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28292 to 22174. [2022-12-13 19:05:29,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22174 states, 22174 states have (on average 1.4561197799224317) internal successors, (32288), 22173 states have internal predecessors, (32288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:29,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22174 states to 22174 states and 32288 transitions. [2022-12-13 19:05:29,902 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22174 states and 32288 transitions. [2022-12-13 19:05:29,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:05:29,903 INFO L428 stractBuchiCegarLoop]: Abstraction has 22174 states and 32288 transitions. [2022-12-13 19:05:29,903 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 19:05:29,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22174 states and 32288 transitions. [2022-12-13 19:05:29,970 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 21960 [2022-12-13 19:05:29,970 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:29,970 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:29,971 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:29,971 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:29,972 INFO L748 eck$LassoCheckResult]: Stem: 116622#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 116623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 117434#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 117435#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 117296#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 117297#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 117394#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 117721#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 117861#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 117862#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 116598#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 116599#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 117787#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 117193#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 117194#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 117102#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 117103#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 117513#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 116837#L1174 assume !(0 == ~M_E~0); 116838#L1174-2 assume !(0 == ~T1_E~0); 116691#L1179-1 assume !(0 == ~T2_E~0); 116596#L1184-1 assume !(0 == ~T3_E~0); 116597#L1189-1 assume !(0 == ~T4_E~0); 116639#L1194-1 assume !(0 == ~T5_E~0); 116731#L1199-1 assume !(0 == ~T6_E~0); 117648#L1204-1 assume !(0 == ~T7_E~0); 117560#L1209-1 assume !(0 == ~T8_E~0); 117561#L1214-1 assume !(0 == ~T9_E~0); 118018#L1219-1 assume !(0 == ~T10_E~0); 118150#L1224-1 assume !(0 == ~T11_E~0); 116961#L1229-1 assume !(0 == ~T12_E~0); 116529#L1234-1 assume !(0 == ~E_1~0); 116530#L1239-1 assume !(0 == ~E_2~0); 116562#L1244-1 assume !(0 == ~E_3~0); 116563#L1249-1 assume !(0 == ~E_4~0); 117212#L1254-1 assume !(0 == ~E_5~0); 116462#L1259-1 assume !(0 == ~E_6~0); 116418#L1264-1 assume !(0 == ~E_7~0); 116419#L1269-1 assume !(0 == ~E_8~0); 118164#L1274-1 assume !(0 == ~E_9~0); 118060#L1279-1 assume !(0 == ~E_10~0); 116642#L1284-1 assume !(0 == ~E_11~0); 116643#L1289-1 assume !(0 == ~E_12~0); 117264#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117265#L566 assume !(1 == ~m_pc~0); 117717#L566-2 is_master_triggered_~__retres1~0#1 := 0; 117718#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117310#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 117311#L1455 assume !(0 != activate_threads_~tmp~1#1); 116864#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116865#L585 assume !(1 == ~t1_pc~0); 117050#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 117051#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117710#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 117711#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 118100#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118095#L604 assume !(1 == ~t2_pc~0); 117608#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 117609#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116807#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 116808#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117820#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117821#L623 assume 1 == ~t3_pc~0; 117049#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 116397#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117682#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 117683#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 117854#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116432#L642 assume !(1 == ~t4_pc~0); 116433#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 116879#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116484#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 116485#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 116506#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117623#L661 assume 1 == ~t5_pc~0; 116657#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 116658#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117530#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 117927#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 117655#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 117656#L680 assume !(1 == ~t6_pc~0); 117084#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 117085#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 116798#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 116799#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 117938#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 118092#L699 assume 1 == ~t7_pc~0; 117492#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 117493#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 117745#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 117376#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 117377#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 117266#L718 assume !(1 == ~t8_pc~0); 117267#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 116637#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 116638#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 116673#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 116674#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 116804#L737 assume 1 == ~t9_pc~0; 117698#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 116943#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 116844#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 116845#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 117122#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 117123#L756 assume 1 == ~t10_pc~0; 117735#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 117365#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 117643#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 117303#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 116921#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 116922#L775 assume !(1 == ~t11_pc~0); 117182#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 117183#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 118011#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 116572#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 116573#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 116752#L794 assume 1 == ~t12_pc~0; 116594#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 116575#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 116435#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 116436#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 116717#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117197#L1307 assume !(1 == ~M_E~0); 117198#L1307-2 assume !(1 == ~T1_E~0); 117307#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 117225#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 117226#L1322-1 assume !(1 == ~T4_E~0); 116933#L1327-1 assume !(1 == ~T5_E~0); 116934#L1332-1 assume !(1 == ~T6_E~0); 118108#L1337-1 assume !(1 == ~T7_E~0); 118109#L1342-1 assume !(1 == ~T8_E~0); 118058#L1347-1 assume !(1 == ~T9_E~0); 118059#L1352-1 assume !(1 == ~T10_E~0); 117746#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 117747#L1362-1 assume !(1 == ~T12_E~0); 117953#L1367-1 assume !(1 == ~E_1~0); 117954#L1372-1 assume !(1 == ~E_2~0); 117236#L1377-1 assume !(1 == ~E_3~0); 117237#L1382-1 assume !(1 == ~E_4~0); 117610#L1387-1 assume !(1 == ~E_5~0); 117611#L1392-1 assume !(1 == ~E_6~0); 117054#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 117055#L1402-1 assume !(1 == ~E_8~0); 116747#L1407-1 assume !(1 == ~E_9~0); 116748#L1412-1 assume !(1 == ~E_10~0); 117815#L1417-1 assume !(1 == ~E_11~0); 117816#L1422-1 assume !(1 == ~E_12~0); 118087#L1427-1 assume { :end_inline_reset_delta_events } true; 116558#L1768-2 [2022-12-13 19:05:29,972 INFO L750 eck$LassoCheckResult]: Loop: 116558#L1768-2 assume !false; 116559#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 117291#L1149 assume !false; 117687#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 117873#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 116940#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 117794#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 117868#L976 assume !(0 != eval_~tmp~0#1); 118081#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 138489#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 138487#L1174-3 assume !(0 == ~M_E~0); 138485#L1174-5 assume !(0 == ~T1_E~0); 138483#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 138481#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 138479#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 138477#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 138476#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 138474#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 138472#L1209-3 assume !(0 == ~T8_E~0); 138470#L1214-3 assume !(0 == ~T9_E~0); 138468#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 138466#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 138463#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 138461#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 138459#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 138457#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 138442#L1249-3 assume !(0 == ~E_4~0); 138440#L1254-3 assume !(0 == ~E_5~0); 138438#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 138436#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 138434#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 138432#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 138429#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 138427#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 138425#L1289-3 assume !(0 == ~E_12~0); 138423#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138421#L566-39 assume !(1 == ~m_pc~0); 138419#L566-41 is_master_triggered_~__retres1~0#1 := 0; 138416#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138414#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 138412#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 138410#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138408#L585-39 assume !(1 == ~t1_pc~0); 129241#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 138404#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138402#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 138400#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 138398#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 138396#L604-39 assume !(1 == ~t2_pc~0); 138394#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 138390#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 138388#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 138386#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 138384#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138382#L623-39 assume !(1 == ~t3_pc~0); 138379#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 138376#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 138374#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 138372#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 138370#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 138365#L642-39 assume 1 == ~t4_pc~0; 117187#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 117188#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 138362#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 138361#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 138360#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138359#L661-39 assume 1 == ~t5_pc~0; 138358#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 138356#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 138355#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 138354#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 138353#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 138352#L680-39 assume 1 == ~t6_pc~0; 138350#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 138349#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 138347#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 138345#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 138343#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 138327#L699-39 assume !(1 == ~t7_pc~0); 117363#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 117087#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 117088#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 117700#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 117959#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 117956#L718-39 assume 1 == ~t8_pc~0; 117270#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 117271#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 117799#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 117800#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 117529#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 117506#L737-39 assume 1 == ~t9_pc~0; 116897#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 116898#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 116495#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 116496#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 117926#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 117855#L756-39 assume 1 == ~t10_pc~0; 117856#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 117286#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 118007#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 117167#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 117168#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 116516#L775-39 assume 1 == ~t11_pc~0; 116517#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 117159#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 117160#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 117419#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 118146#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 138286#L794-39 assume !(1 == ~t12_pc~0); 138283#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 138280#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 138278#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 138275#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 138274#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138147#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 117991#L1307-5 assume !(1 == ~T1_E~0); 117992#L1312-3 assume !(1 == ~T2_E~0); 118163#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 137587#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 137586#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 137584#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 137582#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 137580#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 137578#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 117801#L1352-3 assume !(1 == ~T10_E~0); 137575#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 137573#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 137571#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 137569#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 137567#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 137565#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 137563#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 137206#L1392-3 assume !(1 == ~E_6~0); 137560#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 137558#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 137557#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 116669#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 116670#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 117315#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 117316#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 116677#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 116678#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 116743#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 116744#L1787 assume !(0 == start_simulation_~tmp~3#1); 117410#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 118000#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 116652#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 116410#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 116411#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 117002#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 117003#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 117966#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 116558#L1768-2 [2022-12-13 19:05:29,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:29,972 INFO L85 PathProgramCache]: Analyzing trace with hash 1220887001, now seen corresponding path program 1 times [2022-12-13 19:05:29,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:29,973 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919092633] [2022-12-13 19:05:29,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:29,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:29,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:30,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:30,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:30,017 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919092633] [2022-12-13 19:05:30,017 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [919092633] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:30,017 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:30,017 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:05:30,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [949661781] [2022-12-13 19:05:30,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:30,017 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:30,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:30,018 INFO L85 PathProgramCache]: Analyzing trace with hash 1291309479, now seen corresponding path program 1 times [2022-12-13 19:05:30,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:30,018 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962043019] [2022-12-13 19:05:30,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:30,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:30,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:30,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:30,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:30,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [962043019] [2022-12-13 19:05:30,048 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [962043019] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:30,048 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:30,048 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:30,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647413588] [2022-12-13 19:05:30,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:30,048 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:30,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:30,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:05:30,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:05:30,049 INFO L87 Difference]: Start difference. First operand 22174 states and 32288 transitions. cyclomatic complexity: 10122 Second operand has 5 states, 5 states have (on average 29.6) internal successors, (148), 5 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:30,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:30,460 INFO L93 Difference]: Finished difference Result 61985 states and 90255 transitions. [2022-12-13 19:05:30,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61985 states and 90255 transitions. [2022-12-13 19:05:30,702 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 61464 [2022-12-13 19:05:30,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61985 states to 61985 states and 90255 transitions. [2022-12-13 19:05:30,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61985 [2022-12-13 19:05:30,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61985 [2022-12-13 19:05:30,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61985 states and 90255 transitions. [2022-12-13 19:05:30,840 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:30,840 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61985 states and 90255 transitions. [2022-12-13 19:05:30,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61985 states and 90255 transitions. [2022-12-13 19:05:31,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61985 to 22777. [2022-12-13 19:05:31,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22777 states, 22777 states have (on average 1.4440444307854414) internal successors, (32891), 22776 states have internal predecessors, (32891), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:31,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22777 states to 22777 states and 32891 transitions. [2022-12-13 19:05:31,178 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22777 states and 32891 transitions. [2022-12-13 19:05:31,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 19:05:31,178 INFO L428 stractBuchiCegarLoop]: Abstraction has 22777 states and 32891 transitions. [2022-12-13 19:05:31,179 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 19:05:31,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22777 states and 32891 transitions. [2022-12-13 19:05:31,228 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22560 [2022-12-13 19:05:31,228 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:31,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:31,229 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:31,229 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:31,229 INFO L748 eck$LassoCheckResult]: Stem: 200795#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 200796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 201633#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 201634#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 201482#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 201483#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 201590#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 201939#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 202105#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 202106#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 200771#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 200772#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 202016#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 201375#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 201376#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 201285#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 201286#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 201718#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 201016#L1174 assume !(0 == ~M_E~0); 201017#L1174-2 assume !(0 == ~T1_E~0); 200864#L1179-1 assume !(0 == ~T2_E~0); 200769#L1184-1 assume !(0 == ~T3_E~0); 200770#L1189-1 assume !(0 == ~T4_E~0); 200812#L1194-1 assume !(0 == ~T5_E~0); 200906#L1199-1 assume !(0 == ~T6_E~0); 201859#L1204-1 assume !(0 == ~T7_E~0); 201765#L1209-1 assume !(0 == ~T8_E~0); 201766#L1214-1 assume !(0 == ~T9_E~0); 202292#L1219-1 assume !(0 == ~T10_E~0); 202456#L1224-1 assume !(0 == ~T11_E~0); 201138#L1229-1 assume !(0 == ~T12_E~0); 200702#L1234-1 assume !(0 == ~E_1~0); 200703#L1239-1 assume !(0 == ~E_2~0); 200735#L1244-1 assume !(0 == ~E_3~0); 200736#L1249-1 assume !(0 == ~E_4~0); 201396#L1254-1 assume !(0 == ~E_5~0); 200634#L1259-1 assume !(0 == ~E_6~0); 200590#L1264-1 assume !(0 == ~E_7~0); 200591#L1269-1 assume !(0 == ~E_8~0); 202480#L1274-1 assume !(0 == ~E_9~0); 202337#L1279-1 assume !(0 == ~E_10~0); 200815#L1284-1 assume !(0 == ~E_11~0); 200816#L1289-1 assume !(0 == ~E_12~0); 201449#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 201450#L566 assume !(1 == ~m_pc~0); 201935#L566-2 is_master_triggered_~__retres1~0#1 := 0; 201936#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 201500#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 201501#L1455 assume !(0 != activate_threads_~tmp~1#1); 201043#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 201044#L585 assume !(1 == ~t1_pc~0); 201229#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 201230#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201925#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 201926#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 202387#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 202381#L604 assume !(1 == ~t2_pc~0); 201814#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 201815#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 202355#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 202254#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 202058#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 202059#L623 assume 1 == ~t3_pc~0; 201228#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 200569#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 201896#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 201897#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 202096#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 200604#L642 assume !(1 == ~t4_pc~0); 200605#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 201056#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 200656#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 200657#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 200679#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 201830#L661 assume 1 == ~t5_pc~0; 200830#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 200831#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 201735#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 202181#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 201868#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 201869#L680 assume !(1 == ~t6_pc~0); 201266#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 201267#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 200975#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 200976#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 202195#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 202378#L699 assume 1 == ~t7_pc~0; 201691#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 201692#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 201968#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 201570#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 201571#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 201451#L718 assume !(1 == ~t8_pc~0); 201452#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 200810#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 200811#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 200846#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 200847#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 200982#L737 assume 1 == ~t9_pc~0; 201911#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 201120#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 201023#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 201024#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 201305#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 201306#L756 assume 1 == ~t10_pc~0; 201957#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 201558#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 201854#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 201489#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 201096#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 201097#L775 assume !(1 == ~t11_pc~0); 201364#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 201365#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 202283#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 200745#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 200746#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 200927#L794 assume 1 == ~t12_pc~0; 200767#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 200748#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 200607#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 200608#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 200891#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 201381#L1307 assume !(1 == ~M_E~0); 201382#L1307-2 assume !(1 == ~T1_E~0); 201494#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 202412#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 213659#L1322-1 assume !(1 == ~T4_E~0); 213658#L1327-1 assume !(1 == ~T5_E~0); 213657#L1332-1 assume !(1 == ~T6_E~0); 213656#L1337-1 assume !(1 == ~T7_E~0); 213655#L1342-1 assume !(1 == ~T8_E~0); 202336#L1347-1 assume !(1 == ~T9_E~0); 202142#L1352-1 assume !(1 == ~T10_E~0); 201969#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 201283#L1362-1 assume !(1 == ~T12_E~0); 201284#L1367-1 assume !(1 == ~E_1~0); 200907#L1372-1 assume !(1 == ~E_2~0); 200908#L1377-1 assume !(1 == ~E_3~0); 201212#L1382-1 assume !(1 == ~E_4~0); 201213#L1387-1 assume !(1 == ~E_5~0); 201816#L1392-1 assume !(1 == ~E_6~0); 201233#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 201234#L1402-1 assume !(1 == ~E_8~0); 200922#L1407-1 assume !(1 == ~E_9~0); 200923#L1412-1 assume !(1 == ~E_10~0); 202048#L1417-1 assume !(1 == ~E_11~0); 202049#L1422-1 assume !(1 == ~E_12~0); 202371#L1427-1 assume { :end_inline_reset_delta_events } true; 200731#L1768-2 [2022-12-13 19:05:31,230 INFO L750 eck$LassoCheckResult]: Loop: 200731#L1768-2 assume !false; 200732#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 201476#L1149 assume !false; 201901#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 202119#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 201117#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 202026#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 202113#L976 assume !(0 != eval_~tmp~0#1); 201440#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 201159#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 201160#L1174-3 assume !(0 == ~M_E~0); 202063#L1174-5 assume !(0 == ~T1_E~0); 201746#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 201747#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 201970#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 201553#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 200882#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 200883#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 201864#L1209-3 assume !(0 == ~T8_E~0); 207223#L1214-3 assume !(0 == ~T9_E~0); 223289#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 223288#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 223287#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 223286#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 223285#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 223284#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 223283#L1249-3 assume !(0 == ~E_4~0); 223282#L1254-3 assume !(0 == ~E_5~0); 223281#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 223280#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 223279#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 223278#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 223277#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 223276#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 223275#L1289-3 assume !(0 == ~E_12~0); 223274#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 206895#L566-39 assume !(1 == ~m_pc~0); 206896#L566-41 is_master_triggered_~__retres1~0#1 := 0; 206891#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 206892#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 206875#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 206876#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 206872#L585-39 assume !(1 == ~t1_pc~0); 206443#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 206868#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 206869#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 202279#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 202280#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 206861#L604-39 assume !(1 == ~t2_pc~0); 206863#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 206855#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 206856#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 206848#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 206846#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 206845#L623-39 assume !(1 == ~t3_pc~0); 206843#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 206842#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 206841#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 206839#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 206840#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223236#L642-39 assume !(1 == ~t4_pc~0); 223235#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 223233#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 223232#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 223231#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 223230#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 223229#L661-39 assume !(1 == ~t5_pc~0); 223227#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 223226#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 223225#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 223224#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 223223#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 202236#L680-39 assume !(1 == ~t6_pc~0); 200641#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 200640#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 202217#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 201094#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 201095#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 202295#L699-39 assume 1 == ~t7_pc~0; 201555#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 201269#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 201270#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 201913#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 202302#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 223210#L718-39 assume !(1 == ~t8_pc~0); 223209#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 223207#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 223206#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 223205#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 223204#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 223203#L737-39 assume 1 == ~t9_pc~0; 201074#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 201075#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 223152#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 223151#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 223150#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 223149#L756-39 assume !(1 == ~t10_pc~0); 223147#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 223146#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 223145#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 222918#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 222917#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 222916#L775-39 assume !(1 == ~t11_pc~0); 222915#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 222913#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 222912#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 222911#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 222910#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 222909#L794-39 assume !(1 == ~t12_pc~0); 222907#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 222906#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 222905#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 222613#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 222484#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 222483#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 222482#L1307-5 assume !(1 == ~T1_E~0); 222481#L1312-3 assume !(1 == ~T2_E~0); 202479#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 222480#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 222479#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 222478#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 222477#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 222476#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 222475#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 215363#L1352-3 assume !(1 == ~T10_E~0); 222474#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 222473#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 222472#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 222471#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 222470#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 222469#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 222468#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 201196#L1392-3 assume !(1 == ~E_6~0); 222467#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 222466#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 222465#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 222464#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 222463#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 222462#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 202185#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 200850#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 200851#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 200918#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 200919#L1787 assume !(0 == start_simulation_~tmp~3#1); 201605#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 202266#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 200825#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 200582#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 200583#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 201178#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 201179#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 202220#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 200731#L1768-2 [2022-12-13 19:05:31,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:31,230 INFO L85 PathProgramCache]: Analyzing trace with hash 226193303, now seen corresponding path program 1 times [2022-12-13 19:05:31,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:31,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432629777] [2022-12-13 19:05:31,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:31,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:31,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:31,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:31,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:31,306 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432629777] [2022-12-13 19:05:31,306 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [432629777] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:31,306 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:31,306 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:31,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [611412964] [2022-12-13 19:05:31,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:31,307 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:31,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:31,307 INFO L85 PathProgramCache]: Analyzing trace with hash 1949231680, now seen corresponding path program 1 times [2022-12-13 19:05:31,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:31,308 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1419540245] [2022-12-13 19:05:31,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:31,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:31,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:31,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:31,350 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:31,350 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1419540245] [2022-12-13 19:05:31,350 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1419540245] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:31,350 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:31,350 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:31,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1038770846] [2022-12-13 19:05:31,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:31,351 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:31,351 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:31,351 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:05:31,351 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:05:31,351 INFO L87 Difference]: Start difference. First operand 22777 states and 32891 transitions. cyclomatic complexity: 10122 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:31,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:31,652 INFO L93 Difference]: Finished difference Result 55470 states and 79580 transitions. [2022-12-13 19:05:31,653 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55470 states and 79580 transitions. [2022-12-13 19:05:31,860 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 54434 [2022-12-13 19:05:31,996 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55470 states to 55470 states and 79580 transitions. [2022-12-13 19:05:31,996 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55470 [2022-12-13 19:05:32,016 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55470 [2022-12-13 19:05:32,016 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55470 states and 79580 transitions. [2022-12-13 19:05:32,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:32,043 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55470 states and 79580 transitions. [2022-12-13 19:05:32,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55470 states and 79580 transitions. [2022-12-13 19:05:32,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55470 to 43592. [2022-12-13 19:05:32,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43592 states, 43592 states have (on average 1.4387043494219123) internal successors, (62716), 43591 states have internal predecessors, (62716), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:32,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43592 states to 43592 states and 62716 transitions. [2022-12-13 19:05:32,560 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43592 states and 62716 transitions. [2022-12-13 19:05:32,560 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:05:32,561 INFO L428 stractBuchiCegarLoop]: Abstraction has 43592 states and 62716 transitions. [2022-12-13 19:05:32,561 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 19:05:32,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43592 states and 62716 transitions. [2022-12-13 19:05:32,664 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 43368 [2022-12-13 19:05:32,664 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:32,664 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:32,666 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:32,666 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:32,667 INFO L748 eck$LassoCheckResult]: Stem: 279049#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 279050#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 279875#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 279876#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 279735#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 279736#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 279836#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 280179#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 280334#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 280335#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 279025#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 279026#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 280246#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 279630#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 279631#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 279539#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 279540#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 279960#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 279265#L1174 assume !(0 == ~M_E~0); 279266#L1174-2 assume !(0 == ~T1_E~0); 279120#L1179-1 assume !(0 == ~T2_E~0); 279023#L1184-1 assume !(0 == ~T3_E~0); 279024#L1189-1 assume !(0 == ~T4_E~0); 279066#L1194-1 assume !(0 == ~T5_E~0); 279161#L1199-1 assume !(0 == ~T6_E~0); 280105#L1204-1 assume !(0 == ~T7_E~0); 280012#L1209-1 assume !(0 == ~T8_E~0); 280013#L1214-1 assume !(0 == ~T9_E~0); 280528#L1219-1 assume !(0 == ~T10_E~0); 280685#L1224-1 assume !(0 == ~T11_E~0); 279394#L1229-1 assume !(0 == ~T12_E~0); 278956#L1234-1 assume !(0 == ~E_1~0); 278957#L1239-1 assume !(0 == ~E_2~0); 278991#L1244-1 assume !(0 == ~E_3~0); 278992#L1249-1 assume !(0 == ~E_4~0); 279651#L1254-1 assume !(0 == ~E_5~0); 278889#L1259-1 assume !(0 == ~E_6~0); 278846#L1264-1 assume !(0 == ~E_7~0); 278847#L1269-1 assume !(0 == ~E_8~0); 280701#L1274-1 assume !(0 == ~E_9~0); 280572#L1279-1 assume !(0 == ~E_10~0); 279069#L1284-1 assume !(0 == ~E_11~0); 279070#L1289-1 assume !(0 == ~E_12~0); 279704#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 279705#L566 assume !(1 == ~m_pc~0); 280174#L566-2 is_master_triggered_~__retres1~0#1 := 0; 280175#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 279752#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 279753#L1455 assume !(0 != activate_threads_~tmp~1#1); 279292#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 279293#L585 assume !(1 == ~t1_pc~0); 279483#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 279484#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 280166#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 280167#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 280619#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 280613#L604 assume !(1 == ~t2_pc~0); 280062#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 280063#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 279239#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 279240#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 280288#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 280289#L623 assume !(1 == ~t3_pc~0); 278824#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 278825#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 280141#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 280142#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 280325#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 278860#L642 assume !(1 == ~t4_pc~0); 278861#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 279309#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 278917#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 278918#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 278933#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 280079#L661 assume 1 == ~t5_pc~0; 279084#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 279085#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 279977#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 280412#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 280114#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 280115#L680 assume !(1 == ~t6_pc~0); 279518#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 279519#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 279228#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 279229#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 280424#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 280610#L699 assume 1 == ~t7_pc~0; 279939#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 279940#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 280202#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 279818#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 279819#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 279706#L718 assume !(1 == ~t8_pc~0); 279707#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 279064#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 279065#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 279100#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 279101#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 279231#L737 assume 1 == ~t9_pc~0; 280156#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 279377#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 279272#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 279273#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 279559#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 279560#L756 assume 1 == ~t10_pc~0; 280192#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 279807#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 280100#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 279745#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 279352#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 279353#L775 assume !(1 == ~t11_pc~0); 279619#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 279620#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 280517#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 278999#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 279000#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 279179#L794 assume 1 == ~t12_pc~0; 279022#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 279002#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 278865#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 278866#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 279146#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 279634#L1307 assume !(1 == ~M_E~0); 279635#L1307-2 assume !(1 == ~T1_E~0); 279749#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 279665#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 279666#L1322-1 assume !(1 == ~T4_E~0); 279364#L1327-1 assume !(1 == ~T5_E~0); 279365#L1332-1 assume !(1 == ~T6_E~0); 280629#L1337-1 assume !(1 == ~T7_E~0); 280630#L1342-1 assume !(1 == ~T8_E~0); 280567#L1347-1 assume !(1 == ~T9_E~0); 280568#L1352-1 assume !(1 == ~T10_E~0); 280203#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 280204#L1362-1 assume !(1 == ~T12_E~0); 280439#L1367-1 assume !(1 == ~E_1~0); 280440#L1372-1 assume !(1 == ~E_2~0); 279676#L1377-1 assume !(1 == ~E_3~0); 279677#L1382-1 assume !(1 == ~E_4~0); 280064#L1387-1 assume !(1 == ~E_5~0); 280065#L1392-1 assume !(1 == ~E_6~0); 279489#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 279490#L1402-1 assume !(1 == ~E_8~0); 279175#L1407-1 assume !(1 == ~E_9~0); 279176#L1412-1 assume !(1 == ~E_10~0); 280276#L1417-1 assume !(1 == ~E_11~0); 280277#L1422-1 assume !(1 == ~E_12~0); 280605#L1427-1 assume { :end_inline_reset_delta_events } true; 280606#L1768-2 [2022-12-13 19:05:32,667 INFO L750 eck$LassoCheckResult]: Loop: 280606#L1768-2 assume !false; 279729#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 279730#L1149 assume !false; 280144#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 280347#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 279372#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 280253#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 280341#L976 assume !(0 != eval_~tmp~0#1); 279696#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 279414#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 279415#L1174-3 assume !(0 == ~M_E~0); 280291#L1174-5 assume !(0 == ~T1_E~0); 279991#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 279992#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 280205#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 279802#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 279138#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 279139#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 279384#L1209-3 assume !(0 == ~T8_E~0); 278811#L1214-3 assume !(0 == ~T9_E~0); 278812#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 279571#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 279572#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 279587#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 278993#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 278994#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 279445#L1249-3 assume !(0 == ~E_4~0); 279931#L1254-3 assume !(0 == ~E_5~0); 280521#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 280045#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 278997#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 278998#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 280566#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 279569#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 279570#L1289-3 assume !(0 == ~E_12~0); 279556#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 279211#L566-39 assume !(1 == ~m_pc~0); 279212#L566-41 is_master_triggered_~__retres1~0#1 := 0; 279847#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 279848#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 279905#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 280127#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 280128#L585-39 assume !(1 == ~t1_pc~0); 279220#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 279221#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 279440#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 280514#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 280170#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 279825#L604-39 assume 1 == ~t2_pc~0; 279826#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 279449#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 279450#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 279633#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 279881#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 279424#L623-39 assume !(1 == ~t3_pc~0); 279425#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 279911#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 280148#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 279267#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 279268#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 280087#L642-39 assume 1 == ~t4_pc~0; 279624#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 279625#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 279797#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 279798#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 280480#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 279184#L661-39 assume 1 == ~t5_pc~0; 279185#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 278835#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 279831#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 279832#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 280150#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 280151#L680-39 assume !(1 == ~t6_pc~0); 278896#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 278895#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 280454#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 279350#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 279351#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 280531#L699-39 assume 1 == ~t7_pc~0; 279804#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 279522#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 279523#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 280155#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 280445#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 280442#L718-39 assume !(1 == ~t8_pc~0); 279712#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 279711#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 280258#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 280259#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 279976#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 279953#L737-39 assume 1 == ~t9_pc~0; 279329#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 279330#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 278922#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 278923#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 280408#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 280327#L756-39 assume 1 == ~t10_pc~0; 280328#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 279724#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 280513#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 279604#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 279605#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 278943#L775-39 assume 1 == ~t11_pc~0; 278944#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 279596#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 279597#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 279859#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 280038#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 279650#L794-39 assume 1 == ~t12_pc~0; 279333#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 279326#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 279422#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 279423#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 278885#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 278886#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 280490#L1307-5 assume !(1 == ~T1_E~0); 280491#L1312-3 assume !(1 == ~T2_E~0); 280698#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 280112#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 280113#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 279011#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 278989#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 278990#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 279743#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 279878#L1352-3 assume !(1 == ~T10_E~0); 279879#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 280420#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 280680#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 280667#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 278819#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 278820#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 279452#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 279453#L1392-3 assume !(1 == ~E_6~0); 280232#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 280695#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 279846#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 279096#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 279097#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 279756#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 279757#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 279104#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 279105#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 279171#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 279172#L1787 assume !(0 == start_simulation_~tmp~3#1); 279849#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 280504#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 279079#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 278838#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 278839#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 279436#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 279437#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 280450#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 280606#L1768-2 [2022-12-13 19:05:32,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:32,667 INFO L85 PathProgramCache]: Analyzing trace with hash 1148113654, now seen corresponding path program 1 times [2022-12-13 19:05:32,667 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:32,668 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1384055860] [2022-12-13 19:05:32,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:32,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:32,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:32,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:32,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:32,717 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1384055860] [2022-12-13 19:05:32,717 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1384055860] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:32,717 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:32,718 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:05:32,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [66406527] [2022-12-13 19:05:32,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:32,718 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:32,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:32,719 INFO L85 PathProgramCache]: Analyzing trace with hash 696719304, now seen corresponding path program 1 times [2022-12-13 19:05:32,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:32,719 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920177078] [2022-12-13 19:05:32,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:32,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:32,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:32,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:32,759 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:32,760 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [920177078] [2022-12-13 19:05:32,760 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [920177078] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:32,760 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:32,760 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:32,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550476048] [2022-12-13 19:05:32,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:32,760 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:32,760 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:32,761 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:05:32,761 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:05:32,761 INFO L87 Difference]: Start difference. First operand 43592 states and 62716 transitions. cyclomatic complexity: 19132 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:33,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:33,012 INFO L93 Difference]: Finished difference Result 83567 states and 119801 transitions. [2022-12-13 19:05:33,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83567 states and 119801 transitions. [2022-12-13 19:05:33,326 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 83264 [2022-12-13 19:05:33,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83567 states to 83567 states and 119801 transitions. [2022-12-13 19:05:33,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83567 [2022-12-13 19:05:33,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83567 [2022-12-13 19:05:33,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83567 states and 119801 transitions. [2022-12-13 19:05:33,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:33,493 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83567 states and 119801 transitions. [2022-12-13 19:05:33,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83567 states and 119801 transitions. [2022-12-13 19:05:34,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83567 to 83503. [2022-12-13 19:05:34,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83503 states, 83503 states have (on average 1.433924529657617) internal successors, (119737), 83502 states have internal predecessors, (119737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:34,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83503 states to 83503 states and 119737 transitions. [2022-12-13 19:05:34,247 INFO L240 hiAutomatonCegarLoop]: Abstraction has 83503 states and 119737 transitions. [2022-12-13 19:05:34,248 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:05:34,248 INFO L428 stractBuchiCegarLoop]: Abstraction has 83503 states and 119737 transitions. [2022-12-13 19:05:34,248 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 19:05:34,249 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83503 states and 119737 transitions. [2022-12-13 19:05:34,469 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 83200 [2022-12-13 19:05:34,469 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:34,469 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:34,471 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:34,471 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:34,472 INFO L748 eck$LassoCheckResult]: Stem: 406216#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 406217#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 407050#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 407051#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 406909#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 406910#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 407011#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 407361#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 407518#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 407519#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 406192#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 406193#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 407430#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 406802#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 406803#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 406703#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 406704#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 407138#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 406435#L1174 assume !(0 == ~M_E~0); 406436#L1174-2 assume !(0 == ~T1_E~0); 406285#L1179-1 assume !(0 == ~T2_E~0); 406190#L1184-1 assume !(0 == ~T3_E~0); 406191#L1189-1 assume !(0 == ~T4_E~0); 406233#L1194-1 assume !(0 == ~T5_E~0); 406325#L1199-1 assume !(0 == ~T6_E~0); 407284#L1204-1 assume !(0 == ~T7_E~0); 407191#L1209-1 assume !(0 == ~T8_E~0); 407192#L1214-1 assume !(0 == ~T9_E~0); 407714#L1219-1 assume !(0 == ~T10_E~0); 407898#L1224-1 assume !(0 == ~T11_E~0); 406561#L1229-1 assume !(0 == ~T12_E~0); 406123#L1234-1 assume !(0 == ~E_1~0); 406124#L1239-1 assume !(0 == ~E_2~0); 406158#L1244-1 assume !(0 == ~E_3~0); 406159#L1249-1 assume !(0 == ~E_4~0); 406826#L1254-1 assume !(0 == ~E_5~0); 406056#L1259-1 assume !(0 == ~E_6~0); 406012#L1264-1 assume !(0 == ~E_7~0); 406013#L1269-1 assume !(0 == ~E_8~0); 407920#L1274-1 assume !(0 == ~E_9~0); 407768#L1279-1 assume !(0 == ~E_10~0); 406236#L1284-1 assume !(0 == ~E_11~0); 406237#L1289-1 assume !(0 == ~E_12~0); 406877#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 406878#L566 assume !(1 == ~m_pc~0); 407357#L566-2 is_master_triggered_~__retres1~0#1 := 0; 407358#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 406926#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 406927#L1455 assume !(0 != activate_threads_~tmp~1#1); 406462#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 406463#L585 assume !(1 == ~t1_pc~0); 406650#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 406651#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 407349#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 407350#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 407825#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 407818#L604 assume !(1 == ~t2_pc~0); 407240#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 407241#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 406409#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 406410#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 407471#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 407472#L623 assume !(1 == ~t3_pc~0); 405990#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 405991#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 407319#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 407320#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 407511#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 406026#L642 assume !(1 == ~t4_pc~0); 406027#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 406478#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 406081#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 406082#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 406100#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 407255#L661 assume !(1 == ~t5_pc~0); 407434#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 407156#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 407157#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 407596#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 407293#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 407294#L680 assume !(1 == ~t6_pc~0); 406686#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 406687#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 406395#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 406396#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 407610#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 407815#L699 assume 1 == ~t7_pc~0; 407115#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 407116#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 407386#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 406993#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 406994#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 406879#L718 assume !(1 == ~t8_pc~0); 406880#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 406231#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 406232#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 406265#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 406266#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 406401#L737 assume 1 == ~t9_pc~0; 407337#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 406542#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 406442#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 406443#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 406727#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 406728#L756 assume 1 == ~t10_pc~0; 407375#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 406983#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 407276#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 406919#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 406520#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 406521#L775 assume !(1 == ~t11_pc~0); 406790#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 406791#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 407706#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 406166#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 406167#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 406345#L794 assume 1 == ~t12_pc~0; 406189#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 406169#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 406032#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 406033#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 406309#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 406806#L1307 assume !(1 == ~M_E~0); 406807#L1307-2 assume !(1 == ~T1_E~0); 406923#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 406838#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 406839#L1322-1 assume !(1 == ~T4_E~0); 406531#L1327-1 assume !(1 == ~T5_E~0); 406532#L1332-1 assume !(1 == ~T6_E~0); 407120#L1337-1 assume !(1 == ~T7_E~0); 407064#L1342-1 assume !(1 == ~T8_E~0); 407065#L1347-1 assume !(1 == ~T9_E~0); 407559#L1352-1 assume !(1 == ~T10_E~0); 407387#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 406701#L1362-1 assume !(1 == ~T12_E~0); 406702#L1367-1 assume !(1 == ~E_1~0); 406326#L1372-1 assume !(1 == ~E_2~0); 406327#L1377-1 assume !(1 == ~E_3~0); 406635#L1382-1 assume !(1 == ~E_4~0); 406636#L1387-1 assume !(1 == ~E_5~0); 407242#L1392-1 assume !(1 == ~E_6~0); 406655#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 406656#L1402-1 assume !(1 == ~E_8~0); 406341#L1407-1 assume !(1 == ~E_9~0); 406342#L1412-1 assume !(1 == ~E_10~0); 407464#L1417-1 assume !(1 == ~E_11~0); 407465#L1422-1 assume !(1 == ~E_12~0); 407804#L1427-1 assume { :end_inline_reset_delta_events } true; 407805#L1768-2 [2022-12-13 19:05:34,472 INFO L750 eck$LassoCheckResult]: Loop: 407805#L1768-2 assume !false; 441998#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 441994#L1149 assume !false; 441993#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 441816#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 441804#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 441798#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 441791#L976 assume !(0 != eval_~tmp~0#1); 441792#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 446068#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 446066#L1174-3 assume !(0 == ~M_E~0); 446064#L1174-5 assume !(0 == ~T1_E~0); 446062#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 446060#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 446058#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 446056#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 446054#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 446052#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 446050#L1209-3 assume !(0 == ~T8_E~0); 446048#L1214-3 assume !(0 == ~T9_E~0); 446046#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 446044#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 446042#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 446040#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 446038#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 446036#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 446034#L1249-3 assume !(0 == ~E_4~0); 446032#L1254-3 assume !(0 == ~E_5~0); 446030#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 446028#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 446026#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 446024#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 446022#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 446020#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 446018#L1289-3 assume !(0 == ~E_12~0); 446016#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 446014#L566-39 assume !(1 == ~m_pc~0); 446012#L566-41 is_master_triggered_~__retres1~0#1 := 0; 446010#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 446005#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 445743#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 445744#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 442343#L585-39 assume !(1 == ~t1_pc~0); 442341#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 442339#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 442337#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 442335#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 442333#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 442331#L604-39 assume !(1 == ~t2_pc~0); 442327#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 442325#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 442323#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 442321#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 442318#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 442316#L623-39 assume !(1 == ~t3_pc~0); 441475#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 442313#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 442311#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 442309#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 442307#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 442305#L642-39 assume 1 == ~t4_pc~0; 442302#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 442300#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 442298#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 442296#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 442294#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 442292#L661-39 assume !(1 == ~t5_pc~0); 442290#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 442288#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 442286#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 442284#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 442282#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 442280#L680-39 assume 1 == ~t6_pc~0; 442278#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 442276#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 442274#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 442272#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 442270#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 442266#L699-39 assume !(1 == ~t7_pc~0); 442263#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 442261#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 442259#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 442256#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 442254#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 442252#L718-39 assume 1 == ~t8_pc~0; 442250#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 442248#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 442246#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 442244#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 442242#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 442240#L737-39 assume 1 == ~t9_pc~0; 442236#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 442234#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 442232#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 442230#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 442228#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 442226#L756-39 assume 1 == ~t10_pc~0; 442224#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 442221#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 442219#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 442217#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 442215#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 442213#L775-39 assume !(1 == ~t11_pc~0); 442210#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 442207#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 442205#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 442203#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 442201#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 442199#L794-39 assume 1 == ~t12_pc~0; 442196#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 442193#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 442191#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 442189#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 442187#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 442185#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 442182#L1307-5 assume !(1 == ~T1_E~0); 442120#L1312-3 assume !(1 == ~T2_E~0); 430827#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 442117#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 442114#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 442112#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 442110#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 442108#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 442106#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 442102#L1352-3 assume !(1 == ~T10_E~0); 442099#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 442097#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 442095#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 442093#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 442091#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 442089#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 442086#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 435255#L1392-3 assume !(1 == ~E_6~0); 442083#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 442081#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 442079#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 442077#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 442074#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 442072#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 442070#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 442065#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 442051#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 442049#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 442046#L1787 assume !(0 == start_simulation_~tmp~3#1); 442043#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 442023#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 442016#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 442011#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 442006#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 442005#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 442004#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 442002#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 407805#L1768-2 [2022-12-13 19:05:34,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:34,473 INFO L85 PathProgramCache]: Analyzing trace with hash -1479734059, now seen corresponding path program 1 times [2022-12-13 19:05:34,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:34,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1626536204] [2022-12-13 19:05:34,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:34,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:34,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:34,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:34,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:34,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1626536204] [2022-12-13 19:05:34,538 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1626536204] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:34,538 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:34,538 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:34,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987226493] [2022-12-13 19:05:34,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:34,539 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:34,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:34,539 INFO L85 PathProgramCache]: Analyzing trace with hash -639475068, now seen corresponding path program 1 times [2022-12-13 19:05:34,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:34,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093149288] [2022-12-13 19:05:34,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:34,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:34,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:34,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:34,578 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:34,579 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093149288] [2022-12-13 19:05:34,579 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1093149288] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:34,579 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:34,579 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:34,579 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1244591088] [2022-12-13 19:05:34,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:34,580 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:34,580 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:34,580 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:05:34,580 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:05:34,580 INFO L87 Difference]: Start difference. First operand 83503 states and 119737 transitions. cyclomatic complexity: 36250 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:35,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:35,410 INFO L93 Difference]: Finished difference Result 202214 states and 288294 transitions. [2022-12-13 19:05:35,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 202214 states and 288294 transitions. [2022-12-13 19:05:36,136 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 198568 [2022-12-13 19:05:36,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 202214 states to 202214 states and 288294 transitions. [2022-12-13 19:05:36,436 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 202214 [2022-12-13 19:05:36,501 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 202214 [2022-12-13 19:05:36,501 INFO L73 IsDeterministic]: Start isDeterministic. Operand 202214 states and 288294 transitions. [2022-12-13 19:05:36,560 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:36,561 INFO L218 hiAutomatonCegarLoop]: Abstraction has 202214 states and 288294 transitions. [2022-12-13 19:05:36,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202214 states and 288294 transitions. [2022-12-13 19:05:37,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202214 to 159918. [2022-12-13 19:05:37,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 159918 states, 159918 states have (on average 1.429570154704286) internal successors, (228614), 159917 states have internal predecessors, (228614), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:38,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159918 states to 159918 states and 228614 transitions. [2022-12-13 19:05:38,130 INFO L240 hiAutomatonCegarLoop]: Abstraction has 159918 states and 228614 transitions. [2022-12-13 19:05:38,131 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:05:38,131 INFO L428 stractBuchiCegarLoop]: Abstraction has 159918 states and 228614 transitions. [2022-12-13 19:05:38,131 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 19:05:38,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 159918 states and 228614 transitions. [2022-12-13 19:05:38,707 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 159520 [2022-12-13 19:05:38,707 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:38,707 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:38,708 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:38,709 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:38,709 INFO L748 eck$LassoCheckResult]: Stem: 691942#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 691943#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 692768#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 692769#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 692626#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 692627#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 692727#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 693072#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 693227#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 693228#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 691918#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 691919#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 693141#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 692521#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 692522#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 692430#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 692431#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 692850#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 692158#L1174 assume !(0 == ~M_E~0); 692159#L1174-2 assume !(0 == ~T1_E~0); 692010#L1179-1 assume !(0 == ~T2_E~0); 691916#L1184-1 assume !(0 == ~T3_E~0); 691917#L1189-1 assume !(0 == ~T4_E~0); 691959#L1194-1 assume !(0 == ~T5_E~0); 692051#L1199-1 assume !(0 == ~T6_E~0); 692990#L1204-1 assume !(0 == ~T7_E~0); 692901#L1209-1 assume !(0 == ~T8_E~0); 692902#L1214-1 assume !(0 == ~T9_E~0); 693399#L1219-1 assume !(0 == ~T10_E~0); 693553#L1224-1 assume !(0 == ~T11_E~0); 692284#L1229-1 assume !(0 == ~T12_E~0); 691849#L1234-1 assume !(0 == ~E_1~0); 691850#L1239-1 assume !(0 == ~E_2~0); 691884#L1244-1 assume !(0 == ~E_3~0); 691885#L1249-1 assume !(0 == ~E_4~0); 692544#L1254-1 assume !(0 == ~E_5~0); 691782#L1259-1 assume !(0 == ~E_6~0); 691739#L1264-1 assume !(0 == ~E_7~0); 691740#L1269-1 assume !(0 == ~E_8~0); 693572#L1274-1 assume !(0 == ~E_9~0); 693445#L1279-1 assume !(0 == ~E_10~0); 691962#L1284-1 assume !(0 == ~E_11~0); 691963#L1289-1 assume !(0 == ~E_12~0); 692595#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 692596#L566 assume !(1 == ~m_pc~0); 693064#L566-2 is_master_triggered_~__retres1~0#1 := 0; 693065#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 692641#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 692642#L1455 assume !(0 != activate_threads_~tmp~1#1); 692185#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 692186#L585 assume !(1 == ~t1_pc~0); 692372#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 692373#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 693054#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 693055#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 693493#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 693486#L604 assume !(1 == ~t2_pc~0); 692950#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 692951#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 692132#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 692133#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 693181#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 693182#L623 assume !(1 == ~t3_pc~0); 691717#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 691718#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 693026#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 693027#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 693220#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 691753#L642 assume !(1 == ~t4_pc~0); 691754#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 692198#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 691810#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 691811#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 691826#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 692964#L661 assume !(1 == ~t5_pc~0); 693147#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 692867#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 692868#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 693298#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 692999#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 693000#L680 assume !(1 == ~t6_pc~0); 692409#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 692410#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 692121#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 692122#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 693309#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 693483#L699 assume !(1 == ~t7_pc~0); 693484#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 693091#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 693092#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 692707#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 692708#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 692597#L718 assume !(1 == ~t8_pc~0); 692598#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 691957#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 691958#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 691992#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 691993#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 692124#L737 assume 1 == ~t9_pc~0; 693044#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 692266#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 692165#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 692166#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 692449#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 692450#L756 assume 1 == ~t10_pc~0; 693081#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 692699#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 692985#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 692634#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 692242#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 692243#L775 assume !(1 == ~t11_pc~0); 692509#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 692510#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 693392#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 691892#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 691893#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 692070#L794 assume 1 == ~t12_pc~0; 691915#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 691895#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 691758#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 691759#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 692036#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 692526#L1307 assume !(1 == ~M_E~0); 692527#L1307-2 assume !(1 == ~T1_E~0); 692638#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 692556#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 692557#L1322-1 assume !(1 == ~T4_E~0); 692254#L1327-1 assume !(1 == ~T5_E~0); 692255#L1332-1 assume !(1 == ~T6_E~0); 692833#L1337-1 assume !(1 == ~T7_E~0); 692780#L1342-1 assume !(1 == ~T8_E~0); 692781#L1347-1 assume !(1 == ~T9_E~0); 693264#L1352-1 assume !(1 == ~T10_E~0); 693093#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 692426#L1362-1 assume !(1 == ~T12_E~0); 692427#L1367-1 assume !(1 == ~E_1~0); 692052#L1372-1 assume !(1 == ~E_2~0); 692053#L1377-1 assume !(1 == ~E_3~0); 692357#L1382-1 assume !(1 == ~E_4~0); 692358#L1387-1 assume !(1 == ~E_5~0); 692952#L1392-1 assume !(1 == ~E_6~0); 759372#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 759371#L1402-1 assume !(1 == ~E_8~0); 759369#L1407-1 assume !(1 == ~E_9~0); 759367#L1412-1 assume !(1 == ~E_10~0); 759365#L1417-1 assume !(1 == ~E_11~0); 759363#L1422-1 assume !(1 == ~E_12~0); 693475#L1427-1 assume { :end_inline_reset_delta_events } true; 693476#L1768-2 [2022-12-13 19:05:38,709 INFO L750 eck$LassoCheckResult]: Loop: 693476#L1768-2 assume !false; 821968#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 820619#L1149 assume !false; 820599#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 811453#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 811445#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 811443#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 811440#L976 assume !(0 != eval_~tmp~0#1); 811441#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 850459#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 850457#L1174-3 assume !(0 == ~M_E~0); 850455#L1174-5 assume !(0 == ~T1_E~0); 850453#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 850451#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 850449#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 850447#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 850445#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 850443#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 850441#L1209-3 assume !(0 == ~T8_E~0); 850439#L1214-3 assume !(0 == ~T9_E~0); 850437#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 850435#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 850433#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 850431#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 850429#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 850427#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 850425#L1249-3 assume !(0 == ~E_4~0); 850423#L1254-3 assume !(0 == ~E_5~0); 850421#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 850419#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 850417#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 850415#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 850413#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 850411#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 850409#L1289-3 assume !(0 == ~E_12~0); 850407#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 850405#L566-39 assume !(1 == ~m_pc~0); 850403#L566-41 is_master_triggered_~__retres1~0#1 := 0; 850401#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 850399#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 850397#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 850282#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 823624#L585-39 assume !(1 == ~t1_pc~0); 823622#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 823620#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 823618#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 823616#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 823614#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 823612#L604-39 assume !(1 == ~t2_pc~0); 823609#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 823607#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 823605#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 823603#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 823600#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 823596#L623-39 assume !(1 == ~t3_pc~0); 778987#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 823593#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 823591#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 823588#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 823586#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 823584#L642-39 assume 1 == ~t4_pc~0; 823582#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 823580#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 823578#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 823576#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 823574#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 823572#L661-39 assume !(1 == ~t5_pc~0); 823569#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 823567#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 823565#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 823563#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 823561#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 823559#L680-39 assume 1 == ~t6_pc~0; 823556#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 823554#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 823552#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 823550#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 823548#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 823546#L699-39 assume !(1 == ~t7_pc~0); 770437#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 823542#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 823540#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 823538#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 823536#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 823534#L718-39 assume 1 == ~t8_pc~0; 823532#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 823530#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 823528#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 823526#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 823524#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 823522#L737-39 assume 1 == ~t9_pc~0; 823518#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 823516#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 823514#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 823512#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 823510#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 823508#L756-39 assume !(1 == ~t10_pc~0); 823504#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 823502#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 823500#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 823498#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 823496#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 823494#L775-39 assume 1 == ~t11_pc~0; 823490#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 823488#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 823486#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 823484#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 823482#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 823480#L794-39 assume !(1 == ~t12_pc~0); 823476#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 823474#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 823472#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 823470#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 823468#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 823466#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 823463#L1307-5 assume !(1 == ~T1_E~0); 823461#L1312-3 assume !(1 == ~T2_E~0); 756276#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 823458#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 823456#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 823454#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 823452#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 823450#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 823449#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 756260#L1352-3 assume !(1 == ~T10_E~0); 823446#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 823444#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 823442#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 823440#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 823438#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 823437#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 823435#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 809643#L1392-3 assume !(1 == ~E_6~0); 823432#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 823430#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 823428#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 823426#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 823424#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 823423#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 823421#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 823416#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 823403#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 823401#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 823399#L1787 assume !(0 == start_simulation_~tmp~3#1); 823397#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 823364#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 823356#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 823354#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 823352#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 823350#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 823348#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 823345#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 693476#L1768-2 [2022-12-13 19:05:38,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:38,709 INFO L85 PathProgramCache]: Analyzing trace with hash 339991860, now seen corresponding path program 1 times [2022-12-13 19:05:38,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:38,709 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955601503] [2022-12-13 19:05:38,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:38,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:38,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:38,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:38,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:38,753 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955601503] [2022-12-13 19:05:38,753 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [955601503] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:38,753 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:38,753 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:38,753 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50260601] [2022-12-13 19:05:38,753 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:38,754 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:38,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:38,754 INFO L85 PathProgramCache]: Analyzing trace with hash -176490141, now seen corresponding path program 1 times [2022-12-13 19:05:38,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:38,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046959377] [2022-12-13 19:05:38,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:38,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:38,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:38,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:38,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:38,791 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046959377] [2022-12-13 19:05:38,791 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046959377] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:38,791 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:38,791 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:38,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1823463574] [2022-12-13 19:05:38,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:38,792 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:38,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:38,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:05:38,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:05:38,792 INFO L87 Difference]: Start difference. First operand 159918 states and 228614 transitions. cyclomatic complexity: 68712 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:39,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:39,968 INFO L93 Difference]: Finished difference Result 385421 states and 547955 transitions. [2022-12-13 19:05:39,968 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 385421 states and 547955 transitions. [2022-12-13 19:05:41,438 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 378368 [2022-12-13 19:05:42,172 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 385421 states to 385421 states and 547955 transitions. [2022-12-13 19:05:42,173 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 385421 [2022-12-13 19:05:42,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 385421 [2022-12-13 19:05:42,422 INFO L73 IsDeterministic]: Start isDeterministic. Operand 385421 states and 547955 transitions. [2022-12-13 19:05:42,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:42,545 INFO L218 hiAutomatonCegarLoop]: Abstraction has 385421 states and 547955 transitions. [2022-12-13 19:05:42,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 385421 states and 547955 transitions. [2022-12-13 19:05:44,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 385421 to 305997. [2022-12-13 19:05:44,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 305997 states, 305997 states have (on average 1.4255924077687037) internal successors, (436227), 305996 states have internal predecessors, (436227), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:45,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 305997 states to 305997 states and 436227 transitions. [2022-12-13 19:05:45,353 INFO L240 hiAutomatonCegarLoop]: Abstraction has 305997 states and 436227 transitions. [2022-12-13 19:05:45,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:05:45,354 INFO L428 stractBuchiCegarLoop]: Abstraction has 305997 states and 436227 transitions. [2022-12-13 19:05:45,354 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 19:05:45,354 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 305997 states and 436227 transitions. [2022-12-13 19:05:46,228 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 305408 [2022-12-13 19:05:46,228 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:05:46,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:05:46,231 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:46,231 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:05:46,231 INFO L748 eck$LassoCheckResult]: Stem: 1237290#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1237291#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1238123#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1238124#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1237977#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 1237978#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1238080#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1238444#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1238606#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1238607#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1237268#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1237269#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1238519#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1237870#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1237871#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1237781#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1237782#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1238215#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1237507#L1174 assume !(0 == ~M_E~0); 1237508#L1174-2 assume !(0 == ~T1_E~0); 1237358#L1179-1 assume !(0 == ~T2_E~0); 1237266#L1184-1 assume !(0 == ~T3_E~0); 1237267#L1189-1 assume !(0 == ~T4_E~0); 1237307#L1194-1 assume !(0 == ~T5_E~0); 1237399#L1199-1 assume !(0 == ~T6_E~0); 1238355#L1204-1 assume !(0 == ~T7_E~0); 1238268#L1209-1 assume !(0 == ~T8_E~0); 1238269#L1214-1 assume !(0 == ~T9_E~0); 1238801#L1219-1 assume !(0 == ~T10_E~0); 1239005#L1224-1 assume !(0 == ~T11_E~0); 1237638#L1229-1 assume !(0 == ~T12_E~0); 1237199#L1234-1 assume !(0 == ~E_1~0); 1237200#L1239-1 assume !(0 == ~E_2~0); 1237233#L1244-1 assume !(0 == ~E_3~0); 1237234#L1249-1 assume !(0 == ~E_4~0); 1237891#L1254-1 assume !(0 == ~E_5~0); 1237132#L1259-1 assume !(0 == ~E_6~0); 1237088#L1264-1 assume !(0 == ~E_7~0); 1237089#L1269-1 assume !(0 == ~E_8~0); 1239031#L1274-1 assume !(0 == ~E_9~0); 1238855#L1279-1 assume !(0 == ~E_10~0); 1237310#L1284-1 assume !(0 == ~E_11~0); 1237311#L1289-1 assume !(0 == ~E_12~0); 1237943#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1237944#L566 assume !(1 == ~m_pc~0); 1238436#L566-2 is_master_triggered_~__retres1~0#1 := 0; 1238437#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1237995#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1237996#L1455 assume !(0 != activate_threads_~tmp~1#1); 1237534#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1237535#L585 assume !(1 == ~t1_pc~0); 1237723#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1237724#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1238426#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1238427#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 1238917#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1238910#L604 assume !(1 == ~t2_pc~0); 1238313#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1238314#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1237481#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1237482#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 1238556#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1238557#L623 assume !(1 == ~t3_pc~0); 1237066#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1237067#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1238396#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1238397#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 1238598#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1237102#L642 assume !(1 == ~t4_pc~0); 1237103#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1237550#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1237160#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1237161#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 1237176#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1238327#L661 assume !(1 == ~t5_pc~0); 1238523#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1238233#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1238234#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1238684#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 1238366#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1238367#L680 assume !(1 == ~t6_pc~0); 1237761#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1237762#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1237470#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1237471#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 1238700#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1238906#L699 assume !(1 == ~t7_pc~0); 1238907#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1238464#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1238465#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1238062#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 1238063#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1237945#L718 assume !(1 == ~t8_pc~0); 1237946#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1237305#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1237306#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1237340#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 1237341#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1237473#L737 assume !(1 == ~t9_pc~0); 1237617#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1237618#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1237514#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1237515#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 1237799#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1237800#L756 assume 1 == ~t10_pc~0; 1238453#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1238053#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1238347#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1237987#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 1237594#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1237595#L775 assume !(1 == ~t11_pc~0); 1237859#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1237860#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1238794#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1237241#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1237242#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1237418#L794 assume 1 == ~t12_pc~0; 1237265#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1237244#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1237108#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1237109#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 1237384#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1237874#L1307 assume !(1 == ~M_E~0); 1237875#L1307-2 assume !(1 == ~T1_E~0); 1237992#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1237905#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1237906#L1322-1 assume !(1 == ~T4_E~0); 1237606#L1327-1 assume !(1 == ~T5_E~0); 1237607#L1332-1 assume !(1 == ~T6_E~0); 1238926#L1337-1 assume !(1 == ~T7_E~0); 1238927#L1342-1 assume !(1 == ~T8_E~0); 1238853#L1347-1 assume !(1 == ~T9_E~0); 1238647#L1352-1 assume !(1 == ~T10_E~0); 1238466#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1237777#L1362-1 assume !(1 == ~T12_E~0); 1237778#L1367-1 assume !(1 == ~E_1~0); 1237400#L1372-1 assume !(1 == ~E_2~0); 1237401#L1377-1 assume !(1 == ~E_3~0); 1237708#L1382-1 assume !(1 == ~E_4~0); 1237709#L1387-1 assume !(1 == ~E_5~0); 1238315#L1392-1 assume !(1 == ~E_6~0); 1237730#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1237731#L1402-1 assume !(1 == ~E_8~0); 1293789#L1407-1 assume !(1 == ~E_9~0); 1238977#L1412-1 assume !(1 == ~E_10~0); 1238978#L1417-1 assume !(1 == ~E_11~0); 1239049#L1422-1 assume !(1 == ~E_12~0); 1239050#L1427-1 assume { :end_inline_reset_delta_events } true; 1293786#L1768-2 [2022-12-13 19:05:46,231 INFO L750 eck$LassoCheckResult]: Loop: 1293786#L1768-2 assume !false; 1293772#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1293767#L1149 assume !false; 1293765#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1293743#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1293737#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1293732#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1293728#L976 assume !(0 != eval_~tmp~0#1); 1293729#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1317361#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1317347#L1174-3 assume !(0 == ~M_E~0); 1317348#L1174-5 assume !(0 == ~T1_E~0); 1317314#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1317315#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1317300#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1317301#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1317282#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1317283#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1317267#L1209-3 assume !(0 == ~T8_E~0); 1317268#L1214-3 assume !(0 == ~T9_E~0); 1317253#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1317254#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1317240#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1317241#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1317227#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1317228#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1317211#L1249-3 assume !(0 == ~E_4~0); 1317212#L1254-3 assume !(0 == ~E_5~0); 1317194#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1317195#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1317178#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1317179#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1317162#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1317163#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1317147#L1289-3 assume !(0 == ~E_12~0); 1317148#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1317130#L566-39 assume !(1 == ~m_pc~0); 1317131#L566-41 is_master_triggered_~__retres1~0#1 := 0; 1317111#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1317112#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1317094#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1317095#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1316627#L585-39 assume !(1 == ~t1_pc~0); 1316624#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1316620#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1316617#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1316614#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1316611#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1316609#L604-39 assume 1 == ~t2_pc~0; 1316605#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1316601#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1316597#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1316592#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1316589#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1316217#L623-39 assume !(1 == ~t3_pc~0); 1316215#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1316213#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1316210#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1316207#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1316203#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1316200#L642-39 assume 1 == ~t4_pc~0; 1316196#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1316193#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1316190#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1316187#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1316183#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1316180#L661-39 assume !(1 == ~t5_pc~0); 1316176#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1316172#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1316168#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1316162#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1316157#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1316153#L680-39 assume 1 == ~t6_pc~0; 1316148#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1316145#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1316142#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1316140#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1316136#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1316133#L699-39 assume !(1 == ~t7_pc~0); 1313981#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1316128#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1316125#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1316119#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1316115#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1316112#L718-39 assume 1 == ~t8_pc~0; 1316108#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1316105#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1316101#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1316099#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 1316097#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1316095#L737-39 assume !(1 == ~t9_pc~0); 1279682#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1316090#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1316087#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1316083#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1316080#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1316077#L756-39 assume !(1 == ~t10_pc~0); 1316073#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1316071#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1316068#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1316066#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1316063#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1316060#L775-39 assume 1 == ~t11_pc~0; 1316056#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1316052#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1316048#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1316043#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1316039#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1316036#L794-39 assume !(1 == ~t12_pc~0); 1316032#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 1316030#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1316027#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1316025#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1316022#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1316019#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1316016#L1307-5 assume !(1 == ~T1_E~0); 1316012#L1312-3 assume !(1 == ~T2_E~0); 1299922#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1316006#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1316003#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1316000#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1315997#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1315994#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1315991#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1299903#L1352-3 assume !(1 == ~T10_E~0); 1315985#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1315982#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1315979#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1315975#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1315973#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1315971#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1315969#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1313953#L1392-3 assume !(1 == ~E_6~0); 1315965#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1315964#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1315962#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1315960#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1315958#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1315955#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1315952#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1315855#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1315840#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1315836#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1315831#L1787 assume !(0 == start_simulation_~tmp~3#1); 1314133#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1297413#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1297405#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1297403#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1297401#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1297399#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1297396#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1293788#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 1293786#L1768-2 [2022-12-13 19:05:46,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:46,232 INFO L85 PathProgramCache]: Analyzing trace with hash -1390345197, now seen corresponding path program 1 times [2022-12-13 19:05:46,232 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:46,232 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709607363] [2022-12-13 19:05:46,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:46,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:46,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:46,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:46,288 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:46,288 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709607363] [2022-12-13 19:05:46,288 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709607363] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:46,288 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:46,288 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:46,288 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [803615434] [2022-12-13 19:05:46,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:46,289 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:05:46,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:05:46,289 INFO L85 PathProgramCache]: Analyzing trace with hash 983392101, now seen corresponding path program 1 times [2022-12-13 19:05:46,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:05:46,289 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [204374972] [2022-12-13 19:05:46,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:05:46,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:05:46,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:05:46,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:05:46,333 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:05:46,333 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [204374972] [2022-12-13 19:05:46,334 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [204374972] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:05:46,334 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:05:46,334 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:05:46,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8194927] [2022-12-13 19:05:46,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:05:46,334 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:05:46,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:05:46,335 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:05:46,335 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:05:46,335 INFO L87 Difference]: Start difference. First operand 305997 states and 436227 transitions. cyclomatic complexity: 130246 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:48,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:05:48,553 INFO L93 Difference]: Finished difference Result 735148 states and 1042496 transitions. [2022-12-13 19:05:48,554 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 735148 states and 1042496 transitions. [2022-12-13 19:05:51,185 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 721312 [2022-12-13 19:05:52,375 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 735148 states to 735148 states and 1042496 transitions. [2022-12-13 19:05:52,375 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 735148 [2022-12-13 19:05:52,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 735148 [2022-12-13 19:05:52,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 735148 states and 1042496 transitions. [2022-12-13 19:05:52,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:05:52,934 INFO L218 hiAutomatonCegarLoop]: Abstraction has 735148 states and 1042496 transitions. [2022-12-13 19:05:53,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 735148 states and 1042496 transitions. [2022-12-13 19:05:57,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 735148 to 584780. [2022-12-13 19:05:57,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 584780 states, 584780 states have (on average 1.4219911761688155) internal successors, (831552), 584779 states have internal predecessors, (831552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:05:58,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 584780 states to 584780 states and 831552 transitions. [2022-12-13 19:05:58,991 INFO L240 hiAutomatonCegarLoop]: Abstraction has 584780 states and 831552 transitions. [2022-12-13 19:05:58,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:05:58,992 INFO L428 stractBuchiCegarLoop]: Abstraction has 584780 states and 831552 transitions. [2022-12-13 19:05:58,992 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 19:05:58,992 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 584780 states and 831552 transitions. [2022-12-13 19:06:00,504 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 583808 [2022-12-13 19:06:00,504 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:06:00,504 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:06:00,509 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:06:00,510 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:06:00,510 INFO L748 eck$LassoCheckResult]: Stem: 2278444#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 2278445#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 2279284#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2279285#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2279136#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 2279137#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2279243#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2279620#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2279782#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2279783#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2278421#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2278422#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2279696#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2279024#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2279025#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2278928#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2278929#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 2279381#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2278658#L1174 assume !(0 == ~M_E~0); 2278659#L1174-2 assume !(0 == ~T1_E~0); 2278515#L1179-1 assume !(0 == ~T2_E~0); 2278419#L1184-1 assume !(0 == ~T3_E~0); 2278420#L1189-1 assume !(0 == ~T4_E~0); 2278461#L1194-1 assume !(0 == ~T5_E~0); 2278556#L1199-1 assume !(0 == ~T6_E~0); 2279533#L1204-1 assume !(0 == ~T7_E~0); 2279438#L1209-1 assume !(0 == ~T8_E~0); 2279439#L1214-1 assume !(0 == ~T9_E~0); 2279985#L1219-1 assume !(0 == ~T10_E~0); 2280174#L1224-1 assume !(0 == ~T11_E~0); 2278784#L1229-1 assume !(0 == ~T12_E~0); 2278353#L1234-1 assume !(0 == ~E_1~0); 2278354#L1239-1 assume !(0 == ~E_2~0); 2278387#L1244-1 assume !(0 == ~E_3~0); 2278388#L1249-1 assume !(0 == ~E_4~0); 2279046#L1254-1 assume !(0 == ~E_5~0); 2278286#L1259-1 assume !(0 == ~E_6~0); 2278243#L1264-1 assume !(0 == ~E_7~0); 2278244#L1269-1 assume !(0 == ~E_8~0); 2280193#L1274-1 assume !(0 == ~E_9~0); 2280029#L1279-1 assume !(0 == ~E_10~0); 2278464#L1284-1 assume !(0 == ~E_11~0); 2278465#L1289-1 assume !(0 == ~E_12~0); 2279102#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2279103#L566 assume !(1 == ~m_pc~0); 2279615#L566-2 is_master_triggered_~__retres1~0#1 := 0; 2279616#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2279155#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2279156#L1455 assume !(0 != activate_threads_~tmp~1#1); 2278684#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2278685#L585 assume !(1 == ~t1_pc~0); 2278873#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2278874#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2279603#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2279604#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 2280089#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2280085#L604 assume !(1 == ~t2_pc~0); 2279490#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2279491#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2278633#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2278634#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 2279733#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2279734#L623 assume !(1 == ~t3_pc~0); 2278221#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2278222#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2279575#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2279576#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 2279773#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2278257#L642 assume !(1 == ~t4_pc~0); 2278258#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2278697#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2278314#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2278315#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 2278330#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2279506#L661 assume !(1 == ~t5_pc~0); 2279702#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2279398#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2279399#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2279866#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 2279545#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2279546#L680 assume !(1 == ~t6_pc~0); 2278909#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2278910#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2278619#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2278620#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 2279882#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2280082#L699 assume !(1 == ~t7_pc~0); 2280083#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2279642#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2279643#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2279225#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 2279226#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2279104#L718 assume !(1 == ~t8_pc~0); 2279105#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2278459#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2278460#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2278496#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 2278497#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2278625#L737 assume !(1 == ~t9_pc~0); 2278763#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2278764#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2278665#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2278666#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 2278948#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2278949#L756 assume !(1 == ~t10_pc~0); 2279213#L756-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2279214#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2279527#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2279144#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 2278742#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2278743#L775 assume !(1 == ~t11_pc~0); 2279013#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 2279014#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2279976#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2278395#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2278396#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2278575#L794 assume 1 == ~t12_pc~0; 2278418#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 2278398#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2278262#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2278263#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 2278541#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2279028#L1307 assume !(1 == ~M_E~0); 2279029#L1307-2 assume !(1 == ~T1_E~0); 2279150#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2279059#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2279060#L1322-1 assume !(1 == ~T4_E~0); 2278754#L1327-1 assume !(1 == ~T5_E~0); 2278755#L1332-1 assume !(1 == ~T6_E~0); 2280101#L1337-1 assume !(1 == ~T7_E~0); 2280102#L1342-1 assume !(1 == ~T8_E~0); 2280026#L1347-1 assume !(1 == ~T9_E~0); 2279822#L1352-1 assume !(1 == ~T10_E~0); 2279823#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2278926#L1362-1 assume !(1 == ~T12_E~0); 2278927#L1367-1 assume !(1 == ~E_1~0); 2278557#L1372-1 assume !(1 == ~E_2~0); 2278558#L1377-1 assume !(1 == ~E_3~0); 2278858#L1382-1 assume !(1 == ~E_4~0); 2278859#L1387-1 assume !(1 == ~E_5~0); 2279493#L1392-1 assume !(1 == ~E_6~0); 2278880#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2278881#L1402-1 assume !(1 == ~E_8~0); 2278571#L1407-1 assume !(1 == ~E_9~0); 2278572#L1412-1 assume !(1 == ~E_10~0); 2279728#L1417-1 assume !(1 == ~E_11~0); 2279729#L1422-1 assume !(1 == ~E_12~0); 2280075#L1427-1 assume { :end_inline_reset_delta_events } true; 2280076#L1768-2 [2022-12-13 19:06:00,511 INFO L750 eck$LassoCheckResult]: Loop: 2280076#L1768-2 assume !false; 2826778#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2826773#L1149 assume !false; 2826770#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2826661#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2826654#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2826652#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2826650#L976 assume !(0 != eval_~tmp~0#1); 2826651#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2859449#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2859447#L1174-3 assume !(0 == ~M_E~0); 2859445#L1174-5 assume !(0 == ~T1_E~0); 2859443#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2859441#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2859439#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2859437#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2859435#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2859433#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2859431#L1209-3 assume !(0 == ~T8_E~0); 2859429#L1214-3 assume !(0 == ~T9_E~0); 2859427#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2859425#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2859423#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 2859421#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2859399#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2859398#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2859397#L1249-3 assume !(0 == ~E_4~0); 2859396#L1254-3 assume !(0 == ~E_5~0); 2859395#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2859394#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2859392#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2859390#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2859388#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2859386#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2859384#L1289-3 assume !(0 == ~E_12~0); 2859382#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2859380#L566-39 assume !(1 == ~m_pc~0); 2859379#L566-41 is_master_triggered_~__retres1~0#1 := 0; 2859377#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2859375#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2859282#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2859073#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2280013#L585-39 assume !(1 == ~t1_pc~0); 2278614#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 2278615#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2278830#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2279973#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2279608#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2279232#L604-39 assume !(1 == ~t2_pc~0); 2279234#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 2278839#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2278840#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2279027#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 2279291#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2278814#L623-39 assume !(1 == ~t3_pc~0); 2278815#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 2279329#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2279585#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2278660#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2278661#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2279515#L642-39 assume 1 == ~t4_pc~0; 2279018#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2279019#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2279200#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2279201#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2279795#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2278580#L661-39 assume !(1 == ~t5_pc~0); 2278228#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 2278229#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2279238#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2279239#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2279587#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2279588#L680-39 assume 1 == ~t6_pc~0; 2278291#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2278292#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2279908#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2280176#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2857280#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2826966#L699-39 assume !(1 == ~t7_pc~0); 2826965#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 2826964#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2826963#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2826962#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2826961#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2826960#L718-39 assume !(1 == ~t8_pc~0); 2826958#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 2826955#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2826953#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2826951#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 2826948#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2826946#L737-39 assume !(1 == ~t9_pc~0); 2746269#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 2826943#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2826941#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2826938#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2826937#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2826934#L756-39 assume !(1 == ~t10_pc~0); 2526920#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 2826931#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2826929#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2826927#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2826925#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2826922#L775-39 assume !(1 == ~t11_pc~0); 2826920#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 2826917#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2826915#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2826913#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2826911#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2826910#L794-39 assume !(1 == ~t12_pc~0); 2826907#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 2826905#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2826903#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2826901#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 2826899#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2826898#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2826896#L1307-5 assume !(1 == ~T1_E~0); 2826894#L1312-3 assume !(1 == ~T2_E~0); 2716428#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2826891#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2826889#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2826886#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2826884#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2826882#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2826880#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2814057#L1352-3 assume !(1 == ~T10_E~0); 2826877#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2826875#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2826873#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2826870#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2826868#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2826866#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2826864#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2811424#L1392-3 assume !(1 == ~E_6~0); 2826861#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2826859#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2826857#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2826855#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2826853#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2826851#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 2826849#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2826843#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2826830#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2826828#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 2826825#L1787 assume !(0 == start_simulation_~tmp~3#1); 2826823#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2826806#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2826798#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2826796#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 2826795#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2826793#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2826791#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 2826789#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 2280076#L1768-2 [2022-12-13 19:06:00,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:06:00,512 INFO L85 PathProgramCache]: Analyzing trace with hash 1629519410, now seen corresponding path program 1 times [2022-12-13 19:06:00,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:06:00,512 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849373134] [2022-12-13 19:06:00,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:06:00,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:06:00,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:06:00,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:06:00,593 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:06:00,593 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [849373134] [2022-12-13 19:06:00,594 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [849373134] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:06:00,594 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:06:00,594 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:06:00,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86984580] [2022-12-13 19:06:00,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:06:00,594 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:06:00,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:06:00,595 INFO L85 PathProgramCache]: Analyzing trace with hash 1750711744, now seen corresponding path program 1 times [2022-12-13 19:06:00,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:06:00,595 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765099774] [2022-12-13 19:06:00,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:06:00,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:06:00,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:06:00,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:06:00,631 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:06:00,631 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765099774] [2022-12-13 19:06:00,631 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765099774] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:06:00,631 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:06:00,631 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:06:00,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778355023] [2022-12-13 19:06:00,631 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:06:00,632 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:06:00,632 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:06:00,632 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:06:00,632 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:06:00,632 INFO L87 Difference]: Start difference. First operand 584780 states and 831552 transitions. cyclomatic complexity: 246788 Second operand has 5 states, 5 states have (on average 29.6) internal successors, (148), 5 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:06:04,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:06:04,223 INFO L93 Difference]: Finished difference Result 1315185 states and 1889779 transitions. [2022-12-13 19:06:04,223 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1315185 states and 1889779 transitions. [2022-12-13 19:06:08,919 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 1312512 [2022-12-13 19:06:11,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1315185 states to 1315185 states and 1889779 transitions. [2022-12-13 19:06:11,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1315185 [2022-12-13 19:06:11,745 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1315185 [2022-12-13 19:06:11,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1315185 states and 1889779 transitions. [2022-12-13 19:06:12,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:06:12,124 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1315185 states and 1889779 transitions. [2022-12-13 19:06:12,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1315185 states and 1889779 transitions. [2022-12-13 19:06:18,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1315185 to 600143. [2022-12-13 19:06:18,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 600143 states, 600143 states have (on average 1.4111886667011029) internal successors, (846915), 600142 states have internal predecessors, (846915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:06:20,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 600143 states to 600143 states and 846915 transitions. [2022-12-13 19:06:20,116 INFO L240 hiAutomatonCegarLoop]: Abstraction has 600143 states and 846915 transitions. [2022-12-13 19:06:20,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 19:06:20,117 INFO L428 stractBuchiCegarLoop]: Abstraction has 600143 states and 846915 transitions. [2022-12-13 19:06:20,117 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 19:06:20,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 600143 states and 846915 transitions. [2022-12-13 19:06:21,659 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 599168 [2022-12-13 19:06:21,659 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:06:21,659 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:06:21,663 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:06:21,664 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:06:21,664 INFO L748 eck$LassoCheckResult]: Stem: 4178422#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 4178423#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4179264#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4179265#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4179117#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 4179118#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4179224#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4179587#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4179754#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4179755#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4178400#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4178401#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4179666#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4179004#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4179005#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4178910#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 4178911#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 4179360#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4178634#L1174 assume !(0 == ~M_E~0); 4178635#L1174-2 assume !(0 == ~T1_E~0); 4178488#L1179-1 assume !(0 == ~T2_E~0); 4178398#L1184-1 assume !(0 == ~T3_E~0); 4178399#L1189-1 assume !(0 == ~T4_E~0); 4178439#L1194-1 assume !(0 == ~T5_E~0); 4178529#L1199-1 assume !(0 == ~T6_E~0); 4179502#L1204-1 assume !(0 == ~T7_E~0); 4179411#L1209-1 assume !(0 == ~T8_E~0); 4179412#L1214-1 assume !(0 == ~T9_E~0); 4179941#L1219-1 assume !(0 == ~T10_E~0); 4180138#L1224-1 assume !(0 == ~T11_E~0); 4178762#L1229-1 assume !(0 == ~T12_E~0); 4178332#L1234-1 assume !(0 == ~E_1~0); 4178333#L1239-1 assume !(0 == ~E_2~0); 4178364#L1244-1 assume !(0 == ~E_3~0); 4178365#L1249-1 assume !(0 == ~E_4~0); 4179025#L1254-1 assume !(0 == ~E_5~0); 4178264#L1259-1 assume !(0 == ~E_6~0); 4178221#L1264-1 assume !(0 == ~E_7~0); 4178222#L1269-1 assume !(0 == ~E_8~0); 4180166#L1274-1 assume !(0 == ~E_9~0); 4180001#L1279-1 assume !(0 == ~E_10~0); 4178442#L1284-1 assume !(0 == ~E_11~0); 4178443#L1289-1 assume !(0 == ~E_12~0); 4179083#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4179084#L566 assume !(1 == ~m_pc~0); 4179581#L566-2 is_master_triggered_~__retres1~0#1 := 0; 4179582#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4179132#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4179133#L1455 assume !(0 != activate_threads_~tmp~1#1); 4178660#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4178661#L585 assume !(1 == ~t1_pc~0); 4178852#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4178853#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4179572#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4179573#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 4180053#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4180047#L604 assume !(1 == ~t2_pc~0); 4179460#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4179461#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4180202#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4179900#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 4179704#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4179705#L623 assume !(1 == ~t3_pc~0); 4178199#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4178200#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4179537#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4179538#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 4179747#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4178235#L642 assume !(1 == ~t4_pc~0); 4178236#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4178675#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4178286#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4178287#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 4178308#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4179477#L661 assume !(1 == ~t5_pc~0); 4179670#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4179378#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4179379#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4179827#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 4179511#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4179512#L680 assume !(1 == ~t6_pc~0); 4178891#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4178892#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4178594#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4178595#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 4179840#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4180043#L699 assume !(1 == ~t7_pc~0); 4180044#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4179614#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4179615#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4179205#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 4179206#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4179085#L718 assume !(1 == ~t8_pc~0); 4179086#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4178437#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4178438#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4178471#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 4178472#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4178600#L737 assume !(1 == ~t9_pc~0); 4178741#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4178742#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4178641#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4178642#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 4178931#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4178932#L756 assume !(1 == ~t10_pc~0); 4179193#L756-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4179194#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4179496#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4179125#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 4178718#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4178719#L775 assume !(1 == ~t11_pc~0); 4178993#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4178994#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4179954#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4178374#L1543 assume !(0 != activate_threads_~tmp___10~0#1); 4178375#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4178548#L794 assume 1 == ~t12_pc~0; 4178396#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4178377#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4178238#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4178239#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 4178514#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4179009#L1307 assume !(1 == ~M_E~0); 4179010#L1307-2 assume !(1 == ~T1_E~0); 4179129#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4179039#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4179040#L1322-1 assume !(1 == ~T4_E~0); 4178730#L1327-1 assume !(1 == ~T5_E~0); 4178731#L1332-1 assume !(1 == ~T6_E~0); 4180059#L1337-1 assume !(1 == ~T7_E~0); 4180060#L1342-1 assume !(1 == ~T8_E~0); 4180000#L1347-1 assume !(1 == ~T9_E~0); 4179795#L1352-1 assume !(1 == ~T10_E~0); 4179616#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4178908#L1362-1 assume !(1 == ~T12_E~0); 4178909#L1367-1 assume !(1 == ~E_1~0); 4178530#L1372-1 assume !(1 == ~E_2~0); 4178531#L1377-1 assume !(1 == ~E_3~0); 4178837#L1382-1 assume !(1 == ~E_4~0); 4178838#L1387-1 assume !(1 == ~E_5~0); 4299004#L1392-1 assume !(1 == ~E_6~0); 4298951#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4298943#L1402-1 assume !(1 == ~E_8~0); 4298933#L1407-1 assume !(1 == ~E_9~0); 4298925#L1412-1 assume !(1 == ~E_10~0); 4298918#L1417-1 assume !(1 == ~E_11~0); 4298908#L1422-1 assume !(1 == ~E_12~0); 4298902#L1427-1 assume { :end_inline_reset_delta_events } true; 4298896#L1768-2 [2022-12-13 19:06:21,664 INFO L750 eck$LassoCheckResult]: Loop: 4298896#L1768-2 assume !false; 4298889#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4298767#L1149 assume !false; 4298765#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4298744#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4298723#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4298719#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4298712#L976 assume !(0 != eval_~tmp~0#1); 4298713#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4332843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4332839#L1174-3 assume !(0 == ~M_E~0); 4332835#L1174-5 assume !(0 == ~T1_E~0); 4332831#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4332827#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4332823#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4332819#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4332815#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4332811#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4332807#L1209-3 assume !(0 == ~T8_E~0); 4332803#L1214-3 assume !(0 == ~T9_E~0); 4332799#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4332795#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4332791#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4332787#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4332783#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4332779#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4332775#L1249-3 assume !(0 == ~E_4~0); 4332771#L1254-3 assume !(0 == ~E_5~0); 4332767#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4332763#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4332759#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4332755#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4332751#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4332747#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4332743#L1289-3 assume !(0 == ~E_12~0); 4332729#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4332726#L566-39 assume !(1 == ~m_pc~0); 4332723#L566-41 is_master_triggered_~__retres1~0#1 := 0; 4332718#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4332713#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4332708#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4332703#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4332700#L585-39 assume !(1 == ~t1_pc~0); 4332697#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 4332694#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4332691#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4332687#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4332683#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4332679#L604-39 assume !(1 == ~t2_pc~0); 4332674#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 4332667#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4332661#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4332655#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 4332649#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4332644#L623-39 assume !(1 == ~t3_pc~0); 4298379#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 4332636#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4332632#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4332628#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4332623#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4332618#L642-39 assume 1 == ~t4_pc~0; 4332611#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4332605#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4332600#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4332594#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4332587#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4332581#L661-39 assume !(1 == ~t5_pc~0); 4332576#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 4332568#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4332561#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4332554#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4332548#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4332541#L680-39 assume 1 == ~t6_pc~0; 4332531#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4332522#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4332513#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4332505#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4332468#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4299469#L699-39 assume !(1 == ~t7_pc~0); 4299468#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 4299467#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4299466#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4299465#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4299464#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4299463#L718-39 assume 1 == ~t8_pc~0; 4299461#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4299460#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4299459#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4299458#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 4299457#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4299456#L737-39 assume !(1 == ~t9_pc~0); 4276138#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 4299455#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4299454#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4299453#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4299452#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4299451#L756-39 assume !(1 == ~t10_pc~0); 4281895#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 4299450#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4299449#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4299448#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4299447#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4299446#L775-39 assume !(1 == ~t11_pc~0); 4299445#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 4299443#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4299441#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4299439#L1543-39 assume !(0 != activate_threads_~tmp___10~0#1); 4299402#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4299396#L794-39 assume !(1 == ~t12_pc~0); 4299389#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 4299381#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4299375#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4299368#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4299329#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4299321#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4299313#L1307-5 assume !(1 == ~T1_E~0); 4299304#L1312-3 assume !(1 == ~T2_E~0); 4299296#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4299290#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4299284#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4299278#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4299272#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4299267#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4299262#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4299252#L1352-3 assume !(1 == ~T10_E~0); 4299244#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4299238#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4299232#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4299226#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4299190#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4299182#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4299145#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4299137#L1392-3 assume !(1 == ~E_6~0); 4299132#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4299126#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4299121#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4299116#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4299111#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4299087#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4299085#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4299062#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4299017#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4299015#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 4299012#L1787 assume !(0 == start_simulation_~tmp~3#1); 4299006#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4298958#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4298944#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4298934#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 4298926#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4298919#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4298909#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4298903#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 4298896#L1768-2 [2022-12-13 19:06:21,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:06:21,664 INFO L85 PathProgramCache]: Analyzing trace with hash -614463888, now seen corresponding path program 1 times [2022-12-13 19:06:21,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:06:21,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265385615] [2022-12-13 19:06:21,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:06:21,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:06:21,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:06:21,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:06:21,709 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:06:21,709 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265385615] [2022-12-13 19:06:21,710 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1265385615] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:06:21,710 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:06:21,710 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:06:21,710 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873840045] [2022-12-13 19:06:21,710 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:06:21,710 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:06:21,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:06:21,711 INFO L85 PathProgramCache]: Analyzing trace with hash 1841171423, now seen corresponding path program 1 times [2022-12-13 19:06:21,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:06:21,711 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [266285894] [2022-12-13 19:06:21,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:06:21,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:06:21,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:06:21,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:06:21,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:06:21,738 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [266285894] [2022-12-13 19:06:21,738 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [266285894] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:06:21,738 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:06:21,738 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:06:21,739 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199058855] [2022-12-13 19:06:21,739 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:06:21,739 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:06:21,739 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:06:21,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:06:21,739 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:06:21,740 INFO L87 Difference]: Start difference. First operand 600143 states and 846915 transitions. cyclomatic complexity: 246788 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:06:26,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:06:26,083 INFO L93 Difference]: Finished difference Result 1501006 states and 2103168 transitions. [2022-12-13 19:06:26,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1501006 states and 2103168 transitions. [2022-12-13 19:06:31,491 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 1472896 [2022-12-13 19:06:34,405 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1501006 states to 1501006 states and 2103168 transitions. [2022-12-13 19:06:34,405 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1501006 [2022-12-13 19:06:34,877 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1501006 [2022-12-13 19:06:34,877 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1501006 states and 2103168 transitions. [2022-12-13 19:06:35,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:06:35,423 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1501006 states and 2103168 transitions. [2022-12-13 19:06:36,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1501006 states and 2103168 transitions.