./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 12:47:28,124 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 12:47:28,126 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 12:47:28,144 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 12:47:28,144 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 12:47:28,145 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 12:47:28,146 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 12:47:28,147 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 12:47:28,148 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 12:47:28,148 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 12:47:28,149 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 12:47:28,150 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 12:47:28,150 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 12:47:28,150 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 12:47:28,151 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 12:47:28,152 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 12:47:28,152 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 12:47:28,153 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 12:47:28,154 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 12:47:28,155 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 12:47:28,156 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 12:47:28,157 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 12:47:28,158 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 12:47:28,158 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 12:47:28,161 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 12:47:28,161 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 12:47:28,161 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 12:47:28,162 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 12:47:28,162 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 12:47:28,163 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 12:47:28,163 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 12:47:28,164 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 12:47:28,164 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 12:47:28,165 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 12:47:28,165 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 12:47:28,165 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 12:47:28,166 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 12:47:28,166 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 12:47:28,166 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 12:47:28,167 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 12:47:28,167 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 12:47:28,168 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 12:47:28,183 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 12:47:28,183 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 12:47:28,183 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 12:47:28,183 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 12:47:28,184 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 12:47:28,184 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 12:47:28,184 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 12:47:28,185 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 12:47:28,185 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 12:47:28,185 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 12:47:28,185 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 12:47:28,185 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 12:47:28,185 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 12:47:28,186 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 12:47:28,186 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 12:47:28,186 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 12:47:28,186 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 12:47:28,186 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 12:47:28,186 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 12:47:28,187 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 12:47:28,187 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 12:47:28,187 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 12:47:28,187 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 12:47:28,187 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 12:47:28,187 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 12:47:28,187 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 12:47:28,187 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 12:47:28,188 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 12:47:28,188 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 12:47:28,188 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 12:47:28,188 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 12:47:28,189 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 12:47:28,189 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 [2022-12-13 12:47:28,366 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 12:47:28,384 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 12:47:28,387 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 12:47:28,388 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 12:47:28,388 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 12:47:28,389 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/transmitter.16.cil.c [2022-12-13 12:47:30,954 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 12:47:31,119 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 12:47:31,119 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/sv-benchmarks/c/systemc/transmitter.16.cil.c [2022-12-13 12:47:31,129 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8/data/4b5b6e115/0e9292c0fe9a49c6a3260bb618bf76bc/FLAGb193e9820 [2022-12-13 12:47:31,536 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8/data/4b5b6e115/0e9292c0fe9a49c6a3260bb618bf76bc [2022-12-13 12:47:31,541 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 12:47:31,544 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 12:47:31,546 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 12:47:31,550 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 12:47:31,556 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 12:47:31,557 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:47:31" (1/1) ... [2022-12-13 12:47:31,558 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@68b4182a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31, skipping insertion in model container [2022-12-13 12:47:31,558 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:47:31" (1/1) ... [2022-12-13 12:47:31,565 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 12:47:31,602 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 12:47:31,709 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2022-12-13 12:47:31,823 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:47:31,837 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 12:47:31,846 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2022-12-13 12:47:31,898 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:47:31,916 INFO L208 MainTranslator]: Completed translation [2022-12-13 12:47:31,917 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31 WrapperNode [2022-12-13 12:47:31,917 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 12:47:31,918 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 12:47:31,918 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 12:47:31,918 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 12:47:31,925 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31" (1/1) ... [2022-12-13 12:47:31,935 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31" (1/1) ... [2022-12-13 12:47:32,017 INFO L138 Inliner]: procedures = 56, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4715 [2022-12-13 12:47:32,017 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 12:47:32,018 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 12:47:32,018 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 12:47:32,018 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 12:47:32,027 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31" (1/1) ... [2022-12-13 12:47:32,027 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31" (1/1) ... [2022-12-13 12:47:32,037 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31" (1/1) ... [2022-12-13 12:47:32,038 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31" (1/1) ... [2022-12-13 12:47:32,070 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31" (1/1) ... [2022-12-13 12:47:32,099 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31" (1/1) ... [2022-12-13 12:47:32,105 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31" (1/1) ... [2022-12-13 12:47:32,113 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31" (1/1) ... [2022-12-13 12:47:32,127 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 12:47:32,128 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 12:47:32,128 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 12:47:32,128 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 12:47:32,129 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31" (1/1) ... [2022-12-13 12:47:32,135 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 12:47:32,144 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 12:47:32,155 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 12:47:32,157 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_028008a5-2e61-4d5c-adcd-45275035f856/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 12:47:32,190 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 12:47:32,190 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 12:47:32,190 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 12:47:32,191 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 12:47:32,286 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 12:47:32,287 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 12:47:33,902 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 12:47:33,920 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 12:47:33,921 INFO L300 CfgBuilder]: Removed 18 assume(true) statements. [2022-12-13 12:47:33,925 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:47:33 BoogieIcfgContainer [2022-12-13 12:47:33,925 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 12:47:33,926 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 12:47:33,926 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 12:47:33,930 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 12:47:33,930 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:47:33,931 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 12:47:31" (1/3) ... [2022-12-13 12:47:33,931 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3e8c7e4c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:47:33, skipping insertion in model container [2022-12-13 12:47:33,932 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:47:33,932 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:47:31" (2/3) ... [2022-12-13 12:47:33,932 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3e8c7e4c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:47:33, skipping insertion in model container [2022-12-13 12:47:33,932 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:47:33,932 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:47:33" (3/3) ... [2022-12-13 12:47:33,933 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.16.cil.c [2022-12-13 12:47:34,010 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 12:47:34,010 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 12:47:34,010 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 12:47:34,010 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 12:47:34,010 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 12:47:34,010 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 12:47:34,010 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 12:47:34,010 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 12:47:34,021 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:34,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1864 [2022-12-13 12:47:34,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:34,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:34,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:34,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:34,091 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 12:47:34,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:34,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1864 [2022-12-13 12:47:34,113 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:34,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:34,116 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:34,117 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:34,126 INFO L748 eck$LassoCheckResult]: Stem: 165#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1964#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 743#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1961#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1925#L939true assume !(1 == ~m_i~0);~m_st~0 := 2; 459#L939-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1666#L944-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 299#L949-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1329#L954-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1968#L959-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 668#L964-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1171#L969-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1779#L974-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 602#L979-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 949#L984-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 246#L989-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 438#L994-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1202#L999-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 566#L1004-1true assume !(1 == ~t14_i~0);~t14_st~0 := 2; 44#L1009-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 123#L1342true assume !(0 == ~M_E~0); 419#L1342-2true assume !(0 == ~T1_E~0); 1612#L1347-1true assume !(0 == ~T2_E~0); 1302#L1352-1true assume !(0 == ~T3_E~0); 1071#L1357-1true assume !(0 == ~T4_E~0); 434#L1362-1true assume !(0 == ~T5_E~0); 1383#L1367-1true assume !(0 == ~T6_E~0); 203#L1372-1true assume 0 == ~T7_E~0;~T7_E~0 := 1; 551#L1377-1true assume !(0 == ~T8_E~0); 386#L1382-1true assume !(0 == ~T9_E~0); 942#L1387-1true assume !(0 == ~T10_E~0); 1524#L1392-1true assume !(0 == ~T11_E~0); 408#L1397-1true assume !(0 == ~T12_E~0); 1680#L1402-1true assume !(0 == ~T13_E~0); 214#L1407-1true assume !(0 == ~T14_E~0); 1861#L1412-1true assume 0 == ~E_1~0;~E_1~0 := 1; 1197#L1417-1true assume !(0 == ~E_2~0); 2052#L1422-1true assume !(0 == ~E_3~0); 1679#L1427-1true assume !(0 == ~E_4~0); 316#L1432-1true assume !(0 == ~E_5~0); 1532#L1437-1true assume !(0 == ~E_6~0); 1117#L1442-1true assume !(0 == ~E_7~0); 1456#L1447-1true assume !(0 == ~E_8~0); 935#L1452-1true assume 0 == ~E_9~0;~E_9~0 := 1; 108#L1457-1true assume !(0 == ~E_10~0); 1149#L1462-1true assume !(0 == ~E_11~0); 1858#L1467-1true assume !(0 == ~E_12~0); 1166#L1472-1true assume !(0 == ~E_13~0); 1357#L1477-1true assume !(0 == ~E_14~0); 887#L1482-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 198#L646true assume 1 == ~m_pc~0; 609#L647true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 617#L657true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 635#is_master_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 247#L1666true assume !(0 != activate_threads_~tmp~1#1); 1986#L1666-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1744#L665true assume !(1 == ~t1_pc~0); 526#L665-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1195#L676true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1038#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1702#L1674true assume !(0 != activate_threads_~tmp___0~0#1); 777#L1674-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 884#L684true assume 1 == ~t2_pc~0; 1869#L685true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 875#L695true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 239#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1309#L1682true assume !(0 != activate_threads_~tmp___1~0#1); 1815#L1682-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1790#L703true assume !(1 == ~t3_pc~0); 328#L703-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1401#L714true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1022#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32#L1690true assume !(0 != activate_threads_~tmp___2~0#1); 261#L1690-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1326#L722true assume 1 == ~t4_pc~0; 747#L723true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 589#L733true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1618#L1698true assume !(0 != activate_threads_~tmp___3~0#1); 636#L1698-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124#L741true assume 1 == ~t5_pc~0; 275#L742true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 806#L752true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1658#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 857#L1706true assume !(0 != activate_threads_~tmp___4~0#1); 1382#L1706-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 420#L760true assume !(1 == ~t6_pc~0); 732#L760-2true is_transmit6_triggered_~__retres1~6#1 := 0; 982#L771true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 235#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1659#L1714true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 713#L1714-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1400#L779true assume 1 == ~t7_pc~0; 140#L780true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 69#L790true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1978#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1375#L1722true assume !(0 != activate_threads_~tmp___6~0#1); 283#L1722-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1689#L798true assume !(1 == ~t8_pc~0); 1941#L798-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1251#L809true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1603#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1746#L1730true assume !(0 != activate_threads_~tmp___7~0#1); 1913#L1730-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60#L817true assume 1 == ~t9_pc~0; 825#L818true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 481#L828true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 264#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1863#L1738true assume !(0 != activate_threads_~tmp___8~0#1); 252#L1738-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 769#L836true assume !(1 == ~t10_pc~0); 265#L836-2true is_transmit10_triggered_~__retres1~10#1 := 0; 227#L847true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1363#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 365#L1746true assume !(0 != activate_threads_~tmp___9~0#1); 1265#L1746-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1271#L855true assume 1 == ~t11_pc~0; 615#L856true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1142#L866true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1485#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 933#L1754true assume !(0 != activate_threads_~tmp___10~0#1); 782#L1754-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 197#L874true assume !(1 == ~t12_pc~0); 1640#L874-2true is_transmit12_triggered_~__retres1~12#1 := 0; 288#L885true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1989#L1762true assume !(0 != activate_threads_~tmp___11~0#1); 48#L1762-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1862#L893true assume 1 == ~t13_pc~0; 1540#L894true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 385#L904true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1415#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1557#L1770true assume !(0 != activate_threads_~tmp___12~0#1); 1394#L1770-2true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1764#L912true assume 1 == ~t14_pc~0; 1122#L913true assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 2025#L923true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1193#is_transmit14_triggered_returnLabel#1true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 164#L1778true assume !(0 != activate_threads_~tmp___13~0#1); 629#L1778-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1343#L1495true assume 1 == ~M_E~0;~M_E~0 := 2; 996#L1495-2true assume !(1 == ~T1_E~0); 1671#L1500-1true assume !(1 == ~T2_E~0); 709#L1505-1true assume !(1 == ~T3_E~0); 1919#L1510-1true assume !(1 == ~T4_E~0); 754#L1515-1true assume !(1 == ~T5_E~0); 1723#L1520-1true assume !(1 == ~T6_E~0); 1390#L1525-1true assume !(1 == ~T7_E~0); 1023#L1530-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 249#L1535-1true assume !(1 == ~T9_E~0); 1839#L1540-1true assume !(1 == ~T10_E~0); 15#L1545-1true assume !(1 == ~T11_E~0); 1973#L1550-1true assume !(1 == ~T12_E~0); 128#L1555-1true assume !(1 == ~T13_E~0); 277#L1560-1true assume !(1 == ~T14_E~0); 1700#L1565-1true assume !(1 == ~E_1~0); 1932#L1570-1true assume 1 == ~E_2~0;~E_2~0 := 2; 905#L1575-1true assume !(1 == ~E_3~0); 436#L1580-1true assume !(1 == ~E_4~0); 771#L1585-1true assume !(1 == ~E_5~0); 1040#L1590-1true assume !(1 == ~E_6~0); 455#L1595-1true assume !(1 == ~E_7~0); 1898#L1600-1true assume !(1 == ~E_8~0); 717#L1605-1true assume !(1 == ~E_9~0); 1647#L1610-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1233#L1615-1true assume !(1 == ~E_11~0); 353#L1620-1true assume !(1 == ~E_12~0); 1104#L1625-1true assume !(1 == ~E_13~0); 936#L1630-1true assume !(1 == ~E_14~0); 454#L1635-1true assume { :end_inline_reset_delta_events } true; 421#L2017-2true [2022-12-13 12:47:34,129 INFO L750 eck$LassoCheckResult]: Loop: 421#L2017-2true assume !false; 47#L2018true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 876#L1316true assume !true; 577#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 349#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 614#L1342-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1077#L1342-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1161#L1347-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 745#L1352-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1352#L1357-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 2037#L1362-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1883#L1367-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1848#L1372-3true assume !(0 == ~T7_E~0); 38#L1377-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 477#L1382-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 373#L1387-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1123#L1392-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1953#L1397-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1664#L1402-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 702#L1407-3true assume 0 == ~T14_E~0;~T14_E~0 := 1; 177#L1412-3true assume !(0 == ~E_1~0); 1395#L1417-3true assume 0 == ~E_2~0;~E_2~0 := 1; 640#L1422-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1345#L1427-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1534#L1432-3true assume 0 == ~E_5~0;~E_5~0 := 1; 973#L1437-3true assume 0 == ~E_6~0;~E_6~0 := 1; 714#L1442-3true assume 0 == ~E_7~0;~E_7~0 := 1; 995#L1447-3true assume 0 == ~E_8~0;~E_8~0 := 1; 67#L1452-3true assume !(0 == ~E_9~0); 2003#L1457-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1248#L1462-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1687#L1467-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1042#L1472-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1707#L1477-3true assume 0 == ~E_14~0;~E_14~0 := 1; 176#L1482-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 508#L646-42true assume 1 == ~m_pc~0; 1979#L647-14true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1305#L657-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 426#is_master_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1616#L1666-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1705#L1666-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1212#L665-42true assume !(1 == ~t1_pc~0); 1453#L665-44true is_transmit1_triggered_~__retres1~1#1 := 0; 1537#L676-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1874#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 266#L1674-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1885#L1674-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1882#L684-42true assume !(1 == ~t2_pc~0); 1794#L684-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1895#L695-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 659#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 665#L1682-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 763#L1682-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1737#L703-42true assume !(1 == ~t3_pc~0); 1579#L703-44true is_transmit3_triggered_~__retres1~3#1 := 0; 1852#L714-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1010#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1627#L1690-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1047#L1690-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 688#L722-42true assume 1 == ~t4_pc~0; 1091#L723-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1714#L733-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1088#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 344#L1698-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1926#L1698-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1726#L741-42true assume !(1 == ~t5_pc~0); 1063#L741-44true is_transmit5_triggered_~__retres1~5#1 := 0; 593#L752-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 710#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1903#L1706-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 521#L1706-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 622#L760-42true assume !(1 == ~t6_pc~0); 859#L760-44true is_transmit6_triggered_~__retres1~6#1 := 0; 724#L771-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 221#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1637#L1714-42true assume !(0 != activate_threads_~tmp___5~0#1); 492#L1714-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1319#L779-42true assume !(1 == ~t7_pc~0); 1182#L779-44true is_transmit7_triggered_~__retres1~7#1 := 0; 1872#L790-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 730#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1697#L1722-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 226#L1722-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 487#L798-42true assume !(1 == ~t8_pc~0); 43#L798-44true is_transmit8_triggered_~__retres1~8#1 := 0; 1432#L809-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 870#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 740#L1730-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 142#L1730-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1368#L817-42true assume !(1 == ~t9_pc~0); 1144#L817-44true is_transmit9_triggered_~__retres1~9#1 := 0; 291#L828-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1900#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1180#L1738-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 971#L1738-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1513#L836-42true assume !(1 == ~t10_pc~0); 1818#L836-44true is_transmit10_triggered_~__retres1~10#1 := 0; 313#L847-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 854#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1550#L1746-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1693#L1746-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2045#L855-42true assume !(1 == ~t11_pc~0); 1796#L855-44true is_transmit11_triggered_~__retres1~11#1 := 0; 85#L866-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1556#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1163#L1754-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2047#L1754-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 406#L874-42true assume 1 == ~t12_pc~0; 560#L875-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1484#L885-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 692#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 886#L1762-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 162#L1762-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1984#L893-42true assume 1 == ~t13_pc~0; 999#L894-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1838#L904-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 387#is_transmit13_triggered_returnLabel#15true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 723#L1770-42true assume !(0 != activate_threads_~tmp___12~0#1); 363#L1770-44true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1850#L912-42true assume 1 == ~t14_pc~0; 1668#L913-14true assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 25#L923-14true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 430#is_transmit14_triggered_returnLabel#15true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1215#L1778-42true assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 224#L1778-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 600#L1495-3true assume !(1 == ~M_E~0); 964#L1495-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1570#L1500-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1067#L1505-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 347#L1510-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 329#L1515-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 781#L1520-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 993#L1525-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1576#L1530-3true assume !(1 == ~T8_E~0); 243#L1535-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 263#L1540-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1286#L1545-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1533#L1550-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1511#L1555-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 501#L1560-3true assume 1 == ~T14_E~0;~T14_E~0 := 2; 1016#L1565-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1877#L1570-3true assume !(1 == ~E_2~0); 967#L1575-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1416#L1580-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1521#L1585-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1756#L1590-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1662#L1595-3true assume 1 == ~E_7~0;~E_7~0 := 2; 803#L1600-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1311#L1605-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1396#L1610-3true assume !(1 == ~E_10~0); 355#L1615-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1918#L1620-3true assume 1 == ~E_12~0;~E_12~0 := 2; 772#L1625-3true assume 1 == ~E_13~0;~E_13~0 := 2; 2040#L1630-3true assume 1 == ~E_14~0;~E_14~0 := 2; 691#L1635-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 322#L1022-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 524#L1100-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 213#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 994#L2036true assume !(0 == start_simulation_~tmp~3#1); 1170#L2036-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1629#L1022-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1417#L1100-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 725#L1991true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1731#L1998true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1392#stop_simulation_returnLabel#1true start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1808#L2049true assume !(0 != start_simulation_~tmp___0~1#1); 421#L2017-2true [2022-12-13 12:47:34,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:34,135 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 1 times [2022-12-13 12:47:34,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:34,145 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [42530894] [2022-12-13 12:47:34,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:34,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:34,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:34,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:34,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:34,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [42530894] [2022-12-13 12:47:34,437 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [42530894] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:34,437 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:34,438 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:34,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1751214318] [2022-12-13 12:47:34,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:34,453 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:34,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:34,454 INFO L85 PathProgramCache]: Analyzing trace with hash -1220690324, now seen corresponding path program 1 times [2022-12-13 12:47:34,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:34,455 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082690620] [2022-12-13 12:47:34,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:34,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:34,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:34,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:34,514 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:34,514 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1082690620] [2022-12-13 12:47:34,515 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1082690620] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:34,515 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:34,515 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:47:34,515 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366873495] [2022-12-13 12:47:34,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:34,517 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:34,518 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:34,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 12:47:34,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 12:47:34,554 INFO L87 Difference]: Start difference. First operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 83.5) internal successors, (167), 2 states have internal predecessors, (167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:34,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:34,613 INFO L93 Difference]: Finished difference Result 2052 states and 3039 transitions. [2022-12-13 12:47:34,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2052 states and 3039 transitions. [2022-12-13 12:47:34,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:34,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2052 states to 2047 states and 3034 transitions. [2022-12-13 12:47:34,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:34,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:34,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3034 transitions. [2022-12-13 12:47:34,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:34,659 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2022-12-13 12:47:34,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3034 transitions. [2022-12-13 12:47:34,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:34,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4821690278456277) internal successors, (3034), 2046 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:34,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3034 transitions. [2022-12-13 12:47:34,738 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2022-12-13 12:47:34,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 12:47:34,742 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2022-12-13 12:47:34,742 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 12:47:34,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3034 transitions. [2022-12-13 12:47:34,752 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:34,752 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:34,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:34,755 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:34,756 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:34,756 INFO L748 eck$LassoCheckResult]: Stem: 4469#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 4470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 5388#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5389#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6150#L939 assume !(1 == ~m_i~0);~m_st~0 := 2; 4993#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4994#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4713#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4714#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5961#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5285#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5286#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5826#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5191#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5192#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4625#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4626#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4960#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5145#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 4212#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4213#L1342 assume !(0 == ~M_E~0); 4379#L1342-2 assume !(0 == ~T1_E~0); 4929#L1347-1 assume !(0 == ~T2_E~0); 5942#L1352-1 assume !(0 == ~T3_E~0); 5734#L1357-1 assume !(0 == ~T4_E~0); 4951#L1362-1 assume !(0 == ~T5_E~0); 4952#L1367-1 assume !(0 == ~T6_E~0); 4544#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4545#L1377-1 assume !(0 == ~T8_E~0); 4874#L1382-1 assume !(0 == ~T9_E~0); 4875#L1387-1 assume !(0 == ~T10_E~0); 5615#L1392-1 assume !(0 == ~T11_E~0); 4913#L1397-1 assume !(0 == ~T12_E~0); 4914#L1402-1 assume !(0 == ~T13_E~0); 4566#L1407-1 assume !(0 == ~T14_E~0); 4567#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5860#L1417-1 assume !(0 == ~E_2~0); 5861#L1422-1 assume !(0 == ~E_3~0); 6096#L1427-1 assume !(0 == ~E_4~0); 4742#L1432-1 assume !(0 == ~E_5~0); 4743#L1437-1 assume !(0 == ~E_6~0); 5778#L1442-1 assume !(0 == ~E_7~0); 5779#L1447-1 assume !(0 == ~E_8~0); 5609#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 4348#L1457-1 assume !(0 == ~E_10~0); 4349#L1462-1 assume !(0 == ~E_11~0); 5808#L1467-1 assume !(0 == ~E_12~0); 5821#L1472-1 assume !(0 == ~E_13~0); 5822#L1477-1 assume !(0 == ~E_14~0); 5556#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4533#L646 assume 1 == ~m_pc~0; 4534#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5200#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5215#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4627#L1666 assume !(0 != activate_threads_~tmp~1#1); 4628#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6117#L665 assume !(1 == ~t1_pc~0); 5096#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5097#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5706#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5707#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 5437#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5438#L684 assume 1 == ~t2_pc~0; 5553#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5477#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4613#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4614#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 5947#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6130#L703 assume !(1 == ~t3_pc~0); 4767#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4768#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5694#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4184#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 4185#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4655#L722 assume 1 == ~t4_pc~0; 5395#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4839#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4295#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4296#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 5236#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4380#L741 assume 1 == ~t5_pc~0; 4381#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4677#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5471#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5523#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 5524#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4930#L760 assume !(1 == ~t6_pc~0); 4766#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4765#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4605#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4606#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5352#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5353#L779 assume 1 == ~t7_pc~0; 4417#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4266#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4267#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5979#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 4689#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4690#L798 assume !(1 == ~t8_pc~0); 5989#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5907#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5908#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6072#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 6119#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4245#L817 assume 1 == ~t9_pc~0; 4246#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5029#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4659#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4660#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 4639#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4640#L836 assume !(1 == ~t10_pc~0); 4661#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4591#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4592#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4840#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 4841#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5920#L855 assume 1 == ~t11_pc~0; 5211#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5212#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5802#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5606#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 5443#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4530#L874 assume !(1 == ~t12_pc~0); 4531#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4698#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4234#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4235#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 4220#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4221#L893 assume 1 == ~t13_pc~0; 6054#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4569#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4873#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 6003#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 5994#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 5995#L912 assume 1 == ~t14_pc~0; 5785#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 5786#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 5857#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4467#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 4468#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5229#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 5664#L1495-2 assume !(1 == ~T1_E~0); 5665#L1500-1 assume !(1 == ~T2_E~0); 5346#L1505-1 assume !(1 == ~T3_E~0); 5347#L1510-1 assume !(1 == ~T4_E~0); 5405#L1515-1 assume !(1 == ~T5_E~0); 5406#L1520-1 assume !(1 == ~T6_E~0); 5990#L1525-1 assume !(1 == ~T7_E~0); 5695#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4632#L1535-1 assume !(1 == ~T9_E~0); 4633#L1540-1 assume !(1 == ~T10_E~0); 4145#L1545-1 assume !(1 == ~T11_E~0); 4146#L1550-1 assume !(1 == ~T12_E~0); 4390#L1555-1 assume !(1 == ~T13_E~0); 4391#L1560-1 assume !(1 == ~T14_E~0); 4680#L1565-1 assume !(1 == ~E_1~0); 6105#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 5577#L1575-1 assume !(1 == ~E_3~0); 4955#L1580-1 assume !(1 == ~E_4~0); 4956#L1585-1 assume !(1 == ~E_5~0); 5429#L1590-1 assume !(1 == ~E_6~0); 4987#L1595-1 assume !(1 == ~E_7~0); 4988#L1600-1 assume !(1 == ~E_8~0); 5360#L1605-1 assume !(1 == ~E_9~0); 5361#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5894#L1615-1 assume !(1 == ~E_11~0); 4814#L1620-1 assume !(1 == ~E_12~0); 4815#L1625-1 assume !(1 == ~E_13~0); 5610#L1630-1 assume !(1 == ~E_14~0); 4986#L1635-1 assume { :end_inline_reset_delta_events } true; 4931#L2017-2 [2022-12-13 12:47:34,757 INFO L750 eck$LassoCheckResult]: Loop: 4931#L2017-2 assume !false; 4218#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4219#L1316 assume !false; 5543#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5605#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4158#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4493#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5629#L1115 assume !(0 != eval_~tmp~0#1); 5157#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4809#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4810#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5210#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5741#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5391#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5392#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5973#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6144#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6138#L1372-3 assume !(0 == ~T7_E~0); 4198#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4199#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4853#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4854#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5788#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 6092#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5338#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 4491#L1412-3 assume !(0 == ~E_1~0); 4492#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5242#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5243#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5971#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5649#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5354#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5355#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4262#L1452-3 assume !(0 == ~E_9~0); 4263#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5905#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5906#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 5711#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5712#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 4489#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4490#L646-42 assume 1 == ~m_pc~0; 5072#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5943#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4939#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4940#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6076#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5876#L665-42 assume 1 == ~t1_pc~0; 5833#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5835#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6050#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4662#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4663#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6143#L684-42 assume !(1 == ~t2_pc~0); 5521#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5520#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5271#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5272#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5281#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5417#L703-42 assume 1 == ~t3_pc~0; 5620#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5621#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5684#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5685#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5718#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5321#L722-42 assume 1 == ~t4_pc~0; 5322#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5754#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5750#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4802#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4803#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6111#L741-42 assume !(1 == ~t5_pc~0); 5730#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 5176#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5177#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5348#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5090#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5091#L760-42 assume !(1 == ~t6_pc~0); 5217#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 5367#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4580#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4581#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 5045#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5046#L779-42 assume !(1 == ~t7_pc~0); 5840#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 5841#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5375#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5376#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4589#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4590#L798-42 assume !(1 == ~t8_pc~0); 4210#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 4211#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5538#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5385#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4423#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4424#L817-42 assume !(1 == ~t9_pc~0); 5184#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 4700#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4701#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5839#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5644#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5645#L836-42 assume 1 == ~t10_pc~0; 5745#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4737#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4738#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5518#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6057#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6099#L855-42 assume 1 == ~t11_pc~0; 6109#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4301#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4302#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5819#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5820#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4910#L874-42 assume !(1 == ~t12_pc~0); 4912#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 5136#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5326#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5327#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4463#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4464#L893-42 assume !(1 == ~t13_pc~0); 5457#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 5458#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4876#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4877#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 4836#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 4837#L912-42 assume !(1 == ~t14_pc~0); 5652#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 4168#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 4169#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4945#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 4586#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4587#L1495-3 assume !(1 == ~M_E~0); 5188#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5635#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5731#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4808#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4769#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4770#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5442#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5661#L1530-3 assume !(1 == ~T8_E~0); 4621#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4622#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4658#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5934#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 6041#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5060#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 5061#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5691#L1570-3 assume !(1 == ~E_2~0); 5639#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5640#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6004#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6045#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6091#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5465#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5466#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5948#L1610-3 assume !(1 == ~E_10~0); 4818#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4819#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5430#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5431#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 5325#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 4753#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4375#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4564#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4565#L2036 assume !(0 == start_simulation_~tmp~3#1); 5662#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5825#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4974#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4214#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 4215#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5368#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5992#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 5993#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 4931#L2017-2 [2022-12-13 12:47:34,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:34,758 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 2 times [2022-12-13 12:47:34,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:34,758 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141772125] [2022-12-13 12:47:34,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:34,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:34,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:34,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:34,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:34,842 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2141772125] [2022-12-13 12:47:34,843 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2141772125] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:34,843 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:34,843 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:34,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308561689] [2022-12-13 12:47:34,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:34,844 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:34,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:34,844 INFO L85 PathProgramCache]: Analyzing trace with hash -1869683352, now seen corresponding path program 1 times [2022-12-13 12:47:34,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:34,845 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748777814] [2022-12-13 12:47:34,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:34,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:34,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:34,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:34,952 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:34,952 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1748777814] [2022-12-13 12:47:34,952 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1748777814] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:34,952 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:34,953 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:34,953 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [221755244] [2022-12-13 12:47:34,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:34,953 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:34,954 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:34,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:34,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:34,955 INFO L87 Difference]: Start difference. First operand 2047 states and 3034 transitions. cyclomatic complexity: 988 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:34,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:34,994 INFO L93 Difference]: Finished difference Result 2047 states and 3033 transitions. [2022-12-13 12:47:34,994 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3033 transitions. [2022-12-13 12:47:35,001 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:35,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3033 transitions. [2022-12-13 12:47:35,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:35,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:35,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3033 transitions. [2022-12-13 12:47:35,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:35,010 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2022-12-13 12:47:35,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3033 transitions. [2022-12-13 12:47:35,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:35,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4816805080605764) internal successors, (3033), 2046 states have internal predecessors, (3033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:35,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3033 transitions. [2022-12-13 12:47:35,033 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2022-12-13 12:47:35,033 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:35,034 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2022-12-13 12:47:35,034 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 12:47:35,034 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3033 transitions. [2022-12-13 12:47:35,040 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:35,040 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:35,040 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:35,042 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:35,042 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:35,042 INFO L748 eck$LassoCheckResult]: Stem: 8570#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 8571#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 9489#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9490#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10251#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 9094#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9095#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8814#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8815#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10062#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9386#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9387#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9927#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9292#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9293#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8726#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8727#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9061#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9246#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 8313#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8314#L1342 assume !(0 == ~M_E~0); 8480#L1342-2 assume !(0 == ~T1_E~0); 9030#L1347-1 assume !(0 == ~T2_E~0); 10043#L1352-1 assume !(0 == ~T3_E~0); 9835#L1357-1 assume !(0 == ~T4_E~0); 9052#L1362-1 assume !(0 == ~T5_E~0); 9053#L1367-1 assume !(0 == ~T6_E~0); 8645#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8646#L1377-1 assume !(0 == ~T8_E~0); 8975#L1382-1 assume !(0 == ~T9_E~0); 8976#L1387-1 assume !(0 == ~T10_E~0); 9716#L1392-1 assume !(0 == ~T11_E~0); 9014#L1397-1 assume !(0 == ~T12_E~0); 9015#L1402-1 assume !(0 == ~T13_E~0); 8667#L1407-1 assume !(0 == ~T14_E~0); 8668#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 9961#L1417-1 assume !(0 == ~E_2~0); 9962#L1422-1 assume !(0 == ~E_3~0); 10197#L1427-1 assume !(0 == ~E_4~0); 8843#L1432-1 assume !(0 == ~E_5~0); 8844#L1437-1 assume !(0 == ~E_6~0); 9879#L1442-1 assume !(0 == ~E_7~0); 9880#L1447-1 assume !(0 == ~E_8~0); 9710#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 8449#L1457-1 assume !(0 == ~E_10~0); 8450#L1462-1 assume !(0 == ~E_11~0); 9909#L1467-1 assume !(0 == ~E_12~0); 9922#L1472-1 assume !(0 == ~E_13~0); 9923#L1477-1 assume !(0 == ~E_14~0); 9657#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8634#L646 assume 1 == ~m_pc~0; 8635#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9301#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9316#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8728#L1666 assume !(0 != activate_threads_~tmp~1#1); 8729#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10218#L665 assume !(1 == ~t1_pc~0); 9197#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9198#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9807#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9808#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 9538#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9539#L684 assume 1 == ~t2_pc~0; 9654#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9578#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8714#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8715#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 10048#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10231#L703 assume !(1 == ~t3_pc~0); 8868#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8869#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9795#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8285#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 8286#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8756#L722 assume 1 == ~t4_pc~0; 9496#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8940#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8396#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8397#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 9337#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8481#L741 assume 1 == ~t5_pc~0; 8482#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8778#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9572#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9624#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 9625#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9031#L760 assume !(1 == ~t6_pc~0); 8867#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8866#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8706#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8707#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9453#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9454#L779 assume 1 == ~t7_pc~0; 8518#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8367#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8368#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10080#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 8790#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8791#L798 assume !(1 == ~t8_pc~0); 10090#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10008#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10009#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10173#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 10220#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8346#L817 assume 1 == ~t9_pc~0; 8347#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9130#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8760#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8761#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 8740#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8741#L836 assume !(1 == ~t10_pc~0); 8762#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8692#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8693#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8941#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 8942#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10021#L855 assume 1 == ~t11_pc~0; 9312#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9313#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9903#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9707#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 9544#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8631#L874 assume !(1 == ~t12_pc~0); 8632#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8799#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8335#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8336#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 8321#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8322#L893 assume 1 == ~t13_pc~0; 10155#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8670#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8974#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 10104#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 10095#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 10096#L912 assume 1 == ~t14_pc~0; 9886#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 9887#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 9958#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 8568#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 8569#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9330#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 9765#L1495-2 assume !(1 == ~T1_E~0); 9766#L1500-1 assume !(1 == ~T2_E~0); 9447#L1505-1 assume !(1 == ~T3_E~0); 9448#L1510-1 assume !(1 == ~T4_E~0); 9506#L1515-1 assume !(1 == ~T5_E~0); 9507#L1520-1 assume !(1 == ~T6_E~0); 10091#L1525-1 assume !(1 == ~T7_E~0); 9796#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8733#L1535-1 assume !(1 == ~T9_E~0); 8734#L1540-1 assume !(1 == ~T10_E~0); 8246#L1545-1 assume !(1 == ~T11_E~0); 8247#L1550-1 assume !(1 == ~T12_E~0); 8491#L1555-1 assume !(1 == ~T13_E~0); 8492#L1560-1 assume !(1 == ~T14_E~0); 8781#L1565-1 assume !(1 == ~E_1~0); 10206#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9678#L1575-1 assume !(1 == ~E_3~0); 9056#L1580-1 assume !(1 == ~E_4~0); 9057#L1585-1 assume !(1 == ~E_5~0); 9530#L1590-1 assume !(1 == ~E_6~0); 9088#L1595-1 assume !(1 == ~E_7~0); 9089#L1600-1 assume !(1 == ~E_8~0); 9461#L1605-1 assume !(1 == ~E_9~0); 9462#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 9995#L1615-1 assume !(1 == ~E_11~0); 8915#L1620-1 assume !(1 == ~E_12~0); 8916#L1625-1 assume !(1 == ~E_13~0); 9711#L1630-1 assume !(1 == ~E_14~0); 9087#L1635-1 assume { :end_inline_reset_delta_events } true; 9032#L2017-2 [2022-12-13 12:47:35,043 INFO L750 eck$LassoCheckResult]: Loop: 9032#L2017-2 assume !false; 8319#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8320#L1316 assume !false; 9644#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 9706#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8259#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 8594#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9730#L1115 assume !(0 != eval_~tmp~0#1); 9258#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8910#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8911#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9311#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9842#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9492#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9493#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10074#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10245#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10239#L1372-3 assume !(0 == ~T7_E~0); 8299#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8300#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8954#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8955#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9889#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 10193#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9439#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 8592#L1412-3 assume !(0 == ~E_1~0); 8593#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9343#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9344#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10072#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9750#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9455#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9456#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8363#L1452-3 assume !(0 == ~E_9~0); 8364#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10006#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10007#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 9812#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9813#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 8590#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8591#L646-42 assume 1 == ~m_pc~0; 9173#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10044#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9040#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9041#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10177#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9977#L665-42 assume 1 == ~t1_pc~0; 9934#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9936#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10151#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8763#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8764#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10244#L684-42 assume 1 == ~t2_pc~0; 9620#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9621#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9372#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9373#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9382#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9518#L703-42 assume 1 == ~t3_pc~0; 9721#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9722#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9785#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9786#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9819#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9422#L722-42 assume !(1 == ~t4_pc~0); 9424#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 9855#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9851#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8903#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8904#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10212#L741-42 assume !(1 == ~t5_pc~0); 9831#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 9277#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9278#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9449#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9191#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9192#L760-42 assume !(1 == ~t6_pc~0); 9318#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 9468#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8681#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8682#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 9146#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9147#L779-42 assume !(1 == ~t7_pc~0); 9941#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 9942#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9476#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9477#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8690#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8691#L798-42 assume 1 == ~t8_pc~0; 9139#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8312#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9639#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9486#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8524#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8525#L817-42 assume 1 == ~t9_pc~0; 9284#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8801#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8802#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9940#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9745#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9746#L836-42 assume 1 == ~t10_pc~0; 9846#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8838#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8839#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9619#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10158#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10200#L855-42 assume 1 == ~t11_pc~0; 10210#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8402#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8403#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9920#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9921#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9011#L874-42 assume 1 == ~t12_pc~0; 9012#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 9237#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9427#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9428#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8564#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8565#L893-42 assume !(1 == ~t13_pc~0); 9558#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 9559#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8977#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8978#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 8937#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 8938#L912-42 assume 1 == ~t14_pc~0; 10194#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 8269#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 8270#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9046#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 8687#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8688#L1495-3 assume !(1 == ~M_E~0); 9289#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9736#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9832#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8909#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8870#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8871#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9543#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9762#L1530-3 assume !(1 == ~T8_E~0); 8722#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8723#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8759#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10035#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 10142#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9161#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 9162#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9792#L1570-3 assume !(1 == ~E_2~0); 9740#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9741#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10105#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10146#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10192#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9566#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9567#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10049#L1610-3 assume !(1 == ~E_10~0); 8919#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8920#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9531#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9532#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 9426#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 8854#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8476#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 8665#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 8666#L2036 assume !(0 == start_simulation_~tmp~3#1); 9763#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 9926#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 9075#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 8315#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 8316#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9469#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10093#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 10094#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 9032#L2017-2 [2022-12-13 12:47:35,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:35,043 INFO L85 PathProgramCache]: Analyzing trace with hash -1949208090, now seen corresponding path program 1 times [2022-12-13 12:47:35,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:35,044 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983943419] [2022-12-13 12:47:35,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:35,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:35,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:35,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:35,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:35,095 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983943419] [2022-12-13 12:47:35,095 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1983943419] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:35,095 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:35,095 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:35,095 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816222385] [2022-12-13 12:47:35,096 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:35,096 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:35,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:35,096 INFO L85 PathProgramCache]: Analyzing trace with hash 1117555628, now seen corresponding path program 1 times [2022-12-13 12:47:35,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:35,097 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609555113] [2022-12-13 12:47:35,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:35,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:35,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:35,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:35,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:35,169 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1609555113] [2022-12-13 12:47:35,169 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1609555113] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:35,169 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:35,169 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:35,169 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1474688856] [2022-12-13 12:47:35,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:35,170 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:35,170 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:35,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:35,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:35,170 INFO L87 Difference]: Start difference. First operand 2047 states and 3033 transitions. cyclomatic complexity: 987 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:35,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:35,199 INFO L93 Difference]: Finished difference Result 2047 states and 3032 transitions. [2022-12-13 12:47:35,199 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3032 transitions. [2022-12-13 12:47:35,207 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:35,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3032 transitions. [2022-12-13 12:47:35,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:35,213 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:35,213 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3032 transitions. [2022-12-13 12:47:35,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:35,215 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2022-12-13 12:47:35,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3032 transitions. [2022-12-13 12:47:35,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:35,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4811919882755251) internal successors, (3032), 2046 states have internal predecessors, (3032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:35,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3032 transitions. [2022-12-13 12:47:35,239 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2022-12-13 12:47:35,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:35,239 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2022-12-13 12:47:35,240 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 12:47:35,240 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3032 transitions. [2022-12-13 12:47:35,245 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:35,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:35,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:35,247 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:35,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:35,247 INFO L748 eck$LassoCheckResult]: Stem: 12671#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 12672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 13590#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13591#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14352#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 13195#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13196#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12915#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12916#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14163#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13487#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13488#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14028#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13393#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13394#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12827#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12828#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13162#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13347#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 12414#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12415#L1342 assume !(0 == ~M_E~0); 12581#L1342-2 assume !(0 == ~T1_E~0); 13131#L1347-1 assume !(0 == ~T2_E~0); 14144#L1352-1 assume !(0 == ~T3_E~0); 13936#L1357-1 assume !(0 == ~T4_E~0); 13153#L1362-1 assume !(0 == ~T5_E~0); 13154#L1367-1 assume !(0 == ~T6_E~0); 12746#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12747#L1377-1 assume !(0 == ~T8_E~0); 13076#L1382-1 assume !(0 == ~T9_E~0); 13077#L1387-1 assume !(0 == ~T10_E~0); 13817#L1392-1 assume !(0 == ~T11_E~0); 13115#L1397-1 assume !(0 == ~T12_E~0); 13116#L1402-1 assume !(0 == ~T13_E~0); 12768#L1407-1 assume !(0 == ~T14_E~0); 12769#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 14062#L1417-1 assume !(0 == ~E_2~0); 14063#L1422-1 assume !(0 == ~E_3~0); 14298#L1427-1 assume !(0 == ~E_4~0); 12944#L1432-1 assume !(0 == ~E_5~0); 12945#L1437-1 assume !(0 == ~E_6~0); 13980#L1442-1 assume !(0 == ~E_7~0); 13981#L1447-1 assume !(0 == ~E_8~0); 13811#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 12550#L1457-1 assume !(0 == ~E_10~0); 12551#L1462-1 assume !(0 == ~E_11~0); 14010#L1467-1 assume !(0 == ~E_12~0); 14023#L1472-1 assume !(0 == ~E_13~0); 14024#L1477-1 assume !(0 == ~E_14~0); 13758#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12735#L646 assume 1 == ~m_pc~0; 12736#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13402#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13417#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12829#L1666 assume !(0 != activate_threads_~tmp~1#1); 12830#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14319#L665 assume !(1 == ~t1_pc~0); 13298#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13299#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13908#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13909#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 13639#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13640#L684 assume 1 == ~t2_pc~0; 13755#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13679#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12815#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12816#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 14149#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14332#L703 assume !(1 == ~t3_pc~0); 12969#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12970#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13896#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12386#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 12387#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12857#L722 assume 1 == ~t4_pc~0; 13597#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13041#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12497#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12498#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 13438#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12582#L741 assume 1 == ~t5_pc~0; 12583#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12879#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13673#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13725#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 13726#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13132#L760 assume !(1 == ~t6_pc~0); 12968#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12967#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12807#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12808#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13554#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13555#L779 assume 1 == ~t7_pc~0; 12619#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12468#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12469#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14181#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 12891#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12892#L798 assume !(1 == ~t8_pc~0); 14191#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14109#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14110#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14274#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 14321#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12447#L817 assume 1 == ~t9_pc~0; 12448#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13231#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12861#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12862#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 12841#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12842#L836 assume !(1 == ~t10_pc~0); 12863#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12793#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12794#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13042#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 13043#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14122#L855 assume 1 == ~t11_pc~0; 13413#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13414#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14004#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13808#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 13645#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12732#L874 assume !(1 == ~t12_pc~0); 12733#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 12900#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12436#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12437#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 12422#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12423#L893 assume 1 == ~t13_pc~0; 14256#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12771#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13075#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 14205#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 14196#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 14197#L912 assume 1 == ~t14_pc~0; 13987#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 13988#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 14059#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 12669#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 12670#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13431#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 13866#L1495-2 assume !(1 == ~T1_E~0); 13867#L1500-1 assume !(1 == ~T2_E~0); 13548#L1505-1 assume !(1 == ~T3_E~0); 13549#L1510-1 assume !(1 == ~T4_E~0); 13607#L1515-1 assume !(1 == ~T5_E~0); 13608#L1520-1 assume !(1 == ~T6_E~0); 14192#L1525-1 assume !(1 == ~T7_E~0); 13897#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12834#L1535-1 assume !(1 == ~T9_E~0); 12835#L1540-1 assume !(1 == ~T10_E~0); 12347#L1545-1 assume !(1 == ~T11_E~0); 12348#L1550-1 assume !(1 == ~T12_E~0); 12592#L1555-1 assume !(1 == ~T13_E~0); 12593#L1560-1 assume !(1 == ~T14_E~0); 12882#L1565-1 assume !(1 == ~E_1~0); 14307#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13779#L1575-1 assume !(1 == ~E_3~0); 13157#L1580-1 assume !(1 == ~E_4~0); 13158#L1585-1 assume !(1 == ~E_5~0); 13631#L1590-1 assume !(1 == ~E_6~0); 13189#L1595-1 assume !(1 == ~E_7~0); 13190#L1600-1 assume !(1 == ~E_8~0); 13562#L1605-1 assume !(1 == ~E_9~0); 13563#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14096#L1615-1 assume !(1 == ~E_11~0); 13016#L1620-1 assume !(1 == ~E_12~0); 13017#L1625-1 assume !(1 == ~E_13~0); 13812#L1630-1 assume !(1 == ~E_14~0); 13188#L1635-1 assume { :end_inline_reset_delta_events } true; 13133#L2017-2 [2022-12-13 12:47:35,248 INFO L750 eck$LassoCheckResult]: Loop: 13133#L2017-2 assume !false; 12420#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12421#L1316 assume !false; 13745#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 13807#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12360#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12695#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13831#L1115 assume !(0 != eval_~tmp~0#1); 13359#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13011#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13012#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13412#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13943#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13593#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13594#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14175#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14346#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14340#L1372-3 assume !(0 == ~T7_E~0); 12400#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12401#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13055#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13056#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13990#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14294#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13540#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 12693#L1412-3 assume !(0 == ~E_1~0); 12694#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13444#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13445#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14173#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13851#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13556#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13557#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12464#L1452-3 assume !(0 == ~E_9~0); 12465#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14107#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14108#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 13913#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13914#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 12691#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12692#L646-42 assume 1 == ~m_pc~0; 13274#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14145#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13141#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13142#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14278#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14078#L665-42 assume 1 == ~t1_pc~0; 14035#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14037#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14252#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12864#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12865#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14345#L684-42 assume 1 == ~t2_pc~0; 13721#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13722#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13473#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13474#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13483#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13619#L703-42 assume !(1 == ~t3_pc~0); 13824#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 13823#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13886#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13887#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13920#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13523#L722-42 assume 1 == ~t4_pc~0; 13524#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13956#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13952#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13004#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13005#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14313#L741-42 assume 1 == ~t5_pc~0; 14257#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13378#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13379#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13550#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13292#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13293#L760-42 assume !(1 == ~t6_pc~0); 13419#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 13569#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12782#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12783#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 13247#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13248#L779-42 assume 1 == ~t7_pc~0; 14097#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14043#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13577#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13578#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12791#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12792#L798-42 assume 1 == ~t8_pc~0; 13240#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12413#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13740#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13587#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12625#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12626#L817-42 assume 1 == ~t9_pc~0; 13385#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12902#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12903#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14041#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13846#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13847#L836-42 assume 1 == ~t10_pc~0; 13947#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12939#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12940#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13720#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14259#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14301#L855-42 assume 1 == ~t11_pc~0; 14311#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12503#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12504#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14021#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14022#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13112#L874-42 assume 1 == ~t12_pc~0; 13113#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13338#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13528#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13529#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12665#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12666#L893-42 assume !(1 == ~t13_pc~0); 13659#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 13660#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13078#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13079#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 13038#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 13039#L912-42 assume 1 == ~t14_pc~0; 14295#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 12370#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 12371#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13147#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 12788#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12789#L1495-3 assume !(1 == ~M_E~0); 13390#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13837#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13933#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13010#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12971#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12972#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13644#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13863#L1530-3 assume !(1 == ~T8_E~0); 12823#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12824#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12860#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14136#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 14243#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13262#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 13263#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13893#L1570-3 assume !(1 == ~E_2~0); 13841#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13842#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14206#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14247#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14293#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13667#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13668#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14150#L1610-3 assume !(1 == ~E_10~0); 13020#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13021#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13632#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13633#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 13527#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 12955#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12577#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12766#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 12767#L2036 assume !(0 == start_simulation_~tmp~3#1); 13864#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 14027#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 13176#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12416#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 12417#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 13570#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14194#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14195#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 13133#L2017-2 [2022-12-13 12:47:35,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:35,249 INFO L85 PathProgramCache]: Analyzing trace with hash -224599768, now seen corresponding path program 1 times [2022-12-13 12:47:35,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:35,249 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [778444540] [2022-12-13 12:47:35,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:35,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:35,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:35,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:35,300 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:35,300 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [778444540] [2022-12-13 12:47:35,300 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [778444540] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:35,300 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:35,300 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:35,301 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638724789] [2022-12-13 12:47:35,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:35,301 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:35,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:35,301 INFO L85 PathProgramCache]: Analyzing trace with hash 622384942, now seen corresponding path program 1 times [2022-12-13 12:47:35,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:35,302 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [93308466] [2022-12-13 12:47:35,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:35,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:35,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:35,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:35,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:35,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [93308466] [2022-12-13 12:47:35,378 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [93308466] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:35,378 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:35,379 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:35,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1530791997] [2022-12-13 12:47:35,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:35,379 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:35,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:35,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:35,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:35,380 INFO L87 Difference]: Start difference. First operand 2047 states and 3032 transitions. cyclomatic complexity: 986 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:35,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:35,408 INFO L93 Difference]: Finished difference Result 2047 states and 3031 transitions. [2022-12-13 12:47:35,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3031 transitions. [2022-12-13 12:47:35,415 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:35,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3031 transitions. [2022-12-13 12:47:35,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:35,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:35,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3031 transitions. [2022-12-13 12:47:35,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:35,423 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2022-12-13 12:47:35,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3031 transitions. [2022-12-13 12:47:35,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:35,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4807034684904739) internal successors, (3031), 2046 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:35,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3031 transitions. [2022-12-13 12:47:35,447 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2022-12-13 12:47:35,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:35,448 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2022-12-13 12:47:35,448 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 12:47:35,448 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3031 transitions. [2022-12-13 12:47:35,454 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:35,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:35,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:35,455 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:35,455 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:35,456 INFO L748 eck$LassoCheckResult]: Stem: 16772#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 16773#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 17691#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17692#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18453#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 17296#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17297#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17016#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17017#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18264#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17588#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17589#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18129#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17494#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17495#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16928#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16929#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17263#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17448#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 16515#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16516#L1342 assume !(0 == ~M_E~0); 16682#L1342-2 assume !(0 == ~T1_E~0); 17232#L1347-1 assume !(0 == ~T2_E~0); 18245#L1352-1 assume !(0 == ~T3_E~0); 18037#L1357-1 assume !(0 == ~T4_E~0); 17254#L1362-1 assume !(0 == ~T5_E~0); 17255#L1367-1 assume !(0 == ~T6_E~0); 16847#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16848#L1377-1 assume !(0 == ~T8_E~0); 17177#L1382-1 assume !(0 == ~T9_E~0); 17178#L1387-1 assume !(0 == ~T10_E~0); 17918#L1392-1 assume !(0 == ~T11_E~0); 17216#L1397-1 assume !(0 == ~T12_E~0); 17217#L1402-1 assume !(0 == ~T13_E~0); 16869#L1407-1 assume !(0 == ~T14_E~0); 16870#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 18163#L1417-1 assume !(0 == ~E_2~0); 18164#L1422-1 assume !(0 == ~E_3~0); 18399#L1427-1 assume !(0 == ~E_4~0); 17045#L1432-1 assume !(0 == ~E_5~0); 17046#L1437-1 assume !(0 == ~E_6~0); 18081#L1442-1 assume !(0 == ~E_7~0); 18082#L1447-1 assume !(0 == ~E_8~0); 17912#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 16651#L1457-1 assume !(0 == ~E_10~0); 16652#L1462-1 assume !(0 == ~E_11~0); 18111#L1467-1 assume !(0 == ~E_12~0); 18124#L1472-1 assume !(0 == ~E_13~0); 18125#L1477-1 assume !(0 == ~E_14~0); 17859#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16836#L646 assume 1 == ~m_pc~0; 16837#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17503#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17518#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16930#L1666 assume !(0 != activate_threads_~tmp~1#1); 16931#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18420#L665 assume !(1 == ~t1_pc~0); 17399#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17400#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18009#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18010#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 17740#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17741#L684 assume 1 == ~t2_pc~0; 17856#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17780#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16916#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16917#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 18250#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18433#L703 assume !(1 == ~t3_pc~0); 17070#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17071#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17997#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16487#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 16488#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16958#L722 assume 1 == ~t4_pc~0; 17698#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17142#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16598#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16599#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 17539#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16683#L741 assume 1 == ~t5_pc~0; 16684#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16980#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17774#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17826#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 17827#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17233#L760 assume !(1 == ~t6_pc~0); 17069#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17068#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16908#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16909#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17655#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17656#L779 assume 1 == ~t7_pc~0; 16720#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16569#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16570#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18282#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 16992#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16993#L798 assume !(1 == ~t8_pc~0); 18292#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18210#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18211#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18375#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 18422#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16548#L817 assume 1 == ~t9_pc~0; 16549#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17332#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16962#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16963#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 16942#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16943#L836 assume !(1 == ~t10_pc~0); 16964#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16894#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16895#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17143#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 17144#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18223#L855 assume 1 == ~t11_pc~0; 17514#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17515#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18105#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17909#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 17746#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16833#L874 assume !(1 == ~t12_pc~0); 16834#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17001#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16537#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16538#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 16523#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16524#L893 assume 1 == ~t13_pc~0; 18357#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16872#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17176#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18306#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 18297#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 18298#L912 assume 1 == ~t14_pc~0; 18088#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 18089#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 18160#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 16770#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 16771#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17532#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 17967#L1495-2 assume !(1 == ~T1_E~0); 17968#L1500-1 assume !(1 == ~T2_E~0); 17649#L1505-1 assume !(1 == ~T3_E~0); 17650#L1510-1 assume !(1 == ~T4_E~0); 17708#L1515-1 assume !(1 == ~T5_E~0); 17709#L1520-1 assume !(1 == ~T6_E~0); 18293#L1525-1 assume !(1 == ~T7_E~0); 17998#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16935#L1535-1 assume !(1 == ~T9_E~0); 16936#L1540-1 assume !(1 == ~T10_E~0); 16448#L1545-1 assume !(1 == ~T11_E~0); 16449#L1550-1 assume !(1 == ~T12_E~0); 16693#L1555-1 assume !(1 == ~T13_E~0); 16694#L1560-1 assume !(1 == ~T14_E~0); 16983#L1565-1 assume !(1 == ~E_1~0); 18408#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17880#L1575-1 assume !(1 == ~E_3~0); 17258#L1580-1 assume !(1 == ~E_4~0); 17259#L1585-1 assume !(1 == ~E_5~0); 17732#L1590-1 assume !(1 == ~E_6~0); 17290#L1595-1 assume !(1 == ~E_7~0); 17291#L1600-1 assume !(1 == ~E_8~0); 17663#L1605-1 assume !(1 == ~E_9~0); 17664#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 18197#L1615-1 assume !(1 == ~E_11~0); 17117#L1620-1 assume !(1 == ~E_12~0); 17118#L1625-1 assume !(1 == ~E_13~0); 17913#L1630-1 assume !(1 == ~E_14~0); 17289#L1635-1 assume { :end_inline_reset_delta_events } true; 17234#L2017-2 [2022-12-13 12:47:35,456 INFO L750 eck$LassoCheckResult]: Loop: 17234#L2017-2 assume !false; 16521#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16522#L1316 assume !false; 17846#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 17908#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 16461#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 16796#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17932#L1115 assume !(0 != eval_~tmp~0#1); 17460#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17112#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17113#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17513#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18044#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17694#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17695#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18276#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18447#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18441#L1372-3 assume !(0 == ~T7_E~0); 16501#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16502#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17156#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17157#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18091#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18395#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17641#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 16794#L1412-3 assume !(0 == ~E_1~0); 16795#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17545#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17546#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18274#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17952#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17657#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17658#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16565#L1452-3 assume !(0 == ~E_9~0); 16566#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18208#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18209#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18014#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 18015#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 16792#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16793#L646-42 assume !(1 == ~m_pc~0); 17376#L646-44 is_master_triggered_~__retres1~0#1 := 0; 18246#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17242#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17243#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18379#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18179#L665-42 assume 1 == ~t1_pc~0; 18136#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18138#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18353#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16965#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16966#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18446#L684-42 assume !(1 == ~t2_pc~0); 17824#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 17823#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17574#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17575#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17584#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17720#L703-42 assume 1 == ~t3_pc~0; 17923#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17924#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17987#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17988#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18021#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17624#L722-42 assume 1 == ~t4_pc~0; 17625#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18057#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18053#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17105#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17106#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18414#L741-42 assume !(1 == ~t5_pc~0); 18033#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 17479#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17480#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17651#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17393#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17394#L760-42 assume !(1 == ~t6_pc~0); 17520#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 17670#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16883#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16884#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 17348#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17349#L779-42 assume 1 == ~t7_pc~0; 18198#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18144#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17678#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17679#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16892#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16893#L798-42 assume !(1 == ~t8_pc~0); 16513#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 16514#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17841#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17688#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16726#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16727#L817-42 assume 1 == ~t9_pc~0; 17486#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17003#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17004#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18142#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17947#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17948#L836-42 assume 1 == ~t10_pc~0; 18048#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17040#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17041#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17821#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18360#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18402#L855-42 assume 1 == ~t11_pc~0; 18412#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16604#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16605#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18122#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18123#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17213#L874-42 assume 1 == ~t12_pc~0; 17214#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17439#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17629#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17630#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 16766#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16767#L893-42 assume !(1 == ~t13_pc~0); 17760#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 17761#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17179#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17180#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 17139#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 17140#L912-42 assume !(1 == ~t14_pc~0); 17955#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 16471#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 16472#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17248#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 16889#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16890#L1495-3 assume !(1 == ~M_E~0); 17491#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17938#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18034#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17111#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17072#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17073#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17745#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17964#L1530-3 assume !(1 == ~T8_E~0); 16924#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16925#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16961#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18237#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18344#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17363#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 17364#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17994#L1570-3 assume !(1 == ~E_2~0); 17942#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17943#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18307#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18348#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18394#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17768#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17769#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18251#L1610-3 assume !(1 == ~E_10~0); 17121#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17122#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17733#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17734#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 17628#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 17056#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 16678#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 16867#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 16868#L2036 assume !(0 == start_simulation_~tmp~3#1); 17965#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 18128#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 17277#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 16517#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 16518#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 17671#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18295#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18296#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 17234#L2017-2 [2022-12-13 12:47:35,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:35,457 INFO L85 PathProgramCache]: Analyzing trace with hash -723156570, now seen corresponding path program 1 times [2022-12-13 12:47:35,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:35,457 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [693611598] [2022-12-13 12:47:35,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:35,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:35,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:35,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:35,507 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:35,507 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [693611598] [2022-12-13 12:47:35,507 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [693611598] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:35,507 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:35,507 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:35,507 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [752549535] [2022-12-13 12:47:35,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:35,508 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:35,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:35,508 INFO L85 PathProgramCache]: Analyzing trace with hash 727650346, now seen corresponding path program 1 times [2022-12-13 12:47:35,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:35,508 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022767498] [2022-12-13 12:47:35,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:35,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:35,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:35,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:35,565 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:35,565 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1022767498] [2022-12-13 12:47:35,565 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1022767498] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:35,565 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:35,565 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:35,565 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [544937161] [2022-12-13 12:47:35,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:35,565 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:35,566 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:35,566 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:35,566 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:35,566 INFO L87 Difference]: Start difference. First operand 2047 states and 3031 transitions. cyclomatic complexity: 985 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:35,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:35,595 INFO L93 Difference]: Finished difference Result 2047 states and 3030 transitions. [2022-12-13 12:47:35,595 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3030 transitions. [2022-12-13 12:47:35,602 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:35,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3030 transitions. [2022-12-13 12:47:35,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:35,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:35,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3030 transitions. [2022-12-13 12:47:35,610 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:35,610 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2022-12-13 12:47:35,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3030 transitions. [2022-12-13 12:47:35,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:35,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4802149487054226) internal successors, (3030), 2046 states have internal predecessors, (3030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:35,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3030 transitions. [2022-12-13 12:47:35,633 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2022-12-13 12:47:35,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:35,634 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2022-12-13 12:47:35,634 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 12:47:35,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3030 transitions. [2022-12-13 12:47:35,639 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:35,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:35,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:35,641 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:35,641 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:35,641 INFO L748 eck$LassoCheckResult]: Stem: 20873#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 20874#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 21792#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21793#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22554#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 21397#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21398#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21117#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21118#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22365#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21689#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21690#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22230#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21595#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21596#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21029#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21030#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21364#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21549#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 20616#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20617#L1342 assume !(0 == ~M_E~0); 20783#L1342-2 assume !(0 == ~T1_E~0); 21333#L1347-1 assume !(0 == ~T2_E~0); 22346#L1352-1 assume !(0 == ~T3_E~0); 22138#L1357-1 assume !(0 == ~T4_E~0); 21355#L1362-1 assume !(0 == ~T5_E~0); 21356#L1367-1 assume !(0 == ~T6_E~0); 20948#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20949#L1377-1 assume !(0 == ~T8_E~0); 21278#L1382-1 assume !(0 == ~T9_E~0); 21279#L1387-1 assume !(0 == ~T10_E~0); 22019#L1392-1 assume !(0 == ~T11_E~0); 21317#L1397-1 assume !(0 == ~T12_E~0); 21318#L1402-1 assume !(0 == ~T13_E~0); 20970#L1407-1 assume !(0 == ~T14_E~0); 20971#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 22264#L1417-1 assume !(0 == ~E_2~0); 22265#L1422-1 assume !(0 == ~E_3~0); 22500#L1427-1 assume !(0 == ~E_4~0); 21146#L1432-1 assume !(0 == ~E_5~0); 21147#L1437-1 assume !(0 == ~E_6~0); 22182#L1442-1 assume !(0 == ~E_7~0); 22183#L1447-1 assume !(0 == ~E_8~0); 22013#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 20752#L1457-1 assume !(0 == ~E_10~0); 20753#L1462-1 assume !(0 == ~E_11~0); 22212#L1467-1 assume !(0 == ~E_12~0); 22225#L1472-1 assume !(0 == ~E_13~0); 22226#L1477-1 assume !(0 == ~E_14~0); 21960#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20937#L646 assume 1 == ~m_pc~0; 20938#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21604#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21619#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21031#L1666 assume !(0 != activate_threads_~tmp~1#1); 21032#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22521#L665 assume !(1 == ~t1_pc~0); 21500#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21501#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22110#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22111#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 21841#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21842#L684 assume 1 == ~t2_pc~0; 21957#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21881#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21017#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21018#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 22351#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22534#L703 assume !(1 == ~t3_pc~0); 21171#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21172#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22098#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20588#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 20589#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21059#L722 assume 1 == ~t4_pc~0; 21799#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21243#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20699#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20700#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 21640#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20784#L741 assume 1 == ~t5_pc~0; 20785#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21081#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21875#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21927#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 21928#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21334#L760 assume !(1 == ~t6_pc~0); 21170#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21169#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21009#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21010#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21756#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21757#L779 assume 1 == ~t7_pc~0; 20821#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20670#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20671#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22383#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 21093#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21094#L798 assume !(1 == ~t8_pc~0); 22393#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22311#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22312#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22476#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 22523#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20649#L817 assume 1 == ~t9_pc~0; 20650#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21433#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21063#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21064#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 21043#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21044#L836 assume !(1 == ~t10_pc~0); 21065#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20995#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20996#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21244#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 21245#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22324#L855 assume 1 == ~t11_pc~0; 21615#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21616#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22206#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22010#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 21847#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20934#L874 assume !(1 == ~t12_pc~0); 20935#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21102#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20638#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20639#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 20624#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20625#L893 assume 1 == ~t13_pc~0; 22458#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 20973#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21277#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22407#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 22398#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 22399#L912 assume 1 == ~t14_pc~0; 22189#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 22190#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 22261#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 20871#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 20872#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21633#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 22068#L1495-2 assume !(1 == ~T1_E~0); 22069#L1500-1 assume !(1 == ~T2_E~0); 21750#L1505-1 assume !(1 == ~T3_E~0); 21751#L1510-1 assume !(1 == ~T4_E~0); 21809#L1515-1 assume !(1 == ~T5_E~0); 21810#L1520-1 assume !(1 == ~T6_E~0); 22394#L1525-1 assume !(1 == ~T7_E~0); 22099#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21036#L1535-1 assume !(1 == ~T9_E~0); 21037#L1540-1 assume !(1 == ~T10_E~0); 20549#L1545-1 assume !(1 == ~T11_E~0); 20550#L1550-1 assume !(1 == ~T12_E~0); 20794#L1555-1 assume !(1 == ~T13_E~0); 20795#L1560-1 assume !(1 == ~T14_E~0); 21084#L1565-1 assume !(1 == ~E_1~0); 22509#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 21981#L1575-1 assume !(1 == ~E_3~0); 21359#L1580-1 assume !(1 == ~E_4~0); 21360#L1585-1 assume !(1 == ~E_5~0); 21833#L1590-1 assume !(1 == ~E_6~0); 21391#L1595-1 assume !(1 == ~E_7~0); 21392#L1600-1 assume !(1 == ~E_8~0); 21764#L1605-1 assume !(1 == ~E_9~0); 21765#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22298#L1615-1 assume !(1 == ~E_11~0); 21218#L1620-1 assume !(1 == ~E_12~0); 21219#L1625-1 assume !(1 == ~E_13~0); 22014#L1630-1 assume !(1 == ~E_14~0); 21390#L1635-1 assume { :end_inline_reset_delta_events } true; 21335#L2017-2 [2022-12-13 12:47:35,642 INFO L750 eck$LassoCheckResult]: Loop: 21335#L2017-2 assume !false; 20622#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20623#L1316 assume !false; 21947#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22009#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20562#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 20897#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22033#L1115 assume !(0 != eval_~tmp~0#1); 21561#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21213#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21214#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21614#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22145#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21795#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21796#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22377#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22548#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22542#L1372-3 assume !(0 == ~T7_E~0); 20602#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20603#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21257#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21258#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22192#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22496#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21742#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 20895#L1412-3 assume !(0 == ~E_1~0); 20896#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21646#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21647#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22375#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22053#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21758#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21759#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20666#L1452-3 assume !(0 == ~E_9~0); 20667#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22309#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22310#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22115#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22116#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 20893#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20894#L646-42 assume 1 == ~m_pc~0; 21476#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 22347#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21343#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21344#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22480#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22280#L665-42 assume 1 == ~t1_pc~0; 22237#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22239#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22454#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21066#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21067#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22547#L684-42 assume 1 == ~t2_pc~0; 21923#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21924#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21675#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21676#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21685#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21821#L703-42 assume 1 == ~t3_pc~0; 22024#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22025#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22088#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22089#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22122#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21725#L722-42 assume 1 == ~t4_pc~0; 21726#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22158#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22154#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21206#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21207#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22515#L741-42 assume !(1 == ~t5_pc~0); 22134#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 21580#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21581#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21752#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21494#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21495#L760-42 assume !(1 == ~t6_pc~0); 21621#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 21771#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20984#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20985#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 21449#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21450#L779-42 assume !(1 == ~t7_pc~0); 22244#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 22245#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21779#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21780#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20993#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20994#L798-42 assume 1 == ~t8_pc~0; 21442#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20615#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21942#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21789#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20827#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20828#L817-42 assume 1 == ~t9_pc~0; 21587#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21104#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21105#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22243#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22048#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22049#L836-42 assume 1 == ~t10_pc~0; 22149#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21141#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21142#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21922#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22461#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22503#L855-42 assume 1 == ~t11_pc~0; 22513#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20705#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20706#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22223#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22224#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21314#L874-42 assume 1 == ~t12_pc~0; 21315#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 21540#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21730#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21731#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20867#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20868#L893-42 assume !(1 == ~t13_pc~0); 21861#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 21862#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21280#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21281#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 21240#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 21241#L912-42 assume 1 == ~t14_pc~0; 22497#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 20572#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 20573#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21349#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 20990#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20991#L1495-3 assume !(1 == ~M_E~0); 21592#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22039#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22135#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21212#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21173#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21174#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21846#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22065#L1530-3 assume !(1 == ~T8_E~0); 21025#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21026#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21062#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22338#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22445#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21464#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 21465#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22095#L1570-3 assume !(1 == ~E_2~0); 22043#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22044#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22408#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22449#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22495#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21869#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21870#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22352#L1610-3 assume !(1 == ~E_10~0); 21222#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21223#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21834#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21835#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 21729#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 21157#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20779#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 20968#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 20969#L2036 assume !(0 == start_simulation_~tmp~3#1); 22066#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22229#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 21378#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 20618#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 20619#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 21772#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22396#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22397#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 21335#L2017-2 [2022-12-13 12:47:35,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:35,642 INFO L85 PathProgramCache]: Analyzing trace with hash -1293428376, now seen corresponding path program 1 times [2022-12-13 12:47:35,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:35,642 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584810111] [2022-12-13 12:47:35,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:35,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:35,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:35,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:35,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:35,675 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584810111] [2022-12-13 12:47:35,675 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [584810111] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:35,675 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:35,676 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:35,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1747721794] [2022-12-13 12:47:35,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:35,676 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:35,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:35,676 INFO L85 PathProgramCache]: Analyzing trace with hash 1564313997, now seen corresponding path program 1 times [2022-12-13 12:47:35,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:35,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1426119949] [2022-12-13 12:47:35,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:35,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:35,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:35,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:35,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:35,720 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1426119949] [2022-12-13 12:47:35,720 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1426119949] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:35,720 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:35,721 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:35,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [176471342] [2022-12-13 12:47:35,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:35,721 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:35,721 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:35,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:35,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:35,722 INFO L87 Difference]: Start difference. First operand 2047 states and 3030 transitions. cyclomatic complexity: 984 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:35,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:35,763 INFO L93 Difference]: Finished difference Result 2047 states and 3029 transitions. [2022-12-13 12:47:35,763 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3029 transitions. [2022-12-13 12:47:35,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:35,777 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3029 transitions. [2022-12-13 12:47:35,777 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:35,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:35,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3029 transitions. [2022-12-13 12:47:35,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:35,781 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2022-12-13 12:47:35,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3029 transitions. [2022-12-13 12:47:35,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:35,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4797264289203713) internal successors, (3029), 2046 states have internal predecessors, (3029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:35,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3029 transitions. [2022-12-13 12:47:35,810 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2022-12-13 12:47:35,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:35,811 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2022-12-13 12:47:35,811 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 12:47:35,812 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3029 transitions. [2022-12-13 12:47:35,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:35,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:35,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:35,820 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:35,821 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:35,821 INFO L748 eck$LassoCheckResult]: Stem: 24974#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 24975#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 25893#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25894#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26655#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 25498#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25499#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25218#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25219#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26466#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25790#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25791#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26331#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25696#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25697#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25130#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25131#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25465#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25650#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 24717#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24718#L1342 assume !(0 == ~M_E~0); 24884#L1342-2 assume !(0 == ~T1_E~0); 25434#L1347-1 assume !(0 == ~T2_E~0); 26447#L1352-1 assume !(0 == ~T3_E~0); 26239#L1357-1 assume !(0 == ~T4_E~0); 25456#L1362-1 assume !(0 == ~T5_E~0); 25457#L1367-1 assume !(0 == ~T6_E~0); 25049#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25050#L1377-1 assume !(0 == ~T8_E~0); 25379#L1382-1 assume !(0 == ~T9_E~0); 25380#L1387-1 assume !(0 == ~T10_E~0); 26120#L1392-1 assume !(0 == ~T11_E~0); 25418#L1397-1 assume !(0 == ~T12_E~0); 25419#L1402-1 assume !(0 == ~T13_E~0); 25071#L1407-1 assume !(0 == ~T14_E~0); 25072#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 26365#L1417-1 assume !(0 == ~E_2~0); 26366#L1422-1 assume !(0 == ~E_3~0); 26601#L1427-1 assume !(0 == ~E_4~0); 25247#L1432-1 assume !(0 == ~E_5~0); 25248#L1437-1 assume !(0 == ~E_6~0); 26283#L1442-1 assume !(0 == ~E_7~0); 26284#L1447-1 assume !(0 == ~E_8~0); 26114#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 24853#L1457-1 assume !(0 == ~E_10~0); 24854#L1462-1 assume !(0 == ~E_11~0); 26313#L1467-1 assume !(0 == ~E_12~0); 26326#L1472-1 assume !(0 == ~E_13~0); 26327#L1477-1 assume !(0 == ~E_14~0); 26061#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25038#L646 assume 1 == ~m_pc~0; 25039#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 25705#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25720#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25132#L1666 assume !(0 != activate_threads_~tmp~1#1); 25133#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26622#L665 assume !(1 == ~t1_pc~0); 25601#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25602#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26211#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26212#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 25942#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25943#L684 assume 1 == ~t2_pc~0; 26058#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25982#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25118#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25119#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 26452#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26635#L703 assume !(1 == ~t3_pc~0); 25272#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25273#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26199#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24689#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 24690#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25160#L722 assume 1 == ~t4_pc~0; 25900#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25344#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24800#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24801#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 25741#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24885#L741 assume 1 == ~t5_pc~0; 24886#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25182#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25976#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26028#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 26029#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25435#L760 assume !(1 == ~t6_pc~0); 25271#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25270#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25110#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25111#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25857#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25858#L779 assume 1 == ~t7_pc~0; 24922#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24771#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24772#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26484#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 25194#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25195#L798 assume !(1 == ~t8_pc~0); 26494#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26412#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26413#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26577#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 26624#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24750#L817 assume 1 == ~t9_pc~0; 24751#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25534#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25164#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25165#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 25144#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25145#L836 assume !(1 == ~t10_pc~0); 25166#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25096#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25097#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25345#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 25346#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26425#L855 assume 1 == ~t11_pc~0; 25716#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25717#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26307#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26111#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 25948#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25035#L874 assume !(1 == ~t12_pc~0); 25036#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25203#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24739#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24740#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 24725#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24726#L893 assume 1 == ~t13_pc~0; 26559#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25074#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25378#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26508#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 26499#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 26500#L912 assume 1 == ~t14_pc~0; 26290#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 26291#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 26362#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 24972#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 24973#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25734#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 26169#L1495-2 assume !(1 == ~T1_E~0); 26170#L1500-1 assume !(1 == ~T2_E~0); 25851#L1505-1 assume !(1 == ~T3_E~0); 25852#L1510-1 assume !(1 == ~T4_E~0); 25910#L1515-1 assume !(1 == ~T5_E~0); 25911#L1520-1 assume !(1 == ~T6_E~0); 26495#L1525-1 assume !(1 == ~T7_E~0); 26200#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25137#L1535-1 assume !(1 == ~T9_E~0); 25138#L1540-1 assume !(1 == ~T10_E~0); 24650#L1545-1 assume !(1 == ~T11_E~0); 24651#L1550-1 assume !(1 == ~T12_E~0); 24895#L1555-1 assume !(1 == ~T13_E~0); 24896#L1560-1 assume !(1 == ~T14_E~0); 25185#L1565-1 assume !(1 == ~E_1~0); 26610#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 26082#L1575-1 assume !(1 == ~E_3~0); 25460#L1580-1 assume !(1 == ~E_4~0); 25461#L1585-1 assume !(1 == ~E_5~0); 25934#L1590-1 assume !(1 == ~E_6~0); 25492#L1595-1 assume !(1 == ~E_7~0); 25493#L1600-1 assume !(1 == ~E_8~0); 25865#L1605-1 assume !(1 == ~E_9~0); 25866#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26399#L1615-1 assume !(1 == ~E_11~0); 25319#L1620-1 assume !(1 == ~E_12~0); 25320#L1625-1 assume !(1 == ~E_13~0); 26115#L1630-1 assume !(1 == ~E_14~0); 25491#L1635-1 assume { :end_inline_reset_delta_events } true; 25436#L2017-2 [2022-12-13 12:47:35,821 INFO L750 eck$LassoCheckResult]: Loop: 25436#L2017-2 assume !false; 24723#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24724#L1316 assume !false; 26048#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26110#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 24663#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 24998#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26134#L1115 assume !(0 != eval_~tmp~0#1); 25662#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25314#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25315#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25715#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26246#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25896#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25897#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26478#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26649#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26643#L1372-3 assume !(0 == ~T7_E~0); 24703#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24704#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25358#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25359#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26293#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 26597#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25843#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 24996#L1412-3 assume !(0 == ~E_1~0); 24997#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25747#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25748#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26476#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26154#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25859#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25860#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24767#L1452-3 assume !(0 == ~E_9~0); 24768#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26410#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26411#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 26216#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 26217#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 24994#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24995#L646-42 assume 1 == ~m_pc~0; 25577#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 26448#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25444#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25445#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26581#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26381#L665-42 assume 1 == ~t1_pc~0; 26338#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26340#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26555#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25167#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25168#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26648#L684-42 assume 1 == ~t2_pc~0; 26024#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26025#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25776#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25777#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25786#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25922#L703-42 assume 1 == ~t3_pc~0; 26125#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26126#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26189#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26190#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26223#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25826#L722-42 assume 1 == ~t4_pc~0; 25827#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26259#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26255#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25307#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25308#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26616#L741-42 assume 1 == ~t5_pc~0; 26560#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25681#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25682#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25853#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25595#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25596#L760-42 assume !(1 == ~t6_pc~0); 25722#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 25872#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25085#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25086#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 25550#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25551#L779-42 assume 1 == ~t7_pc~0; 26400#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26346#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25880#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25881#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25094#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25095#L798-42 assume 1 == ~t8_pc~0; 25543#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24716#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26043#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25890#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24928#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24929#L817-42 assume 1 == ~t9_pc~0; 25688#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25205#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25206#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26344#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26149#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26150#L836-42 assume 1 == ~t10_pc~0; 26250#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25242#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25243#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26023#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26562#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26604#L855-42 assume 1 == ~t11_pc~0; 26614#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24806#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24807#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26324#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26325#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25415#L874-42 assume 1 == ~t12_pc~0; 25416#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25641#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25831#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25832#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24968#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24969#L893-42 assume !(1 == ~t13_pc~0); 25962#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 25963#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25381#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25382#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 25341#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 25342#L912-42 assume 1 == ~t14_pc~0; 26598#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 24673#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 24674#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 25450#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 25091#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25092#L1495-3 assume !(1 == ~M_E~0); 25693#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26140#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26236#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25313#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25274#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25275#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25947#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26166#L1530-3 assume !(1 == ~T8_E~0); 25126#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25127#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25163#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26439#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26546#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 25565#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 25566#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26196#L1570-3 assume !(1 == ~E_2~0); 26144#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26145#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26509#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26550#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26596#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25970#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25971#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 26453#L1610-3 assume !(1 == ~E_10~0); 25323#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25324#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25935#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25936#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 25830#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 25258#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 24880#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 25069#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 25070#L2036 assume !(0 == start_simulation_~tmp~3#1); 26167#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26330#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 25479#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 24719#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 24720#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 25873#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26497#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26498#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 25436#L2017-2 [2022-12-13 12:47:35,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:35,822 INFO L85 PathProgramCache]: Analyzing trace with hash 1597669734, now seen corresponding path program 1 times [2022-12-13 12:47:35,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:35,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [639178930] [2022-12-13 12:47:35,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:35,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:35,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:35,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:35,864 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:35,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [639178930] [2022-12-13 12:47:35,864 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [639178930] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:35,864 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:35,864 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:35,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1824539501] [2022-12-13 12:47:35,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:35,865 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:35,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:35,865 INFO L85 PathProgramCache]: Analyzing trace with hash -828233649, now seen corresponding path program 1 times [2022-12-13 12:47:35,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:35,865 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717708513] [2022-12-13 12:47:35,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:35,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:35,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:35,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:35,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:35,909 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1717708513] [2022-12-13 12:47:35,909 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1717708513] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:35,909 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:35,909 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:35,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764412492] [2022-12-13 12:47:35,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:35,910 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:35,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:35,910 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:35,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:35,911 INFO L87 Difference]: Start difference. First operand 2047 states and 3029 transitions. cyclomatic complexity: 983 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:35,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:35,934 INFO L93 Difference]: Finished difference Result 2047 states and 3028 transitions. [2022-12-13 12:47:35,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3028 transitions. [2022-12-13 12:47:35,940 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:35,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3028 transitions. [2022-12-13 12:47:35,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:35,946 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:35,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3028 transitions. [2022-12-13 12:47:35,947 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:35,947 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2022-12-13 12:47:35,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3028 transitions. [2022-12-13 12:47:35,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:35,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.47923790913532) internal successors, (3028), 2046 states have internal predecessors, (3028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:35,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3028 transitions. [2022-12-13 12:47:35,970 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2022-12-13 12:47:35,971 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:35,971 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2022-12-13 12:47:35,971 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 12:47:35,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3028 transitions. [2022-12-13 12:47:35,976 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:35,976 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:35,976 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:35,977 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:35,977 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:35,978 INFO L748 eck$LassoCheckResult]: Stem: 29075#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 29076#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 29994#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29995#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30756#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 29599#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29600#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29319#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29320#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30567#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29891#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29892#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30432#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29797#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29798#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29231#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29232#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29566#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29751#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 28818#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28819#L1342 assume !(0 == ~M_E~0); 28985#L1342-2 assume !(0 == ~T1_E~0); 29535#L1347-1 assume !(0 == ~T2_E~0); 30548#L1352-1 assume !(0 == ~T3_E~0); 30340#L1357-1 assume !(0 == ~T4_E~0); 29557#L1362-1 assume !(0 == ~T5_E~0); 29558#L1367-1 assume !(0 == ~T6_E~0); 29150#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29151#L1377-1 assume !(0 == ~T8_E~0); 29480#L1382-1 assume !(0 == ~T9_E~0); 29481#L1387-1 assume !(0 == ~T10_E~0); 30221#L1392-1 assume !(0 == ~T11_E~0); 29519#L1397-1 assume !(0 == ~T12_E~0); 29520#L1402-1 assume !(0 == ~T13_E~0); 29172#L1407-1 assume !(0 == ~T14_E~0); 29173#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 30466#L1417-1 assume !(0 == ~E_2~0); 30467#L1422-1 assume !(0 == ~E_3~0); 30702#L1427-1 assume !(0 == ~E_4~0); 29348#L1432-1 assume !(0 == ~E_5~0); 29349#L1437-1 assume !(0 == ~E_6~0); 30384#L1442-1 assume !(0 == ~E_7~0); 30385#L1447-1 assume !(0 == ~E_8~0); 30215#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 28954#L1457-1 assume !(0 == ~E_10~0); 28955#L1462-1 assume !(0 == ~E_11~0); 30414#L1467-1 assume !(0 == ~E_12~0); 30427#L1472-1 assume !(0 == ~E_13~0); 30428#L1477-1 assume !(0 == ~E_14~0); 30162#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29139#L646 assume 1 == ~m_pc~0; 29140#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 29806#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29821#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29233#L1666 assume !(0 != activate_threads_~tmp~1#1); 29234#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30723#L665 assume !(1 == ~t1_pc~0); 29702#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29703#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30312#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30313#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 30043#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30044#L684 assume 1 == ~t2_pc~0; 30159#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30083#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29219#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29220#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 30553#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30736#L703 assume !(1 == ~t3_pc~0); 29373#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29374#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30300#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28790#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 28791#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29261#L722 assume 1 == ~t4_pc~0; 30001#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29445#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28901#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28902#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 29842#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28986#L741 assume 1 == ~t5_pc~0; 28987#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29283#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30077#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30129#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 30130#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29536#L760 assume !(1 == ~t6_pc~0); 29372#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29371#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29211#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29212#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29958#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29959#L779 assume 1 == ~t7_pc~0; 29023#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28872#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28873#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30585#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 29295#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29296#L798 assume !(1 == ~t8_pc~0); 30595#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30513#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30514#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30678#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 30725#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28851#L817 assume 1 == ~t9_pc~0; 28852#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29635#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29265#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29266#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 29245#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29246#L836 assume !(1 == ~t10_pc~0); 29267#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29197#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29198#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29446#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 29447#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30526#L855 assume 1 == ~t11_pc~0; 29817#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29818#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30408#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30212#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 30049#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29136#L874 assume !(1 == ~t12_pc~0); 29137#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29304#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28840#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28841#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 28826#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28827#L893 assume 1 == ~t13_pc~0; 30660#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29175#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29479#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30609#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 30600#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 30601#L912 assume 1 == ~t14_pc~0; 30391#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 30392#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 30463#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29073#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 29074#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29835#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 30270#L1495-2 assume !(1 == ~T1_E~0); 30271#L1500-1 assume !(1 == ~T2_E~0); 29952#L1505-1 assume !(1 == ~T3_E~0); 29953#L1510-1 assume !(1 == ~T4_E~0); 30011#L1515-1 assume !(1 == ~T5_E~0); 30012#L1520-1 assume !(1 == ~T6_E~0); 30596#L1525-1 assume !(1 == ~T7_E~0); 30301#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29238#L1535-1 assume !(1 == ~T9_E~0); 29239#L1540-1 assume !(1 == ~T10_E~0); 28751#L1545-1 assume !(1 == ~T11_E~0); 28752#L1550-1 assume !(1 == ~T12_E~0); 28996#L1555-1 assume !(1 == ~T13_E~0); 28997#L1560-1 assume !(1 == ~T14_E~0); 29286#L1565-1 assume !(1 == ~E_1~0); 30711#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30183#L1575-1 assume !(1 == ~E_3~0); 29561#L1580-1 assume !(1 == ~E_4~0); 29562#L1585-1 assume !(1 == ~E_5~0); 30035#L1590-1 assume !(1 == ~E_6~0); 29593#L1595-1 assume !(1 == ~E_7~0); 29594#L1600-1 assume !(1 == ~E_8~0); 29966#L1605-1 assume !(1 == ~E_9~0); 29967#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30500#L1615-1 assume !(1 == ~E_11~0); 29420#L1620-1 assume !(1 == ~E_12~0); 29421#L1625-1 assume !(1 == ~E_13~0); 30216#L1630-1 assume !(1 == ~E_14~0); 29592#L1635-1 assume { :end_inline_reset_delta_events } true; 29537#L2017-2 [2022-12-13 12:47:35,978 INFO L750 eck$LassoCheckResult]: Loop: 29537#L2017-2 assume !false; 28824#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28825#L1316 assume !false; 30149#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30211#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 28764#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 29099#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30235#L1115 assume !(0 != eval_~tmp~0#1); 29763#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29415#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29416#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29816#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30347#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29997#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29998#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30579#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30750#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30744#L1372-3 assume !(0 == ~T7_E~0); 28804#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28805#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29459#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29460#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 30394#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 30698#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29944#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 29097#L1412-3 assume !(0 == ~E_1~0); 29098#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29848#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29849#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30577#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30255#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29960#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29961#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28868#L1452-3 assume !(0 == ~E_9~0); 28869#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30511#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30512#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 30317#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30318#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 29095#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29096#L646-42 assume 1 == ~m_pc~0; 29678#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30549#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29545#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29546#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30682#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30482#L665-42 assume 1 == ~t1_pc~0; 30439#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30441#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30656#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29268#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29269#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30749#L684-42 assume 1 == ~t2_pc~0; 30125#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30126#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29877#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29878#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29887#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30023#L703-42 assume 1 == ~t3_pc~0; 30226#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30227#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30290#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30291#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30324#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29927#L722-42 assume 1 == ~t4_pc~0; 29928#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30360#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30356#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29408#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29409#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30717#L741-42 assume !(1 == ~t5_pc~0); 30336#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 29782#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29783#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29954#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29696#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29697#L760-42 assume 1 == ~t6_pc~0; 29824#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29973#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29186#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29187#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 29651#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29652#L779-42 assume 1 == ~t7_pc~0; 30501#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30447#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29981#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29982#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29195#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29196#L798-42 assume !(1 == ~t8_pc~0); 28816#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 28817#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30144#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29991#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29029#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29030#L817-42 assume 1 == ~t9_pc~0; 29789#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29306#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29307#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30445#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30250#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30251#L836-42 assume !(1 == ~t10_pc~0); 30352#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 29343#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29344#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30124#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30663#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30705#L855-42 assume 1 == ~t11_pc~0; 30715#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28907#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28908#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30425#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30426#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29516#L874-42 assume 1 == ~t12_pc~0; 29517#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29742#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29932#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29933#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29069#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29070#L893-42 assume 1 == ~t13_pc~0; 30276#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 30064#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29482#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29483#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 29442#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 29443#L912-42 assume !(1 == ~t14_pc~0); 30258#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 28774#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 28775#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29551#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 29192#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29193#L1495-3 assume !(1 == ~M_E~0); 29794#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30241#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30337#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29414#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29375#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29376#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30048#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30267#L1530-3 assume !(1 == ~T8_E~0); 29227#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29228#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29264#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30540#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30647#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29666#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 29667#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30297#L1570-3 assume !(1 == ~E_2~0); 30245#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30246#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30610#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30651#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30697#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30071#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30072#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30554#L1610-3 assume !(1 == ~E_10~0); 29424#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29425#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30036#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 30037#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 29931#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 29359#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 28981#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 29170#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 29171#L2036 assume !(0 == start_simulation_~tmp~3#1); 30268#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30431#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 29580#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 28820#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 28821#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 29974#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30598#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30599#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 29537#L2017-2 [2022-12-13 12:47:35,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:35,978 INFO L85 PathProgramCache]: Analyzing trace with hash -1911299672, now seen corresponding path program 1 times [2022-12-13 12:47:35,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:35,978 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984573589] [2022-12-13 12:47:35,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:35,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:35,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:36,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:36,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:36,028 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984573589] [2022-12-13 12:47:36,028 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [984573589] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:36,028 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:36,028 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:36,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1476211160] [2022-12-13 12:47:36,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:36,029 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:36,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:36,030 INFO L85 PathProgramCache]: Analyzing trace with hash 1635876109, now seen corresponding path program 1 times [2022-12-13 12:47:36,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:36,030 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1958511654] [2022-12-13 12:47:36,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:36,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:36,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:36,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:36,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:36,091 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1958511654] [2022-12-13 12:47:36,091 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1958511654] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:36,091 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:36,091 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:36,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [637371906] [2022-12-13 12:47:36,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:36,092 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:36,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:36,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:36,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:36,092 INFO L87 Difference]: Start difference. First operand 2047 states and 3028 transitions. cyclomatic complexity: 982 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:36,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:36,127 INFO L93 Difference]: Finished difference Result 2047 states and 3027 transitions. [2022-12-13 12:47:36,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3027 transitions. [2022-12-13 12:47:36,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:36,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3027 transitions. [2022-12-13 12:47:36,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:36,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:36,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3027 transitions. [2022-12-13 12:47:36,148 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:36,148 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2022-12-13 12:47:36,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3027 transitions. [2022-12-13 12:47:36,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:36,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4787493893502688) internal successors, (3027), 2046 states have internal predecessors, (3027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:36,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3027 transitions. [2022-12-13 12:47:36,183 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2022-12-13 12:47:36,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:36,184 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2022-12-13 12:47:36,184 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 12:47:36,184 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3027 transitions. [2022-12-13 12:47:36,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:36,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:36,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:36,194 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:36,194 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:36,194 INFO L748 eck$LassoCheckResult]: Stem: 33176#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 33177#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 34095#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34096#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34857#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 33700#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33701#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33420#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33421#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34668#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33992#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33993#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34533#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33898#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33899#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33332#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33333#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33667#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33852#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 32919#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32920#L1342 assume !(0 == ~M_E~0); 33086#L1342-2 assume !(0 == ~T1_E~0); 33636#L1347-1 assume !(0 == ~T2_E~0); 34649#L1352-1 assume !(0 == ~T3_E~0); 34441#L1357-1 assume !(0 == ~T4_E~0); 33658#L1362-1 assume !(0 == ~T5_E~0); 33659#L1367-1 assume !(0 == ~T6_E~0); 33251#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33252#L1377-1 assume !(0 == ~T8_E~0); 33581#L1382-1 assume !(0 == ~T9_E~0); 33582#L1387-1 assume !(0 == ~T10_E~0); 34322#L1392-1 assume !(0 == ~T11_E~0); 33620#L1397-1 assume !(0 == ~T12_E~0); 33621#L1402-1 assume !(0 == ~T13_E~0); 33273#L1407-1 assume !(0 == ~T14_E~0); 33274#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 34567#L1417-1 assume !(0 == ~E_2~0); 34568#L1422-1 assume !(0 == ~E_3~0); 34803#L1427-1 assume !(0 == ~E_4~0); 33449#L1432-1 assume !(0 == ~E_5~0); 33450#L1437-1 assume !(0 == ~E_6~0); 34485#L1442-1 assume !(0 == ~E_7~0); 34486#L1447-1 assume !(0 == ~E_8~0); 34316#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 33055#L1457-1 assume !(0 == ~E_10~0); 33056#L1462-1 assume !(0 == ~E_11~0); 34515#L1467-1 assume !(0 == ~E_12~0); 34528#L1472-1 assume !(0 == ~E_13~0); 34529#L1477-1 assume !(0 == ~E_14~0); 34263#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33240#L646 assume 1 == ~m_pc~0; 33241#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33907#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33922#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33334#L1666 assume !(0 != activate_threads_~tmp~1#1); 33335#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34824#L665 assume !(1 == ~t1_pc~0); 33803#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33804#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34413#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34414#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 34144#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34145#L684 assume 1 == ~t2_pc~0; 34260#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34184#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33320#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33321#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 34654#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34837#L703 assume !(1 == ~t3_pc~0); 33474#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33475#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34401#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32891#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 32892#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33362#L722 assume 1 == ~t4_pc~0; 34102#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33546#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33002#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33003#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 33943#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33087#L741 assume 1 == ~t5_pc~0; 33088#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33384#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34178#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34230#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 34231#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33637#L760 assume !(1 == ~t6_pc~0); 33473#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33472#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33312#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33313#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34059#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34060#L779 assume 1 == ~t7_pc~0; 33124#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32973#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32974#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34686#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 33396#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33397#L798 assume !(1 == ~t8_pc~0); 34696#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34614#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34615#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34779#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 34826#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32952#L817 assume 1 == ~t9_pc~0; 32953#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33736#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33366#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33367#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 33346#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33347#L836 assume !(1 == ~t10_pc~0); 33368#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33298#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33299#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33547#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 33548#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34627#L855 assume 1 == ~t11_pc~0; 33918#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33919#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34509#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34313#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 34150#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33237#L874 assume !(1 == ~t12_pc~0); 33238#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33405#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32941#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32942#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 32927#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32928#L893 assume 1 == ~t13_pc~0; 34761#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33276#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33580#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34710#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 34701#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 34702#L912 assume 1 == ~t14_pc~0; 34492#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 34493#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 34564#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33174#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 33175#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33936#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 34371#L1495-2 assume !(1 == ~T1_E~0); 34372#L1500-1 assume !(1 == ~T2_E~0); 34053#L1505-1 assume !(1 == ~T3_E~0); 34054#L1510-1 assume !(1 == ~T4_E~0); 34112#L1515-1 assume !(1 == ~T5_E~0); 34113#L1520-1 assume !(1 == ~T6_E~0); 34697#L1525-1 assume !(1 == ~T7_E~0); 34402#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33339#L1535-1 assume !(1 == ~T9_E~0); 33340#L1540-1 assume !(1 == ~T10_E~0); 32852#L1545-1 assume !(1 == ~T11_E~0); 32853#L1550-1 assume !(1 == ~T12_E~0); 33097#L1555-1 assume !(1 == ~T13_E~0); 33098#L1560-1 assume !(1 == ~T14_E~0); 33387#L1565-1 assume !(1 == ~E_1~0); 34812#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 34284#L1575-1 assume !(1 == ~E_3~0); 33662#L1580-1 assume !(1 == ~E_4~0); 33663#L1585-1 assume !(1 == ~E_5~0); 34136#L1590-1 assume !(1 == ~E_6~0); 33694#L1595-1 assume !(1 == ~E_7~0); 33695#L1600-1 assume !(1 == ~E_8~0); 34067#L1605-1 assume !(1 == ~E_9~0); 34068#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 34601#L1615-1 assume !(1 == ~E_11~0); 33521#L1620-1 assume !(1 == ~E_12~0); 33522#L1625-1 assume !(1 == ~E_13~0); 34317#L1630-1 assume !(1 == ~E_14~0); 33693#L1635-1 assume { :end_inline_reset_delta_events } true; 33638#L2017-2 [2022-12-13 12:47:36,194 INFO L750 eck$LassoCheckResult]: Loop: 33638#L2017-2 assume !false; 32925#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32926#L1316 assume !false; 34250#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34312#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 32865#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33200#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34336#L1115 assume !(0 != eval_~tmp~0#1); 33864#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33516#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33517#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33917#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34448#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34098#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34099#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34680#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34851#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34845#L1372-3 assume !(0 == ~T7_E~0); 32905#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32906#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33560#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33561#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34495#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 34799#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34045#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 33198#L1412-3 assume !(0 == ~E_1~0); 33199#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33949#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33950#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34678#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34356#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34061#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34062#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32969#L1452-3 assume !(0 == ~E_9~0); 32970#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34612#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34613#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 34418#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 34419#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 33196#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33197#L646-42 assume 1 == ~m_pc~0; 33779#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34650#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33646#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33647#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34783#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34583#L665-42 assume 1 == ~t1_pc~0; 34540#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34542#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34757#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33369#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33370#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34850#L684-42 assume 1 == ~t2_pc~0; 34226#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34227#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33978#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33979#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33988#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34124#L703-42 assume 1 == ~t3_pc~0; 34327#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34328#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34391#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34392#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34425#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34028#L722-42 assume 1 == ~t4_pc~0; 34029#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34461#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34457#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33509#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33510#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34818#L741-42 assume !(1 == ~t5_pc~0); 34437#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 33883#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33884#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34055#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33797#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33798#L760-42 assume !(1 == ~t6_pc~0); 33924#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 34074#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33287#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33288#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 33752#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33753#L779-42 assume !(1 == ~t7_pc~0); 34547#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 34548#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34082#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34083#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33296#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33297#L798-42 assume 1 == ~t8_pc~0; 33745#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32918#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34245#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34092#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33130#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33131#L817-42 assume 1 == ~t9_pc~0; 33890#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33407#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33408#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34546#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34351#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34352#L836-42 assume 1 == ~t10_pc~0; 34452#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33444#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33445#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34225#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34764#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34806#L855-42 assume 1 == ~t11_pc~0; 34816#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33008#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33009#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34526#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34527#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33617#L874-42 assume 1 == ~t12_pc~0; 33618#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 33846#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34033#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34034#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33170#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33171#L893-42 assume !(1 == ~t13_pc~0); 34164#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 34165#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33583#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33584#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 33543#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 33544#L912-42 assume 1 == ~t14_pc~0; 34800#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 32875#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 32876#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33652#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 33293#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33294#L1495-3 assume !(1 == ~M_E~0); 33895#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34342#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34438#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33515#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33476#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33477#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34149#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34368#L1530-3 assume !(1 == ~T8_E~0); 33328#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33329#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33365#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34641#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 34748#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 33767#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 33768#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34398#L1570-3 assume !(1 == ~E_2~0); 34346#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34347#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34711#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34752#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34798#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34172#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34173#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34655#L1610-3 assume !(1 == ~E_10~0); 33525#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33526#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 34137#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 34138#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 34032#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 33460#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33082#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33271#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 33272#L2036 assume !(0 == start_simulation_~tmp~3#1); 34369#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34532#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33681#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 32921#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 32922#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 34075#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34699#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34700#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 33638#L2017-2 [2022-12-13 12:47:36,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:36,195 INFO L85 PathProgramCache]: Analyzing trace with hash 1716285734, now seen corresponding path program 1 times [2022-12-13 12:47:36,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:36,195 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565808667] [2022-12-13 12:47:36,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:36,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:36,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:36,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:36,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:36,242 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565808667] [2022-12-13 12:47:36,242 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1565808667] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:36,242 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:36,242 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:36,242 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2032653956] [2022-12-13 12:47:36,242 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:36,243 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:36,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:36,243 INFO L85 PathProgramCache]: Analyzing trace with hash 1564313997, now seen corresponding path program 2 times [2022-12-13 12:47:36,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:36,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1155487409] [2022-12-13 12:47:36,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:36,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:36,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:36,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:36,305 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:36,305 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1155487409] [2022-12-13 12:47:36,305 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1155487409] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:36,305 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:36,305 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:36,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [581223967] [2022-12-13 12:47:36,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:36,306 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:36,306 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:36,306 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:36,306 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:36,306 INFO L87 Difference]: Start difference. First operand 2047 states and 3027 transitions. cyclomatic complexity: 981 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:36,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:36,337 INFO L93 Difference]: Finished difference Result 2047 states and 3026 transitions. [2022-12-13 12:47:36,337 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3026 transitions. [2022-12-13 12:47:36,345 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:36,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3026 transitions. [2022-12-13 12:47:36,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:36,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:36,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3026 transitions. [2022-12-13 12:47:36,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:36,358 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2022-12-13 12:47:36,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3026 transitions. [2022-12-13 12:47:36,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:36,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4782608695652173) internal successors, (3026), 2046 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:36,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3026 transitions. [2022-12-13 12:47:36,392 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2022-12-13 12:47:36,393 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:36,393 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2022-12-13 12:47:36,394 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 12:47:36,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3026 transitions. [2022-12-13 12:47:36,401 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:36,401 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:36,401 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:36,403 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:36,404 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:36,404 INFO L748 eck$LassoCheckResult]: Stem: 37277#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 37278#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 38196#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38197#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38958#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 37801#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37802#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37521#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37522#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38769#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38093#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38094#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38634#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37999#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38000#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37433#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37434#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37768#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37953#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 37020#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37021#L1342 assume !(0 == ~M_E~0); 37187#L1342-2 assume !(0 == ~T1_E~0); 37737#L1347-1 assume !(0 == ~T2_E~0); 38750#L1352-1 assume !(0 == ~T3_E~0); 38542#L1357-1 assume !(0 == ~T4_E~0); 37759#L1362-1 assume !(0 == ~T5_E~0); 37760#L1367-1 assume !(0 == ~T6_E~0); 37352#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37353#L1377-1 assume !(0 == ~T8_E~0); 37682#L1382-1 assume !(0 == ~T9_E~0); 37683#L1387-1 assume !(0 == ~T10_E~0); 38423#L1392-1 assume !(0 == ~T11_E~0); 37721#L1397-1 assume !(0 == ~T12_E~0); 37722#L1402-1 assume !(0 == ~T13_E~0); 37374#L1407-1 assume !(0 == ~T14_E~0); 37375#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 38668#L1417-1 assume !(0 == ~E_2~0); 38669#L1422-1 assume !(0 == ~E_3~0); 38904#L1427-1 assume !(0 == ~E_4~0); 37550#L1432-1 assume !(0 == ~E_5~0); 37551#L1437-1 assume !(0 == ~E_6~0); 38586#L1442-1 assume !(0 == ~E_7~0); 38587#L1447-1 assume !(0 == ~E_8~0); 38417#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 37156#L1457-1 assume !(0 == ~E_10~0); 37157#L1462-1 assume !(0 == ~E_11~0); 38616#L1467-1 assume !(0 == ~E_12~0); 38629#L1472-1 assume !(0 == ~E_13~0); 38630#L1477-1 assume !(0 == ~E_14~0); 38364#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37341#L646 assume 1 == ~m_pc~0; 37342#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38008#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38023#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37435#L1666 assume !(0 != activate_threads_~tmp~1#1); 37436#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38925#L665 assume !(1 == ~t1_pc~0); 37904#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37905#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38514#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38515#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 38245#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38246#L684 assume 1 == ~t2_pc~0; 38361#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38285#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37421#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37422#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 38755#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38938#L703 assume !(1 == ~t3_pc~0); 37575#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37576#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38502#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36992#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 36993#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37463#L722 assume 1 == ~t4_pc~0; 38203#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37647#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37103#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37104#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 38044#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37188#L741 assume 1 == ~t5_pc~0; 37189#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37485#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38279#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38331#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 38332#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37738#L760 assume !(1 == ~t6_pc~0); 37574#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37573#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37413#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37414#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38160#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38161#L779 assume 1 == ~t7_pc~0; 37225#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37074#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37075#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38787#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 37497#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37498#L798 assume !(1 == ~t8_pc~0); 38797#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 38715#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38716#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38880#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 38927#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37053#L817 assume 1 == ~t9_pc~0; 37054#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37837#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37467#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37468#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 37447#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37448#L836 assume !(1 == ~t10_pc~0); 37469#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37399#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37400#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37648#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 37649#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38728#L855 assume 1 == ~t11_pc~0; 38019#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38020#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38610#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38414#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 38251#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37338#L874 assume !(1 == ~t12_pc~0); 37339#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37506#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37042#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37043#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 37028#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37029#L893 assume 1 == ~t13_pc~0; 38862#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37377#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37681#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38811#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 38802#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 38803#L912 assume 1 == ~t14_pc~0; 38593#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 38594#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 38665#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37275#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 37276#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38037#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 38472#L1495-2 assume !(1 == ~T1_E~0); 38473#L1500-1 assume !(1 == ~T2_E~0); 38154#L1505-1 assume !(1 == ~T3_E~0); 38155#L1510-1 assume !(1 == ~T4_E~0); 38213#L1515-1 assume !(1 == ~T5_E~0); 38214#L1520-1 assume !(1 == ~T6_E~0); 38798#L1525-1 assume !(1 == ~T7_E~0); 38503#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37440#L1535-1 assume !(1 == ~T9_E~0); 37441#L1540-1 assume !(1 == ~T10_E~0); 36953#L1545-1 assume !(1 == ~T11_E~0); 36954#L1550-1 assume !(1 == ~T12_E~0); 37198#L1555-1 assume !(1 == ~T13_E~0); 37199#L1560-1 assume !(1 == ~T14_E~0); 37488#L1565-1 assume !(1 == ~E_1~0); 38913#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 38385#L1575-1 assume !(1 == ~E_3~0); 37763#L1580-1 assume !(1 == ~E_4~0); 37764#L1585-1 assume !(1 == ~E_5~0); 38237#L1590-1 assume !(1 == ~E_6~0); 37795#L1595-1 assume !(1 == ~E_7~0); 37796#L1600-1 assume !(1 == ~E_8~0); 38168#L1605-1 assume !(1 == ~E_9~0); 38169#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 38702#L1615-1 assume !(1 == ~E_11~0); 37622#L1620-1 assume !(1 == ~E_12~0); 37623#L1625-1 assume !(1 == ~E_13~0); 38418#L1630-1 assume !(1 == ~E_14~0); 37794#L1635-1 assume { :end_inline_reset_delta_events } true; 37739#L2017-2 [2022-12-13 12:47:36,404 INFO L750 eck$LassoCheckResult]: Loop: 37739#L2017-2 assume !false; 37026#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37027#L1316 assume !false; 38351#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38413#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 36966#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37301#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38437#L1115 assume !(0 != eval_~tmp~0#1); 37965#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37617#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37618#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38018#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38549#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38199#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38200#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38781#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38952#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38946#L1372-3 assume !(0 == ~T7_E~0); 37006#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37007#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37661#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37662#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38596#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38900#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38146#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 37299#L1412-3 assume !(0 == ~E_1~0); 37300#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38050#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38051#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38779#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38457#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38162#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38163#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37070#L1452-3 assume !(0 == ~E_9~0); 37071#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38713#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38714#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 38519#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38520#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 37297#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37298#L646-42 assume 1 == ~m_pc~0; 37880#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38751#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37747#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37748#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38884#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38684#L665-42 assume 1 == ~t1_pc~0; 38641#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38643#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38858#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37470#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37471#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38951#L684-42 assume 1 == ~t2_pc~0; 38327#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38328#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38079#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38080#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38089#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38225#L703-42 assume 1 == ~t3_pc~0; 38428#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38429#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38492#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38493#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38526#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38129#L722-42 assume 1 == ~t4_pc~0; 38130#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38562#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38558#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37610#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37611#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38919#L741-42 assume !(1 == ~t5_pc~0); 38538#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 37984#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37985#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38156#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37898#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37899#L760-42 assume !(1 == ~t6_pc~0); 38025#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 38175#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37388#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37389#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 37853#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37854#L779-42 assume !(1 == ~t7_pc~0); 38648#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 38649#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38183#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38184#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37397#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37398#L798-42 assume 1 == ~t8_pc~0; 37846#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37019#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38346#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38193#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37231#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37232#L817-42 assume 1 == ~t9_pc~0; 37991#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37508#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37509#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38647#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38452#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38453#L836-42 assume 1 == ~t10_pc~0; 38553#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37545#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37546#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38326#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38865#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38907#L855-42 assume 1 == ~t11_pc~0; 38917#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37109#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37110#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38627#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38628#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37718#L874-42 assume 1 == ~t12_pc~0; 37719#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37947#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38134#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38135#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37271#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37272#L893-42 assume !(1 == ~t13_pc~0); 38265#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 38266#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37684#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37685#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 37644#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 37645#L912-42 assume 1 == ~t14_pc~0; 38901#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 36976#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 36977#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37753#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 37394#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37395#L1495-3 assume !(1 == ~M_E~0); 37996#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38443#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38539#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37616#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37577#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37578#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38250#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38469#L1530-3 assume !(1 == ~T8_E~0); 37429#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37430#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37466#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38742#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38849#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 37868#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 37869#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38499#L1570-3 assume !(1 == ~E_2~0); 38447#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38448#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38812#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38853#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38899#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38273#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38274#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38756#L1610-3 assume !(1 == ~E_10~0); 37626#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37627#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38238#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 38239#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 38133#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 37561#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37183#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37372#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 37373#L2036 assume !(0 == start_simulation_~tmp~3#1); 38470#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38633#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37782#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37022#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 37023#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 38176#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38800#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38801#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 37739#L2017-2 [2022-12-13 12:47:36,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:36,405 INFO L85 PathProgramCache]: Analyzing trace with hash -383452696, now seen corresponding path program 1 times [2022-12-13 12:47:36,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:36,405 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [820058891] [2022-12-13 12:47:36,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:36,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:36,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:36,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:36,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:36,449 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [820058891] [2022-12-13 12:47:36,449 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [820058891] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:36,450 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:36,450 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:36,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [375060114] [2022-12-13 12:47:36,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:36,450 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:36,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:36,451 INFO L85 PathProgramCache]: Analyzing trace with hash 1564313997, now seen corresponding path program 3 times [2022-12-13 12:47:36,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:36,451 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683555123] [2022-12-13 12:47:36,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:36,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:36,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:36,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:36,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:36,509 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683555123] [2022-12-13 12:47:36,510 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1683555123] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:36,510 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:36,510 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:36,510 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1044096081] [2022-12-13 12:47:36,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:36,511 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:36,511 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:36,511 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:36,511 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:36,511 INFO L87 Difference]: Start difference. First operand 2047 states and 3026 transitions. cyclomatic complexity: 980 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:36,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:36,541 INFO L93 Difference]: Finished difference Result 2047 states and 3025 transitions. [2022-12-13 12:47:36,541 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3025 transitions. [2022-12-13 12:47:36,548 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:36,555 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3025 transitions. [2022-12-13 12:47:36,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:36,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:36,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3025 transitions. [2022-12-13 12:47:36,560 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:36,560 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2022-12-13 12:47:36,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3025 transitions. [2022-12-13 12:47:36,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:36,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.477772349780166) internal successors, (3025), 2046 states have internal predecessors, (3025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:36,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3025 transitions. [2022-12-13 12:47:36,589 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2022-12-13 12:47:36,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:36,590 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2022-12-13 12:47:36,590 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 12:47:36,590 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3025 transitions. [2022-12-13 12:47:36,595 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:36,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:36,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:36,597 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:36,597 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:36,597 INFO L748 eck$LassoCheckResult]: Stem: 41378#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 41379#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 42297#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42298#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43059#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 41902#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41903#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41622#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41623#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42870#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42194#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42195#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42735#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42100#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42101#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41534#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41535#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41869#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42054#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 41121#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41122#L1342 assume !(0 == ~M_E~0); 41288#L1342-2 assume !(0 == ~T1_E~0); 41838#L1347-1 assume !(0 == ~T2_E~0); 42851#L1352-1 assume !(0 == ~T3_E~0); 42643#L1357-1 assume !(0 == ~T4_E~0); 41860#L1362-1 assume !(0 == ~T5_E~0); 41861#L1367-1 assume !(0 == ~T6_E~0); 41453#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41454#L1377-1 assume !(0 == ~T8_E~0); 41783#L1382-1 assume !(0 == ~T9_E~0); 41784#L1387-1 assume !(0 == ~T10_E~0); 42524#L1392-1 assume !(0 == ~T11_E~0); 41822#L1397-1 assume !(0 == ~T12_E~0); 41823#L1402-1 assume !(0 == ~T13_E~0); 41475#L1407-1 assume !(0 == ~T14_E~0); 41476#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 42769#L1417-1 assume !(0 == ~E_2~0); 42770#L1422-1 assume !(0 == ~E_3~0); 43005#L1427-1 assume !(0 == ~E_4~0); 41651#L1432-1 assume !(0 == ~E_5~0); 41652#L1437-1 assume !(0 == ~E_6~0); 42687#L1442-1 assume !(0 == ~E_7~0); 42688#L1447-1 assume !(0 == ~E_8~0); 42518#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 41257#L1457-1 assume !(0 == ~E_10~0); 41258#L1462-1 assume !(0 == ~E_11~0); 42717#L1467-1 assume !(0 == ~E_12~0); 42730#L1472-1 assume !(0 == ~E_13~0); 42731#L1477-1 assume !(0 == ~E_14~0); 42465#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41442#L646 assume 1 == ~m_pc~0; 41443#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42109#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42124#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41536#L1666 assume !(0 != activate_threads_~tmp~1#1); 41537#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43026#L665 assume !(1 == ~t1_pc~0); 42005#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42006#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42615#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42616#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 42346#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42347#L684 assume 1 == ~t2_pc~0; 42462#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42386#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41522#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41523#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 42856#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43039#L703 assume !(1 == ~t3_pc~0); 41676#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41677#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42603#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41093#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 41094#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41564#L722 assume 1 == ~t4_pc~0; 42304#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41748#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41204#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41205#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 42145#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41289#L741 assume 1 == ~t5_pc~0; 41290#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41586#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42380#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42432#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 42433#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41839#L760 assume !(1 == ~t6_pc~0); 41675#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41674#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41514#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41515#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42261#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42262#L779 assume 1 == ~t7_pc~0; 41326#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41175#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41176#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42888#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 41598#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41599#L798 assume !(1 == ~t8_pc~0); 42898#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42816#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42817#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42981#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 43028#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41154#L817 assume 1 == ~t9_pc~0; 41155#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41938#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41568#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41569#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 41548#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41549#L836 assume !(1 == ~t10_pc~0); 41570#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41500#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41501#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41749#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 41750#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42829#L855 assume 1 == ~t11_pc~0; 42120#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42121#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42711#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42515#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 42352#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41439#L874 assume !(1 == ~t12_pc~0); 41440#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 41607#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41143#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41144#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 41129#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41130#L893 assume 1 == ~t13_pc~0; 42963#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41478#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41782#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42912#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 42903#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 42904#L912 assume 1 == ~t14_pc~0; 42694#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 42695#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 42766#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 41376#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 41377#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42138#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 42573#L1495-2 assume !(1 == ~T1_E~0); 42574#L1500-1 assume !(1 == ~T2_E~0); 42255#L1505-1 assume !(1 == ~T3_E~0); 42256#L1510-1 assume !(1 == ~T4_E~0); 42314#L1515-1 assume !(1 == ~T5_E~0); 42315#L1520-1 assume !(1 == ~T6_E~0); 42899#L1525-1 assume !(1 == ~T7_E~0); 42604#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41541#L1535-1 assume !(1 == ~T9_E~0); 41542#L1540-1 assume !(1 == ~T10_E~0); 41054#L1545-1 assume !(1 == ~T11_E~0); 41055#L1550-1 assume !(1 == ~T12_E~0); 41299#L1555-1 assume !(1 == ~T13_E~0); 41300#L1560-1 assume !(1 == ~T14_E~0); 41589#L1565-1 assume !(1 == ~E_1~0); 43014#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 42486#L1575-1 assume !(1 == ~E_3~0); 41864#L1580-1 assume !(1 == ~E_4~0); 41865#L1585-1 assume !(1 == ~E_5~0); 42338#L1590-1 assume !(1 == ~E_6~0); 41896#L1595-1 assume !(1 == ~E_7~0); 41897#L1600-1 assume !(1 == ~E_8~0); 42269#L1605-1 assume !(1 == ~E_9~0); 42270#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 42803#L1615-1 assume !(1 == ~E_11~0); 41723#L1620-1 assume !(1 == ~E_12~0); 41724#L1625-1 assume !(1 == ~E_13~0); 42519#L1630-1 assume !(1 == ~E_14~0); 41895#L1635-1 assume { :end_inline_reset_delta_events } true; 41840#L2017-2 [2022-12-13 12:47:36,597 INFO L750 eck$LassoCheckResult]: Loop: 41840#L2017-2 assume !false; 41127#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41128#L1316 assume !false; 42452#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 42514#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41067#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 41402#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42538#L1115 assume !(0 != eval_~tmp~0#1); 42066#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41718#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41719#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42119#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42650#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42300#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42301#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42882#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43053#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43047#L1372-3 assume !(0 == ~T7_E~0); 41107#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41108#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41762#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41763#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 42697#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43001#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42247#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 41400#L1412-3 assume !(0 == ~E_1~0); 41401#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42151#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42152#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42880#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42558#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42263#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42264#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41171#L1452-3 assume !(0 == ~E_9~0); 41172#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42814#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 42815#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 42620#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 42621#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 41398#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41399#L646-42 assume 1 == ~m_pc~0; 41981#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42852#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41848#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41849#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42985#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42785#L665-42 assume 1 == ~t1_pc~0; 42742#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42744#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42959#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41571#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41572#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43052#L684-42 assume 1 == ~t2_pc~0; 42428#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42429#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42180#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42181#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42190#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42326#L703-42 assume 1 == ~t3_pc~0; 42529#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42530#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42593#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42594#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42627#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42230#L722-42 assume 1 == ~t4_pc~0; 42231#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42663#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42659#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41711#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41712#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43020#L741-42 assume 1 == ~t5_pc~0; 42964#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42085#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42086#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42257#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41999#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42000#L760-42 assume !(1 == ~t6_pc~0); 42126#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 42276#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41489#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41490#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 41954#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41955#L779-42 assume 1 == ~t7_pc~0; 42804#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42750#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42284#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42285#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41498#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41499#L798-42 assume 1 == ~t8_pc~0; 41947#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41120#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42447#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42294#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41332#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41333#L817-42 assume 1 == ~t9_pc~0; 42092#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41609#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41610#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42748#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42553#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42554#L836-42 assume 1 == ~t10_pc~0; 42654#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41646#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41647#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42427#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42966#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43008#L855-42 assume 1 == ~t11_pc~0; 43018#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41210#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41211#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42728#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42729#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41819#L874-42 assume 1 == ~t12_pc~0; 41820#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42048#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42235#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42236#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41372#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41373#L893-42 assume 1 == ~t13_pc~0; 42579#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 42367#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41785#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41786#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 41745#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 41746#L912-42 assume !(1 == ~t14_pc~0); 42561#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 41077#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 41078#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 41854#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 41495#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41496#L1495-3 assume !(1 == ~M_E~0); 42097#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42544#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42640#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41717#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41678#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41679#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42351#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42570#L1530-3 assume !(1 == ~T8_E~0); 41530#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41531#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41567#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42843#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42950#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 41969#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 41970#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42600#L1570-3 assume !(1 == ~E_2~0); 42548#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42549#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42913#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42955#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43000#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42374#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 42375#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42857#L1610-3 assume !(1 == ~E_10~0); 41727#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41728#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 42339#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42340#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 42234#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 41662#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41284#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 41473#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 41474#L2036 assume !(0 == start_simulation_~tmp~3#1); 42571#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 42734#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41883#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 41123#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 41124#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 42277#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42901#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 42902#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 41840#L2017-2 [2022-12-13 12:47:36,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:36,597 INFO L85 PathProgramCache]: Analyzing trace with hash -1364407510, now seen corresponding path program 1 times [2022-12-13 12:47:36,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:36,598 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740830810] [2022-12-13 12:47:36,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:36,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:36,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:36,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:36,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:36,627 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740830810] [2022-12-13 12:47:36,627 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740830810] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:36,627 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:36,627 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:36,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1107426471] [2022-12-13 12:47:36,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:36,628 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:36,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:36,628 INFO L85 PathProgramCache]: Analyzing trace with hash 501799823, now seen corresponding path program 1 times [2022-12-13 12:47:36,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:36,628 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488994977] [2022-12-13 12:47:36,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:36,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:36,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:36,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:36,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:36,683 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [488994977] [2022-12-13 12:47:36,683 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [488994977] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:36,684 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:36,684 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:36,684 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [548557880] [2022-12-13 12:47:36,684 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:36,684 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:36,684 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:36,685 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:36,685 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:36,685 INFO L87 Difference]: Start difference. First operand 2047 states and 3025 transitions. cyclomatic complexity: 979 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:36,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:36,706 INFO L93 Difference]: Finished difference Result 2047 states and 3024 transitions. [2022-12-13 12:47:36,706 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3024 transitions. [2022-12-13 12:47:36,711 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:36,715 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3024 transitions. [2022-12-13 12:47:36,715 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:36,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:36,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3024 transitions. [2022-12-13 12:47:36,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:36,718 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2022-12-13 12:47:36,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3024 transitions. [2022-12-13 12:47:36,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:36,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4772838299951148) internal successors, (3024), 2046 states have internal predecessors, (3024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:36,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3024 transitions. [2022-12-13 12:47:36,741 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2022-12-13 12:47:36,741 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:36,741 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2022-12-13 12:47:36,741 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 12:47:36,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3024 transitions. [2022-12-13 12:47:36,746 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:36,746 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:36,746 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:36,747 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:36,747 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:36,748 INFO L748 eck$LassoCheckResult]: Stem: 45479#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 45480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 46398#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46399#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47160#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 46003#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46004#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45723#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45724#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46971#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46295#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46296#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46836#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46201#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46202#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45635#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45636#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45970#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46155#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 45222#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45223#L1342 assume !(0 == ~M_E~0); 45389#L1342-2 assume !(0 == ~T1_E~0); 45939#L1347-1 assume !(0 == ~T2_E~0); 46952#L1352-1 assume !(0 == ~T3_E~0); 46744#L1357-1 assume !(0 == ~T4_E~0); 45961#L1362-1 assume !(0 == ~T5_E~0); 45962#L1367-1 assume !(0 == ~T6_E~0); 45554#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45555#L1377-1 assume !(0 == ~T8_E~0); 45884#L1382-1 assume !(0 == ~T9_E~0); 45885#L1387-1 assume !(0 == ~T10_E~0); 46625#L1392-1 assume !(0 == ~T11_E~0); 45923#L1397-1 assume !(0 == ~T12_E~0); 45924#L1402-1 assume !(0 == ~T13_E~0); 45576#L1407-1 assume !(0 == ~T14_E~0); 45577#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 46870#L1417-1 assume !(0 == ~E_2~0); 46871#L1422-1 assume !(0 == ~E_3~0); 47106#L1427-1 assume !(0 == ~E_4~0); 45752#L1432-1 assume !(0 == ~E_5~0); 45753#L1437-1 assume !(0 == ~E_6~0); 46788#L1442-1 assume !(0 == ~E_7~0); 46789#L1447-1 assume !(0 == ~E_8~0); 46619#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 45358#L1457-1 assume !(0 == ~E_10~0); 45359#L1462-1 assume !(0 == ~E_11~0); 46818#L1467-1 assume !(0 == ~E_12~0); 46831#L1472-1 assume !(0 == ~E_13~0); 46832#L1477-1 assume !(0 == ~E_14~0); 46566#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45543#L646 assume 1 == ~m_pc~0; 45544#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46210#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46225#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45637#L1666 assume !(0 != activate_threads_~tmp~1#1); 45638#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47127#L665 assume !(1 == ~t1_pc~0); 46106#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46107#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46716#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46717#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 46447#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46448#L684 assume 1 == ~t2_pc~0; 46563#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46487#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45623#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45624#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 46957#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47140#L703 assume !(1 == ~t3_pc~0); 45777#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45778#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46704#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45194#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 45195#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45665#L722 assume 1 == ~t4_pc~0; 46405#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45849#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45305#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45306#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 46246#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45390#L741 assume 1 == ~t5_pc~0; 45391#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45687#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46481#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46533#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 46534#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45940#L760 assume !(1 == ~t6_pc~0); 45776#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 45775#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45615#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45616#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46362#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46363#L779 assume 1 == ~t7_pc~0; 45427#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45276#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45277#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46989#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 45699#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45700#L798 assume !(1 == ~t8_pc~0); 46999#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46917#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46918#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47082#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 47129#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45255#L817 assume 1 == ~t9_pc~0; 45256#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46039#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45669#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45670#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 45649#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45650#L836 assume !(1 == ~t10_pc~0); 45671#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45601#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45602#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45850#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 45851#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46930#L855 assume 1 == ~t11_pc~0; 46221#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46222#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46812#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46616#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 46453#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45540#L874 assume !(1 == ~t12_pc~0); 45541#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 45708#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45244#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45245#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 45230#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45231#L893 assume 1 == ~t13_pc~0; 47064#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45579#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45883#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 47013#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 47004#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 47005#L912 assume 1 == ~t14_pc~0; 46795#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 46796#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 46867#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 45477#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 45478#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46239#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 46674#L1495-2 assume !(1 == ~T1_E~0); 46675#L1500-1 assume !(1 == ~T2_E~0); 46356#L1505-1 assume !(1 == ~T3_E~0); 46357#L1510-1 assume !(1 == ~T4_E~0); 46415#L1515-1 assume !(1 == ~T5_E~0); 46416#L1520-1 assume !(1 == ~T6_E~0); 47000#L1525-1 assume !(1 == ~T7_E~0); 46705#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45642#L1535-1 assume !(1 == ~T9_E~0); 45643#L1540-1 assume !(1 == ~T10_E~0); 45155#L1545-1 assume !(1 == ~T11_E~0); 45156#L1550-1 assume !(1 == ~T12_E~0); 45400#L1555-1 assume !(1 == ~T13_E~0); 45401#L1560-1 assume !(1 == ~T14_E~0); 45690#L1565-1 assume !(1 == ~E_1~0); 47115#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 46587#L1575-1 assume !(1 == ~E_3~0); 45965#L1580-1 assume !(1 == ~E_4~0); 45966#L1585-1 assume !(1 == ~E_5~0); 46439#L1590-1 assume !(1 == ~E_6~0); 45997#L1595-1 assume !(1 == ~E_7~0); 45998#L1600-1 assume !(1 == ~E_8~0); 46370#L1605-1 assume !(1 == ~E_9~0); 46371#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 46904#L1615-1 assume !(1 == ~E_11~0); 45824#L1620-1 assume !(1 == ~E_12~0); 45825#L1625-1 assume !(1 == ~E_13~0); 46620#L1630-1 assume !(1 == ~E_14~0); 45996#L1635-1 assume { :end_inline_reset_delta_events } true; 45941#L2017-2 [2022-12-13 12:47:36,748 INFO L750 eck$LassoCheckResult]: Loop: 45941#L2017-2 assume !false; 45228#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45229#L1316 assume !false; 46553#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46615#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45168#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45503#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46639#L1115 assume !(0 != eval_~tmp~0#1); 46167#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45819#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45820#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46220#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46751#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46401#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46402#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46983#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47154#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47148#L1372-3 assume !(0 == ~T7_E~0); 45208#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45209#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45863#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 45864#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46798#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47102#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46348#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 45501#L1412-3 assume !(0 == ~E_1~0); 45502#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46252#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46253#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46981#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46659#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46364#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46365#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45272#L1452-3 assume !(0 == ~E_9~0); 45273#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46915#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46916#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 46721#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 46722#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 45499#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45500#L646-42 assume 1 == ~m_pc~0; 46082#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46953#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45949#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45950#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47086#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46886#L665-42 assume 1 == ~t1_pc~0; 46843#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46845#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47060#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45672#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45673#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47153#L684-42 assume 1 == ~t2_pc~0; 46529#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46530#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46281#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46282#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46291#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46427#L703-42 assume 1 == ~t3_pc~0; 46630#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46631#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46694#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46695#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46728#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46331#L722-42 assume 1 == ~t4_pc~0; 46332#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46764#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46760#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45812#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45813#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47121#L741-42 assume !(1 == ~t5_pc~0); 46740#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 46186#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46187#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46358#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46100#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46101#L760-42 assume !(1 == ~t6_pc~0); 46227#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 46377#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45590#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45591#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 46055#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46056#L779-42 assume !(1 == ~t7_pc~0); 46850#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 46851#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46385#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46386#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45599#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45600#L798-42 assume 1 == ~t8_pc~0; 46048#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45221#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46548#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46395#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45433#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45434#L817-42 assume 1 == ~t9_pc~0; 46193#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45710#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45711#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46849#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46654#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46655#L836-42 assume 1 == ~t10_pc~0; 46755#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45747#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45748#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46528#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47067#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47109#L855-42 assume !(1 == ~t11_pc~0); 47120#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 45311#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45312#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46829#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46830#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45920#L874-42 assume 1 == ~t12_pc~0; 45921#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46149#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46336#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46337#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45473#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45474#L893-42 assume !(1 == ~t13_pc~0); 46467#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 46468#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45886#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45887#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 45846#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 45847#L912-42 assume !(1 == ~t14_pc~0); 46662#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 45178#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 45179#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 45955#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 45596#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45597#L1495-3 assume !(1 == ~M_E~0); 46198#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46645#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46741#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45818#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45779#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45780#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46452#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46671#L1530-3 assume !(1 == ~T8_E~0); 45631#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45632#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45668#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46944#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47051#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46070#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 46071#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46701#L1570-3 assume !(1 == ~E_2~0); 46649#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46650#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47014#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47056#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47101#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46475#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46476#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46958#L1610-3 assume !(1 == ~E_10~0); 45828#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45829#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46440#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46441#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 46335#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 45763#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45385#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45574#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 45575#L2036 assume !(0 == start_simulation_~tmp~3#1); 46672#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46835#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45984#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45224#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 45225#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 46378#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47002#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 47003#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 45941#L2017-2 [2022-12-13 12:47:36,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:36,748 INFO L85 PathProgramCache]: Analyzing trace with hash 405064104, now seen corresponding path program 1 times [2022-12-13 12:47:36,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:36,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669661998] [2022-12-13 12:47:36,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:36,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:36,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:36,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:36,777 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:36,777 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669661998] [2022-12-13 12:47:36,778 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669661998] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:36,778 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:36,778 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:36,778 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369518381] [2022-12-13 12:47:36,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:36,778 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:36,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:36,779 INFO L85 PathProgramCache]: Analyzing trace with hash 1819174155, now seen corresponding path program 1 times [2022-12-13 12:47:36,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:36,779 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170533430] [2022-12-13 12:47:36,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:36,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:36,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:36,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:36,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:36,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [170533430] [2022-12-13 12:47:36,819 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [170533430] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:36,819 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:36,819 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:36,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396795674] [2022-12-13 12:47:36,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:36,820 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:36,820 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:36,820 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:36,820 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:36,821 INFO L87 Difference]: Start difference. First operand 2047 states and 3024 transitions. cyclomatic complexity: 978 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:36,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:36,840 INFO L93 Difference]: Finished difference Result 2047 states and 3023 transitions. [2022-12-13 12:47:36,840 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3023 transitions. [2022-12-13 12:47:36,844 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:36,848 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3023 transitions. [2022-12-13 12:47:36,849 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:36,849 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:36,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3023 transitions. [2022-12-13 12:47:36,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:36,851 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2022-12-13 12:47:36,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3023 transitions. [2022-12-13 12:47:36,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:36,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4767953102100635) internal successors, (3023), 2046 states have internal predecessors, (3023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:36,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3023 transitions. [2022-12-13 12:47:36,888 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2022-12-13 12:47:36,888 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:36,889 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2022-12-13 12:47:36,889 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 12:47:36,889 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3023 transitions. [2022-12-13 12:47:36,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:36,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:36,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:36,895 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:36,896 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:36,896 INFO L748 eck$LassoCheckResult]: Stem: 49580#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 49581#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 50499#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50500#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51261#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 50104#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50105#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49824#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49825#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51072#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50396#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50397#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50937#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50302#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50303#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49736#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49737#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50071#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50256#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 49323#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49324#L1342 assume !(0 == ~M_E~0); 49490#L1342-2 assume !(0 == ~T1_E~0); 50040#L1347-1 assume !(0 == ~T2_E~0); 51053#L1352-1 assume !(0 == ~T3_E~0); 50845#L1357-1 assume !(0 == ~T4_E~0); 50062#L1362-1 assume !(0 == ~T5_E~0); 50063#L1367-1 assume !(0 == ~T6_E~0); 49655#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49656#L1377-1 assume !(0 == ~T8_E~0); 49985#L1382-1 assume !(0 == ~T9_E~0); 49986#L1387-1 assume !(0 == ~T10_E~0); 50726#L1392-1 assume !(0 == ~T11_E~0); 50024#L1397-1 assume !(0 == ~T12_E~0); 50025#L1402-1 assume !(0 == ~T13_E~0); 49677#L1407-1 assume !(0 == ~T14_E~0); 49678#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 50971#L1417-1 assume !(0 == ~E_2~0); 50972#L1422-1 assume !(0 == ~E_3~0); 51207#L1427-1 assume !(0 == ~E_4~0); 49853#L1432-1 assume !(0 == ~E_5~0); 49854#L1437-1 assume !(0 == ~E_6~0); 50889#L1442-1 assume !(0 == ~E_7~0); 50890#L1447-1 assume !(0 == ~E_8~0); 50720#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 49459#L1457-1 assume !(0 == ~E_10~0); 49460#L1462-1 assume !(0 == ~E_11~0); 50919#L1467-1 assume !(0 == ~E_12~0); 50932#L1472-1 assume !(0 == ~E_13~0); 50933#L1477-1 assume !(0 == ~E_14~0); 50667#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49644#L646 assume 1 == ~m_pc~0; 49645#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50311#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50326#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49738#L1666 assume !(0 != activate_threads_~tmp~1#1); 49739#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51228#L665 assume !(1 == ~t1_pc~0); 50207#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50208#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50817#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50818#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 50548#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50549#L684 assume 1 == ~t2_pc~0; 50664#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50588#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49724#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49725#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 51058#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51241#L703 assume !(1 == ~t3_pc~0); 49878#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49879#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50805#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49295#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 49296#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49766#L722 assume 1 == ~t4_pc~0; 50506#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49950#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49406#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49407#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 50347#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49491#L741 assume 1 == ~t5_pc~0; 49492#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49788#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50582#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50634#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 50635#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50041#L760 assume !(1 == ~t6_pc~0); 49877#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49876#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49716#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49717#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50463#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50464#L779 assume 1 == ~t7_pc~0; 49528#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49377#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49378#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51090#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 49800#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49801#L798 assume !(1 == ~t8_pc~0); 51100#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 51018#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51019#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51183#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 51230#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49356#L817 assume 1 == ~t9_pc~0; 49357#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50140#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49770#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49771#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 49750#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49751#L836 assume !(1 == ~t10_pc~0); 49772#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49702#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49703#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49951#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 49952#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51031#L855 assume 1 == ~t11_pc~0; 50322#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50323#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50913#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50717#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 50554#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49641#L874 assume !(1 == ~t12_pc~0); 49642#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 49809#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49345#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49346#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 49331#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49332#L893 assume 1 == ~t13_pc~0; 51165#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49680#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49984#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 51114#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 51105#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 51106#L912 assume 1 == ~t14_pc~0; 50896#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 50897#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 50968#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 49578#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 49579#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50340#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 50775#L1495-2 assume !(1 == ~T1_E~0); 50776#L1500-1 assume !(1 == ~T2_E~0); 50457#L1505-1 assume !(1 == ~T3_E~0); 50458#L1510-1 assume !(1 == ~T4_E~0); 50516#L1515-1 assume !(1 == ~T5_E~0); 50517#L1520-1 assume !(1 == ~T6_E~0); 51101#L1525-1 assume !(1 == ~T7_E~0); 50806#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49743#L1535-1 assume !(1 == ~T9_E~0); 49744#L1540-1 assume !(1 == ~T10_E~0); 49256#L1545-1 assume !(1 == ~T11_E~0); 49257#L1550-1 assume !(1 == ~T12_E~0); 49501#L1555-1 assume !(1 == ~T13_E~0); 49502#L1560-1 assume !(1 == ~T14_E~0); 49791#L1565-1 assume !(1 == ~E_1~0); 51216#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50688#L1575-1 assume !(1 == ~E_3~0); 50066#L1580-1 assume !(1 == ~E_4~0); 50067#L1585-1 assume !(1 == ~E_5~0); 50540#L1590-1 assume !(1 == ~E_6~0); 50098#L1595-1 assume !(1 == ~E_7~0); 50099#L1600-1 assume !(1 == ~E_8~0); 50471#L1605-1 assume !(1 == ~E_9~0); 50472#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 51005#L1615-1 assume !(1 == ~E_11~0); 49925#L1620-1 assume !(1 == ~E_12~0); 49926#L1625-1 assume !(1 == ~E_13~0); 50721#L1630-1 assume !(1 == ~E_14~0); 50097#L1635-1 assume { :end_inline_reset_delta_events } true; 50042#L2017-2 [2022-12-13 12:47:36,896 INFO L750 eck$LassoCheckResult]: Loop: 50042#L2017-2 assume !false; 49329#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49330#L1316 assume !false; 50654#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 50716#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 49269#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 49604#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 50740#L1115 assume !(0 != eval_~tmp~0#1); 50268#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49920#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49921#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50321#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50852#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50502#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50503#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51084#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51255#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51249#L1372-3 assume !(0 == ~T7_E~0); 49309#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49310#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49964#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49965#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 50899#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51203#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50449#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 49602#L1412-3 assume !(0 == ~E_1~0); 49603#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50353#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50354#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51082#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50760#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50465#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50466#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49373#L1452-3 assume !(0 == ~E_9~0); 49374#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51016#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51017#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 50822#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 50823#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 49600#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49601#L646-42 assume 1 == ~m_pc~0; 50183#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 51054#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50050#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50051#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51187#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50987#L665-42 assume 1 == ~t1_pc~0; 50944#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50946#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51161#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49773#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49774#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51254#L684-42 assume 1 == ~t2_pc~0; 50630#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50631#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50382#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50383#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50392#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50528#L703-42 assume 1 == ~t3_pc~0; 50731#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50732#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50795#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50796#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50829#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50432#L722-42 assume 1 == ~t4_pc~0; 50433#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50865#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50861#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49913#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49914#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51222#L741-42 assume !(1 == ~t5_pc~0); 50841#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 50287#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50288#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50459#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50201#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50202#L760-42 assume !(1 == ~t6_pc~0); 50328#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 50478#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49691#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49692#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 50156#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50157#L779-42 assume !(1 == ~t7_pc~0); 50951#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 50952#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50486#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50487#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49700#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49701#L798-42 assume 1 == ~t8_pc~0; 50149#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49322#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50649#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50496#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49534#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49535#L817-42 assume 1 == ~t9_pc~0; 50296#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49811#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49812#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50950#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50755#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50756#L836-42 assume 1 == ~t10_pc~0; 50856#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49848#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49849#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50629#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51168#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51210#L855-42 assume 1 == ~t11_pc~0; 51220#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49412#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49413#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50930#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50931#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50021#L874-42 assume 1 == ~t12_pc~0; 50022#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50250#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50437#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50438#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49574#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49575#L893-42 assume !(1 == ~t13_pc~0); 50568#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 50569#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49987#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49988#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 49947#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 49948#L912-42 assume 1 == ~t14_pc~0; 51204#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 49279#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 49280#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50056#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 49697#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49698#L1495-3 assume !(1 == ~M_E~0); 50299#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50746#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50842#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49919#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49880#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49881#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50553#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50772#L1530-3 assume !(1 == ~T8_E~0); 49732#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49733#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49769#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 51045#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51152#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50171#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 50172#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50802#L1570-3 assume !(1 == ~E_2~0); 50750#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50751#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51115#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51157#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51202#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50576#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50577#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51059#L1610-3 assume !(1 == ~E_10~0); 49929#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49930#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50541#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50542#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 50436#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 49864#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 49486#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 49675#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 49676#L2036 assume !(0 == start_simulation_~tmp~3#1); 50773#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 50936#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 50085#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 49325#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 49326#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 50479#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51103#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 51104#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 50042#L2017-2 [2022-12-13 12:47:36,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:36,897 INFO L85 PathProgramCache]: Analyzing trace with hash 1016333162, now seen corresponding path program 1 times [2022-12-13 12:47:36,897 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:36,897 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970530850] [2022-12-13 12:47:36,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:36,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:36,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:36,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:36,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:36,936 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970530850] [2022-12-13 12:47:36,936 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1970530850] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:36,936 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:36,936 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:36,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821760348] [2022-12-13 12:47:36,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:36,937 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:36,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:36,937 INFO L85 PathProgramCache]: Analyzing trace with hash 1564313997, now seen corresponding path program 4 times [2022-12-13 12:47:36,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:36,937 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [731529108] [2022-12-13 12:47:36,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:36,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:36,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:36,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:36,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:36,986 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [731529108] [2022-12-13 12:47:36,986 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [731529108] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:36,987 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:36,987 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:36,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402391242] [2022-12-13 12:47:36,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:36,988 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:36,988 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:36,988 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:36,988 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:36,988 INFO L87 Difference]: Start difference. First operand 2047 states and 3023 transitions. cyclomatic complexity: 977 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:37,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:37,015 INFO L93 Difference]: Finished difference Result 2047 states and 3022 transitions. [2022-12-13 12:47:37,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3022 transitions. [2022-12-13 12:47:37,020 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:37,023 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3022 transitions. [2022-12-13 12:47:37,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:37,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:37,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3022 transitions. [2022-12-13 12:47:37,026 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:37,026 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2022-12-13 12:47:37,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3022 transitions. [2022-12-13 12:47:37,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:37,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4763067904250122) internal successors, (3022), 2046 states have internal predecessors, (3022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:37,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3022 transitions. [2022-12-13 12:47:37,047 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2022-12-13 12:47:37,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:37,048 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2022-12-13 12:47:37,048 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 12:47:37,048 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3022 transitions. [2022-12-13 12:47:37,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:37,053 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:37,053 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:37,054 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:37,055 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:37,055 INFO L748 eck$LassoCheckResult]: Stem: 53681#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 53682#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 54600#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54601#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55362#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 54205#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54206#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53925#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53926#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55173#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54497#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54498#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55038#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54403#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54404#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53837#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53838#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54172#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 54357#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 53424#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53425#L1342 assume !(0 == ~M_E~0); 53591#L1342-2 assume !(0 == ~T1_E~0); 54141#L1347-1 assume !(0 == ~T2_E~0); 55154#L1352-1 assume !(0 == ~T3_E~0); 54946#L1357-1 assume !(0 == ~T4_E~0); 54163#L1362-1 assume !(0 == ~T5_E~0); 54164#L1367-1 assume !(0 == ~T6_E~0); 53756#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53757#L1377-1 assume !(0 == ~T8_E~0); 54086#L1382-1 assume !(0 == ~T9_E~0); 54087#L1387-1 assume !(0 == ~T10_E~0); 54827#L1392-1 assume !(0 == ~T11_E~0); 54125#L1397-1 assume !(0 == ~T12_E~0); 54126#L1402-1 assume !(0 == ~T13_E~0); 53778#L1407-1 assume !(0 == ~T14_E~0); 53779#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 55072#L1417-1 assume !(0 == ~E_2~0); 55073#L1422-1 assume !(0 == ~E_3~0); 55308#L1427-1 assume !(0 == ~E_4~0); 53954#L1432-1 assume !(0 == ~E_5~0); 53955#L1437-1 assume !(0 == ~E_6~0); 54990#L1442-1 assume !(0 == ~E_7~0); 54991#L1447-1 assume !(0 == ~E_8~0); 54821#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 53560#L1457-1 assume !(0 == ~E_10~0); 53561#L1462-1 assume !(0 == ~E_11~0); 55020#L1467-1 assume !(0 == ~E_12~0); 55033#L1472-1 assume !(0 == ~E_13~0); 55034#L1477-1 assume !(0 == ~E_14~0); 54768#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53745#L646 assume 1 == ~m_pc~0; 53746#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 54412#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54427#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53839#L1666 assume !(0 != activate_threads_~tmp~1#1); 53840#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55329#L665 assume !(1 == ~t1_pc~0); 54308#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54309#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54918#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54919#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 54649#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54650#L684 assume 1 == ~t2_pc~0; 54765#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54689#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53825#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53826#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 55159#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55342#L703 assume !(1 == ~t3_pc~0); 53979#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53980#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54906#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53396#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 53397#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53867#L722 assume 1 == ~t4_pc~0; 54607#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54051#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53507#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53508#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 54448#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53592#L741 assume 1 == ~t5_pc~0; 53593#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53889#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54683#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54735#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 54736#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54142#L760 assume !(1 == ~t6_pc~0); 53978#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 53977#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53817#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53818#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54564#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54565#L779 assume 1 == ~t7_pc~0; 53629#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53478#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53479#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55191#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 53901#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53902#L798 assume !(1 == ~t8_pc~0); 55201#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 55119#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55120#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55284#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 55331#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53457#L817 assume 1 == ~t9_pc~0; 53458#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54241#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53871#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53872#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 53851#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53852#L836 assume !(1 == ~t10_pc~0); 53873#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53803#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53804#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54052#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 54053#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55132#L855 assume 1 == ~t11_pc~0; 54423#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54424#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55014#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54818#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 54655#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53742#L874 assume !(1 == ~t12_pc~0); 53743#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53910#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53446#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53447#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 53432#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53433#L893 assume 1 == ~t13_pc~0; 55266#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53781#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54085#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 55215#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 55206#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 55207#L912 assume 1 == ~t14_pc~0; 54997#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 54998#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 55069#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 53679#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 53680#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54441#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 54876#L1495-2 assume !(1 == ~T1_E~0); 54877#L1500-1 assume !(1 == ~T2_E~0); 54558#L1505-1 assume !(1 == ~T3_E~0); 54559#L1510-1 assume !(1 == ~T4_E~0); 54617#L1515-1 assume !(1 == ~T5_E~0); 54618#L1520-1 assume !(1 == ~T6_E~0); 55202#L1525-1 assume !(1 == ~T7_E~0); 54907#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53844#L1535-1 assume !(1 == ~T9_E~0); 53845#L1540-1 assume !(1 == ~T10_E~0); 53357#L1545-1 assume !(1 == ~T11_E~0); 53358#L1550-1 assume !(1 == ~T12_E~0); 53602#L1555-1 assume !(1 == ~T13_E~0); 53603#L1560-1 assume !(1 == ~T14_E~0); 53892#L1565-1 assume !(1 == ~E_1~0); 55317#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 54789#L1575-1 assume !(1 == ~E_3~0); 54167#L1580-1 assume !(1 == ~E_4~0); 54168#L1585-1 assume !(1 == ~E_5~0); 54641#L1590-1 assume !(1 == ~E_6~0); 54199#L1595-1 assume !(1 == ~E_7~0); 54200#L1600-1 assume !(1 == ~E_8~0); 54572#L1605-1 assume !(1 == ~E_9~0); 54573#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 55106#L1615-1 assume !(1 == ~E_11~0); 54026#L1620-1 assume !(1 == ~E_12~0); 54027#L1625-1 assume !(1 == ~E_13~0); 54822#L1630-1 assume !(1 == ~E_14~0); 54198#L1635-1 assume { :end_inline_reset_delta_events } true; 54143#L2017-2 [2022-12-13 12:47:37,055 INFO L750 eck$LassoCheckResult]: Loop: 54143#L2017-2 assume !false; 53430#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53431#L1316 assume !false; 54755#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 54817#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53370#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 53705#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 54841#L1115 assume !(0 != eval_~tmp~0#1); 54369#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54021#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54022#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54422#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54953#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54603#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54604#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55185#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55356#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55350#L1372-3 assume !(0 == ~T7_E~0); 53410#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53411#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54065#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54066#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 55000#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 55304#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 54550#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 53703#L1412-3 assume !(0 == ~E_1~0); 53704#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54454#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54455#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55183#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54861#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54566#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54567#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53474#L1452-3 assume !(0 == ~E_9~0); 53475#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55117#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55118#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 54923#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54924#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 53701#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53702#L646-42 assume 1 == ~m_pc~0; 54284#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 55155#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54151#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54152#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55288#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55088#L665-42 assume 1 == ~t1_pc~0; 55045#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55047#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55262#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53874#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53875#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55355#L684-42 assume 1 == ~t2_pc~0; 54731#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54732#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54483#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54484#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54493#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54629#L703-42 assume 1 == ~t3_pc~0; 54832#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54833#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54896#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54897#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54930#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54533#L722-42 assume 1 == ~t4_pc~0; 54534#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54966#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54962#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54014#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54015#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55323#L741-42 assume 1 == ~t5_pc~0; 55267#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54388#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54389#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54560#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54302#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54303#L760-42 assume !(1 == ~t6_pc~0); 54429#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 54579#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53792#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53793#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 54257#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54258#L779-42 assume 1 == ~t7_pc~0; 55107#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55053#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54587#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54588#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53801#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53802#L798-42 assume 1 == ~t8_pc~0; 54250#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53423#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54750#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54597#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53635#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53636#L817-42 assume 1 == ~t9_pc~0; 54397#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53912#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53913#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55051#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54856#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54857#L836-42 assume 1 == ~t10_pc~0; 54957#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53949#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53950#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54730#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55269#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55311#L855-42 assume 1 == ~t11_pc~0; 55321#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53513#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53514#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55031#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 55032#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54122#L874-42 assume 1 == ~t12_pc~0; 54123#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54351#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54538#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54539#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53675#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53676#L893-42 assume 1 == ~t13_pc~0; 54882#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54670#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54088#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54089#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 54048#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 54049#L912-42 assume !(1 == ~t14_pc~0); 54864#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 53380#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 53381#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54157#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 53798#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53799#L1495-3 assume !(1 == ~M_E~0); 54400#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54847#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54943#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54020#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53981#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53982#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54654#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54873#L1530-3 assume !(1 == ~T8_E~0); 53833#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53834#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53870#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 55146#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55253#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54272#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 54273#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54903#L1570-3 assume !(1 == ~E_2~0); 54851#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54852#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55216#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55258#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 55303#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54677#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 54678#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 55160#L1610-3 assume !(1 == ~E_10~0); 54030#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54031#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54642#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54643#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 54537#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 53965#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53587#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 53776#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 53777#L2036 assume !(0 == start_simulation_~tmp~3#1); 54874#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 55037#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 54186#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 53426#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 53427#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 54580#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55204#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 55205#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 54143#L2017-2 [2022-12-13 12:47:37,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:37,056 INFO L85 PathProgramCache]: Analyzing trace with hash -1873442456, now seen corresponding path program 1 times [2022-12-13 12:47:37,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:37,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1951809811] [2022-12-13 12:47:37,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:37,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:37,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:37,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:37,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:37,084 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1951809811] [2022-12-13 12:47:37,084 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1951809811] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:37,084 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:37,084 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:37,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174941664] [2022-12-13 12:47:37,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:37,085 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:37,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:37,085 INFO L85 PathProgramCache]: Analyzing trace with hash 501799823, now seen corresponding path program 2 times [2022-12-13 12:47:37,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:37,086 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748238931] [2022-12-13 12:47:37,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:37,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:37,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:37,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:37,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:37,122 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1748238931] [2022-12-13 12:47:37,122 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1748238931] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:37,122 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:37,122 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:37,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [915584456] [2022-12-13 12:47:37,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:37,123 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:37,123 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:37,123 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:37,124 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:37,124 INFO L87 Difference]: Start difference. First operand 2047 states and 3022 transitions. cyclomatic complexity: 976 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:37,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:37,144 INFO L93 Difference]: Finished difference Result 2047 states and 3021 transitions. [2022-12-13 12:47:37,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3021 transitions. [2022-12-13 12:47:37,149 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:37,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3021 transitions. [2022-12-13 12:47:37,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-12-13 12:47:37,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-12-13 12:47:37,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3021 transitions. [2022-12-13 12:47:37,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:37,155 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2022-12-13 12:47:37,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3021 transitions. [2022-12-13 12:47:37,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-12-13 12:47:37,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.475818270639961) internal successors, (3021), 2046 states have internal predecessors, (3021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:37,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3021 transitions. [2022-12-13 12:47:37,175 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2022-12-13 12:47:37,176 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:37,176 INFO L428 stractBuchiCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2022-12-13 12:47:37,176 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 12:47:37,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3021 transitions. [2022-12-13 12:47:37,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-12-13 12:47:37,181 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:37,181 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:37,183 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:37,183 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:37,183 INFO L748 eck$LassoCheckResult]: Stem: 57782#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 57783#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 58701#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 58702#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59463#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 58306#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58307#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58026#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58027#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59274#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58598#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58599#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59139#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 58504#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58505#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 57938#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 57939#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 58273#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 58458#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 57525#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57526#L1342 assume !(0 == ~M_E~0); 57692#L1342-2 assume !(0 == ~T1_E~0); 58242#L1347-1 assume !(0 == ~T2_E~0); 59255#L1352-1 assume !(0 == ~T3_E~0); 59047#L1357-1 assume !(0 == ~T4_E~0); 58264#L1362-1 assume !(0 == ~T5_E~0); 58265#L1367-1 assume !(0 == ~T6_E~0); 57857#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 57858#L1377-1 assume !(0 == ~T8_E~0); 58187#L1382-1 assume !(0 == ~T9_E~0); 58188#L1387-1 assume !(0 == ~T10_E~0); 58928#L1392-1 assume !(0 == ~T11_E~0); 58226#L1397-1 assume !(0 == ~T12_E~0); 58227#L1402-1 assume !(0 == ~T13_E~0); 57879#L1407-1 assume !(0 == ~T14_E~0); 57880#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 59173#L1417-1 assume !(0 == ~E_2~0); 59174#L1422-1 assume !(0 == ~E_3~0); 59409#L1427-1 assume !(0 == ~E_4~0); 58055#L1432-1 assume !(0 == ~E_5~0); 58056#L1437-1 assume !(0 == ~E_6~0); 59091#L1442-1 assume !(0 == ~E_7~0); 59092#L1447-1 assume !(0 == ~E_8~0); 58922#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 57661#L1457-1 assume !(0 == ~E_10~0); 57662#L1462-1 assume !(0 == ~E_11~0); 59121#L1467-1 assume !(0 == ~E_12~0); 59134#L1472-1 assume !(0 == ~E_13~0); 59135#L1477-1 assume !(0 == ~E_14~0); 58869#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57846#L646 assume 1 == ~m_pc~0; 57847#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58513#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58528#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57940#L1666 assume !(0 != activate_threads_~tmp~1#1); 57941#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59430#L665 assume !(1 == ~t1_pc~0); 58409#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58410#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59019#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59020#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 58750#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58751#L684 assume 1 == ~t2_pc~0; 58866#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58790#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57926#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57927#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 59260#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59443#L703 assume !(1 == ~t3_pc~0); 58080#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 58081#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59007#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57497#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 57498#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57968#L722 assume 1 == ~t4_pc~0; 58708#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58152#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57608#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57609#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 58549#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57693#L741 assume 1 == ~t5_pc~0; 57694#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 57990#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58784#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58836#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 58837#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58243#L760 assume !(1 == ~t6_pc~0); 58079#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 58078#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57918#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57919#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58665#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58666#L779 assume 1 == ~t7_pc~0; 57730#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57579#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57580#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59292#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 58002#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58003#L798 assume !(1 == ~t8_pc~0); 59302#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 59220#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59221#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59385#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 59432#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57558#L817 assume 1 == ~t9_pc~0; 57559#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58342#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57972#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 57973#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 57952#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57953#L836 assume !(1 == ~t10_pc~0); 57974#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 57904#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57905#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58153#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 58154#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59233#L855 assume 1 == ~t11_pc~0; 58524#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58525#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59115#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58919#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 58756#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57843#L874 assume !(1 == ~t12_pc~0); 57844#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 58011#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57547#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57548#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 57533#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 57534#L893 assume 1 == ~t13_pc~0; 59367#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 57882#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58186#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59316#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 59307#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 59308#L912 assume 1 == ~t14_pc~0; 59098#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 59099#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 59170#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 57780#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 57781#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58542#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 58977#L1495-2 assume !(1 == ~T1_E~0); 58978#L1500-1 assume !(1 == ~T2_E~0); 58659#L1505-1 assume !(1 == ~T3_E~0); 58660#L1510-1 assume !(1 == ~T4_E~0); 58718#L1515-1 assume !(1 == ~T5_E~0); 58719#L1520-1 assume !(1 == ~T6_E~0); 59303#L1525-1 assume !(1 == ~T7_E~0); 59008#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57945#L1535-1 assume !(1 == ~T9_E~0); 57946#L1540-1 assume !(1 == ~T10_E~0); 57458#L1545-1 assume !(1 == ~T11_E~0); 57459#L1550-1 assume !(1 == ~T12_E~0); 57703#L1555-1 assume !(1 == ~T13_E~0); 57704#L1560-1 assume !(1 == ~T14_E~0); 57993#L1565-1 assume !(1 == ~E_1~0); 59418#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 58890#L1575-1 assume !(1 == ~E_3~0); 58268#L1580-1 assume !(1 == ~E_4~0); 58269#L1585-1 assume !(1 == ~E_5~0); 58742#L1590-1 assume !(1 == ~E_6~0); 58300#L1595-1 assume !(1 == ~E_7~0); 58301#L1600-1 assume !(1 == ~E_8~0); 58673#L1605-1 assume !(1 == ~E_9~0); 58674#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 59207#L1615-1 assume !(1 == ~E_11~0); 58127#L1620-1 assume !(1 == ~E_12~0); 58128#L1625-1 assume !(1 == ~E_13~0); 58923#L1630-1 assume !(1 == ~E_14~0); 58299#L1635-1 assume { :end_inline_reset_delta_events } true; 58244#L2017-2 [2022-12-13 12:47:37,183 INFO L750 eck$LassoCheckResult]: Loop: 58244#L2017-2 assume !false; 57531#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57532#L1316 assume !false; 58856#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 58918#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 57471#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 57806#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 58942#L1115 assume !(0 != eval_~tmp~0#1); 58470#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58122#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58123#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 58523#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59054#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58704#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58705#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59286#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59457#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 59451#L1372-3 assume !(0 == ~T7_E~0); 57511#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57512#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 58166#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58167#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 59101#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59405#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 58651#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 57804#L1412-3 assume !(0 == ~E_1~0); 57805#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58555#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58556#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 59284#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 58962#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 58667#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 58668#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57575#L1452-3 assume !(0 == ~E_9~0); 57576#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59218#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 59219#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 59024#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 59025#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 57802#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57803#L646-42 assume 1 == ~m_pc~0; 58385#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 59256#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58252#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58253#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59389#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59189#L665-42 assume 1 == ~t1_pc~0; 59146#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59148#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59363#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57975#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57976#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59456#L684-42 assume 1 == ~t2_pc~0; 58832#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58833#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58584#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58585#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58594#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58730#L703-42 assume 1 == ~t3_pc~0; 58933#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58934#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58997#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58998#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59031#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58634#L722-42 assume 1 == ~t4_pc~0; 58635#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59067#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59063#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58115#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58116#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59424#L741-42 assume !(1 == ~t5_pc~0); 59043#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 58489#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58490#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58661#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58403#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58404#L760-42 assume !(1 == ~t6_pc~0); 58530#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 58680#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57893#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57894#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 58358#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58359#L779-42 assume !(1 == ~t7_pc~0); 59153#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 59154#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58688#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58689#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 57902#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57903#L798-42 assume !(1 == ~t8_pc~0); 57523#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 57524#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58851#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58698#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57736#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57737#L817-42 assume 1 == ~t9_pc~0; 58498#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58013#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58014#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59152#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 58957#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58958#L836-42 assume 1 == ~t10_pc~0; 59058#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58050#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58051#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58831#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59370#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59412#L855-42 assume 1 == ~t11_pc~0; 59422#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 57614#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57615#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59132#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 59133#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58223#L874-42 assume 1 == ~t12_pc~0; 58224#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58452#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58639#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58640#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 57776#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 57777#L893-42 assume !(1 == ~t13_pc~0); 58770#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 58771#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58189#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 58190#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 58149#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 58150#L912-42 assume !(1 == ~t14_pc~0); 58965#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 57481#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 57482#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 58258#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 57899#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57900#L1495-3 assume !(1 == ~M_E~0); 58501#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58948#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59044#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58121#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58082#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58083#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58755#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 58974#L1530-3 assume !(1 == ~T8_E~0); 57934#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57935#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 57971#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59247#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59354#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 58373#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 58374#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59004#L1570-3 assume !(1 == ~E_2~0); 58952#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 58953#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59317#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59359#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59404#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58778#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 58779#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59261#L1610-3 assume !(1 == ~E_10~0); 58131#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58132#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58743#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58744#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 58638#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 58066#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 57688#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 57877#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 57878#L2036 assume !(0 == start_simulation_~tmp~3#1); 58975#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 59138#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 58287#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 57527#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 57528#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 58681#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59305#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 59306#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 58244#L2017-2 [2022-12-13 12:47:37,184 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:37,184 INFO L85 PathProgramCache]: Analyzing trace with hash 527190954, now seen corresponding path program 1 times [2022-12-13 12:47:37,184 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:37,184 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [931557714] [2022-12-13 12:47:37,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:37,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:37,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:37,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:37,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:37,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [931557714] [2022-12-13 12:47:37,249 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [931557714] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:37,249 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:37,249 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:37,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574490277] [2022-12-13 12:47:37,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:37,249 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:37,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:37,250 INFO L85 PathProgramCache]: Analyzing trace with hash -1752724661, now seen corresponding path program 1 times [2022-12-13 12:47:37,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:37,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817672616] [2022-12-13 12:47:37,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:37,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:37,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:37,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:37,294 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:37,294 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817672616] [2022-12-13 12:47:37,295 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [817672616] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:37,295 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:37,295 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:37,295 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [138131633] [2022-12-13 12:47:37,295 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:37,295 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:37,295 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:37,296 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:47:37,296 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:47:37,296 INFO L87 Difference]: Start difference. First operand 2047 states and 3021 transitions. cyclomatic complexity: 975 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:37,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:37,433 INFO L93 Difference]: Finished difference Result 3936 states and 5800 transitions. [2022-12-13 12:47:37,433 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3936 states and 5800 transitions. [2022-12-13 12:47:37,445 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3724 [2022-12-13 12:47:37,453 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3936 states to 3936 states and 5800 transitions. [2022-12-13 12:47:37,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3936 [2022-12-13 12:47:37,455 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3936 [2022-12-13 12:47:37,455 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3936 states and 5800 transitions. [2022-12-13 12:47:37,458 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:37,458 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3936 states and 5800 transitions. [2022-12-13 12:47:37,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3936 states and 5800 transitions. [2022-12-13 12:47:37,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3936 to 3936. [2022-12-13 12:47:37,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3936 states, 3936 states have (on average 1.4735772357723578) internal successors, (5800), 3935 states have internal predecessors, (5800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:37,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3936 states to 3936 states and 5800 transitions. [2022-12-13 12:47:37,507 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3936 states and 5800 transitions. [2022-12-13 12:47:37,507 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:47:37,508 INFO L428 stractBuchiCegarLoop]: Abstraction has 3936 states and 5800 transitions. [2022-12-13 12:47:37,508 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 12:47:37,508 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3936 states and 5800 transitions. [2022-12-13 12:47:37,515 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3724 [2022-12-13 12:47:37,516 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:37,516 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:37,517 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:37,517 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:37,517 INFO L748 eck$LassoCheckResult]: Stem: 63776#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 63777#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 64700#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64701#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65509#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 64301#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64302#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64020#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64021#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65299#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64594#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64595#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65156#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64500#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64501#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 63932#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63933#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 64268#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 64454#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 63518#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63519#L1342 assume !(0 == ~M_E~0); 63685#L1342-2 assume !(0 == ~T1_E~0); 64236#L1347-1 assume !(0 == ~T2_E~0); 65279#L1352-1 assume !(0 == ~T3_E~0); 65056#L1357-1 assume !(0 == ~T4_E~0); 64259#L1362-1 assume !(0 == ~T5_E~0); 64260#L1367-1 assume !(0 == ~T6_E~0); 63851#L1372-1 assume !(0 == ~T7_E~0); 63852#L1377-1 assume !(0 == ~T8_E~0); 64181#L1382-1 assume !(0 == ~T9_E~0); 64182#L1387-1 assume !(0 == ~T10_E~0); 64933#L1392-1 assume !(0 == ~T11_E~0); 64220#L1397-1 assume !(0 == ~T12_E~0); 64221#L1402-1 assume !(0 == ~T13_E~0); 63873#L1407-1 assume !(0 == ~T14_E~0); 63874#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 65190#L1417-1 assume !(0 == ~E_2~0); 65191#L1422-1 assume !(0 == ~E_3~0); 65444#L1427-1 assume !(0 == ~E_4~0); 64049#L1432-1 assume !(0 == ~E_5~0); 64050#L1437-1 assume !(0 == ~E_6~0); 65103#L1442-1 assume !(0 == ~E_7~0); 65104#L1447-1 assume !(0 == ~E_8~0); 64926#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 63654#L1457-1 assume !(0 == ~E_10~0); 63655#L1462-1 assume !(0 == ~E_11~0); 65134#L1467-1 assume !(0 == ~E_12~0); 65150#L1472-1 assume !(0 == ~E_13~0); 65151#L1477-1 assume !(0 == ~E_14~0); 64870#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63840#L646 assume 1 == ~m_pc~0; 63841#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 64509#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64524#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63934#L1666 assume !(0 != activate_threads_~tmp~1#1); 63935#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65467#L665 assume !(1 == ~t1_pc~0); 64404#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64405#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65028#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65029#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 64749#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64750#L684 assume 1 == ~t2_pc~0; 64867#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64790#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63920#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63921#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 65284#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65483#L703 assume !(1 == ~t3_pc~0); 64074#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64075#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65014#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63490#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 63491#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63962#L722 assume 1 == ~t4_pc~0; 64707#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64146#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63601#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63602#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 64545#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63686#L741 assume 1 == ~t5_pc~0; 63687#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63984#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64784#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64836#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 64837#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64237#L760 assume !(1 == ~t6_pc~0); 64073#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64072#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63912#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63913#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64662#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64663#L779 assume 1 == ~t7_pc~0; 63724#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63572#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63573#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65321#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 63996#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63997#L798 assume !(1 == ~t8_pc~0); 65331#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 65239#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65240#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65418#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 65469#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63551#L817 assume 1 == ~t9_pc~0; 63552#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64337#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63966#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 63967#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 63946#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 63947#L836 assume !(1 == ~t10_pc~0); 63968#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 63898#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63899#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64147#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 64148#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65253#L855 assume 1 == ~t11_pc~0; 64520#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64521#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65128#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64923#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 64755#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 63837#L874 assume !(1 == ~t12_pc~0); 63838#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 64005#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 63540#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 63541#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 63526#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 63527#L893 assume 1 == ~t13_pc~0; 65398#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 63876#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 64180#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 65345#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 65336#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 65337#L912 assume 1 == ~t14_pc~0; 65110#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 65111#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 65187#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 63774#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 63775#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64538#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 64983#L1495-2 assume !(1 == ~T1_E~0); 64984#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64656#L1505-1 assume !(1 == ~T3_E~0); 64657#L1510-1 assume !(1 == ~T4_E~0); 64717#L1515-1 assume !(1 == ~T5_E~0); 64718#L1520-1 assume !(1 == ~T6_E~0); 65332#L1525-1 assume !(1 == ~T7_E~0); 65015#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63939#L1535-1 assume !(1 == ~T9_E~0); 63940#L1540-1 assume !(1 == ~T10_E~0); 63451#L1545-1 assume !(1 == ~T11_E~0); 63452#L1550-1 assume !(1 == ~T12_E~0); 63697#L1555-1 assume !(1 == ~T13_E~0); 63698#L1560-1 assume !(1 == ~T14_E~0); 63987#L1565-1 assume !(1 == ~E_1~0); 65453#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 64891#L1575-1 assume !(1 == ~E_3~0); 64263#L1580-1 assume !(1 == ~E_4~0); 64264#L1585-1 assume !(1 == ~E_5~0); 64741#L1590-1 assume !(1 == ~E_6~0); 64295#L1595-1 assume !(1 == ~E_7~0); 64296#L1600-1 assume !(1 == ~E_8~0); 64670#L1605-1 assume !(1 == ~E_9~0); 64671#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65224#L1615-1 assume !(1 == ~E_11~0); 64121#L1620-1 assume !(1 == ~E_12~0); 64122#L1625-1 assume !(1 == ~E_13~0); 65088#L1630-1 assume !(1 == ~E_14~0); 64294#L1635-1 assume { :end_inline_reset_delta_events } true; 64238#L2017-2 [2022-12-13 12:47:37,517 INFO L750 eck$LassoCheckResult]: Loop: 64238#L2017-2 assume !false; 64239#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64856#L1316 assume !false; 64857#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 65539#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 65528#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 65256#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 65257#L1115 assume !(0 != eval_~tmp~0#1); 65527#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65526#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65525#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65063#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65064#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 65524#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67101#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67100#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67099#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67098#L1372-3 assume !(0 == ~T7_E~0); 67097#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67096#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 67095#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 67094#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 67093#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 67092#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 67091#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 67090#L1412-3 assume !(0 == ~E_1~0); 67089#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67088#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67087#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 67086#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67085#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 67084#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 67083#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 67082#L1452-3 assume !(0 == ~E_9~0); 67081#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 67080#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 67079#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 67078#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 67077#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 67076#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67075#L646-42 assume 1 == ~m_pc~0; 67073#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 67072#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67071#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67070#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67069#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67068#L665-42 assume 1 == ~t1_pc~0; 67067#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 67065#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67064#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67063#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 67062#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67061#L684-42 assume 1 == ~t2_pc~0; 67059#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 67058#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67057#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 67056#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 67055#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67054#L703-42 assume 1 == ~t3_pc~0; 67053#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 67051#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67050#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67049#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67048#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67047#L722-42 assume 1 == ~t4_pc~0; 67045#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 67044#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67043#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67042#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67041#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67040#L741-42 assume 1 == ~t5_pc~0; 67039#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 67037#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67036#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 67035#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 67034#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 67033#L760-42 assume 1 == ~t6_pc~0; 67031#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 67030#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 67029#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 67028#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 67027#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67026#L779-42 assume !(1 == ~t7_pc~0); 67025#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 67023#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 67022#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67021#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 67020#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67019#L798-42 assume !(1 == ~t8_pc~0); 67017#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 67016#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67015#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 67014#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 67013#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67012#L817-42 assume !(1 == ~t9_pc~0); 67011#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 67009#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67008#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 67007#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 67006#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 67005#L836-42 assume !(1 == ~t10_pc~0); 67003#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 67002#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67001#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 67000#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66999#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66998#L855-42 assume !(1 == ~t11_pc~0); 66997#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 66995#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66994#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66993#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 66992#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 66991#L874-42 assume !(1 == ~t12_pc~0); 66989#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 66988#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 66987#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66986#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 66985#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 66984#L893-42 assume !(1 == ~t13_pc~0); 66983#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 66981#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66980#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 66979#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 66978#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 66977#L912-42 assume !(1 == ~t14_pc~0); 66976#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 66974#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 66973#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 66972#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 66971#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66970#L1495-3 assume !(1 == ~M_E~0); 66969#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66968#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65409#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66967#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66966#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66965#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 66964#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64979#L1530-3 assume !(1 == ~T8_E~0); 66963#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 66962#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 66961#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 66960#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 66959#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 66958#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 66957#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 66956#L1570-3 assume !(1 == ~E_2~0); 66955#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66954#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66953#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 66952#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 66951#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 66950#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 66949#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 66948#L1610-3 assume !(1 == ~E_10~0); 66947#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 66946#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 66945#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 66944#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 66943#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 64060#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 63681#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 63871#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 63872#L2036 assume !(0 == start_simulation_~tmp~3#1); 64981#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 65427#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 64282#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 63520#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 63521#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 64680#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65334#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 65335#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 64238#L2017-2 [2022-12-13 12:47:37,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:37,518 INFO L85 PathProgramCache]: Analyzing trace with hash 1463218542, now seen corresponding path program 1 times [2022-12-13 12:47:37,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:37,518 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711391475] [2022-12-13 12:47:37,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:37,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:37,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:37,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:37,563 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:37,563 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1711391475] [2022-12-13 12:47:37,563 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1711391475] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:37,563 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:37,563 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:37,563 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408140252] [2022-12-13 12:47:37,563 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:37,564 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:37,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:37,564 INFO L85 PathProgramCache]: Analyzing trace with hash -795407799, now seen corresponding path program 1 times [2022-12-13 12:47:37,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:37,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1931854501] [2022-12-13 12:47:37,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:37,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:37,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:37,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:37,611 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:37,611 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1931854501] [2022-12-13 12:47:37,611 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1931854501] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:37,611 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:37,611 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:37,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946668826] [2022-12-13 12:47:37,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:37,612 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:37,612 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:37,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:47:37,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:47:37,613 INFO L87 Difference]: Start difference. First operand 3936 states and 5800 transitions. cyclomatic complexity: 1866 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:37,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:37,770 INFO L93 Difference]: Finished difference Result 7484 states and 11021 transitions. [2022-12-13 12:47:37,770 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7484 states and 11021 transitions. [2022-12-13 12:47:37,793 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7232 [2022-12-13 12:47:37,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7484 states to 7484 states and 11021 transitions. [2022-12-13 12:47:37,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7484 [2022-12-13 12:47:37,814 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7484 [2022-12-13 12:47:37,814 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7484 states and 11021 transitions. [2022-12-13 12:47:37,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:37,819 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7484 states and 11021 transitions. [2022-12-13 12:47:37,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7484 states and 11021 transitions. [2022-12-13 12:47:37,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7484 to 7480. [2022-12-13 12:47:37,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7480 states, 7480 states have (on average 1.472860962566845) internal successors, (11017), 7479 states have internal predecessors, (11017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:37,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7480 states to 7480 states and 11017 transitions. [2022-12-13 12:47:37,899 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7480 states and 11017 transitions. [2022-12-13 12:47:37,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:47:37,899 INFO L428 stractBuchiCegarLoop]: Abstraction has 7480 states and 11017 transitions. [2022-12-13 12:47:37,899 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 12:47:37,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7480 states and 11017 transitions. [2022-12-13 12:47:37,915 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7232 [2022-12-13 12:47:37,915 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:37,915 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:37,916 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:37,916 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:37,916 INFO L748 eck$LassoCheckResult]: Stem: 75206#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 75207#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 76137#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76138#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76980#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 75736#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75737#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75456#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75457#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76737#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76031#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76032#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76593#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75936#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75937#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 75365#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 75366#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 75703#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 75889#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 74948#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74949#L1342 assume !(0 == ~M_E~0); 75115#L1342-2 assume !(0 == ~T1_E~0); 75672#L1347-1 assume !(0 == ~T2_E~0); 76718#L1352-1 assume !(0 == ~T3_E~0); 76495#L1357-1 assume !(0 == ~T4_E~0); 75694#L1362-1 assume !(0 == ~T5_E~0); 75695#L1367-1 assume !(0 == ~T6_E~0); 75283#L1372-1 assume !(0 == ~T7_E~0); 75284#L1377-1 assume !(0 == ~T8_E~0); 75617#L1382-1 assume !(0 == ~T9_E~0); 75618#L1387-1 assume !(0 == ~T10_E~0); 76372#L1392-1 assume !(0 == ~T11_E~0); 75656#L1397-1 assume !(0 == ~T12_E~0); 75657#L1402-1 assume !(0 == ~T13_E~0); 75305#L1407-1 assume !(0 == ~T14_E~0); 75306#L1412-1 assume !(0 == ~E_1~0); 76627#L1417-1 assume !(0 == ~E_2~0); 76628#L1422-1 assume !(0 == ~E_3~0); 76903#L1427-1 assume !(0 == ~E_4~0); 75485#L1432-1 assume !(0 == ~E_5~0); 75486#L1437-1 assume !(0 == ~E_6~0); 76539#L1442-1 assume !(0 == ~E_7~0); 76540#L1447-1 assume !(0 == ~E_8~0); 76366#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 75084#L1457-1 assume !(0 == ~E_10~0); 75085#L1462-1 assume !(0 == ~E_11~0); 76571#L1467-1 assume !(0 == ~E_12~0); 76586#L1472-1 assume !(0 == ~E_13~0); 76587#L1477-1 assume !(0 == ~E_14~0); 76309#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75272#L646 assume 1 == ~m_pc~0; 75273#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 75945#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75961#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75367#L1666 assume !(0 != activate_threads_~tmp~1#1); 75368#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76931#L665 assume !(1 == ~t1_pc~0); 75839#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75840#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76465#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76466#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 76186#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76187#L684 assume 1 == ~t2_pc~0; 76306#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76228#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75353#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75354#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 76723#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76945#L703 assume !(1 == ~t3_pc~0); 75510#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 75511#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76453#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74920#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 74921#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75395#L722 assume 1 == ~t4_pc~0; 76144#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 75582#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75031#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75032#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 75982#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75116#L741 assume 1 == ~t5_pc~0; 75117#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75417#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76221#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76274#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 76275#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75673#L760 assume !(1 == ~t6_pc~0); 75509#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 75508#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75345#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75346#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76101#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76102#L779 assume 1 == ~t7_pc~0; 75153#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75002#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75003#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76759#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 75431#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75432#L798 assume !(1 == ~t8_pc~0); 76770#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 76680#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76681#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76872#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 76933#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74981#L817 assume 1 == ~t9_pc~0; 74982#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75772#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75399#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 75400#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 75379#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75380#L836 assume !(1 == ~t10_pc~0); 75401#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75330#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75331#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 75583#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 75584#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76695#L855 assume 1 == ~t11_pc~0; 75956#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 75957#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76565#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76363#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 76192#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75269#L874 assume !(1 == ~t12_pc~0); 75270#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 75440#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 74970#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 74971#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 74956#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 74957#L893 assume 1 == ~t13_pc~0; 76849#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 75308#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 75616#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 76786#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 76776#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 76777#L912 assume 1 == ~t14_pc~0; 76547#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 76548#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 76624#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 75204#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 75205#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75975#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 76421#L1495-2 assume !(1 == ~T1_E~0); 76422#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76897#L1505-1 assume !(1 == ~T3_E~0); 76978#L1510-1 assume !(1 == ~T4_E~0); 76154#L1515-1 assume !(1 == ~T5_E~0); 76155#L1520-1 assume !(1 == ~T6_E~0); 76923#L1525-1 assume !(1 == ~T7_E~0); 77292#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 77290#L1535-1 assume !(1 == ~T9_E~0); 76954#L1540-1 assume !(1 == ~T10_E~0); 74881#L1545-1 assume !(1 == ~T11_E~0); 74882#L1550-1 assume !(1 == ~T12_E~0); 76990#L1555-1 assume !(1 == ~T13_E~0); 75420#L1560-1 assume !(1 == ~T14_E~0); 75421#L1565-1 assume !(1 == ~E_1~0); 77188#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 77153#L1575-1 assume !(1 == ~E_3~0); 77123#L1580-1 assume !(1 == ~E_4~0); 77096#L1585-1 assume !(1 == ~E_5~0); 77095#L1590-1 assume !(1 == ~E_6~0); 77094#L1595-1 assume !(1 == ~E_7~0); 77092#L1600-1 assume !(1 == ~E_8~0); 77090#L1605-1 assume !(1 == ~E_9~0); 77079#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 77078#L1615-1 assume !(1 == ~E_11~0); 77067#L1620-1 assume !(1 == ~E_12~0); 77058#L1625-1 assume !(1 == ~E_13~0); 77050#L1630-1 assume !(1 == ~E_14~0); 77042#L1635-1 assume { :end_inline_reset_delta_events } true; 77035#L2017-2 [2022-12-13 12:47:37,917 INFO L750 eck$LassoCheckResult]: Loop: 77035#L2017-2 assume !false; 77032#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77028#L1316 assume !false; 77027#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 77022#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 77011#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 77010#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 77008#L1115 assume !(0 != eval_~tmp~0#1); 77007#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77006#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77005#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77004#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77002#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 77003#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 81974#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 81973#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 81972#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 81971#L1372-3 assume !(0 == ~T7_E~0); 81970#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 81969#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 81968#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 81967#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 81966#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 81965#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 81964#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 81963#L1412-3 assume !(0 == ~E_1~0); 81962#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 81961#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 81960#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 81959#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 81958#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 81957#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 81956#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 81955#L1452-3 assume !(0 == ~E_9~0); 81954#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 81953#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 81952#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 81951#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 81950#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 81949#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81948#L646-42 assume !(1 == ~m_pc~0); 81947#L646-44 is_master_triggered_~__retres1~0#1 := 0; 81945#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81944#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81943#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 81942#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81941#L665-42 assume !(1 == ~t1_pc~0); 81939#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 81938#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81937#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81936#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81935#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81934#L684-42 assume !(1 == ~t2_pc~0); 81933#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 81931#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81930#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81929#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 81928#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81927#L703-42 assume !(1 == ~t3_pc~0); 81925#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 81924#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81923#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81922#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 81921#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81920#L722-42 assume !(1 == ~t4_pc~0); 81919#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 81917#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81916#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 81915#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 81914#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81913#L741-42 assume !(1 == ~t5_pc~0); 81911#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 81910#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81909#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 81908#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 81907#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81906#L760-42 assume !(1 == ~t6_pc~0); 81905#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 81903#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81902#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81901#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 81900#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81899#L779-42 assume 1 == ~t7_pc~0; 81897#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 81896#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81895#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 81894#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 81893#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81892#L798-42 assume 1 == ~t8_pc~0; 81891#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 81889#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 81888#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 81887#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 81886#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81885#L817-42 assume 1 == ~t9_pc~0; 81883#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 81882#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81881#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 81880#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 81879#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81878#L836-42 assume 1 == ~t10_pc~0; 81877#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 81875#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81874#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 81873#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 81872#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 81871#L855-42 assume 1 == ~t11_pc~0; 81869#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 81868#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81867#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 81866#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 81865#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 81864#L874-42 assume 1 == ~t12_pc~0; 81863#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 81861#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 81860#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 81859#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 81858#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 81857#L893-42 assume !(1 == ~t13_pc~0); 81856#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 81854#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 81853#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 81852#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 81851#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 81850#L912-42 assume !(1 == ~t14_pc~0); 81849#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 81847#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 81846#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 81845#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 81844#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81843#L1495-3 assume !(1 == ~M_E~0); 81842#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81841#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76859#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75550#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 75512#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75513#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 76191#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 76418#L1530-3 assume !(1 == ~T8_E~0); 75361#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 75362#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 75398#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76709#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 76843#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 75803#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 75804#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77482#L1570-3 assume !(1 == ~E_2~0); 77480#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77477#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77475#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77439#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77402#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 77400#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77367#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 77315#L1610-3 assume !(1 == ~E_10~0); 77276#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 77275#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 77272#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 77270#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 77268#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 77229#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 77214#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 77211#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 77170#L2036 assume !(0 == start_simulation_~tmp~3#1); 77128#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 77099#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 77084#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 77077#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 77066#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 77057#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77049#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 77041#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 77035#L2017-2 [2022-12-13 12:47:37,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:37,917 INFO L85 PathProgramCache]: Analyzing trace with hash -1432795152, now seen corresponding path program 1 times [2022-12-13 12:47:37,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:37,917 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056715150] [2022-12-13 12:47:37,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:37,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:37,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:37,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:37,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:37,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2056715150] [2022-12-13 12:47:37,972 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2056715150] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:37,972 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:37,972 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:37,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719993194] [2022-12-13 12:47:37,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:37,973 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:37,973 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:37,973 INFO L85 PathProgramCache]: Analyzing trace with hash -1437177240, now seen corresponding path program 1 times [2022-12-13 12:47:37,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:37,973 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2684836] [2022-12-13 12:47:37,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:37,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:37,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:38,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:38,006 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:38,006 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2684836] [2022-12-13 12:47:38,007 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2684836] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:38,007 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:38,007 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:38,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755035692] [2022-12-13 12:47:38,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:38,007 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:38,007 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:38,008 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:47:38,008 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:47:38,008 INFO L87 Difference]: Start difference. First operand 7480 states and 11017 transitions. cyclomatic complexity: 3541 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:38,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:38,196 INFO L93 Difference]: Finished difference Result 14320 states and 21070 transitions. [2022-12-13 12:47:38,196 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14320 states and 21070 transitions. [2022-12-13 12:47:38,236 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14036 [2022-12-13 12:47:38,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14320 states to 14320 states and 21070 transitions. [2022-12-13 12:47:38,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14320 [2022-12-13 12:47:38,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14320 [2022-12-13 12:47:38,276 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14320 states and 21070 transitions. [2022-12-13 12:47:38,283 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:38,283 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14320 states and 21070 transitions. [2022-12-13 12:47:38,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14320 states and 21070 transitions. [2022-12-13 12:47:38,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14320 to 14316. [2022-12-13 12:47:38,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14316 states, 14316 states have (on average 1.4715004191114835) internal successors, (21066), 14315 states have internal predecessors, (21066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:38,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14316 states to 14316 states and 21066 transitions. [2022-12-13 12:47:38,540 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14316 states and 21066 transitions. [2022-12-13 12:47:38,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:47:38,541 INFO L428 stractBuchiCegarLoop]: Abstraction has 14316 states and 21066 transitions. [2022-12-13 12:47:38,541 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 12:47:38,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14316 states and 21066 transitions. [2022-12-13 12:47:38,591 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14036 [2022-12-13 12:47:38,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:38,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:38,594 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:38,594 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:38,594 INFO L748 eck$LassoCheckResult]: Stem: 97015#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 97016#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 97950#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97951#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 98804#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 97543#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97544#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97261#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97262#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98564#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 97843#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 97844#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 98417#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 97747#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 97748#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97173#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97174#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 97510#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 97700#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 96758#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96759#L1342 assume !(0 == ~M_E~0); 96925#L1342-2 assume !(0 == ~T1_E~0); 97479#L1347-1 assume !(0 == ~T2_E~0); 98541#L1352-1 assume !(0 == ~T3_E~0); 98318#L1357-1 assume !(0 == ~T4_E~0); 97501#L1362-1 assume !(0 == ~T5_E~0); 97502#L1367-1 assume !(0 == ~T6_E~0); 97092#L1372-1 assume !(0 == ~T7_E~0); 97093#L1377-1 assume !(0 == ~T8_E~0); 97424#L1382-1 assume !(0 == ~T9_E~0); 97425#L1387-1 assume !(0 == ~T10_E~0); 98186#L1392-1 assume !(0 == ~T11_E~0); 97463#L1397-1 assume !(0 == ~T12_E~0); 97464#L1402-1 assume !(0 == ~T13_E~0); 97114#L1407-1 assume !(0 == ~T14_E~0); 97115#L1412-1 assume !(0 == ~E_1~0); 98453#L1417-1 assume !(0 == ~E_2~0); 98454#L1422-1 assume !(0 == ~E_3~0); 98735#L1427-1 assume !(0 == ~E_4~0); 97290#L1432-1 assume !(0 == ~E_5~0); 97291#L1437-1 assume !(0 == ~E_6~0); 98363#L1442-1 assume !(0 == ~E_7~0); 98364#L1447-1 assume !(0 == ~E_8~0); 98180#L1452-1 assume !(0 == ~E_9~0); 96894#L1457-1 assume !(0 == ~E_10~0); 96895#L1462-1 assume !(0 == ~E_11~0); 98394#L1467-1 assume !(0 == ~E_12~0); 98410#L1472-1 assume !(0 == ~E_13~0); 98411#L1477-1 assume !(0 == ~E_14~0); 98124#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97081#L646 assume 1 == ~m_pc~0; 97082#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 97756#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97771#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 97175#L1666 assume !(0 != activate_threads_~tmp~1#1); 97176#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 98762#L665 assume !(1 == ~t1_pc~0); 97649#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 97650#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 98285#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 98286#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 97999#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98000#L684 assume 1 == ~t2_pc~0; 98121#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 98043#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97161#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 97162#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 98546#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98775#L703 assume !(1 == ~t3_pc~0); 97315#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 97316#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98273#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96730#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 96731#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97203#L722 assume 1 == ~t4_pc~0; 97957#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 97387#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96841#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96842#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 97793#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96926#L741 assume 1 == ~t5_pc~0; 96927#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 97225#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98035#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 98089#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 98090#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97480#L760 assume !(1 == ~t6_pc~0); 97314#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 97313#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97153#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 97154#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 97911#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97912#L779 assume 1 == ~t7_pc~0; 96963#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 96812#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96813#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 98588#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 97237#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 97238#L798 assume !(1 == ~t8_pc~0); 98599#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 98503#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 98504#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 98703#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 98764#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96791#L817 assume 1 == ~t9_pc~0; 96792#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 97582#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97207#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 97208#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 97187#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97188#L836 assume !(1 == ~t10_pc~0); 97209#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 97139#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97140#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 97388#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 97389#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 98517#L855 assume 1 == ~t11_pc~0; 97767#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 97768#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 98388#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 98177#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 98006#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 97078#L874 assume !(1 == ~t12_pc~0); 97079#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 97246#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 96780#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 96781#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 96766#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 96767#L893 assume 1 == ~t13_pc~0; 98679#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 97117#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 97423#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 98617#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 98604#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 98605#L912 assume 1 == ~t14_pc~0; 98371#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 98372#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 98450#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 97013#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 97014#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97786#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 98241#L1495-2 assume !(1 == ~T1_E~0); 98242#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98732#L1505-1 assume !(1 == ~T3_E~0); 99160#L1510-1 assume !(1 == ~T4_E~0); 99159#L1515-1 assume !(1 == ~T5_E~0); 99158#L1520-1 assume !(1 == ~T6_E~0); 98600#L1525-1 assume !(1 == ~T7_E~0); 98274#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 97180#L1535-1 assume !(1 == ~T9_E~0); 97181#L1540-1 assume !(1 == ~T10_E~0); 96691#L1545-1 assume !(1 == ~T11_E~0); 96692#L1550-1 assume !(1 == ~T12_E~0); 99022#L1555-1 assume !(1 == ~T13_E~0); 99020#L1560-1 assume !(1 == ~T14_E~0); 99018#L1565-1 assume !(1 == ~E_1~0); 98996#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 98993#L1575-1 assume !(1 == ~E_3~0); 98980#L1580-1 assume !(1 == ~E_4~0); 98974#L1585-1 assume !(1 == ~E_5~0); 98969#L1590-1 assume !(1 == ~E_6~0); 98965#L1595-1 assume !(1 == ~E_7~0); 98962#L1600-1 assume !(1 == ~E_8~0); 98943#L1605-1 assume !(1 == ~E_9~0); 98912#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 98901#L1615-1 assume !(1 == ~E_11~0); 98890#L1620-1 assume !(1 == ~E_12~0); 98881#L1625-1 assume !(1 == ~E_13~0); 98873#L1630-1 assume !(1 == ~E_14~0); 98865#L1635-1 assume { :end_inline_reset_delta_events } true; 98858#L2017-2 [2022-12-13 12:47:38,595 INFO L750 eck$LassoCheckResult]: Loop: 98858#L2017-2 assume !false; 98855#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 98851#L1316 assume !false; 98850#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 98845#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 98834#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 98833#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 98831#L1115 assume !(0 != eval_~tmp~0#1); 98830#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 98829#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 98828#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 98827#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 98825#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 98826#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 106074#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 106073#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 106072#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 106071#L1372-3 assume !(0 == ~T7_E~0); 106070#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 106069#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 106068#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 106067#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 106066#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 106065#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 106064#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 106063#L1412-3 assume !(0 == ~E_1~0); 106062#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 106061#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 106060#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 106059#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 106058#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 106057#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 106056#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 106055#L1452-3 assume !(0 == ~E_9~0); 106054#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 106053#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 106052#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 106051#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 106049#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 106046#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106044#L646-42 assume 1 == ~m_pc~0; 106041#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 106039#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106037#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 106035#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 106032#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 106030#L665-42 assume !(1 == ~t1_pc~0); 106027#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 106025#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 106023#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 106021#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 106018#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106016#L684-42 assume !(1 == ~t2_pc~0); 105697#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 104087#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104082#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 104077#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 104072#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104071#L703-42 assume !(1 == ~t3_pc~0); 104069#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 104068#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104067#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 104066#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 98297#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97879#L722-42 assume !(1 == ~t4_pc~0); 97881#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 98339#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98335#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97350#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 97351#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98755#L741-42 assume !(1 == ~t5_pc~0); 98311#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 97732#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97733#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 101905#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 101904#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101903#L760-42 assume 1 == ~t6_pc~0; 101901#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 101900#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 101899#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 101898#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 101897#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101896#L779-42 assume 1 == ~t7_pc~0; 99573#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 99574#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100911#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 100909#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 100907#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100905#L798-42 assume !(1 == ~t8_pc~0); 100901#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 100899#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 100896#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 100722#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 100720#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 100717#L817-42 assume 1 == ~t9_pc~0; 100715#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 100714#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 100712#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 100710#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 100708#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 99521#L836-42 assume 1 == ~t10_pc~0; 99523#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 100469#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 100468#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 100467#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 100466#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 100464#L855-42 assume 1 == ~t11_pc~0; 100293#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 100291#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 100289#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 100288#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 100287#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 100285#L874-42 assume !(1 == ~t12_pc~0); 100281#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 100280#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 100277#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 100275#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 100273#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 100271#L893-42 assume 1 == ~t13_pc~0; 100269#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 99490#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 99488#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 99489#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 100163#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 100162#L912-42 assume !(1 == ~t14_pc~0); 100161#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 99478#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 99470#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 99471#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 99465#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99463#L1495-3 assume !(1 == ~M_E~0); 99461#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 99462#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98693#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 99728#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 99727#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 98004#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 98005#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 98237#L1530-3 assume !(1 == ~T8_E~0); 99373#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 99367#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 99361#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 99353#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 99349#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 99345#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 99341#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 99336#L1570-3 assume !(1 == ~E_2~0); 99333#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 99330#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 99327#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 99323#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 99321#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 99272#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 99270#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 99227#L1610-3 assume !(1 == ~E_10~0); 99195#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 99192#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 99147#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 99145#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 99143#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 99093#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 99040#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 99039#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 99010#L2036 assume !(0 == start_simulation_~tmp~3#1); 98960#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 98926#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 98911#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 98900#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 98889#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 98880#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98872#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 98864#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 98858#L2017-2 [2022-12-13 12:47:38,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:38,596 INFO L85 PathProgramCache]: Analyzing trace with hash -1867300750, now seen corresponding path program 1 times [2022-12-13 12:47:38,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:38,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [141738866] [2022-12-13 12:47:38,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:38,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:38,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:38,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:38,666 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:38,666 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [141738866] [2022-12-13 12:47:38,666 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [141738866] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:38,666 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:38,666 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:47:38,666 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [909390247] [2022-12-13 12:47:38,667 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:38,667 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:38,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:38,667 INFO L85 PathProgramCache]: Analyzing trace with hash 661751945, now seen corresponding path program 1 times [2022-12-13 12:47:38,667 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:38,668 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867292513] [2022-12-13 12:47:38,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:38,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:38,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:38,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:38,718 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:38,719 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867292513] [2022-12-13 12:47:38,719 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [867292513] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:38,719 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:38,719 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:38,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [578492566] [2022-12-13 12:47:38,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:38,719 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:38,719 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:38,720 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:38,720 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:38,720 INFO L87 Difference]: Start difference. First operand 14316 states and 21066 transitions. cyclomatic complexity: 6758 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:38,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:38,888 INFO L93 Difference]: Finished difference Result 21413 states and 31292 transitions. [2022-12-13 12:47:38,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21413 states and 31292 transitions. [2022-12-13 12:47:38,936 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21126 [2022-12-13 12:47:38,967 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21413 states to 21413 states and 31292 transitions. [2022-12-13 12:47:38,967 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21413 [2022-12-13 12:47:38,975 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21413 [2022-12-13 12:47:38,975 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21413 states and 31292 transitions. [2022-12-13 12:47:38,986 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:38,986 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21413 states and 31292 transitions. [2022-12-13 12:47:38,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21413 states and 31292 transitions. [2022-12-13 12:47:39,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21413 to 20985. [2022-12-13 12:47:39,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20985 states, 20985 states have (on average 1.46256850131046) internal successors, (30692), 20984 states have internal predecessors, (30692), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:39,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20985 states to 20985 states and 30692 transitions. [2022-12-13 12:47:39,179 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20985 states and 30692 transitions. [2022-12-13 12:47:39,180 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:39,180 INFO L428 stractBuchiCegarLoop]: Abstraction has 20985 states and 30692 transitions. [2022-12-13 12:47:39,180 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 12:47:39,180 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20985 states and 30692 transitions. [2022-12-13 12:47:39,221 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 20702 [2022-12-13 12:47:39,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:39,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:39,222 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:39,222 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:39,222 INFO L748 eck$LassoCheckResult]: Stem: 132749#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 132750#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 133714#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 133715#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 134721#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 133285#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 133286#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132997#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132998#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 134384#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 133603#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 133604#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 134219#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 133497#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 133498#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 132907#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 132908#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 133251#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 133451#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 132496#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132497#L1342 assume !(0 == ~M_E~0); 132661#L1342-2 assume !(0 == ~T1_E~0); 133217#L1347-1 assume !(0 == ~T2_E~0); 134359#L1352-1 assume !(0 == ~T3_E~0); 134103#L1357-1 assume !(0 == ~T4_E~0); 133242#L1362-1 assume !(0 == ~T5_E~0); 133243#L1367-1 assume !(0 == ~T6_E~0); 132824#L1372-1 assume !(0 == ~T7_E~0); 132825#L1377-1 assume !(0 == ~T8_E~0); 133161#L1382-1 assume !(0 == ~T9_E~0); 133162#L1387-1 assume !(0 == ~T10_E~0); 133967#L1392-1 assume !(0 == ~T11_E~0); 133203#L1397-1 assume !(0 == ~T12_E~0); 133204#L1402-1 assume !(0 == ~T13_E~0); 132846#L1407-1 assume !(0 == ~T14_E~0); 132847#L1412-1 assume !(0 == ~E_1~0); 134257#L1417-1 assume !(0 == ~E_2~0); 134258#L1422-1 assume !(0 == ~E_3~0); 134601#L1427-1 assume !(0 == ~E_4~0); 133028#L1432-1 assume !(0 == ~E_5~0); 133029#L1437-1 assume !(0 == ~E_6~0); 134157#L1442-1 assume !(0 == ~E_7~0); 134158#L1447-1 assume !(0 == ~E_8~0); 133961#L1452-1 assume !(0 == ~E_9~0); 132630#L1457-1 assume !(0 == ~E_10~0); 132631#L1462-1 assume !(0 == ~E_11~0); 134199#L1467-1 assume !(0 == ~E_12~0); 134213#L1472-1 assume !(0 == ~E_13~0); 134214#L1477-1 assume !(0 == ~E_14~0); 133898#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132814#L646 assume !(1 == ~m_pc~0); 132815#L646-2 is_master_triggered_~__retres1~0#1 := 0; 133525#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 133526#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 132909#L1666 assume !(0 != activate_threads_~tmp~1#1); 132910#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134645#L665 assume !(1 == ~t1_pc~0); 133395#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 133396#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134065#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 134066#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 133765#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133766#L684 assume 1 == ~t2_pc~0; 133895#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 133810#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132895#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 132896#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 134365#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134664#L703 assume !(1 == ~t3_pc~0); 133053#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 133054#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134050#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 132466#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 132467#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132937#L722 assume 1 == ~t4_pc~0; 133721#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 133126#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132577#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 132578#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 133551#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132662#L741 assume 1 == ~t5_pc~0; 132663#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 132960#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133802#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 133862#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 133863#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 133218#L760 assume !(1 == ~t6_pc~0); 133052#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 133051#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132887#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 132888#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 133671#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 133672#L779 assume 1 == ~t7_pc~0; 132698#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 132548#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 132549#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 134414#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 132973#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 132974#L798 assume !(1 == ~t8_pc~0); 134424#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 134312#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 134313#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 134558#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 134647#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 132527#L817 assume 1 == ~t9_pc~0; 132528#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 133323#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 132942#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 132943#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 132921#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 132922#L836 assume !(1 == ~t10_pc~0); 132944#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 132873#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 132874#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 133127#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 133128#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 134326#L855 assume 1 == ~t11_pc~0; 133521#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 133522#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 134190#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 133958#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 133773#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 132811#L874 assume !(1 == ~t12_pc~0); 132812#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 132982#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 132516#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 132517#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 132502#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 132503#L893 assume 1 == ~t13_pc~0; 134525#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 132849#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 133160#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 134446#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 134430#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 134431#L912 assume 1 == ~t14_pc~0; 134167#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 134168#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 134254#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 132747#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 132748#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133542#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 134019#L1495-2 assume !(1 == ~T1_E~0); 134020#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 134594#L1505-1 assume !(1 == ~T3_E~0); 134718#L1510-1 assume !(1 == ~T4_E~0); 134719#L1515-1 assume !(1 == ~T5_E~0); 134626#L1520-1 assume !(1 == ~T6_E~0); 134627#L1525-1 assume !(1 == ~T7_E~0); 141866#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 141865#L1535-1 assume !(1 == ~T9_E~0); 141864#L1540-1 assume !(1 == ~T10_E~0); 141863#L1545-1 assume !(1 == ~T11_E~0); 141862#L1550-1 assume !(1 == ~T12_E~0); 141861#L1555-1 assume !(1 == ~T13_E~0); 141860#L1560-1 assume !(1 == ~T14_E~0); 141859#L1565-1 assume !(1 == ~E_1~0); 141858#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 141857#L1575-1 assume !(1 == ~E_3~0); 141856#L1580-1 assume !(1 == ~E_4~0); 141855#L1585-1 assume !(1 == ~E_5~0); 141854#L1590-1 assume !(1 == ~E_6~0); 141853#L1595-1 assume !(1 == ~E_7~0); 141852#L1600-1 assume !(1 == ~E_8~0); 141850#L1605-1 assume !(1 == ~E_9~0); 141851#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 147591#L1615-1 assume !(1 == ~E_11~0); 147590#L1620-1 assume !(1 == ~E_12~0); 147589#L1625-1 assume !(1 == ~E_13~0); 141747#L1630-1 assume !(1 == ~E_14~0); 141748#L1635-1 assume { :end_inline_reset_delta_events } true; 141719#L2017-2 [2022-12-13 12:47:39,223 INFO L750 eck$LassoCheckResult]: Loop: 141719#L2017-2 assume !false; 141720#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 141704#L1316 assume !false; 141705#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 139643#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 139633#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 139626#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 139627#L1115 assume !(0 != eval_~tmp~0#1); 147416#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 147415#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 147414#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 147413#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 147412#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 133717#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 133718#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 134399#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 134702#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 134703#L1372-3 assume !(0 == ~T7_E~0); 149888#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 149887#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 133140#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 133141#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 134734#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 134735#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 133656#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 132771#L1412-3 assume !(0 == ~E_1~0); 132772#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 133557#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 133558#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 149885#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 134004#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 133673#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 133674#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 132544#L1452-3 assume !(0 == ~E_9~0); 132545#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 149881#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 149880#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 149879#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 134617#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 132769#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132770#L646-42 assume !(1 == ~m_pc~0); 133366#L646-44 is_master_triggered_~__retres1~0#1 := 0; 134597#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 147298#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 147299#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 147292#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 147293#L665-42 assume !(1 == ~t1_pc~0); 147283#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 147284#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 147277#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 147278#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 147271#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 147272#L684-42 assume !(1 == ~t2_pc~0); 147264#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 147263#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 147256#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 147257#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 133743#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 133744#L703-42 assume 1 == ~t3_pc~0; 147243#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 147242#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134039#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 134040#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 134078#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134079#L722-42 assume !(1 == ~t4_pc~0); 134128#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 134127#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 134621#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 147211#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 147212#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 147203#L741-42 assume 1 == ~t5_pc~0; 147204#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 147196#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 147197#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 149863#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 147189#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 147190#L760-42 assume !(1 == ~t6_pc~0); 147185#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 147184#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 147179#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 147180#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 147175#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 147176#L779-42 assume !(1 == ~t7_pc~0); 147171#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 147170#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 133698#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 133699#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 134608#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 149859#L798-42 assume 1 == ~t8_pc~0; 149858#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 134458#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 134459#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 147149#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 147150#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 147144#L817-42 assume !(1 == ~t9_pc~0); 147146#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 147139#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 147140#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 147135#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 147136#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 147130#L836-42 assume !(1 == ~t10_pc~0); 147131#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 149852#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 147123#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 147124#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 149851#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 147116#L855-42 assume !(1 == ~t11_pc~0); 147118#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 132583#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 132584#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 134533#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 147105#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 147106#L874-42 assume !(1 == ~t12_pc~0); 147100#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 147099#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 133644#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 133645#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 132743#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 132744#L893-42 assume !(1 == ~t13_pc~0); 133786#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 133787#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 133163#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 133164#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 149842#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 147083#L912-42 assume !(1 == ~t14_pc~0); 147082#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 147080#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 147079#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 147078#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 147077#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 147076#L1495-3 assume !(1 == ~M_E~0); 133988#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 133989#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 134541#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 133093#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 133055#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 133056#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 133772#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 134015#L1530-3 assume !(1 == ~T8_E~0); 134542#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 132940#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 132941#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 134347#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 134505#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 133356#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 133357#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 134043#L1570-3 assume !(1 == ~E_2~0); 147064#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 134447#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 134448#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 147019#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 147018#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 147017#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 147016#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 144517#L1610-3 assume !(1 == ~E_10~0); 147015#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 147014#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 147013#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 147012#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 147011#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 147010#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 133393#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 133394#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 134016#L2036 assume !(0 == start_simulation_~tmp~3#1); 134017#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 142208#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 141841#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 141837#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 141805#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 141806#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 141745#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 141746#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 141719#L2017-2 [2022-12-13 12:47:39,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:39,223 INFO L85 PathProgramCache]: Analyzing trace with hash 1199377425, now seen corresponding path program 1 times [2022-12-13 12:47:39,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:39,223 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826702385] [2022-12-13 12:47:39,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:39,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:39,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:39,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:39,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:39,302 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826702385] [2022-12-13 12:47:39,302 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826702385] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:39,302 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:39,302 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:39,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221010986] [2022-12-13 12:47:39,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:39,303 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:39,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:39,303 INFO L85 PathProgramCache]: Analyzing trace with hash -1612329211, now seen corresponding path program 1 times [2022-12-13 12:47:39,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:39,303 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598354906] [2022-12-13 12:47:39,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:39,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:39,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:39,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:39,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:39,337 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [598354906] [2022-12-13 12:47:39,337 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [598354906] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:39,337 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:39,337 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:39,337 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833301099] [2022-12-13 12:47:39,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:39,338 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:39,338 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:39,338 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:47:39,338 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:47:39,339 INFO L87 Difference]: Start difference. First operand 20985 states and 30692 transitions. cyclomatic complexity: 9719 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:39,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:39,734 INFO L93 Difference]: Finished difference Result 54264 states and 78850 transitions. [2022-12-13 12:47:39,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54264 states and 78850 transitions. [2022-12-13 12:47:39,921 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 53510 [2022-12-13 12:47:40,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54264 states to 54264 states and 78850 transitions. [2022-12-13 12:47:40,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54264 [2022-12-13 12:47:40,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54264 [2022-12-13 12:47:40,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54264 states and 78850 transitions. [2022-12-13 12:47:40,144 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:40,145 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54264 states and 78850 transitions. [2022-12-13 12:47:40,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54264 states and 78850 transitions. [2022-12-13 12:47:40,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54264 to 40224. [2022-12-13 12:47:40,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40224 states, 40224 states have (on average 1.4569659904534606) internal successors, (58605), 40223 states have internal predecessors, (58605), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:40,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40224 states to 40224 states and 58605 transitions. [2022-12-13 12:47:40,547 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40224 states and 58605 transitions. [2022-12-13 12:47:40,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:47:40,548 INFO L428 stractBuchiCegarLoop]: Abstraction has 40224 states and 58605 transitions. [2022-12-13 12:47:40,548 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 12:47:40,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40224 states and 58605 transitions. [2022-12-13 12:47:40,626 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 39938 [2022-12-13 12:47:40,626 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:40,626 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:40,627 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:40,627 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:40,628 INFO L748 eck$LassoCheckResult]: Stem: 208008#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 208009#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 208950#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 208951#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 209875#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 208536#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 208537#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 208254#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 208255#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 209590#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 208837#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 208838#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 209444#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 208741#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 208742#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 208164#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 208165#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 208502#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 208692#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 207753#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 207754#L1342 assume !(0 == ~M_E~0); 207919#L1342-2 assume !(0 == ~T1_E~0); 208471#L1347-1 assume !(0 == ~T2_E~0); 209568#L1352-1 assume !(0 == ~T3_E~0); 209331#L1357-1 assume !(0 == ~T4_E~0); 208493#L1362-1 assume !(0 == ~T5_E~0); 208494#L1367-1 assume !(0 == ~T6_E~0); 208083#L1372-1 assume !(0 == ~T7_E~0); 208084#L1377-1 assume !(0 == ~T8_E~0); 208416#L1382-1 assume !(0 == ~T9_E~0); 208417#L1387-1 assume !(0 == ~T10_E~0); 209199#L1392-1 assume !(0 == ~T11_E~0); 208455#L1397-1 assume !(0 == ~T12_E~0); 208456#L1402-1 assume !(0 == ~T13_E~0); 208105#L1407-1 assume !(0 == ~T14_E~0); 208106#L1412-1 assume !(0 == ~E_1~0); 209480#L1417-1 assume !(0 == ~E_2~0); 209481#L1422-1 assume !(0 == ~E_3~0); 209780#L1427-1 assume !(0 == ~E_4~0); 208283#L1432-1 assume !(0 == ~E_5~0); 208284#L1437-1 assume !(0 == ~E_6~0); 209386#L1442-1 assume !(0 == ~E_7~0); 209387#L1447-1 assume !(0 == ~E_8~0); 209192#L1452-1 assume !(0 == ~E_9~0); 207888#L1457-1 assume !(0 == ~E_10~0); 207889#L1462-1 assume !(0 == ~E_11~0); 209419#L1467-1 assume !(0 == ~E_12~0); 209437#L1472-1 assume !(0 == ~E_13~0); 209438#L1477-1 assume !(0 == ~E_14~0); 209130#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 208073#L646 assume !(1 == ~m_pc~0); 208074#L646-2 is_master_triggered_~__retres1~0#1 := 0; 208767#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 208768#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 208166#L1666 assume !(0 != activate_threads_~tmp~1#1); 208167#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 209814#L665 assume !(1 == ~t1_pc~0); 208642#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 208643#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 209298#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 209299#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 209002#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 209003#L684 assume !(1 == ~t2_pc~0); 209045#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 209046#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 208152#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 208153#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 209575#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 209830#L703 assume !(1 == ~t3_pc~0); 208308#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 208309#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 209286#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 207725#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 207726#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 208194#L722 assume 1 == ~t4_pc~0; 208957#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 208381#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 207835#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 207836#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 208789#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 207920#L741 assume 1 == ~t5_pc~0; 207921#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 208216#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 209039#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 209098#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 209099#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 208472#L760 assume !(1 == ~t6_pc~0); 208307#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 208306#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 208144#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 208145#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 208907#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 208908#L779 assume 1 == ~t7_pc~0; 207956#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 207807#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 207808#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 209616#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 208229#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 208230#L798 assume !(1 == ~t8_pc~0); 209626#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 209530#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 209531#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 209746#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 209816#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 207786#L817 assume 1 == ~t9_pc~0; 207787#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 208572#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 208198#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 208199#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 208178#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 208179#L836 assume !(1 == ~t10_pc~0); 208200#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 208130#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 208131#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 208382#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 208383#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 209544#L855 assume 1 == ~t11_pc~0; 208763#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 208764#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 209413#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 209189#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 209008#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 208070#L874 assume !(1 == ~t12_pc~0); 208071#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 208238#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 207775#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 207776#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 207761#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 207762#L893 assume 1 == ~t13_pc~0; 209715#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 208108#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 208415#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 209646#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 209632#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 209633#L912 assume 1 == ~t14_pc~0; 209393#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 209394#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 209477#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 208006#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 208007#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 208782#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 209252#L1495-2 assume !(1 == ~T1_E~0); 209253#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 209774#L1505-1 assume !(1 == ~T3_E~0); 209872#L1510-1 assume !(1 == ~T4_E~0); 209873#L1515-1 assume !(1 == ~T5_E~0); 209801#L1520-1 assume !(1 == ~T6_E~0); 209802#L1525-1 assume !(1 == ~T7_E~0); 236819#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 236818#L1535-1 assume !(1 == ~T9_E~0); 236817#L1540-1 assume !(1 == ~T10_E~0); 236816#L1545-1 assume !(1 == ~T11_E~0); 236815#L1550-1 assume !(1 == ~T12_E~0); 236814#L1555-1 assume !(1 == ~T13_E~0); 236813#L1560-1 assume !(1 == ~T14_E~0); 236812#L1565-1 assume !(1 == ~E_1~0); 236811#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 236810#L1575-1 assume !(1 == ~E_3~0); 236809#L1580-1 assume !(1 == ~E_4~0); 236808#L1585-1 assume !(1 == ~E_5~0); 236807#L1590-1 assume !(1 == ~E_6~0); 236806#L1595-1 assume !(1 == ~E_7~0); 236805#L1600-1 assume !(1 == ~E_8~0); 236804#L1605-1 assume !(1 == ~E_9~0); 236801#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 236800#L1615-1 assume !(1 == ~E_11~0); 236799#L1620-1 assume !(1 == ~E_12~0); 236798#L1625-1 assume !(1 == ~E_13~0); 236797#L1630-1 assume !(1 == ~E_14~0); 236796#L1635-1 assume { :end_inline_reset_delta_events } true; 236791#L2017-2 [2022-12-13 12:47:40,628 INFO L750 eck$LassoCheckResult]: Loop: 236791#L2017-2 assume !false; 236773#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 236769#L1316 assume !false; 236764#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 236701#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 236685#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 236574#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 236566#L1115 assume !(0 != eval_~tmp~0#1); 236567#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 239259#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 239257#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 239255#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 239253#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 239251#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 239249#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 239246#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 239244#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 239242#L1372-3 assume !(0 == ~T7_E~0); 239240#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 239238#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 239236#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 239233#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 239231#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 239229#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 239227#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 239225#L1412-3 assume !(0 == ~E_1~0); 239223#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 239220#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 239218#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 239216#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 239214#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 239212#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 239210#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 239207#L1452-3 assume !(0 == ~E_9~0); 239205#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 239203#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 239201#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 239199#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 239197#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 239194#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 239192#L646-42 assume !(1 == ~m_pc~0); 239190#L646-44 is_master_triggered_~__retres1~0#1 := 0; 239188#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 239186#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 239185#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 239184#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 239183#L665-42 assume 1 == ~t1_pc~0; 239182#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 239180#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 239179#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 239177#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 239175#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 239173#L684-42 assume !(1 == ~t2_pc~0); 226382#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 239171#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 239170#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 239169#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 239168#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 239167#L703-42 assume 1 == ~t3_pc~0; 239166#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 239164#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 239163#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 239162#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 239161#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 239160#L722-42 assume !(1 == ~t4_pc~0); 239159#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 239157#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 239156#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 239155#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 239154#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 239153#L741-42 assume 1 == ~t5_pc~0; 239152#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 239150#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 239148#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 239146#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 239144#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 239142#L760-42 assume 1 == ~t6_pc~0; 239139#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 239138#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 239122#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 239120#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 239118#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 239114#L779-42 assume 1 == ~t7_pc~0; 239111#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 239110#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 239109#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 239108#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 239107#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 239106#L798-42 assume 1 == ~t8_pc~0; 239105#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 239103#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 239102#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 239101#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 239100#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 239099#L817-42 assume !(1 == ~t9_pc~0); 239098#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 239096#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 239095#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 239094#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 239093#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 239077#L836-42 assume 1 == ~t10_pc~0; 239075#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 239072#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 239070#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 239068#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 239066#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 237838#L855-42 assume !(1 == ~t11_pc~0); 237835#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 237832#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 237830#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 237828#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 237826#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 237824#L874-42 assume !(1 == ~t12_pc~0); 237819#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 237817#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 237815#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 237813#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 237811#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 237808#L893-42 assume !(1 == ~t13_pc~0); 237806#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 237803#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 237801#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 237799#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 237797#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 237795#L912-42 assume !(1 == ~t14_pc~0); 237793#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 237790#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 237788#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 237786#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 237784#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 237780#L1495-3 assume !(1 == ~M_E~0); 237778#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 237776#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 209729#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 237773#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 237771#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 237769#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 237767#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 237765#L1530-3 assume !(1 == ~T8_E~0); 237764#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 237762#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 237760#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 237758#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 237756#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 237754#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 237752#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 237748#L1570-3 assume !(1 == ~E_2~0); 237745#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 237743#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 237741#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 237739#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 237737#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 237735#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 237734#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 237730#L1610-3 assume !(1 == ~E_10~0); 237728#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 237726#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 237724#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 237722#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 237719#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 237716#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 237700#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 237698#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 237695#L2036 assume !(0 == start_simulation_~tmp~3#1); 237691#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 237454#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 237452#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 237450#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 237448#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 237446#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 237443#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 236795#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 236791#L2017-2 [2022-12-13 12:47:40,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:40,628 INFO L85 PathProgramCache]: Analyzing trace with hash 752619056, now seen corresponding path program 1 times [2022-12-13 12:47:40,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:40,628 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052258620] [2022-12-13 12:47:40,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:40,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:40,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:40,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:40,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:40,668 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1052258620] [2022-12-13 12:47:40,669 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1052258620] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:40,669 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:40,669 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:47:40,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257997878] [2022-12-13 12:47:40,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:40,669 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:40,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:40,670 INFO L85 PathProgramCache]: Analyzing trace with hash -2116436855, now seen corresponding path program 1 times [2022-12-13 12:47:40,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:40,670 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2147006786] [2022-12-13 12:47:40,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:40,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:40,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:40,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:40,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:40,716 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2147006786] [2022-12-13 12:47:40,716 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2147006786] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:40,716 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:40,716 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:40,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1588485541] [2022-12-13 12:47:40,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:40,716 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:40,717 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:40,717 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:40,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:40,717 INFO L87 Difference]: Start difference. First operand 40224 states and 58605 transitions. cyclomatic complexity: 18393 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:40,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:40,980 INFO L93 Difference]: Finished difference Result 77309 states and 112244 transitions. [2022-12-13 12:47:40,980 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77309 states and 112244 transitions. [2022-12-13 12:47:41,243 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 76968 [2022-12-13 12:47:41,411 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77309 states to 77309 states and 112244 transitions. [2022-12-13 12:47:41,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77309 [2022-12-13 12:47:41,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77309 [2022-12-13 12:47:41,446 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77309 states and 112244 transitions. [2022-12-13 12:47:41,489 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:41,489 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77309 states and 112244 transitions. [2022-12-13 12:47:41,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77309 states and 112244 transitions. [2022-12-13 12:47:42,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77309 to 77261. [2022-12-13 12:47:42,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77261 states, 77261 states have (on average 1.452168623238115) internal successors, (112196), 77260 states have internal predecessors, (112196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:42,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77261 states to 77261 states and 112196 transitions. [2022-12-13 12:47:42,263 INFO L240 hiAutomatonCegarLoop]: Abstraction has 77261 states and 112196 transitions. [2022-12-13 12:47:42,264 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:42,264 INFO L428 stractBuchiCegarLoop]: Abstraction has 77261 states and 112196 transitions. [2022-12-13 12:47:42,264 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 12:47:42,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77261 states and 112196 transitions. [2022-12-13 12:47:42,434 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 76920 [2022-12-13 12:47:42,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:42,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:42,436 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:42,436 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:42,436 INFO L748 eck$LassoCheckResult]: Stem: 325546#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 325547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 326492#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 326493#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 327402#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 326079#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 326080#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 325793#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 325794#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 327121#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 326379#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 326380#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 326976#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 326280#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 326281#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 325702#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 325703#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 326045#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 326232#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 325295#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 325296#L1342 assume !(0 == ~M_E~0); 325459#L1342-2 assume !(0 == ~T1_E~0); 326012#L1347-1 assume !(0 == ~T2_E~0); 327101#L1352-1 assume !(0 == ~T3_E~0); 326870#L1357-1 assume !(0 == ~T4_E~0); 326034#L1362-1 assume !(0 == ~T5_E~0); 326035#L1367-1 assume !(0 == ~T6_E~0); 325625#L1372-1 assume !(0 == ~T7_E~0); 325626#L1377-1 assume !(0 == ~T8_E~0); 325956#L1382-1 assume !(0 == ~T9_E~0); 325957#L1387-1 assume !(0 == ~T10_E~0); 326741#L1392-1 assume !(0 == ~T11_E~0); 325998#L1397-1 assume !(0 == ~T12_E~0); 325999#L1402-1 assume !(0 == ~T13_E~0); 325643#L1407-1 assume !(0 == ~T14_E~0); 325644#L1412-1 assume !(0 == ~E_1~0); 327014#L1417-1 assume !(0 == ~E_2~0); 327015#L1422-1 assume !(0 == ~E_3~0); 327312#L1427-1 assume !(0 == ~E_4~0); 325820#L1432-1 assume !(0 == ~E_5~0); 325821#L1437-1 assume !(0 == ~E_6~0); 326921#L1442-1 assume !(0 == ~E_7~0); 326922#L1447-1 assume !(0 == ~E_8~0); 326733#L1452-1 assume !(0 == ~E_9~0); 325430#L1457-1 assume !(0 == ~E_10~0); 325431#L1462-1 assume !(0 == ~E_11~0); 326955#L1467-1 assume !(0 == ~E_12~0); 326969#L1472-1 assume !(0 == ~E_13~0); 326970#L1477-1 assume !(0 == ~E_14~0); 326674#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 325615#L646 assume !(1 == ~m_pc~0); 325616#L646-2 is_master_triggered_~__retres1~0#1 := 0; 326308#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 326309#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 325704#L1666 assume !(0 != activate_threads_~tmp~1#1); 325705#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 327343#L665 assume !(1 == ~t1_pc~0); 326181#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 326182#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 326839#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 326840#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 326543#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 326544#L684 assume !(1 == ~t2_pc~0); 326588#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 326589#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 325692#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 325693#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 327106#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 327361#L703 assume !(1 == ~t3_pc~0); 325845#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 325846#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 326826#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 325265#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 325266#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 325733#L722 assume !(1 == ~t4_pc~0); 325918#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 325919#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 325375#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 325376#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 326331#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 325460#L741 assume 1 == ~t5_pc~0; 325461#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 325753#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 326580#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 326640#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 326641#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 326013#L760 assume !(1 == ~t6_pc~0); 325844#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 325843#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 325682#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 325683#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 326449#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 326450#L779 assume 1 == ~t7_pc~0; 325496#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 325347#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 325348#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 327150#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 325766#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 325767#L798 assume !(1 == ~t8_pc~0); 327159#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 327064#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 327065#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 327279#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 327345#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 325328#L817 assume 1 == ~t9_pc~0; 325329#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 326116#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 325735#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 325736#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 325715#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 325716#L836 assume !(1 == ~t10_pc~0); 325737#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 325668#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 325669#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 325920#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 325921#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 327078#L855 assume 1 == ~t11_pc~0; 326304#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 326305#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 326949#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 326730#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 326549#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 325608#L874 assume !(1 == ~t12_pc~0); 325609#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 325776#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 325315#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 325316#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 325303#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 325304#L893 assume 1 == ~t13_pc~0; 327248#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 325646#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 325955#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 327177#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 327164#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 327165#L912 assume 1 == ~t14_pc~0; 326930#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 326931#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 327010#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 325544#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 325545#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 326326#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 326791#L1495-2 assume !(1 == ~T1_E~0); 326792#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 326442#L1505-1 assume !(1 == ~T3_E~0); 326443#L1510-1 assume !(1 == ~T4_E~0); 326510#L1515-1 assume !(1 == ~T5_E~0); 326511#L1520-1 assume !(1 == ~T6_E~0); 327160#L1525-1 assume !(1 == ~T7_E~0); 326827#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 326828#L1535-1 assume !(1 == ~T9_E~0); 327376#L1540-1 assume !(1 == ~T10_E~0); 327377#L1545-1 assume !(1 == ~T11_E~0); 327416#L1550-1 assume !(1 == ~T12_E~0); 327417#L1555-1 assume !(1 == ~T13_E~0); 325758#L1560-1 assume !(1 == ~T14_E~0); 325759#L1565-1 assume !(1 == ~E_1~0); 372647#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 372646#L1575-1 assume !(1 == ~E_3~0); 372645#L1580-1 assume !(1 == ~E_4~0); 372644#L1585-1 assume !(1 == ~E_5~0); 372643#L1590-1 assume !(1 == ~E_6~0); 372642#L1595-1 assume !(1 == ~E_7~0); 372641#L1600-1 assume !(1 == ~E_8~0); 372639#L1605-1 assume !(1 == ~E_9~0); 372640#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 398551#L1615-1 assume !(1 == ~E_11~0); 398550#L1620-1 assume !(1 == ~E_12~0); 398549#L1625-1 assume !(1 == ~E_13~0); 398548#L1630-1 assume !(1 == ~E_14~0); 398547#L1635-1 assume { :end_inline_reset_delta_events } true; 398545#L2017-2 [2022-12-13 12:47:42,437 INFO L750 eck$LassoCheckResult]: Loop: 398545#L2017-2 assume !false; 358623#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 358618#L1316 assume !false; 358616#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 358476#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 358444#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 358363#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 358358#L1115 assume !(0 != eval_~tmp~0#1); 358360#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 399012#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 399010#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 399008#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 399006#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 399005#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 399004#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 399003#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 399002#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 399001#L1372-3 assume !(0 == ~T7_E~0); 399000#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 398999#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 398998#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 398997#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 398996#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 398995#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 398994#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 398993#L1412-3 assume !(0 == ~E_1~0); 398992#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 398991#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 398990#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 398989#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 398988#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 398987#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 398986#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 398985#L1452-3 assume !(0 == ~E_9~0); 398984#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 398983#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 398982#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 398981#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 398980#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 398979#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 398978#L646-42 assume !(1 == ~m_pc~0); 398977#L646-44 is_master_triggered_~__retres1~0#1 := 0; 398976#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 398975#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 398974#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 398973#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 398972#L665-42 assume !(1 == ~t1_pc~0); 398970#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 398969#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 398968#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 398967#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 398966#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 398965#L684-42 assume !(1 == ~t2_pc~0); 398963#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 398962#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 398961#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 398960#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 398959#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 398958#L703-42 assume !(1 == ~t3_pc~0); 398956#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 398955#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 398954#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 398953#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 398952#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 398951#L722-42 assume !(1 == ~t4_pc~0); 398950#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 398949#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 398948#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 398947#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 398946#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 398945#L741-42 assume 1 == ~t5_pc~0; 398944#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 398942#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 398941#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 398940#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 398939#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 398938#L760-42 assume 1 == ~t6_pc~0; 398936#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 398935#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 398934#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 398933#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 398932#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 398931#L779-42 assume !(1 == ~t7_pc~0); 398930#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 398928#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 398927#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 398926#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 398925#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 398924#L798-42 assume !(1 == ~t8_pc~0); 398922#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 398921#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 398920#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 398919#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 398918#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 398917#L817-42 assume 1 == ~t9_pc~0; 398788#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 398787#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 398786#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 398785#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 398784#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 398783#L836-42 assume 1 == ~t10_pc~0; 398782#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 398780#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 398779#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 398778#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 398777#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 398776#L855-42 assume 1 == ~t11_pc~0; 398774#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 398773#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 398772#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 398771#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 398770#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 398769#L874-42 assume 1 == ~t12_pc~0; 398768#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 398766#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 398765#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 398764#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 398763#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 398762#L893-42 assume 1 == ~t13_pc~0; 398760#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 398759#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 398758#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 398757#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 398756#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 398755#L912-42 assume !(1 == ~t14_pc~0); 398754#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 398752#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 398751#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 398750#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 398749#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 398748#L1495-3 assume !(1 == ~M_E~0); 398747#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 398746#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 353348#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 398745#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 398744#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 398743#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 398742#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 355768#L1530-3 assume !(1 == ~T8_E~0); 398741#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 398740#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 398739#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 398738#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 398737#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 398736#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 398735#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 360500#L1570-3 assume !(1 == ~E_2~0); 398734#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 398733#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 398732#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 398731#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 398730#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 398729#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 398728#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 391445#L1610-3 assume !(1 == ~E_10~0); 398727#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 398726#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 398725#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 398724#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 398723#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 398722#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 398707#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 398706#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 398704#L2036 assume !(0 == start_simulation_~tmp~3#1); 398702#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 398557#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 398556#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 398555#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 398554#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 398553#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 398552#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 398546#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 398545#L2017-2 [2022-12-13 12:47:42,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:42,437 INFO L85 PathProgramCache]: Analyzing trace with hash 1108215503, now seen corresponding path program 1 times [2022-12-13 12:47:42,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:42,437 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1163914041] [2022-12-13 12:47:42,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:42,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:42,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:42,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:42,485 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:42,485 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1163914041] [2022-12-13 12:47:42,485 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1163914041] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:42,485 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:42,486 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:47:42,486 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1070146850] [2022-12-13 12:47:42,486 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:42,486 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:42,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:42,486 INFO L85 PathProgramCache]: Analyzing trace with hash -522954743, now seen corresponding path program 1 times [2022-12-13 12:47:42,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:42,487 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539459242] [2022-12-13 12:47:42,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:42,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:42,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:42,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:42,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:42,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539459242] [2022-12-13 12:47:42,523 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1539459242] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:42,523 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:42,523 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:42,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410636245] [2022-12-13 12:47:42,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:42,523 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:42,524 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:42,524 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:47:42,524 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:47:42,524 INFO L87 Difference]: Start difference. First operand 77261 states and 112196 transitions. cyclomatic complexity: 34959 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:43,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:43,039 INFO L93 Difference]: Finished difference Result 148572 states and 215073 transitions. [2022-12-13 12:47:43,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 148572 states and 215073 transitions. [2022-12-13 12:47:43,627 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 148072 [2022-12-13 12:47:43,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 148572 states to 148572 states and 215073 transitions. [2022-12-13 12:47:43,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 148572 [2022-12-13 12:47:43,947 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 148572 [2022-12-13 12:47:43,947 INFO L73 IsDeterministic]: Start isDeterministic. Operand 148572 states and 215073 transitions. [2022-12-13 12:47:44,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:44,013 INFO L218 hiAutomatonCegarLoop]: Abstraction has 148572 states and 215073 transitions. [2022-12-13 12:47:44,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148572 states and 215073 transitions. [2022-12-13 12:47:45,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148572 to 148476. [2022-12-13 12:47:45,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 148476 states, 148476 states have (on average 1.447890568172634) internal successors, (214977), 148475 states have internal predecessors, (214977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:45,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148476 states to 148476 states and 214977 transitions. [2022-12-13 12:47:45,323 INFO L240 hiAutomatonCegarLoop]: Abstraction has 148476 states and 214977 transitions. [2022-12-13 12:47:45,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:47:45,324 INFO L428 stractBuchiCegarLoop]: Abstraction has 148476 states and 214977 transitions. [2022-12-13 12:47:45,324 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 12:47:45,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 148476 states and 214977 transitions. [2022-12-13 12:47:45,652 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 147976 [2022-12-13 12:47:45,652 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:45,652 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:45,654 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:45,654 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:45,654 INFO L748 eck$LassoCheckResult]: Stem: 551386#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 551387#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 552327#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 552328#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 553236#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 551909#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 551910#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 551626#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 551627#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 552947#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 552218#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 552219#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 552795#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 552120#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 552121#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 551540#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 551541#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 551874#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 552072#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 551135#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 551136#L1342 assume !(0 == ~M_E~0); 551299#L1342-2 assume !(0 == ~T1_E~0); 551843#L1347-1 assume !(0 == ~T2_E~0); 552924#L1352-1 assume !(0 == ~T3_E~0); 552694#L1357-1 assume !(0 == ~T4_E~0); 551865#L1362-1 assume !(0 == ~T5_E~0); 551866#L1367-1 assume !(0 == ~T6_E~0); 551461#L1372-1 assume !(0 == ~T7_E~0); 551462#L1377-1 assume !(0 == ~T8_E~0); 551787#L1382-1 assume !(0 == ~T9_E~0); 551788#L1387-1 assume !(0 == ~T10_E~0); 552562#L1392-1 assume !(0 == ~T11_E~0); 551829#L1397-1 assume !(0 == ~T12_E~0); 551830#L1402-1 assume !(0 == ~T13_E~0); 551481#L1407-1 assume !(0 == ~T14_E~0); 551482#L1412-1 assume !(0 == ~E_1~0); 552831#L1417-1 assume !(0 == ~E_2~0); 552832#L1422-1 assume !(0 == ~E_3~0); 553151#L1427-1 assume !(0 == ~E_4~0); 551655#L1432-1 assume !(0 == ~E_5~0); 551656#L1437-1 assume !(0 == ~E_6~0); 552745#L1442-1 assume !(0 == ~E_7~0); 552746#L1447-1 assume !(0 == ~E_8~0); 552556#L1452-1 assume !(0 == ~E_9~0); 551268#L1457-1 assume !(0 == ~E_10~0); 551269#L1462-1 assume !(0 == ~E_11~0); 552777#L1467-1 assume !(0 == ~E_12~0); 552790#L1472-1 assume !(0 == ~E_13~0); 552791#L1477-1 assume !(0 == ~E_14~0); 552498#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 551449#L646 assume !(1 == ~m_pc~0); 551450#L646-2 is_master_triggered_~__retres1~0#1 := 0; 552147#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 552148#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 551542#L1666 assume !(0 != activate_threads_~tmp~1#1); 551543#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 553184#L665 assume !(1 == ~t1_pc~0); 552019#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 552020#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 552663#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 552664#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 552375#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 552376#L684 assume !(1 == ~t2_pc~0); 552420#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 552421#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 551530#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 551531#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 552931#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 553199#L703 assume !(1 == ~t3_pc~0); 551679#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 551680#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 552651#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 551105#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 551106#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 551569#L722 assume !(1 == ~t4_pc~0); 551751#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 551752#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 551215#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 551216#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 552168#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 551300#L741 assume !(1 == ~t5_pc~0); 551301#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 552412#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 552413#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 552466#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 552467#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 551844#L760 assume !(1 == ~t6_pc~0); 551678#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 551677#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 551520#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 551521#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 552289#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 552290#L779 assume 1 == ~t7_pc~0; 551334#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 551187#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 551188#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 552976#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 551602#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 551603#L798 assume !(1 == ~t8_pc~0); 552987#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 552888#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 552889#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 553113#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 553186#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 551168#L817 assume 1 == ~t9_pc~0; 551169#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 551947#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 551573#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 551574#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 551553#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 551554#L836 assume !(1 == ~t10_pc~0); 551575#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 551506#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 551507#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 551753#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 551754#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 552901#L855 assume 1 == ~t11_pc~0; 552142#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 552143#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 552771#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 552553#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 552381#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 551446#L874 assume !(1 == ~t12_pc~0); 551447#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 551611#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 551155#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 551156#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 551141#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 551142#L893 assume 1 == ~t13_pc~0; 553083#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 551484#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 551786#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 553006#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 552993#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 552994#L912 assume 1 == ~t14_pc~0; 552753#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 552754#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 552830#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 551384#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 551385#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 552162#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 552615#L1495-2 assume !(1 == ~T1_E~0); 552616#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 552282#L1505-1 assume !(1 == ~T3_E~0); 552283#L1510-1 assume !(1 == ~T4_E~0); 552343#L1515-1 assume !(1 == ~T5_E~0); 552344#L1520-1 assume !(1 == ~T6_E~0); 552988#L1525-1 assume !(1 == ~T7_E~0); 552989#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 600015#L1535-1 assume !(1 == ~T9_E~0); 600014#L1540-1 assume !(1 == ~T10_E~0); 600013#L1545-1 assume !(1 == ~T11_E~0); 600012#L1550-1 assume !(1 == ~T12_E~0); 600011#L1555-1 assume !(1 == ~T13_E~0); 600010#L1560-1 assume !(1 == ~T14_E~0); 600009#L1565-1 assume !(1 == ~E_1~0); 600008#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 600007#L1575-1 assume !(1 == ~E_3~0); 600006#L1580-1 assume !(1 == ~E_4~0); 599990#L1585-1 assume !(1 == ~E_5~0); 599988#L1590-1 assume !(1 == ~E_6~0); 599986#L1595-1 assume !(1 == ~E_7~0); 599984#L1600-1 assume !(1 == ~E_8~0); 599982#L1605-1 assume !(1 == ~E_9~0); 599978#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 599977#L1615-1 assume !(1 == ~E_11~0); 599976#L1620-1 assume !(1 == ~E_12~0); 599974#L1625-1 assume !(1 == ~E_13~0); 599972#L1630-1 assume !(1 == ~E_14~0); 599970#L1635-1 assume { :end_inline_reset_delta_events } true; 599968#L2017-2 [2022-12-13 12:47:45,654 INFO L750 eck$LassoCheckResult]: Loop: 599968#L2017-2 assume !false; 599050#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 599045#L1316 assume !false; 599042#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 599028#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 599016#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 599014#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 599012#L1115 assume !(0 != eval_~tmp~0#1); 599013#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 600334#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 600333#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 600332#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 600331#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 600330#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 600329#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 600328#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 600327#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 600326#L1372-3 assume !(0 == ~T7_E~0); 600325#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 600324#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 600323#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 600322#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 600321#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 600320#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 600319#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 600318#L1412-3 assume !(0 == ~E_1~0); 600316#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 600314#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 600312#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 600310#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 600308#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 600306#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 600304#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 600301#L1452-3 assume !(0 == ~E_9~0); 600299#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 600297#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 600295#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 600293#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 600291#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 600290#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 600288#L646-42 assume !(1 == ~m_pc~0); 600286#L646-44 is_master_triggered_~__retres1~0#1 := 0; 600284#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 600282#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 600280#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 600277#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 600275#L665-42 assume 1 == ~t1_pc~0; 600273#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 600270#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 600268#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 600266#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 600264#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 600262#L684-42 assume !(1 == ~t2_pc~0); 587388#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 600259#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 600257#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 600255#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 600253#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 600251#L703-42 assume 1 == ~t3_pc~0; 600249#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 600246#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 600244#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 600242#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 600239#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 600237#L722-42 assume !(1 == ~t4_pc~0); 600235#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 600233#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 600231#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 600229#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 600226#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 600224#L741-42 assume !(1 == ~t5_pc~0); 600222#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 600220#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 600218#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 600216#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 600213#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 600211#L760-42 assume !(1 == ~t6_pc~0); 600209#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 600206#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 600204#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 600202#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 600199#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 600197#L779-42 assume !(1 == ~t7_pc~0); 600195#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 600192#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 600190#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 600188#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 600185#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 600183#L798-42 assume 1 == ~t8_pc~0; 600181#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 600178#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 600176#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 600174#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 600171#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 600169#L817-42 assume !(1 == ~t9_pc~0); 600167#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 600164#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 600162#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 600160#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 600157#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 600155#L836-42 assume 1 == ~t10_pc~0; 600153#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 600150#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 600148#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 600146#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 600143#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 600141#L855-42 assume !(1 == ~t11_pc~0); 600139#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 600136#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 600134#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 600132#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 600129#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 600127#L874-42 assume 1 == ~t12_pc~0; 600125#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 600122#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 600120#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 600118#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 600116#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 600112#L893-42 assume !(1 == ~t13_pc~0); 600111#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 600108#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 600106#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 600104#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 600100#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 600098#L912-42 assume 1 == ~t14_pc~0; 600095#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 600093#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 600091#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 600089#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 600087#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 600085#L1495-3 assume !(1 == ~M_E~0); 600083#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 600082#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 589159#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 600077#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 600075#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 600073#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 600071#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 600067#L1530-3 assume !(1 == ~T8_E~0); 600065#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 600064#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 600062#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 600060#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 600058#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 600056#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 600055#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 594784#L1570-3 assume !(1 == ~E_2~0); 600054#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 600053#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 600052#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 600051#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 600050#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 600049#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 600048#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 589109#L1610-3 assume !(1 == ~E_10~0); 600047#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 600046#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 600045#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 600044#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 600043#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 600040#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 600024#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 600022#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 600019#L2036 assume !(0 == start_simulation_~tmp~3#1); 600016#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 599991#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 599989#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 599987#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 599985#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 599983#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 599979#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 599969#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 599968#L2017-2 [2022-12-13 12:47:45,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:45,655 INFO L85 PathProgramCache]: Analyzing trace with hash 1070768814, now seen corresponding path program 1 times [2022-12-13 12:47:45,655 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:45,655 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776417513] [2022-12-13 12:47:45,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:45,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:45,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:45,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:45,729 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:45,729 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776417513] [2022-12-13 12:47:45,730 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776417513] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:45,730 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:45,730 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:47:45,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1124162133] [2022-12-13 12:47:45,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:45,730 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:45,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:45,731 INFO L85 PathProgramCache]: Analyzing trace with hash 1105356712, now seen corresponding path program 1 times [2022-12-13 12:47:45,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:45,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563052044] [2022-12-13 12:47:45,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:45,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:45,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:45,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:45,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:45,772 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563052044] [2022-12-13 12:47:45,772 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [563052044] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:45,772 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:45,772 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:45,772 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1653216393] [2022-12-13 12:47:45,772 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:45,773 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:45,773 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:45,773 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:47:45,773 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:47:45,773 INFO L87 Difference]: Start difference. First operand 148476 states and 214977 transitions. cyclomatic complexity: 66549 Second operand has 5 states, 5 states have (on average 34.0) internal successors, (170), 5 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:47,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:47,115 INFO L93 Difference]: Finished difference Result 387299 states and 563250 transitions. [2022-12-13 12:47:47,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 387299 states and 563250 transitions. [2022-12-13 12:47:48,440 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 385984 [2022-12-13 12:47:49,089 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 387299 states to 387299 states and 563250 transitions. [2022-12-13 12:47:49,090 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 387299 [2022-12-13 12:47:49,165 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 387299 [2022-12-13 12:47:49,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 387299 states and 563250 transitions. [2022-12-13 12:47:49,270 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:49,270 INFO L218 hiAutomatonCegarLoop]: Abstraction has 387299 states and 563250 transitions. [2022-12-13 12:47:49,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 387299 states and 563250 transitions. [2022-12-13 12:47:51,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 387299 to 152031. [2022-12-13 12:47:51,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 152031 states, 152031 states have (on average 1.4374173688260947) internal successors, (218532), 152030 states have internal predecessors, (218532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:51,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152031 states to 152031 states and 218532 transitions. [2022-12-13 12:47:51,458 INFO L240 hiAutomatonCegarLoop]: Abstraction has 152031 states and 218532 transitions. [2022-12-13 12:47:51,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 12:47:51,459 INFO L428 stractBuchiCegarLoop]: Abstraction has 152031 states and 218532 transitions. [2022-12-13 12:47:51,459 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 12:47:51,459 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 152031 states and 218532 transitions. [2022-12-13 12:47:51,879 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 151528 [2022-12-13 12:47:51,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:51,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:51,880 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:51,880 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:51,881 INFO L748 eck$LassoCheckResult]: Stem: 1087174#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1087175#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 1088159#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1088160#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1089319#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 1087714#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1087715#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1087421#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1087422#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1088878#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1088042#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1088043#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1088700#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1087932#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1087933#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1087330#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1087331#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1087677#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1087883#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 1086923#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1086924#L1342 assume !(0 == ~M_E~0); 1087089#L1342-2 assume !(0 == ~T1_E~0); 1087646#L1347-1 assume !(0 == ~T2_E~0); 1088850#L1352-1 assume !(0 == ~T3_E~0); 1088579#L1357-1 assume !(0 == ~T4_E~0); 1087668#L1362-1 assume !(0 == ~T5_E~0); 1087669#L1367-1 assume !(0 == ~T6_E~0); 1087248#L1372-1 assume !(0 == ~T7_E~0); 1087249#L1377-1 assume !(0 == ~T8_E~0); 1087589#L1382-1 assume !(0 == ~T9_E~0); 1087590#L1387-1 assume !(0 == ~T10_E~0); 1088421#L1392-1 assume !(0 == ~T11_E~0); 1087632#L1397-1 assume !(0 == ~T12_E~0); 1087633#L1402-1 assume !(0 == ~T13_E~0); 1087270#L1407-1 assume !(0 == ~T14_E~0); 1087271#L1412-1 assume !(0 == ~E_1~0); 1088738#L1417-1 assume !(0 == ~E_2~0); 1088739#L1422-1 assume !(0 == ~E_3~0); 1089161#L1427-1 assume !(0 == ~E_4~0); 1087450#L1432-1 assume !(0 == ~E_5~0); 1087451#L1437-1 assume !(0 == ~E_6~0); 1088638#L1442-1 assume !(0 == ~E_7~0); 1088639#L1447-1 assume !(0 == ~E_8~0); 1088414#L1452-1 assume !(0 == ~E_9~0); 1087056#L1457-1 assume !(0 == ~E_10~0); 1087057#L1462-1 assume !(0 == ~E_11~0); 1088678#L1467-1 assume !(0 == ~E_12~0); 1088695#L1472-1 assume !(0 == ~E_13~0); 1088696#L1477-1 assume !(0 == ~E_14~0); 1088350#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1087238#L646 assume !(1 == ~m_pc~0); 1087239#L646-2 is_master_triggered_~__retres1~0#1 := 0; 1087958#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1087959#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1087332#L1666 assume !(0 != activate_threads_~tmp~1#1); 1087333#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1089202#L665 assume !(1 == ~t1_pc~0); 1087825#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1087826#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1088534#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1088535#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 1088210#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1088211#L684 assume !(1 == ~t2_pc~0); 1088258#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1088259#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1087318#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1087319#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 1088859#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1089233#L703 assume !(1 == ~t3_pc~0); 1087475#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1087476#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1088520#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1086893#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 1086894#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1087360#L722 assume !(1 == ~t4_pc~0); 1087550#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1087551#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1087003#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1087004#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 1087990#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1087090#L741 assume !(1 == ~t5_pc~0); 1087091#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1088249#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1088250#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1088314#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 1088315#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1087647#L760 assume !(1 == ~t6_pc~0); 1087474#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1088144#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1088468#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1089145#L1714 assume !(0 != activate_threads_~tmp___5~0#1); 1088117#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1088118#L779 assume 1 == ~t7_pc~0; 1087124#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1086975#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1086976#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1088919#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 1087395#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1087396#L798 assume !(1 == ~t8_pc~0); 1088929#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1088802#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1088803#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1089102#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 1089204#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1086954#L817 assume 1 == ~t9_pc~0; 1086955#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1087752#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1087365#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1087366#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 1087343#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1087344#L836 assume !(1 == ~t10_pc~0); 1087367#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1087295#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1087296#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1087552#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 1087553#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1088819#L855 assume 1 == ~t11_pc~0; 1087954#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1087955#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1088672#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1088411#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 1088217#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1087235#L874 assume !(1 == ~t12_pc~0); 1087236#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1087404#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1086943#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1086944#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 1086929#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1086930#L893 assume 1 == ~t13_pc~0; 1089055#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1087273#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1087588#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1088953#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 1088937#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1088938#L912 assume 1 == ~t14_pc~0; 1088646#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1088647#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1088735#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1087172#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 1087173#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1087979#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 1088481#L1495-2 assume !(1 == ~T1_E~0); 1088482#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1088110#L1505-1 assume !(1 == ~T3_E~0); 1088111#L1510-1 assume !(1 == ~T4_E~0); 1088175#L1515-1 assume !(1 == ~T5_E~0); 1088176#L1520-1 assume !(1 == ~T6_E~0); 1088931#L1525-1 assume !(1 == ~T7_E~0); 1088932#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1135270#L1535-1 assume !(1 == ~T9_E~0); 1135269#L1540-1 assume !(1 == ~T10_E~0); 1135268#L1545-1 assume !(1 == ~T11_E~0); 1135267#L1550-1 assume !(1 == ~T12_E~0); 1135266#L1555-1 assume !(1 == ~T13_E~0); 1087385#L1560-1 assume !(1 == ~T14_E~0); 1087386#L1565-1 assume !(1 == ~E_1~0); 1089174#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1088375#L1575-1 assume !(1 == ~E_3~0); 1087672#L1580-1 assume !(1 == ~E_4~0); 1087673#L1585-1 assume !(1 == ~E_5~0); 1088201#L1590-1 assume !(1 == ~E_6~0); 1087708#L1595-1 assume !(1 == ~E_7~0); 1087709#L1600-1 assume !(1 == ~E_8~0); 1088125#L1605-1 assume !(1 == ~E_9~0); 1088126#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1088785#L1615-1 assume !(1 == ~E_11~0); 1087525#L1620-1 assume !(1 == ~E_12~0); 1087526#L1625-1 assume !(1 == ~E_13~0); 1088415#L1630-1 assume !(1 == ~E_14~0); 1087706#L1635-1 assume { :end_inline_reset_delta_events } true; 1087707#L2017-2 [2022-12-13 12:47:51,881 INFO L750 eck$LassoCheckResult]: Loop: 1087707#L2017-2 assume !false; 1159616#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1159610#L1316 assume !false; 1159414#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1151746#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1151720#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1148076#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1115288#L1115 assume !(0 != eval_~tmp~0#1); 1115289#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1162408#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1162407#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1162406#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1162405#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1162404#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1162403#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1162402#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1162401#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1162400#L1372-3 assume !(0 == ~T7_E~0); 1162399#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1162398#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1162397#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1162396#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1162395#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1162394#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1162393#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 1162392#L1412-3 assume !(0 == ~E_1~0); 1162391#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1162390#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1162389#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1162388#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1162387#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1162386#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1162385#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1162384#L1452-3 assume !(0 == ~E_9~0); 1162383#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1162382#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1162381#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1162380#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1162379#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 1162378#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1162377#L646-42 assume !(1 == ~m_pc~0); 1162376#L646-44 is_master_triggered_~__retres1~0#1 := 0; 1162375#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1162374#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1162373#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1162372#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1162371#L665-42 assume !(1 == ~t1_pc~0); 1162369#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1162368#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1162367#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1162366#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1162365#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1162364#L684-42 assume !(1 == ~t2_pc~0); 1160137#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1162363#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1162362#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1162361#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1162360#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1162359#L703-42 assume !(1 == ~t3_pc~0); 1162357#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1162356#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1162355#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1162354#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1162353#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1162352#L722-42 assume !(1 == ~t4_pc~0); 1162351#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1162350#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1162349#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1162348#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1162347#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1162346#L741-42 assume !(1 == ~t5_pc~0); 1162345#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1162344#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1162343#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1162342#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1162341#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1162340#L760-42 assume 1 == ~t6_pc~0; 1162339#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1162337#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1162335#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1162333#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 1162331#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1162330#L779-42 assume !(1 == ~t7_pc~0); 1162329#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1162327#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1162326#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1162325#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1162324#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1162323#L798-42 assume !(1 == ~t8_pc~0); 1162321#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1162320#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1162319#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1162318#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1162317#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1162316#L817-42 assume !(1 == ~t9_pc~0); 1162315#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1162313#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1162312#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1162311#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1162310#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1162309#L836-42 assume !(1 == ~t10_pc~0); 1162307#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1162306#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1162305#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1162257#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1162255#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1162253#L855-42 assume 1 == ~t11_pc~0; 1162249#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1162247#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1162245#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1162243#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1162241#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1162239#L874-42 assume !(1 == ~t12_pc~0); 1162235#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1162233#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1162231#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1162229#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1162227#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1162225#L893-42 assume 1 == ~t13_pc~0; 1162221#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1162219#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1162217#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1162215#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 1162213#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1162211#L912-42 assume !(1 == ~t14_pc~0); 1162161#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 1162157#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1162154#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1162150#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 1162147#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1162144#L1495-3 assume !(1 == ~M_E~0); 1162140#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1162137#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1115478#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1162131#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1162128#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1162125#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1162075#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1157189#L1530-3 assume !(1 == ~T8_E~0); 1162068#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1162062#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1162058#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1162054#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1162049#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1162045#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 1162041#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1136885#L1570-3 assume !(1 == ~E_2~0); 1162032#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1162028#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1162023#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1162019#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1162015#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1162009#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1162005#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1115426#L1610-3 assume !(1 == ~E_10~0); 1161954#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1160730#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1160728#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1160726#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 1160723#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1160720#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1160704#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1160702#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1160699#L2036 assume !(0 == start_simulation_~tmp~3#1); 1160697#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1160670#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1160666#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1160661#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1160563#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1160556#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1160503#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1159782#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 1087707#L2017-2 [2022-12-13 12:47:51,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:51,882 INFO L85 PathProgramCache]: Analyzing trace with hash -71733652, now seen corresponding path program 1 times [2022-12-13 12:47:51,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:51,882 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215072380] [2022-12-13 12:47:51,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:51,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:51,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:51,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:51,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:51,927 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215072380] [2022-12-13 12:47:51,927 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1215072380] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:51,927 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:51,927 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:51,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1834215010] [2022-12-13 12:47:51,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:51,928 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:51,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:51,928 INFO L85 PathProgramCache]: Analyzing trace with hash -1762012795, now seen corresponding path program 1 times [2022-12-13 12:47:51,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:51,928 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1754737245] [2022-12-13 12:47:51,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:51,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:51,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:51,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:51,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:51,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1754737245] [2022-12-13 12:47:51,957 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1754737245] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:51,957 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:51,957 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:51,957 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1580446381] [2022-12-13 12:47:51,957 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:51,958 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:51,958 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:51,958 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:47:51,958 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:47:51,958 INFO L87 Difference]: Start difference. First operand 152031 states and 218532 transitions. cyclomatic complexity: 66549 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:53,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:47:53,172 INFO L93 Difference]: Finished difference Result 391798 states and 560497 transitions. [2022-12-13 12:47:53,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 391798 states and 560497 transitions. [2022-12-13 12:47:54,488 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 387152 [2022-12-13 12:47:55,133 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 391798 states to 391798 states and 560497 transitions. [2022-12-13 12:47:55,133 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 391798 [2022-12-13 12:47:55,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 391798 [2022-12-13 12:47:55,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 391798 states and 560497 transitions. [2022-12-13 12:47:55,394 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:47:55,394 INFO L218 hiAutomatonCegarLoop]: Abstraction has 391798 states and 560497 transitions. [2022-12-13 12:47:55,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 391798 states and 560497 transitions. [2022-12-13 12:47:57,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 391798 to 292054. [2022-12-13 12:47:57,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 292054 states, 292054 states have (on average 1.4336287124983735) internal successors, (418697), 292053 states have internal predecessors, (418697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:47:58,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 292054 states to 292054 states and 418697 transitions. [2022-12-13 12:47:58,534 INFO L240 hiAutomatonCegarLoop]: Abstraction has 292054 states and 418697 transitions. [2022-12-13 12:47:58,534 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:47:58,535 INFO L428 stractBuchiCegarLoop]: Abstraction has 292054 states and 418697 transitions. [2022-12-13 12:47:58,535 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 12:47:58,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 292054 states and 418697 transitions. [2022-12-13 12:47:59,277 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 291328 [2022-12-13 12:47:59,277 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:47:59,277 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:47:59,278 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:59,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:47:59,279 INFO L748 eck$LassoCheckResult]: Stem: 1631009#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1631010#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 1631944#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1631945#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1632916#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 1631535#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1631536#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1631252#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1631253#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1632591#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1631835#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1631836#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1632443#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1631739#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1631740#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1631164#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1631165#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1631500#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1631691#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 1630762#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1630763#L1342 assume !(0 == ~M_E~0); 1630926#L1342-2 assume !(0 == ~T1_E~0); 1631469#L1347-1 assume !(0 == ~T2_E~0); 1632569#L1352-1 assume !(0 == ~T3_E~0); 1632332#L1357-1 assume !(0 == ~T4_E~0); 1631491#L1362-1 assume !(0 == ~T5_E~0); 1631492#L1367-1 assume !(0 == ~T6_E~0); 1631085#L1372-1 assume !(0 == ~T7_E~0); 1631086#L1377-1 assume !(0 == ~T8_E~0); 1631414#L1382-1 assume !(0 == ~T9_E~0); 1631415#L1387-1 assume !(0 == ~T10_E~0); 1632197#L1392-1 assume !(0 == ~T11_E~0); 1631455#L1397-1 assume !(0 == ~T12_E~0); 1631456#L1402-1 assume !(0 == ~T13_E~0); 1631105#L1407-1 assume !(0 == ~T14_E~0); 1631106#L1412-1 assume !(0 == ~E_1~0); 1632480#L1417-1 assume !(0 == ~E_2~0); 1632481#L1422-1 assume !(0 == ~E_3~0); 1632813#L1427-1 assume !(0 == ~E_4~0); 1631282#L1432-1 assume !(0 == ~E_5~0); 1631283#L1437-1 assume !(0 == ~E_6~0); 1632389#L1442-1 assume !(0 == ~E_7~0); 1632390#L1447-1 assume !(0 == ~E_8~0); 1632190#L1452-1 assume !(0 == ~E_9~0); 1630895#L1457-1 assume !(0 == ~E_10~0); 1630896#L1462-1 assume !(0 == ~E_11~0); 1632422#L1467-1 assume !(0 == ~E_12~0); 1632438#L1472-1 assume !(0 == ~E_13~0); 1632439#L1477-1 assume !(0 == ~E_14~0); 1632125#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1631073#L646 assume !(1 == ~m_pc~0); 1631074#L646-2 is_master_triggered_~__retres1~0#1 := 0; 1631766#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1631767#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1631166#L1666 assume !(0 != activate_threads_~tmp~1#1); 1631167#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1632850#L665 assume !(1 == ~t1_pc~0); 1631641#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1631642#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1632299#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1632300#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 1631993#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1631994#L684 assume !(1 == ~t2_pc~0); 1632039#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1632040#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1631154#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1631155#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 1632575#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1632864#L703 assume !(1 == ~t3_pc~0); 1631306#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1631307#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1632286#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1630732#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 1630733#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1631193#L722 assume !(1 == ~t4_pc~0); 1631378#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1631379#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1630842#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1630843#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 1631790#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1630927#L741 assume !(1 == ~t5_pc~0); 1630928#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1632031#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1632032#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1632089#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 1632090#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1631470#L760 assume !(1 == ~t6_pc~0); 1631305#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1631931#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1632242#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1632801#L1714 assume !(0 != activate_threads_~tmp___5~0#1); 1631905#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1631906#L779 assume !(1 == ~t7_pc~0); 1632648#L779-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1630814#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1630815#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1632627#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 1631227#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1631228#L798 assume !(1 == ~t8_pc~0); 1632637#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1632530#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1632531#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1632773#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 1632852#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1630795#L817 assume 1 == ~t9_pc~0; 1630796#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1631571#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1631197#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1631198#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 1631177#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1631178#L836 assume !(1 == ~t10_pc~0); 1631199#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1631130#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1631131#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1631380#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 1631381#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1632546#L855 assume 1 == ~t11_pc~0; 1631761#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1631762#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1632416#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1632187#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 1631999#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1631070#L874 assume !(1 == ~t12_pc~0); 1631071#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1631236#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1630782#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1630783#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 1630768#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1630769#L893 assume 1 == ~t13_pc~0; 1632746#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1631108#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1631413#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1632658#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 1632645#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1632646#L912 assume 1 == ~t14_pc~0; 1632396#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1632397#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1632479#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1631007#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 1631008#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1631782#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 1632254#L1495-2 assume !(1 == ~T1_E~0); 1632255#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1631899#L1505-1 assume !(1 == ~T3_E~0); 1631900#L1510-1 assume !(1 == ~T4_E~0); 1631960#L1515-1 assume !(1 == ~T5_E~0); 1631961#L1520-1 assume !(1 == ~T6_E~0); 1632640#L1525-1 assume !(1 == ~T7_E~0); 1632641#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1631171#L1535-1 assume !(1 == ~T9_E~0); 1631172#L1540-1 assume !(1 == ~T10_E~0); 1630693#L1545-1 assume !(1 == ~T11_E~0); 1630694#L1550-1 assume !(1 == ~T12_E~0); 1630935#L1555-1 assume !(1 == ~T13_E~0); 1630936#L1560-1 assume !(1 == ~T14_E~0); 1632829#L1565-1 assume !(1 == ~E_1~0); 1632830#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1632917#L1575-1 assume !(1 == ~E_3~0); 1631495#L1580-1 assume !(1 == ~E_4~0); 1631496#L1585-1 assume !(1 == ~E_5~0); 1632303#L1590-1 assume !(1 == ~E_6~0); 1632304#L1595-1 assume !(1 == ~E_7~0); 1632907#L1600-1 assume !(1 == ~E_8~0); 1632908#L1605-1 assume !(1 == ~E_9~0); 1687368#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1696954#L1615-1 assume !(1 == ~E_11~0); 1696953#L1620-1 assume !(1 == ~E_12~0); 1696952#L1625-1 assume !(1 == ~E_13~0); 1696951#L1630-1 assume !(1 == ~E_14~0); 1696950#L1635-1 assume { :end_inline_reset_delta_events } true; 1696939#L2017-2 [2022-12-13 12:47:59,279 INFO L750 eck$LassoCheckResult]: Loop: 1696939#L2017-2 assume !false; 1696932#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1696923#L1316 assume !false; 1696921#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1696899#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1696884#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1696878#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1696867#L1115 assume !(0 != eval_~tmp~0#1); 1696868#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1698200#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1698198#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1698196#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1698194#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1698192#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1698190#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1698188#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1698186#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1698184#L1372-3 assume !(0 == ~T7_E~0); 1698182#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1698180#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1698178#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1698176#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1698174#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1698172#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1698170#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 1698168#L1412-3 assume !(0 == ~E_1~0); 1698166#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1698164#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1698162#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1698160#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1698158#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1698156#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1698154#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1698152#L1452-3 assume !(0 == ~E_9~0); 1698150#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1698147#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1698145#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1698143#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1698141#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 1698139#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1698137#L646-42 assume !(1 == ~m_pc~0); 1698136#L646-44 is_master_triggered_~__retres1~0#1 := 0; 1698134#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1698132#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1698130#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1698128#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1698126#L665-42 assume 1 == ~t1_pc~0; 1698123#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1698120#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1698118#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1698116#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1698114#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1698112#L684-42 assume !(1 == ~t2_pc~0); 1691291#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1698109#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1698107#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1698105#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1698103#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1698101#L703-42 assume 1 == ~t3_pc~0; 1698099#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1698096#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1698094#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1698092#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1698090#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1698088#L722-42 assume !(1 == ~t4_pc~0); 1698085#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1698083#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1698081#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1698078#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1698076#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1698074#L741-42 assume !(1 == ~t5_pc~0); 1698073#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1698071#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1698069#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1698067#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1698065#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1698063#L760-42 assume 1 == ~t6_pc~0; 1698059#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1698057#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1698055#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1698053#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 1698050#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1698048#L779-42 assume !(1 == ~t7_pc~0); 1667197#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1698044#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1698042#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1698040#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1698038#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1698036#L798-42 assume 1 == ~t8_pc~0; 1698033#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1698030#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1698028#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1698026#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1698024#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1698022#L817-42 assume !(1 == ~t9_pc~0); 1698019#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1698016#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1698014#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1698012#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1698010#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1698008#L836-42 assume 1 == ~t10_pc~0; 1698005#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1698002#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1698000#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1697998#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1697996#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1697994#L855-42 assume !(1 == ~t11_pc~0); 1697991#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1697988#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1697986#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1697984#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1697982#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1697980#L874-42 assume 1 == ~t12_pc~0; 1697977#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1697974#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1697972#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1697970#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1697968#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1697966#L893-42 assume 1 == ~t13_pc~0; 1697963#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1697962#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1697961#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1697960#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 1697958#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1697956#L912-42 assume 1 == ~t14_pc~0; 1697953#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1697951#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1697950#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1697948#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 1697946#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1697944#L1495-3 assume !(1 == ~M_E~0); 1697942#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1697940#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1680750#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1697936#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1697935#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1697934#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1697932#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1696365#L1530-3 assume !(1 == ~T8_E~0); 1697929#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1697927#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1697925#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1697923#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1697921#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1697918#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 1697916#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1697912#L1570-3 assume !(1 == ~E_2~0); 1697910#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1697908#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1697906#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1697905#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1697903#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1697901#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1697899#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1687441#L1610-3 assume !(1 == ~E_10~0); 1697896#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1697893#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1697891#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1697889#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 1697887#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1697884#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1697868#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1697866#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1697863#L2036 assume !(0 == start_simulation_~tmp~3#1); 1697860#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1697442#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1697052#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1696984#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1696973#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1696964#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1696955#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1696949#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 1696939#L2017-2 [2022-12-13 12:47:59,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:59,280 INFO L85 PathProgramCache]: Analyzing trace with hash -1348886325, now seen corresponding path program 1 times [2022-12-13 12:47:59,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:59,280 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098943120] [2022-12-13 12:47:59,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:59,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:59,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:59,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:59,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:59,328 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1098943120] [2022-12-13 12:47:59,328 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1098943120] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:59,328 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:59,328 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:59,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258542778] [2022-12-13 12:47:59,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:59,328 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:47:59,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:47:59,329 INFO L85 PathProgramCache]: Analyzing trace with hash 646959018, now seen corresponding path program 1 times [2022-12-13 12:47:59,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:47:59,329 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434539242] [2022-12-13 12:47:59,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:47:59,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:47:59,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:47:59,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:47:59,358 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:47:59,358 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [434539242] [2022-12-13 12:47:59,358 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [434539242] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:47:59,359 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:47:59,359 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:47:59,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [540342677] [2022-12-13 12:47:59,359 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:47:59,359 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:47:59,359 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:47:59,360 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:47:59,360 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:47:59,360 INFO L87 Difference]: Start difference. First operand 292054 states and 418697 transitions. cyclomatic complexity: 126691 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:48:01,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:48:01,514 INFO L93 Difference]: Finished difference Result 749685 states and 1069942 transitions. [2022-12-13 12:48:01,514 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 749685 states and 1069942 transitions. [2022-12-13 12:48:03,942 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 740704 [2022-12-13 12:48:05,127 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 749685 states to 749685 states and 1069942 transitions. [2022-12-13 12:48:05,127 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 749685 [2022-12-13 12:48:05,392 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 749685 [2022-12-13 12:48:05,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 749685 states and 1069942 transitions. [2022-12-13 12:48:05,791 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:48:05,791 INFO L218 hiAutomatonCegarLoop]: Abstraction has 749685 states and 1069942 transitions. [2022-12-13 12:48:06,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 749685 states and 1069942 transitions. [2022-12-13 12:48:10,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 749685 to 560565. [2022-12-13 12:48:10,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 560565 states, 560565 states have (on average 1.4301677771534078) internal successors, (801702), 560564 states have internal predecessors, (801702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:48:11,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 560565 states to 560565 states and 801702 transitions. [2022-12-13 12:48:11,889 INFO L240 hiAutomatonCegarLoop]: Abstraction has 560565 states and 801702 transitions. [2022-12-13 12:48:11,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:48:11,890 INFO L428 stractBuchiCegarLoop]: Abstraction has 560565 states and 801702 transitions. [2022-12-13 12:48:11,890 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 12:48:11,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 560565 states and 801702 transitions. [2022-12-13 12:48:13,268 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 559392 [2022-12-13 12:48:13,268 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:48:13,268 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:48:13,270 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:48:13,270 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:48:13,270 INFO L748 eck$LassoCheckResult]: Stem: 2672757#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 2672758#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 2673706#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2673707#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2674711#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 2673290#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2673291#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2673002#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2673003#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2674375#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2673596#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2673597#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2674213#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2673497#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2673498#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2672912#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2672913#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 2673253#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 2673450#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 2672510#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2672511#L1342 assume !(0 == ~M_E~0); 2672673#L1342-2 assume !(0 == ~T1_E~0); 2673220#L1347-1 assume !(0 == ~T2_E~0); 2674349#L1352-1 assume !(0 == ~T3_E~0); 2674095#L1357-1 assume !(0 == ~T4_E~0); 2673242#L1362-1 assume !(0 == ~T5_E~0); 2673243#L1367-1 assume !(0 == ~T6_E~0); 2672834#L1372-1 assume !(0 == ~T7_E~0); 2672835#L1377-1 assume !(0 == ~T8_E~0); 2673165#L1382-1 assume !(0 == ~T9_E~0); 2673166#L1387-1 assume !(0 == ~T10_E~0); 2673958#L1392-1 assume !(0 == ~T11_E~0); 2673206#L1397-1 assume !(0 == ~T12_E~0); 2673207#L1402-1 assume !(0 == ~T13_E~0); 2672852#L1407-1 assume !(0 == ~T14_E~0); 2672853#L1412-1 assume !(0 == ~E_1~0); 2674254#L1417-1 assume !(0 == ~E_2~0); 2674255#L1422-1 assume !(0 == ~E_3~0); 2674603#L1427-1 assume !(0 == ~E_4~0); 2673032#L1432-1 assume !(0 == ~E_5~0); 2673033#L1437-1 assume !(0 == ~E_6~0); 2674150#L1442-1 assume !(0 == ~E_7~0); 2674151#L1447-1 assume !(0 == ~E_8~0); 2673951#L1452-1 assume !(0 == ~E_9~0); 2672644#L1457-1 assume !(0 == ~E_10~0); 2672645#L1462-1 assume !(0 == ~E_11~0); 2674189#L1467-1 assume !(0 == ~E_12~0); 2674207#L1472-1 assume !(0 == ~E_13~0); 2674208#L1477-1 assume !(0 == ~E_14~0); 2673893#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2672824#L646 assume !(1 == ~m_pc~0); 2672825#L646-2 is_master_triggered_~__retres1~0#1 := 0; 2673524#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2673525#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2672914#L1666 assume !(0 != activate_threads_~tmp~1#1); 2672915#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2674639#L665 assume !(1 == ~t1_pc~0); 2673396#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2673397#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2674063#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2674064#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 2673755#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2673756#L684 assume !(1 == ~t2_pc~0); 2673800#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2673801#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2672902#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2672903#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 2674358#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2674657#L703 assume !(1 == ~t3_pc~0); 2673057#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2673058#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2674049#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2672481#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 2672482#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2672944#L722 assume !(1 == ~t4_pc~0); 2673129#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2673130#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2672589#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2672590#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 2673550#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2672674#L741 assume !(1 == ~t5_pc~0); 2672675#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2673790#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2673791#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2673857#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 2673858#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2673221#L760 assume !(1 == ~t6_pc~0); 2673056#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2673692#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2674004#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2674589#L1714 assume !(0 != activate_threads_~tmp___5~0#1); 2673665#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2673666#L779 assume !(1 == ~t7_pc~0); 2674430#L779-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2672561#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2672562#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2674411#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 2672976#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2672977#L798 assume !(1 == ~t8_pc~0); 2674420#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2674304#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2674305#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2674560#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 2674641#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2672543#L817 assume !(1 == ~t9_pc~0); 2672544#L817-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2673328#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2672946#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2672947#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 2672926#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2672927#L836 assume !(1 == ~t10_pc~0); 2672948#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2672877#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2672878#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2673131#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 2673132#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2674319#L855 assume 1 == ~t11_pc~0; 2673520#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2673521#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2674176#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2673949#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 2673761#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2672817#L874 assume !(1 == ~t12_pc~0); 2672818#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 2672985#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2672530#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2672531#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 2672518#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 2672519#L893 assume 1 == ~t13_pc~0; 2674519#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 2672855#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 2673164#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 2674439#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 2674427#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 2674428#L912 assume 1 == ~t14_pc~0; 2674158#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 2674159#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 2674250#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 2672755#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 2672756#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2673543#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 2674016#L1495-2 assume !(1 == ~T1_E~0); 2674017#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2673659#L1505-1 assume !(1 == ~T3_E~0); 2673660#L1510-1 assume !(1 == ~T4_E~0); 2673721#L1515-1 assume !(1 == ~T5_E~0); 2673722#L1520-1 assume !(1 == ~T6_E~0); 2674422#L1525-1 assume !(1 == ~T7_E~0); 2674423#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2672919#L1535-1 assume !(1 == ~T9_E~0); 2672920#L1540-1 assume !(1 == ~T10_E~0); 2672442#L1545-1 assume !(1 == ~T11_E~0); 2672443#L1550-1 assume !(1 == ~T12_E~0); 2672682#L1555-1 assume !(1 == ~T13_E~0); 2672683#L1560-1 assume !(1 == ~T14_E~0); 2674615#L1565-1 assume !(1 == ~E_1~0); 2674616#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2786095#L1575-1 assume !(1 == ~E_3~0); 2786094#L1580-1 assume !(1 == ~E_4~0); 2786092#L1585-1 assume !(1 == ~E_5~0); 2786090#L1590-1 assume !(1 == ~E_6~0); 2786088#L1595-1 assume !(1 == ~E_7~0); 2786086#L1600-1 assume !(1 == ~E_8~0); 2786084#L1605-1 assume !(1 == ~E_9~0); 2786082#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2786081#L1615-1 assume !(1 == ~E_11~0); 2786080#L1620-1 assume !(1 == ~E_12~0); 2786079#L1625-1 assume !(1 == ~E_13~0); 2786078#L1630-1 assume !(1 == ~E_14~0); 2786077#L1635-1 assume { :end_inline_reset_delta_events } true; 2786069#L2017-2 [2022-12-13 12:48:13,270 INFO L750 eck$LassoCheckResult]: Loop: 2786069#L2017-2 assume !false; 2785654#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2785649#L1316 assume !false; 2785647#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 2785636#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 2785620#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 2785614#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2785608#L1115 assume !(0 != eval_~tmp~0#1); 2785609#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2806696#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2806692#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2806688#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2806684#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2806678#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2806674#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2806670#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2806666#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2806662#L1372-3 assume !(0 == ~T7_E~0); 2806660#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2806658#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2806654#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2806650#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2806646#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 2806642#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 2806638#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 2806634#L1412-3 assume !(0 == ~E_1~0); 2806630#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2806624#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2806620#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2806616#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2806612#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2806607#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2806605#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2806603#L1452-3 assume !(0 == ~E_9~0); 2806599#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2806595#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2806592#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 2806589#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 2806585#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 2806581#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2806577#L646-42 assume !(1 == ~m_pc~0); 2806571#L646-44 is_master_triggered_~__retres1~0#1 := 0; 2806567#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2806563#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2806559#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2806554#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2806552#L665-42 assume 1 == ~t1_pc~0; 2806550#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2806546#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2806542#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2806539#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2806536#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2788470#L684-42 assume !(1 == ~t2_pc~0); 2788468#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 2788466#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2788463#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2788461#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2788459#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2788457#L703-42 assume !(1 == ~t3_pc~0); 2788451#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 2788449#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2788447#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2788445#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2788443#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2788441#L722-42 assume !(1 == ~t4_pc~0); 2788438#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 2788436#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2788434#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2788432#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2788430#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2788428#L741-42 assume !(1 == ~t5_pc~0); 2788425#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 2788423#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2788421#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2788419#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2788417#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2788415#L760-42 assume !(1 == ~t6_pc~0); 2788410#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 2788408#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2788406#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2788399#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 2788397#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2788395#L779-42 assume !(1 == ~t7_pc~0); 2769899#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 2788392#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2788390#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2788387#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2788385#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2788383#L798-42 assume !(1 == ~t8_pc~0); 2786335#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 2786333#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2786331#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2786329#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2786326#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2786324#L817-42 assume !(1 == ~t9_pc~0); 2759340#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 2786321#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2786319#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2786317#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2786314#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2786312#L836-42 assume 1 == ~t10_pc~0; 2786310#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2786307#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2786305#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2786303#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2786300#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2786298#L855-42 assume !(1 == ~t11_pc~0); 2786296#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 2786293#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2786291#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2786289#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2786287#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2786286#L874-42 assume !(1 == ~t12_pc~0); 2786284#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 2786283#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2786282#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2786281#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 2786279#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 2786277#L893-42 assume 1 == ~t13_pc~0; 2786274#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 2786272#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 2786271#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 2786269#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 2786267#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 2786265#L912-42 assume 1 == ~t14_pc~0; 2786262#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 2786260#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 2786258#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 2786256#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 2786255#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2786253#L1495-3 assume !(1 == ~M_E~0); 2786251#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2786249#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2767425#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2786244#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2786242#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2786241#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2786240#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2784227#L1530-3 assume !(1 == ~T8_E~0); 2786238#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2786236#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2786234#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2786232#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2786230#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 2786228#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 2786226#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2774446#L1570-3 assume !(1 == ~E_2~0); 2786222#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2786220#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2786218#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2786216#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2786214#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2786213#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2786210#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2786206#L1610-3 assume !(1 == ~E_10~0); 2786204#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2786202#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 2786200#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 2786198#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 2786195#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 2786192#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 2786176#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 2786174#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 2786171#L2036 assume !(0 == start_simulation_~tmp~3#1); 2786168#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 2786124#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 2786122#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 2786119#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 2786117#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2786115#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2786113#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 2786076#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 2786069#L2017-2 [2022-12-13 12:48:13,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:48:13,271 INFO L85 PathProgramCache]: Analyzing trace with hash 1768106410, now seen corresponding path program 1 times [2022-12-13 12:48:13,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:48:13,271 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [38269432] [2022-12-13 12:48:13,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:48:13,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:48:13,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:48:13,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:48:13,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:48:13,337 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [38269432] [2022-12-13 12:48:13,337 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [38269432] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:48:13,337 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:48:13,337 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:48:13,337 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299286617] [2022-12-13 12:48:13,337 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:48:13,338 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:48:13,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:48:13,338 INFO L85 PathProgramCache]: Analyzing trace with hash 91783782, now seen corresponding path program 1 times [2022-12-13 12:48:13,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:48:13,338 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611794392] [2022-12-13 12:48:13,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:48:13,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:48:13,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:48:13,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:48:13,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:48:13,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1611794392] [2022-12-13 12:48:13,373 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1611794392] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:48:13,373 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:48:13,374 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:48:13,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1239731440] [2022-12-13 12:48:13,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:48:13,374 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:48:13,374 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:48:13,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:48:13,375 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:48:13,375 INFO L87 Difference]: Start difference. First operand 560565 states and 801702 transitions. cyclomatic complexity: 241185 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:48:17,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:48:17,681 INFO L93 Difference]: Finished difference Result 1432340 states and 2039779 transitions. [2022-12-13 12:48:17,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1432340 states and 2039779 transitions. [2022-12-13 12:48:22,553 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 1414720 [2022-12-13 12:48:25,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1432340 states to 1432340 states and 2039779 transitions. [2022-12-13 12:48:25,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1432340 [2022-12-13 12:48:25,669 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1432340 [2022-12-13 12:48:25,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1432340 states and 2039779 transitions. [2022-12-13 12:48:26,322 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:48:26,323 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1432340 states and 2039779 transitions. [2022-12-13 12:48:27,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1432340 states and 2039779 transitions. [2022-12-13 12:48:34,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1432340 to 1074708. [2022-12-13 12:48:35,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1074708 states, 1074708 states have (on average 1.4270248290698497) internal successors, (1533635), 1074707 states have internal predecessors, (1533635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:48:38,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1074708 states to 1074708 states and 1533635 transitions. [2022-12-13 12:48:38,080 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1074708 states and 1533635 transitions. [2022-12-13 12:48:38,080 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:48:38,080 INFO L428 stractBuchiCegarLoop]: Abstraction has 1074708 states and 1533635 transitions. [2022-12-13 12:48:38,081 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 12:48:38,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1074708 states and 1533635 transitions. [2022-12-13 12:48:40,187 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 1072640 [2022-12-13 12:48:40,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:48:40,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:48:40,190 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:48:40,190 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:48:40,190 INFO L748 eck$LassoCheckResult]: Stem: 4665673#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 4665674#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 4666630#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4666631#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4667682#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 4666212#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4666213#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4665919#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4665920#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4667314#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4666516#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4666517#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4667142#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4666419#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4666420#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4665827#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 4665828#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 4666177#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 4666370#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 4665425#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4665426#L1342 assume !(0 == ~M_E~0); 4665590#L1342-2 assume !(0 == ~T1_E~0); 4666142#L1347-1 assume !(0 == ~T2_E~0); 4667290#L1352-1 assume !(0 == ~T3_E~0); 4667016#L1357-1 assume !(0 == ~T4_E~0); 4666166#L1362-1 assume !(0 == ~T5_E~0); 4666167#L1367-1 assume !(0 == ~T6_E~0); 4665749#L1372-1 assume !(0 == ~T7_E~0); 4665750#L1377-1 assume !(0 == ~T8_E~0); 4666086#L1382-1 assume !(0 == ~T9_E~0); 4666087#L1387-1 assume !(0 == ~T10_E~0); 4666877#L1392-1 assume !(0 == ~T11_E~0); 4666128#L1397-1 assume !(0 == ~T12_E~0); 4666129#L1402-1 assume !(0 == ~T13_E~0); 4665767#L1407-1 assume !(0 == ~T14_E~0); 4665768#L1412-1 assume !(0 == ~E_1~0); 4667179#L1417-1 assume !(0 == ~E_2~0); 4667180#L1422-1 assume !(0 == ~E_3~0); 4667558#L1427-1 assume !(0 == ~E_4~0); 4665952#L1432-1 assume !(0 == ~E_5~0); 4665953#L1437-1 assume !(0 == ~E_6~0); 4667070#L1442-1 assume !(0 == ~E_7~0); 4667071#L1447-1 assume !(0 == ~E_8~0); 4666870#L1452-1 assume !(0 == ~E_9~0); 4665558#L1457-1 assume !(0 == ~E_10~0); 4665559#L1462-1 assume !(0 == ~E_11~0); 4667115#L1467-1 assume !(0 == ~E_12~0); 4667137#L1472-1 assume !(0 == ~E_13~0); 4667138#L1477-1 assume !(0 == ~E_14~0); 4666815#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4665739#L646 assume !(1 == ~m_pc~0); 4665740#L646-2 is_master_triggered_~__retres1~0#1 := 0; 4666444#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4666445#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4665829#L1666 assume !(0 != activate_threads_~tmp~1#1); 4665830#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4667597#L665 assume !(1 == ~t1_pc~0); 4666317#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4666318#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4666983#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4666984#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 4666684#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4666685#L684 assume !(1 == ~t2_pc~0); 4666729#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4666730#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4665817#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4665818#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 4667298#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4667621#L703 assume !(1 == ~t3_pc~0); 4665976#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4665977#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4666970#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4665396#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 4665397#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4665857#L722 assume !(1 == ~t4_pc~0); 4666050#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4666051#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4665505#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4665506#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 4666470#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4665591#L741 assume !(1 == ~t5_pc~0); 4665592#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4666720#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4666721#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4666781#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 4666782#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4666143#L760 assume !(1 == ~t6_pc~0); 4665975#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4666616#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4666925#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4667544#L1714 assume !(0 != activate_threads_~tmp___5~0#1); 4666586#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4666587#L779 assume !(1 == ~t7_pc~0); 4667374#L779-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4665476#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4665477#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4667353#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 4665891#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4665892#L798 assume !(1 == ~t8_pc~0); 4667362#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4667240#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4667241#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4667518#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 4667599#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4665458#L817 assume !(1 == ~t9_pc~0); 4665459#L817-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4666247#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4665861#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4665862#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 4665840#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4665841#L836 assume !(1 == ~t10_pc~0); 4665863#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4665793#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4665794#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4666052#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 4666053#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4667255#L855 assume !(1 == ~t11_pc~0); 4666905#L855-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4666906#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4667103#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4666868#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 4666690#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4665732#L874 assume !(1 == ~t12_pc~0); 4665733#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4665903#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4665445#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4665446#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 4665433#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4665434#L893 assume 1 == ~t13_pc~0; 4667476#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4665770#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4666085#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4667382#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 4667371#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 4667372#L912 assume 1 == ~t14_pc~0; 4667077#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 4667078#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 4667178#is_transmit14_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4665671#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 4665672#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4666464#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 4666935#L1495-2 assume !(1 == ~T1_E~0); 4666936#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4667552#L1505-1 assume !(1 == ~T3_E~0); 4667678#L1510-1 assume !(1 == ~T4_E~0); 4667679#L1515-1 assume !(1 == ~T5_E~0); 4667584#L1520-1 assume !(1 == ~T6_E~0); 4667585#L1525-1 assume !(1 == ~T7_E~0); 4862830#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4862828#L1535-1 assume !(1 == ~T9_E~0); 4862826#L1540-1 assume !(1 == ~T10_E~0); 4862824#L1545-1 assume !(1 == ~T11_E~0); 4862822#L1550-1 assume !(1 == ~T12_E~0); 4862820#L1555-1 assume !(1 == ~T13_E~0); 4862818#L1560-1 assume !(1 == ~T14_E~0); 4862815#L1565-1 assume !(1 == ~E_1~0); 4862813#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 4862811#L1575-1 assume !(1 == ~E_3~0); 4862809#L1580-1 assume !(1 == ~E_4~0); 4862807#L1585-1 assume !(1 == ~E_5~0); 4862805#L1590-1 assume !(1 == ~E_6~0); 4862803#L1595-1 assume !(1 == ~E_7~0); 4862793#L1600-1 assume !(1 == ~E_8~0); 4862792#L1605-1 assume !(1 == ~E_9~0); 4862789#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4862788#L1615-1 assume !(1 == ~E_11~0); 4862787#L1620-1 assume !(1 == ~E_12~0); 4862786#L1625-1 assume !(1 == ~E_13~0); 4862785#L1630-1 assume !(1 == ~E_14~0); 4862784#L1635-1 assume { :end_inline_reset_delta_events } true; 4862782#L2017-2 [2022-12-13 12:48:40,190 INFO L750 eck$LassoCheckResult]: Loop: 4862782#L2017-2 assume !false; 4862193#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4862188#L1316 assume !false; 4862186#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 4861434#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4861421#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4861419#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4861416#L1115 assume !(0 != eval_~tmp~0#1); 4861417#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4912461#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4912460#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4912459#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4912458#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4912457#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4912456#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4912455#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4912454#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4912453#L1372-3 assume !(0 == ~T7_E~0); 4912452#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4912451#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4912450#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4912449#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4912448#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4912447#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4912446#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 4912445#L1412-3 assume !(0 == ~E_1~0); 4912444#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4912443#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4912442#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4912441#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4912440#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4912439#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4912438#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4912437#L1452-3 assume !(0 == ~E_9~0); 4912436#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4912435#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4912434#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4912433#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 4912432#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 4912431#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4912430#L646-42 assume !(1 == ~m_pc~0); 4912429#L646-44 is_master_triggered_~__retres1~0#1 := 0; 4912428#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4912427#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4912426#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4912425#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4912424#L665-42 assume !(1 == ~t1_pc~0); 4912422#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 4912421#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4912420#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4912419#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4912418#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4912417#L684-42 assume !(1 == ~t2_pc~0); 4906424#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 4912416#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4912413#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4912411#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4912409#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4912407#L703-42 assume !(1 == ~t3_pc~0); 4912404#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4912402#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4912399#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4912397#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4912395#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4912393#L722-42 assume !(1 == ~t4_pc~0); 4912391#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 4912389#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4912387#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4912385#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4912383#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4912381#L741-42 assume !(1 == ~t5_pc~0); 4912378#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4912375#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4912372#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4912369#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4912366#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4912363#L760-42 assume 1 == ~t6_pc~0; 4912360#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4912355#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4912350#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4912298#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 4912288#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4864092#L779-42 assume !(1 == ~t7_pc~0); 4864090#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4864089#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4864087#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4864085#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4864083#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4864081#L798-42 assume !(1 == ~t8_pc~0); 4864078#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 4864075#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4864073#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4864071#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4864069#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4864067#L817-42 assume !(1 == ~t9_pc~0); 4860295#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 4864063#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4864061#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4864059#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4864057#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4864055#L836-42 assume !(1 == ~t10_pc~0); 4864052#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 4864049#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4864047#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4864045#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4864043#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4864041#L855-42 assume !(1 == ~t11_pc~0); 4814417#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 4864040#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4864039#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4864038#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4864037#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4864036#L874-42 assume !(1 == ~t12_pc~0); 4864034#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4864033#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4864032#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4864031#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4864030#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4864029#L893-42 assume 1 == ~t13_pc~0; 4864027#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4864011#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4864009#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4864007#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 4864004#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 4864002#L912-42 assume 1 == ~t14_pc~0; 4863999#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 4863997#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 4863995#is_transmit14_triggered_returnLabel#15 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4863993#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 4863992#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4863990#L1495-3 assume !(1 == ~M_E~0); 4863988#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4863986#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4863982#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4863980#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4863977#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4863975#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4863973#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4863969#L1530-3 assume !(1 == ~T8_E~0); 4863967#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4863965#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4863964#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4863962#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4863960#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4863958#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 4863956#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4863952#L1570-3 assume !(1 == ~E_2~0); 4863949#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4863947#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4863945#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4863943#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4863941#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4863939#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4863936#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4863932#L1610-3 assume !(1 == ~E_10~0); 4863930#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4863928#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4863926#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4863924#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 4863921#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 4863653#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4863636#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4863631#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4863615#L2036 assume !(0 == start_simulation_~tmp~3#1); 4863610#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 4863167#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4863165#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4863163#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 4863161#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4863159#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4863157#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 4862783#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 4862782#L2017-2 [2022-12-13 12:48:40,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:48:40,191 INFO L85 PathProgramCache]: Analyzing trace with hash 1870907657, now seen corresponding path program 1 times [2022-12-13 12:48:40,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:48:40,191 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1115318521] [2022-12-13 12:48:40,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:48:40,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:48:40,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:48:40,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:48:40,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:48:40,227 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1115318521] [2022-12-13 12:48:40,227 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1115318521] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:48:40,227 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:48:40,227 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:48:40,227 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2074476929] [2022-12-13 12:48:40,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:48:40,227 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:48:40,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:48:40,228 INFO L85 PathProgramCache]: Analyzing trace with hash -77854779, now seen corresponding path program 1 times [2022-12-13 12:48:40,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:48:40,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589606071] [2022-12-13 12:48:40,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:48:40,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:48:40,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:48:40,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:48:40,433 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:48:40,433 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1589606071] [2022-12-13 12:48:40,433 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1589606071] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:48:40,433 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:48:40,433 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:48:40,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [26063953] [2022-12-13 12:48:40,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:48:40,433 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:48:40,434 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:48:40,434 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:48:40,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:48:40,434 INFO L87 Difference]: Start difference. First operand 1074708 states and 1533635 transitions. cyclomatic complexity: 458975 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:48:46,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:48:46,201 INFO L93 Difference]: Finished difference Result 2140051 states and 3040320 transitions. [2022-12-13 12:48:46,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2140051 states and 3040320 transitions. [2022-12-13 12:48:54,012 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 2134656 [2022-12-13 12:48:58,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2140051 states to 2140051 states and 3040320 transitions. [2022-12-13 12:48:58,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2140051 [2022-12-13 12:48:59,140 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2140051 [2022-12-13 12:48:59,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2140051 states and 3040320 transitions. [2022-12-13 12:48:59,715 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:48:59,715 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2140051 states and 3040320 transitions. [2022-12-13 12:49:01,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2140051 states and 3040320 transitions.