./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/uthash-2.0.2/uthash_BER_test10-3.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/uthash-2.0.2/uthash_BER_test10-3.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5577528c45849c92d31dcecadbfe6524610e7683d1e420d37b6f0ce59c6c59b8 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 16:54:50,281 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 16:54:50,282 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 16:54:50,299 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 16:54:50,300 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 16:54:50,301 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 16:54:50,302 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 16:54:50,303 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 16:54:50,305 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 16:54:50,306 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 16:54:50,306 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 16:54:50,307 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 16:54:50,308 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 16:54:50,309 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 16:54:50,310 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 16:54:50,311 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 16:54:50,311 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 16:54:50,312 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 16:54:50,314 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 16:54:50,315 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 16:54:50,317 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 16:54:50,318 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 16:54:50,319 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 16:54:50,320 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 16:54:50,323 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 16:54:50,323 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 16:54:50,323 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 16:54:50,324 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 16:54:50,325 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 16:54:50,325 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 16:54:50,326 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 16:54:50,326 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 16:54:50,327 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 16:54:50,327 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 16:54:50,328 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 16:54:50,329 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 16:54:50,329 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 16:54:50,329 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 16:54:50,330 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 16:54:50,330 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 16:54:50,331 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 16:54:50,332 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 16:54:50,352 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 16:54:50,352 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 16:54:50,352 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 16:54:50,352 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 16:54:50,353 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 16:54:50,354 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 16:54:50,354 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 16:54:50,354 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 16:54:50,354 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 16:54:50,354 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 16:54:50,354 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 16:54:50,355 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 16:54:50,355 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 16:54:50,355 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 16:54:50,355 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 16:54:50,355 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 16:54:50,355 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 16:54:50,356 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 16:54:50,356 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 16:54:50,356 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 16:54:50,356 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 16:54:50,356 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 16:54:50,356 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 16:54:50,357 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 16:54:50,357 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 16:54:50,357 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 16:54:50,357 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 16:54:50,357 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 16:54:50,357 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 16:54:50,358 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 16:54:50,358 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 16:54:50,359 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 16:54:50,359 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5577528c45849c92d31dcecadbfe6524610e7683d1e420d37b6f0ce59c6c59b8 [2022-12-13 16:54:50,525 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 16:54:50,545 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 16:54:50,547 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 16:54:50,548 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 16:54:50,549 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 16:54:50,550 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/uthash-2.0.2/uthash_BER_test10-3.i [2022-12-13 16:54:53,113 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 16:54:53,371 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 16:54:53,371 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/sv-benchmarks/c/uthash-2.0.2/uthash_BER_test10-3.i [2022-12-13 16:54:53,385 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/data/08480367b/1de24d506ece47228ef3817e732e3752/FLAG2113da26f [2022-12-13 16:54:53,396 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/data/08480367b/1de24d506ece47228ef3817e732e3752 [2022-12-13 16:54:53,398 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 16:54:53,399 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 16:54:53,400 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 16:54:53,400 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 16:54:53,404 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 16:54:53,405 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 04:54:53" (1/1) ... [2022-12-13 16:54:53,406 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6aa4ccc9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:53, skipping insertion in model container [2022-12-13 16:54:53,406 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 04:54:53" (1/1) ... [2022-12-13 16:54:53,413 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 16:54:53,468 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 16:54:53,785 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/sv-benchmarks/c/uthash-2.0.2/uthash_BER_test10-3.i[33022,33035] [2022-12-13 16:54:53,865 WARN L623 FunctionHandler]: Unknown extern function memcmp [2022-12-13 16:54:53,876 WARN L623 FunctionHandler]: Unknown extern function memcmp [2022-12-13 16:54:53,885 WARN L623 FunctionHandler]: Unknown extern function memcmp [2022-12-13 16:54:53,896 WARN L623 FunctionHandler]: Unknown extern function memcmp [2022-12-13 16:54:53,911 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 16:54:53,920 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 16:54:53,939 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/sv-benchmarks/c/uthash-2.0.2/uthash_BER_test10-3.i[33022,33035] [2022-12-13 16:54:53,978 WARN L623 FunctionHandler]: Unknown extern function memcmp [2022-12-13 16:54:53,985 WARN L623 FunctionHandler]: Unknown extern function memcmp [2022-12-13 16:54:53,992 WARN L623 FunctionHandler]: Unknown extern function memcmp [2022-12-13 16:54:54,014 WARN L623 FunctionHandler]: Unknown extern function memcmp [2022-12-13 16:54:54,035 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 16:54:54,061 INFO L208 MainTranslator]: Completed translation [2022-12-13 16:54:54,062 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:54 WrapperNode [2022-12-13 16:54:54,062 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 16:54:54,063 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 16:54:54,063 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 16:54:54,063 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 16:54:54,068 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:54" (1/1) ... [2022-12-13 16:54:54,097 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:54" (1/1) ... [2022-12-13 16:54:54,160 INFO L138 Inliner]: procedures = 177, calls = 623, calls flagged for inlining = 10, calls inlined = 22, statements flattened = 2597 [2022-12-13 16:54:54,160 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 16:54:54,160 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 16:54:54,161 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 16:54:54,161 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 16:54:54,168 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:54" (1/1) ... [2022-12-13 16:54:54,168 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:54" (1/1) ... [2022-12-13 16:54:54,178 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:54" (1/1) ... [2022-12-13 16:54:54,179 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:54" (1/1) ... [2022-12-13 16:54:54,225 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:54" (1/1) ... [2022-12-13 16:54:54,236 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:54" (1/1) ... [2022-12-13 16:54:54,241 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:54" (1/1) ... [2022-12-13 16:54:54,247 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:54" (1/1) ... [2022-12-13 16:54:54,255 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 16:54:54,255 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 16:54:54,255 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 16:54:54,255 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 16:54:54,256 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:54" (1/1) ... [2022-12-13 16:54:54,261 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 16:54:54,268 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 16:54:54,279 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 16:54:54,281 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 16:54:54,309 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-12-13 16:54:54,310 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-12-13 16:54:54,310 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2022-12-13 16:54:54,310 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2022-12-13 16:54:54,310 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-12-13 16:54:54,310 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 16:54:54,310 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-12-13 16:54:54,310 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-12-13 16:54:54,310 INFO L130 BoogieDeclarations]: Found specification of procedure memcmp [2022-12-13 16:54:54,310 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-12-13 16:54:54,310 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-12-13 16:54:54,310 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 16:54:54,310 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 16:54:54,310 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 16:54:54,537 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 16:54:54,538 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 16:54:54,541 WARN L816 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2022-12-13 16:54:56,652 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 16:54:56,659 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 16:54:56,660 INFO L300 CfgBuilder]: Removed 168 assume(true) statements. [2022-12-13 16:54:56,661 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 04:54:56 BoogieIcfgContainer [2022-12-13 16:54:56,662 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 16:54:56,662 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 16:54:56,662 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 16:54:56,665 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 16:54:56,665 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:54:56,666 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 04:54:53" (1/3) ... [2022-12-13 16:54:56,666 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@669d7a78 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 04:54:56, skipping insertion in model container [2022-12-13 16:54:56,666 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:54:56,666 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:54:54" (2/3) ... [2022-12-13 16:54:56,667 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@669d7a78 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 04:54:56, skipping insertion in model container [2022-12-13 16:54:56,667 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:54:56,667 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 04:54:56" (3/3) ... [2022-12-13 16:54:56,668 INFO L332 chiAutomizerObserver]: Analyzing ICFG uthash_BER_test10-3.i [2022-12-13 16:54:56,714 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 16:54:56,714 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 16:54:56,714 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 16:54:56,714 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 16:54:56,714 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 16:54:56,714 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 16:54:56,714 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 16:54:56,714 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 16:54:56,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 505 states, 497 states have (on average 1.7062374245472838) internal successors, (848), 497 states have internal predecessors, (848), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2022-12-13 16:54:56,747 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 432 [2022-12-13 16:54:56,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:56,748 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:56,753 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 16:54:56,753 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:56,753 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 16:54:56,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 505 states, 497 states have (on average 1.7062374245472838) internal successors, (848), 497 states have internal predecessors, (848), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2022-12-13 16:54:56,764 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 432 [2022-12-13 16:54:56,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:56,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:56,764 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 16:54:56,764 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:56,770 INFO L748 eck$LassoCheckResult]: Stem: 151#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);~count_int_int~0 := 0; 425#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc8#1.base, main_#t~malloc8#1.offset, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem20#1, main_#t~mem22#1, main_#t~mem21#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~switch25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc37#1.base, main_#t~malloc37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~memset~res40#1.base, main_#t~memset~res40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~malloc46#1.base, main_#t~malloc46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~post70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem75#1, main_#t~mem74#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~short78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1, main_#t~malloc81#1.base, main_#t~malloc81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~memset~res86#1.base, main_#t~memset~res86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem91#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem95#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1, main_#t~pre109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1, main_#t~post114#1, main_#t~mem118#1, main_#t~mem116#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem117#1, main_#t~mem119#1, main_#t~post120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~post97#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~post130#1, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~ite140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem145#1, main_#t~mem144#1, main_#t~mem146#1, main_#t~mem147#1, main_#t~mem149#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem151#1, main_#t~mem153#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem155#1, main_#t~switch156#1, main_#t~mem157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~malloc168#1.base, main_#t~malloc168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~memset~res171#1.base, main_#t~memset~res171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~malloc177#1.base, main_#t~malloc177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~memset~res184#1.base, main_#t~memset~res184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1.base, main_#t~mem186#1.offset, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1, main_#t~post195#1, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_#t~mem200#1, main_#t~post201#1, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem206#1, main_#t~mem205#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1, main_#t~short209#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1, main_#t~malloc212#1.base, main_#t~malloc212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~memset~res217#1.base, main_#t~memset~res217#1.offset, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem222#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem226#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem237#1, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~pre240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1, main_#t~post245#1, main_#t~mem249#1, main_#t~mem247#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem248#1, main_#t~mem250#1, main_#t~post251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~post228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1, main_#t~post261#1, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem268#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1, main_#t~ite271#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_~_he_bkt~1#1, main_~_he_bkt_i~1#1, main_~_he_thh~1#1.base, main_~_he_thh~1#1.offset, main_~_he_hh_nxt~1#1.base, main_~_he_hh_nxt~1#1.offset, main_~#_he_new_buckets~1#1.base, main_~#_he_new_buckets~1#1.offset, main_~_he_newbkt~1#1.base, main_~_he_newbkt~1#1.offset, main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, main_~_ha_bkt~1#1, main_~_ha_hashv~1#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem276#1, main_#t~mem275#1, main_#t~mem277#1, main_#t~mem278#1, main_#t~mem280#1, main_#t~mem279#1, main_#t~mem281#1, main_#t~mem282#1, main_#t~mem284#1, main_#t~mem283#1, main_#t~mem285#1, main_#t~mem286#1, main_#t~switch287#1, main_#t~mem288#1, main_#t~mem289#1, main_#t~mem290#1, main_#t~mem291#1, main_#t~mem292#1, main_#t~mem293#1, main_#t~mem294#1, main_#t~mem295#1, main_#t~mem296#1, main_#t~mem297#1, main_#t~mem298#1, main_~_hj_i~2#1, main_~_hj_j~2#1, main_~_hj_k~2#1, main_~_hj_key~2#1.base, main_~_hj_key~2#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1.base, main_#t~mem302#1.offset, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1, main_#t~mem309#1, main_#t~mem310#1, main_#t~short311#1, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~ret313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem318#1, main_#t~mem320#1, main_#t~mem319#1, main_#t~mem321#1, main_#t~mem322#1, main_#t~mem324#1, main_#t~mem323#1, main_#t~mem325#1, main_#t~mem326#1, main_#t~mem328#1, main_#t~mem327#1, main_#t~mem329#1, main_#t~mem330#1, main_#t~switch331#1, main_#t~mem332#1, main_#t~mem333#1, main_#t~mem334#1, main_#t~mem335#1, main_#t~mem336#1, main_#t~mem337#1, main_#t~mem338#1, main_#t~mem339#1, main_#t~mem340#1, main_#t~mem341#1, main_#t~mem342#1, main_~_hj_i~3#1, main_~_hj_j~3#1, main_~_hj_k~3#1, main_~_hj_key~3#1.base, main_~_hj_key~3#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1.base, main_#t~mem349#1.offset, main_#t~mem350#1.base, main_#t~mem350#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_#t~mem352#1, main_#t~mem353#1, main_#t~mem354#1, main_#t~short355#1, main_#t~mem356#1.base, main_#t~mem356#1.offset, main_#t~ret357#1, main_#t~mem358#1.base, main_#t~mem358#1.offset, main_#t~mem359#1.base, main_#t~mem359#1.offset, main_#t~mem360#1.base, main_#t~mem360#1.offset, main_#t~mem361#1, main_~_hf_bkt~1#1, main_~_hf_hashv~1#1, main_#t~mem362#1, main_#t~mem364#1, main_#t~mem363#1, main_#t~mem365#1, main_#t~mem366#1, main_#t~mem368#1, main_#t~mem367#1, main_#t~mem369#1, main_#t~mem370#1, main_#t~mem372#1, main_#t~mem371#1, main_#t~mem373#1, main_#t~mem374#1, main_#t~switch375#1, main_#t~mem376#1, main_#t~mem377#1, main_#t~mem378#1, main_#t~mem379#1, main_#t~mem380#1, main_#t~mem381#1, main_#t~mem382#1, main_#t~mem383#1, main_#t~mem384#1, main_#t~mem385#1, main_#t~mem386#1, main_~_hj_i~4#1, main_~_hj_j~4#1, main_~_hj_k~4#1, main_~_hj_key~4#1.base, main_~_hj_key~4#1.offset, main_#t~mem387#1.base, main_#t~mem387#1.offset, main_#t~mem388#1, main_#t~mem389#1.base, main_#t~mem389#1.offset, main_#t~mem390#1.base, main_#t~mem390#1.offset, main_#t~mem391#1.base, main_#t~mem391#1.offset, main_#t~mem392#1.base, main_#t~mem392#1.offset, main_#t~mem393#1.base, main_#t~mem393#1.offset, main_#t~mem394#1.base, main_#t~mem394#1.offset, main_#t~mem395#1.base, main_#t~mem395#1.offset, main_#t~mem396#1, main_#t~mem397#1, main_#t~mem398#1, main_#t~short399#1, main_#t~mem400#1.base, main_#t~mem400#1.offset, main_#t~ret401#1, main_#t~mem402#1.base, main_#t~mem402#1.offset, main_#t~mem403#1.base, main_#t~mem403#1.offset, main_#t~mem404#1.base, main_#t~mem404#1.offset, main_#t~mem405#1, main_~_hf_bkt~2#1, main_~_hf_hashv~2#1, main_#t~mem406#1, main_#t~mem408#1, main_#t~mem407#1, main_#t~mem409#1, main_#t~mem410#1, main_#t~mem412#1, main_#t~mem411#1, main_#t~mem413#1, main_#t~mem414#1, main_#t~mem416#1, main_#t~mem415#1, main_#t~mem417#1, main_#t~mem418#1, main_#t~switch419#1, main_#t~mem420#1, main_#t~mem421#1, main_#t~mem422#1, main_#t~mem423#1, main_#t~mem424#1, main_#t~mem425#1, main_#t~mem426#1, main_#t~mem427#1, main_#t~mem428#1, main_#t~mem429#1, main_#t~mem430#1, main_~_hj_i~5#1, main_~_hj_j~5#1, main_~_hj_k~5#1, main_~_hj_key~5#1.base, main_~_hj_key~5#1.offset, main_#t~mem431#1.base, main_#t~mem431#1.offset, main_#t~mem432#1, main_#t~mem433#1.base, main_#t~mem433#1.offset, main_#t~mem434#1.base, main_#t~mem434#1.offset, main_#t~mem435#1.base, main_#t~mem435#1.offset, main_#t~mem436#1.base, main_#t~mem436#1.offset, main_#t~mem437#1.base, main_#t~mem437#1.offset, main_#t~mem438#1.base, main_#t~mem438#1.offset, main_#t~mem439#1.base, main_#t~mem439#1.offset, main_#t~mem440#1, main_#t~mem441#1, main_#t~mem442#1, main_#t~short443#1, main_#t~mem444#1.base, main_#t~mem444#1.offset, main_#t~ret445#1, main_#t~mem446#1.base, main_#t~mem446#1.offset, main_#t~mem447#1.base, main_#t~mem447#1.offset, main_#t~mem448#1.base, main_#t~mem448#1.offset, main_#t~mem449#1, main_~_hf_bkt~3#1, main_~_hf_hashv~3#1, main_#t~mem450#1, main_#t~ite452#1.base, main_#t~ite452#1.offset, main_#t~mem451#1.base, main_#t~mem451#1.offset, main_#t~mem455#1.base, main_#t~mem455#1.offset, main_#t~mem456#1.base, main_#t~mem456#1.offset, main_#t~short457#1, main_#t~mem458#1.base, main_#t~mem458#1.offset, main_#t~mem459#1.base, main_#t~mem459#1.offset, main_#t~mem460#1.base, main_#t~mem460#1.offset, main_#t~mem461#1.base, main_#t~mem461#1.offset, main_#t~mem462#1.base, main_#t~mem462#1.offset, main_#t~mem463#1.base, main_#t~mem463#1.offset, main_#t~mem464#1.base, main_#t~mem464#1.offset, main_#t~mem465#1.base, main_#t~mem465#1.offset, main_#t~mem466#1, main_#t~mem467#1.base, main_#t~mem467#1.offset, main_#t~mem468#1.base, main_#t~mem468#1.offset, main_#t~mem469#1.base, main_#t~mem469#1.offset, main_#t~mem470#1, main_#t~mem471#1.base, main_#t~mem471#1.offset, main_#t~mem472#1.base, main_#t~mem472#1.offset, main_#t~mem473#1.base, main_#t~mem473#1.offset, main_#t~mem474#1.base, main_#t~mem474#1.offset, main_#t~mem475#1.base, main_#t~mem475#1.offset, main_#t~mem476#1, main_#t~mem477#1.base, main_#t~mem477#1.offset, main_#t~mem480#1, main_#t~mem478#1.base, main_#t~mem478#1.offset, main_#t~mem479#1, main_#t~mem481#1.base, main_#t~mem481#1.offset, main_#t~mem482#1.base, main_#t~mem482#1.offset, main_#t~mem483#1, main_#t~post484#1, main_#t~mem485#1.base, main_#t~mem485#1.offset, main_#t~mem486#1.base, main_#t~mem486#1.offset, main_#t~mem487#1.base, main_#t~mem487#1.offset, main_#t~mem488#1.base, main_#t~mem488#1.offset, main_#t~mem489#1.base, main_#t~mem489#1.offset, main_#t~mem490#1.base, main_#t~mem490#1.offset, main_#t~mem491#1.base, main_#t~mem491#1.offset, main_#t~mem492#1.base, main_#t~mem492#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem493#1.base, main_#t~mem493#1.offset, main_#t~mem494#1, main_#t~post495#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem496#1.base, main_#t~mem496#1.offset, main_#t~mem497#1.base, main_#t~mem497#1.offset, main_#t~short498#1, main_#t~mem499#1.base, main_#t~mem499#1.offset, main_#t~mem500#1.base, main_#t~mem500#1.offset, main_#t~mem501#1.base, main_#t~mem501#1.offset, main_#t~mem502#1.base, main_#t~mem502#1.offset, main_#t~mem503#1.base, main_#t~mem503#1.offset, main_#t~mem504#1.base, main_#t~mem504#1.offset, main_#t~mem505#1.base, main_#t~mem505#1.offset, main_#t~mem506#1.base, main_#t~mem506#1.offset, main_#t~mem507#1, main_#t~mem508#1.base, main_#t~mem508#1.offset, main_#t~mem509#1.base, main_#t~mem509#1.offset, main_#t~mem510#1.base, main_#t~mem510#1.offset, main_#t~mem511#1, main_#t~mem512#1.base, main_#t~mem512#1.offset, main_#t~mem513#1.base, main_#t~mem513#1.offset, main_#t~mem514#1.base, main_#t~mem514#1.offset, main_#t~mem515#1.base, main_#t~mem515#1.offset, main_#t~mem516#1.base, main_#t~mem516#1.offset, main_#t~mem517#1, main_#t~mem518#1.base, main_#t~mem518#1.offset, main_#t~mem521#1, main_#t~mem519#1.base, main_#t~mem519#1.offset, main_#t~mem520#1, main_#t~mem522#1.base, main_#t~mem522#1.offset, main_#t~mem523#1.base, main_#t~mem523#1.offset, main_#t~mem524#1, main_#t~post525#1, main_#t~mem526#1.base, main_#t~mem526#1.offset, main_#t~mem527#1.base, main_#t~mem527#1.offset, main_#t~mem528#1.base, main_#t~mem528#1.offset, main_#t~mem529#1.base, main_#t~mem529#1.offset, main_#t~mem530#1.base, main_#t~mem530#1.offset, main_#t~mem531#1.base, main_#t~mem531#1.offset, main_#t~mem532#1.base, main_#t~mem532#1.offset, main_#t~mem533#1.base, main_#t~mem533#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem534#1.base, main_#t~mem534#1.offset, main_#t~mem535#1, main_#t~post536#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite454#1.base, main_#t~ite454#1.offset, main_#t~mem453#1.base, main_#t~mem453#1.offset, main_~usertmp~0#1.base, main_~usertmp~0#1.offset, main_~userstmp~0#1.base, main_~userstmp~0#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~altusers~0#1.base, main_~altusers~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~altusers~0#1.base, main_~altusers~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 267#L733-4true [2022-12-13 16:54:56,771 INFO L750 eck$LassoCheckResult]: Loop: 267#L733-4true call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 2#L733-1true assume !!(main_#t~mem7#1 < 1000);havoc main_#t~mem7#1;call main_#t~malloc8#1.base, main_#t~malloc8#1.offset := #Ultimate.allocOnHeap(72);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc8#1.base, main_#t~malloc8#1.offset;havoc main_#t~malloc8#1.base, main_#t~malloc8#1.offset; 497#L735true assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false; 109#L735-2true call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem9#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem9#1;call main_#t~mem10#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem11#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem10#1 * main_#t~mem11#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem10#1;havoc main_#t~mem11#1;call main_#t~mem12#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 432#L740true assume !(main_#t~mem12#1 < 10);havoc main_#t~mem12#1; 376#L743-120true assume !true; 65#L733-3true call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post6#1 := main_#t~mem5#1;call write~int(1 + main_#t~post6#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem5#1;havoc main_#t~post6#1; 267#L733-4true [2022-12-13 16:54:56,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:56,775 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 1 times [2022-12-13 16:54:56,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:56,782 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [691302198] [2022-12-13 16:54:56,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:56,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:56,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:56,871 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:54:56,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:56,920 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:54:56,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:56,922 INFO L85 PathProgramCache]: Analyzing trace with hash -1529490928, now seen corresponding path program 1 times [2022-12-13 16:54:56,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:56,922 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303604823] [2022-12-13 16:54:56,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:56,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:56,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:56,956 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:56,956 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303604823] [2022-12-13 16:54:56,957 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2022-12-13 16:54:56,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1302631170] [2022-12-13 16:54:56,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:56,957 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 16:54:56,957 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 16:54:56,959 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 16:54:56,960 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-12-13 16:54:57,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:57,081 INFO L263 TraceCheckSpWp]: Trace formula consists of 77 conjuncts, 1 conjunts are in the unsatisfiable core [2022-12-13 16:54:57,082 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-13 16:54:57,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:57,097 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-13 16:54:57,098 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1302631170] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:57,098 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:57,098 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:54:57,099 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845196527] [2022-12-13 16:54:57,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:57,103 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:54:57,103 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:54:57,130 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 16:54:57,131 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 16:54:57,133 INFO L87 Difference]: Start difference. First operand has 505 states, 497 states have (on average 1.7062374245472838) internal successors, (848), 497 states have internal predecessors, (848), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) Second operand has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:57,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:54:57,164 INFO L93 Difference]: Finished difference Result 505 states and 669 transitions. [2022-12-13 16:54:57,165 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 505 states and 669 transitions. [2022-12-13 16:54:57,171 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 264 [2022-12-13 16:54:57,180 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 505 states to 501 states and 665 transitions. [2022-12-13 16:54:57,181 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 501 [2022-12-13 16:54:57,182 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 501 [2022-12-13 16:54:57,183 INFO L73 IsDeterministic]: Start isDeterministic. Operand 501 states and 665 transitions. [2022-12-13 16:54:57,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:54:57,186 INFO L218 hiAutomatonCegarLoop]: Abstraction has 501 states and 665 transitions. [2022-12-13 16:54:57,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 501 states and 665 transitions. [2022-12-13 16:54:57,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 501 to 501. [2022-12-13 16:54:57,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 501 states, 494 states have (on average 1.3218623481781377) internal successors, (653), 493 states have internal predecessors, (653), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2022-12-13 16:54:57,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 501 states to 501 states and 665 transitions. [2022-12-13 16:54:57,232 INFO L240 hiAutomatonCegarLoop]: Abstraction has 501 states and 665 transitions. [2022-12-13 16:54:57,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 16:54:57,236 INFO L428 stractBuchiCegarLoop]: Abstraction has 501 states and 665 transitions. [2022-12-13 16:54:57,236 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 16:54:57,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 501 states and 665 transitions. [2022-12-13 16:54:57,240 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 264 [2022-12-13 16:54:57,240 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:57,240 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:57,241 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 16:54:57,241 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:57,241 INFO L748 eck$LassoCheckResult]: Stem: 1302#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);~count_int_int~0 := 0; 1303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc8#1.base, main_#t~malloc8#1.offset, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem20#1, main_#t~mem22#1, main_#t~mem21#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~switch25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc37#1.base, main_#t~malloc37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~memset~res40#1.base, main_#t~memset~res40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~malloc46#1.base, main_#t~malloc46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~post70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem75#1, main_#t~mem74#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~short78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1, main_#t~malloc81#1.base, main_#t~malloc81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~memset~res86#1.base, main_#t~memset~res86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem91#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem95#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1, main_#t~pre109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1, main_#t~post114#1, main_#t~mem118#1, main_#t~mem116#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem117#1, main_#t~mem119#1, main_#t~post120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~post97#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~post130#1, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~ite140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem145#1, main_#t~mem144#1, main_#t~mem146#1, main_#t~mem147#1, main_#t~mem149#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem151#1, main_#t~mem153#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem155#1, main_#t~switch156#1, main_#t~mem157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~malloc168#1.base, main_#t~malloc168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~memset~res171#1.base, main_#t~memset~res171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~malloc177#1.base, main_#t~malloc177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~memset~res184#1.base, main_#t~memset~res184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1.base, main_#t~mem186#1.offset, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1, main_#t~post195#1, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_#t~mem200#1, main_#t~post201#1, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem206#1, main_#t~mem205#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1, main_#t~short209#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1, main_#t~malloc212#1.base, main_#t~malloc212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~memset~res217#1.base, main_#t~memset~res217#1.offset, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem222#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem226#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem237#1, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~pre240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1, main_#t~post245#1, main_#t~mem249#1, main_#t~mem247#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem248#1, main_#t~mem250#1, main_#t~post251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~post228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1, main_#t~post261#1, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem268#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1, main_#t~ite271#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_~_he_bkt~1#1, main_~_he_bkt_i~1#1, main_~_he_thh~1#1.base, main_~_he_thh~1#1.offset, main_~_he_hh_nxt~1#1.base, main_~_he_hh_nxt~1#1.offset, main_~#_he_new_buckets~1#1.base, main_~#_he_new_buckets~1#1.offset, main_~_he_newbkt~1#1.base, main_~_he_newbkt~1#1.offset, main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, main_~_ha_bkt~1#1, main_~_ha_hashv~1#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem276#1, main_#t~mem275#1, main_#t~mem277#1, main_#t~mem278#1, main_#t~mem280#1, main_#t~mem279#1, main_#t~mem281#1, main_#t~mem282#1, main_#t~mem284#1, main_#t~mem283#1, main_#t~mem285#1, main_#t~mem286#1, main_#t~switch287#1, main_#t~mem288#1, main_#t~mem289#1, main_#t~mem290#1, main_#t~mem291#1, main_#t~mem292#1, main_#t~mem293#1, main_#t~mem294#1, main_#t~mem295#1, main_#t~mem296#1, main_#t~mem297#1, main_#t~mem298#1, main_~_hj_i~2#1, main_~_hj_j~2#1, main_~_hj_k~2#1, main_~_hj_key~2#1.base, main_~_hj_key~2#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1.base, main_#t~mem302#1.offset, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1, main_#t~mem309#1, main_#t~mem310#1, main_#t~short311#1, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~ret313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem318#1, main_#t~mem320#1, main_#t~mem319#1, main_#t~mem321#1, main_#t~mem322#1, main_#t~mem324#1, main_#t~mem323#1, main_#t~mem325#1, main_#t~mem326#1, main_#t~mem328#1, main_#t~mem327#1, main_#t~mem329#1, main_#t~mem330#1, main_#t~switch331#1, main_#t~mem332#1, main_#t~mem333#1, main_#t~mem334#1, main_#t~mem335#1, main_#t~mem336#1, main_#t~mem337#1, main_#t~mem338#1, main_#t~mem339#1, main_#t~mem340#1, main_#t~mem341#1, main_#t~mem342#1, main_~_hj_i~3#1, main_~_hj_j~3#1, main_~_hj_k~3#1, main_~_hj_key~3#1.base, main_~_hj_key~3#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1.base, main_#t~mem349#1.offset, main_#t~mem350#1.base, main_#t~mem350#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_#t~mem352#1, main_#t~mem353#1, main_#t~mem354#1, main_#t~short355#1, main_#t~mem356#1.base, main_#t~mem356#1.offset, main_#t~ret357#1, main_#t~mem358#1.base, main_#t~mem358#1.offset, main_#t~mem359#1.base, main_#t~mem359#1.offset, main_#t~mem360#1.base, main_#t~mem360#1.offset, main_#t~mem361#1, main_~_hf_bkt~1#1, main_~_hf_hashv~1#1, main_#t~mem362#1, main_#t~mem364#1, main_#t~mem363#1, main_#t~mem365#1, main_#t~mem366#1, main_#t~mem368#1, main_#t~mem367#1, main_#t~mem369#1, main_#t~mem370#1, main_#t~mem372#1, main_#t~mem371#1, main_#t~mem373#1, main_#t~mem374#1, main_#t~switch375#1, main_#t~mem376#1, main_#t~mem377#1, main_#t~mem378#1, main_#t~mem379#1, main_#t~mem380#1, main_#t~mem381#1, main_#t~mem382#1, main_#t~mem383#1, main_#t~mem384#1, main_#t~mem385#1, main_#t~mem386#1, main_~_hj_i~4#1, main_~_hj_j~4#1, main_~_hj_k~4#1, main_~_hj_key~4#1.base, main_~_hj_key~4#1.offset, main_#t~mem387#1.base, main_#t~mem387#1.offset, main_#t~mem388#1, main_#t~mem389#1.base, main_#t~mem389#1.offset, main_#t~mem390#1.base, main_#t~mem390#1.offset, main_#t~mem391#1.base, main_#t~mem391#1.offset, main_#t~mem392#1.base, main_#t~mem392#1.offset, main_#t~mem393#1.base, main_#t~mem393#1.offset, main_#t~mem394#1.base, main_#t~mem394#1.offset, main_#t~mem395#1.base, main_#t~mem395#1.offset, main_#t~mem396#1, main_#t~mem397#1, main_#t~mem398#1, main_#t~short399#1, main_#t~mem400#1.base, main_#t~mem400#1.offset, main_#t~ret401#1, main_#t~mem402#1.base, main_#t~mem402#1.offset, main_#t~mem403#1.base, main_#t~mem403#1.offset, main_#t~mem404#1.base, main_#t~mem404#1.offset, main_#t~mem405#1, main_~_hf_bkt~2#1, main_~_hf_hashv~2#1, main_#t~mem406#1, main_#t~mem408#1, main_#t~mem407#1, main_#t~mem409#1, main_#t~mem410#1, main_#t~mem412#1, main_#t~mem411#1, main_#t~mem413#1, main_#t~mem414#1, main_#t~mem416#1, main_#t~mem415#1, main_#t~mem417#1, main_#t~mem418#1, main_#t~switch419#1, main_#t~mem420#1, main_#t~mem421#1, main_#t~mem422#1, main_#t~mem423#1, main_#t~mem424#1, main_#t~mem425#1, main_#t~mem426#1, main_#t~mem427#1, main_#t~mem428#1, main_#t~mem429#1, main_#t~mem430#1, main_~_hj_i~5#1, main_~_hj_j~5#1, main_~_hj_k~5#1, main_~_hj_key~5#1.base, main_~_hj_key~5#1.offset, main_#t~mem431#1.base, main_#t~mem431#1.offset, main_#t~mem432#1, main_#t~mem433#1.base, main_#t~mem433#1.offset, main_#t~mem434#1.base, main_#t~mem434#1.offset, main_#t~mem435#1.base, main_#t~mem435#1.offset, main_#t~mem436#1.base, main_#t~mem436#1.offset, main_#t~mem437#1.base, main_#t~mem437#1.offset, main_#t~mem438#1.base, main_#t~mem438#1.offset, main_#t~mem439#1.base, main_#t~mem439#1.offset, main_#t~mem440#1, main_#t~mem441#1, main_#t~mem442#1, main_#t~short443#1, main_#t~mem444#1.base, main_#t~mem444#1.offset, main_#t~ret445#1, main_#t~mem446#1.base, main_#t~mem446#1.offset, main_#t~mem447#1.base, main_#t~mem447#1.offset, main_#t~mem448#1.base, main_#t~mem448#1.offset, main_#t~mem449#1, main_~_hf_bkt~3#1, main_~_hf_hashv~3#1, main_#t~mem450#1, main_#t~ite452#1.base, main_#t~ite452#1.offset, main_#t~mem451#1.base, main_#t~mem451#1.offset, main_#t~mem455#1.base, main_#t~mem455#1.offset, main_#t~mem456#1.base, main_#t~mem456#1.offset, main_#t~short457#1, main_#t~mem458#1.base, main_#t~mem458#1.offset, main_#t~mem459#1.base, main_#t~mem459#1.offset, main_#t~mem460#1.base, main_#t~mem460#1.offset, main_#t~mem461#1.base, main_#t~mem461#1.offset, main_#t~mem462#1.base, main_#t~mem462#1.offset, main_#t~mem463#1.base, main_#t~mem463#1.offset, main_#t~mem464#1.base, main_#t~mem464#1.offset, main_#t~mem465#1.base, main_#t~mem465#1.offset, main_#t~mem466#1, main_#t~mem467#1.base, main_#t~mem467#1.offset, main_#t~mem468#1.base, main_#t~mem468#1.offset, main_#t~mem469#1.base, main_#t~mem469#1.offset, main_#t~mem470#1, main_#t~mem471#1.base, main_#t~mem471#1.offset, main_#t~mem472#1.base, main_#t~mem472#1.offset, main_#t~mem473#1.base, main_#t~mem473#1.offset, main_#t~mem474#1.base, main_#t~mem474#1.offset, main_#t~mem475#1.base, main_#t~mem475#1.offset, main_#t~mem476#1, main_#t~mem477#1.base, main_#t~mem477#1.offset, main_#t~mem480#1, main_#t~mem478#1.base, main_#t~mem478#1.offset, main_#t~mem479#1, main_#t~mem481#1.base, main_#t~mem481#1.offset, main_#t~mem482#1.base, main_#t~mem482#1.offset, main_#t~mem483#1, main_#t~post484#1, main_#t~mem485#1.base, main_#t~mem485#1.offset, main_#t~mem486#1.base, main_#t~mem486#1.offset, main_#t~mem487#1.base, main_#t~mem487#1.offset, main_#t~mem488#1.base, main_#t~mem488#1.offset, main_#t~mem489#1.base, main_#t~mem489#1.offset, main_#t~mem490#1.base, main_#t~mem490#1.offset, main_#t~mem491#1.base, main_#t~mem491#1.offset, main_#t~mem492#1.base, main_#t~mem492#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem493#1.base, main_#t~mem493#1.offset, main_#t~mem494#1, main_#t~post495#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem496#1.base, main_#t~mem496#1.offset, main_#t~mem497#1.base, main_#t~mem497#1.offset, main_#t~short498#1, main_#t~mem499#1.base, main_#t~mem499#1.offset, main_#t~mem500#1.base, main_#t~mem500#1.offset, main_#t~mem501#1.base, main_#t~mem501#1.offset, main_#t~mem502#1.base, main_#t~mem502#1.offset, main_#t~mem503#1.base, main_#t~mem503#1.offset, main_#t~mem504#1.base, main_#t~mem504#1.offset, main_#t~mem505#1.base, main_#t~mem505#1.offset, main_#t~mem506#1.base, main_#t~mem506#1.offset, main_#t~mem507#1, main_#t~mem508#1.base, main_#t~mem508#1.offset, main_#t~mem509#1.base, main_#t~mem509#1.offset, main_#t~mem510#1.base, main_#t~mem510#1.offset, main_#t~mem511#1, main_#t~mem512#1.base, main_#t~mem512#1.offset, main_#t~mem513#1.base, main_#t~mem513#1.offset, main_#t~mem514#1.base, main_#t~mem514#1.offset, main_#t~mem515#1.base, main_#t~mem515#1.offset, main_#t~mem516#1.base, main_#t~mem516#1.offset, main_#t~mem517#1, main_#t~mem518#1.base, main_#t~mem518#1.offset, main_#t~mem521#1, main_#t~mem519#1.base, main_#t~mem519#1.offset, main_#t~mem520#1, main_#t~mem522#1.base, main_#t~mem522#1.offset, main_#t~mem523#1.base, main_#t~mem523#1.offset, main_#t~mem524#1, main_#t~post525#1, main_#t~mem526#1.base, main_#t~mem526#1.offset, main_#t~mem527#1.base, main_#t~mem527#1.offset, main_#t~mem528#1.base, main_#t~mem528#1.offset, main_#t~mem529#1.base, main_#t~mem529#1.offset, main_#t~mem530#1.base, main_#t~mem530#1.offset, main_#t~mem531#1.base, main_#t~mem531#1.offset, main_#t~mem532#1.base, main_#t~mem532#1.offset, main_#t~mem533#1.base, main_#t~mem533#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem534#1.base, main_#t~mem534#1.offset, main_#t~mem535#1, main_#t~post536#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite454#1.base, main_#t~ite454#1.offset, main_#t~mem453#1.base, main_#t~mem453#1.offset, main_~usertmp~0#1.base, main_~usertmp~0#1.offset, main_~userstmp~0#1.base, main_~userstmp~0#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~altusers~0#1.base, main_~altusers~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~altusers~0#1.base, main_~altusers~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1169#L733-4 [2022-12-13 16:54:57,243 INFO L750 eck$LassoCheckResult]: Loop: 1169#L733-4 call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1036#L733-1 assume !!(main_#t~mem7#1 < 1000);havoc main_#t~mem7#1;call main_#t~malloc8#1.base, main_#t~malloc8#1.offset := #Ultimate.allocOnHeap(72);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc8#1.base, main_#t~malloc8#1.offset;havoc main_#t~malloc8#1.base, main_#t~malloc8#1.offset; 1038#L735 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1248#L735-2 call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem9#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem9#1;call main_#t~mem10#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem11#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem10#1 * main_#t~mem11#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem10#1;havoc main_#t~mem11#1;call main_#t~mem12#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1249#L740 assume !(main_#t~mem12#1 < 10);havoc main_#t~mem12#1; 1445#L743-120 havoc main_~_ha_hashv~1#1; 1425#L743-48 goto; 1090#L743-46 havoc main_~_hj_i~1#1;havoc main_~_hj_j~1#1;havoc main_~_hj_k~1#1;main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~1#1 := 4276993775;main_~_hj_j~1#1 := 2654435769;main_~_hj_i~1#1 := main_~_hj_j~1#1;main_~_hj_k~1#1 := 4; 1091#L743-7 assume !(main_~_hj_k~1#1 % 4294967296 >= 12); 1180#L743-8 main_~_ha_hashv~1#1 := 4 + main_~_ha_hashv~1#1;main_#t~switch156#1 := 11 == main_~_hj_k~1#1; 1181#L743-9 assume main_#t~switch156#1;call main_#t~mem157#1 := read~int(main_~_hj_key~1#1.base, 10 + main_~_hj_key~1#1.offset, 1);main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 + 16777216 * (main_#t~mem157#1 % 256);havoc main_#t~mem157#1; 1509#L743-11 main_#t~switch156#1 := main_#t~switch156#1 || 10 == main_~_hj_k~1#1; 1318#L743-12 assume main_#t~switch156#1;call main_#t~mem158#1 := read~int(main_~_hj_key~1#1.base, 9 + main_~_hj_key~1#1.offset, 1);main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 + 65536 * (main_#t~mem158#1 % 256);havoc main_#t~mem158#1; 1319#L743-14 main_#t~switch156#1 := main_#t~switch156#1 || 9 == main_~_hj_k~1#1; 1374#L743-15 assume !main_#t~switch156#1; 1415#L743-17 main_#t~switch156#1 := main_#t~switch156#1 || 8 == main_~_hj_k~1#1; 1416#L743-18 assume main_#t~switch156#1;call main_#t~mem160#1 := read~int(main_~_hj_key~1#1.base, 7 + main_~_hj_key~1#1.offset, 1);main_~_hj_j~1#1 := main_~_hj_j~1#1 + 16777216 * (main_#t~mem160#1 % 256);havoc main_#t~mem160#1; 1381#L743-20 main_#t~switch156#1 := main_#t~switch156#1 || 7 == main_~_hj_k~1#1; 1382#L743-21 assume main_#t~switch156#1;call main_#t~mem161#1 := read~int(main_~_hj_key~1#1.base, 6 + main_~_hj_key~1#1.offset, 1);main_~_hj_j~1#1 := main_~_hj_j~1#1 + 65536 * (main_#t~mem161#1 % 256);havoc main_#t~mem161#1; 1326#L743-23 main_#t~switch156#1 := main_#t~switch156#1 || 6 == main_~_hj_k~1#1; 1327#L743-24 assume main_#t~switch156#1;call main_#t~mem162#1 := read~int(main_~_hj_key~1#1.base, 5 + main_~_hj_key~1#1.offset, 1);main_~_hj_j~1#1 := main_~_hj_j~1#1 + 256 * (main_#t~mem162#1 % 256);havoc main_#t~mem162#1; 1450#L743-26 main_#t~switch156#1 := main_#t~switch156#1 || 5 == main_~_hj_k~1#1; 1320#L743-27 assume main_#t~switch156#1;call main_#t~mem163#1 := read~int(main_~_hj_key~1#1.base, 4 + main_~_hj_key~1#1.offset, 1);main_~_hj_j~1#1 := main_~_hj_j~1#1 + main_#t~mem163#1 % 256;havoc main_#t~mem163#1; 1321#L743-29 main_#t~switch156#1 := main_#t~switch156#1 || 4 == main_~_hj_k~1#1; 1066#L743-30 assume main_#t~switch156#1;call main_#t~mem164#1 := read~int(main_~_hj_key~1#1.base, 3 + main_~_hj_key~1#1.offset, 1);main_~_hj_i~1#1 := main_~_hj_i~1#1 + 16777216 * (main_#t~mem164#1 % 256);havoc main_#t~mem164#1; 1067#L743-32 main_#t~switch156#1 := main_#t~switch156#1 || 3 == main_~_hj_k~1#1; 1274#L743-33 assume main_#t~switch156#1;call main_#t~mem165#1 := read~int(main_~_hj_key~1#1.base, 2 + main_~_hj_key~1#1.offset, 1);main_~_hj_i~1#1 := main_~_hj_i~1#1 + 65536 * (main_#t~mem165#1 % 256);havoc main_#t~mem165#1; 1484#L743-35 main_#t~switch156#1 := main_#t~switch156#1 || 2 == main_~_hj_k~1#1; 1399#L743-36 assume !main_#t~switch156#1; 1400#L743-38 main_#t~switch156#1 := main_#t~switch156#1 || 1 == main_~_hj_k~1#1; 1306#L743-39 assume main_#t~switch156#1;call main_#t~mem167#1 := read~int(main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, 1);main_~_hj_i~1#1 := main_~_hj_i~1#1 + main_#t~mem167#1 % 256;havoc main_#t~mem167#1; 1307#L743-41 havoc main_#t~switch156#1; 1431#L743-44 main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_hj_j~1#1;main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_ha_hashv~1#1;main_~_hj_i~1#1 := (if 0 == main_~_hj_i~1#1 then main_~_ha_hashv~1#1 / 8192 else (if 0 == main_~_ha_hashv~1#1 / 8192 then main_~_hj_i~1#1 else (if main_~_hj_i~1#1 == main_~_ha_hashv~1#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~1#1, main_~_ha_hashv~1#1 / 8192))));main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_ha_hashv~1#1;main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_hj_i~1#1;main_~_hj_j~1#1 := (if 0 == main_~_hj_j~1#1 then 256 * main_~_hj_i~1#1 else (if 0 == 256 * main_~_hj_i~1#1 then main_~_hj_j~1#1 else (if main_~_hj_j~1#1 == 256 * main_~_hj_i~1#1 then 0 else ~bitwiseXor(main_~_hj_j~1#1, 256 * main_~_hj_i~1#1))));main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_i~1#1;main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_j~1#1;main_~_ha_hashv~1#1 := (if 0 == main_~_ha_hashv~1#1 then main_~_hj_j~1#1 / 8192 else (if 0 == main_~_hj_j~1#1 / 8192 then main_~_ha_hashv~1#1 else (if main_~_ha_hashv~1#1 == main_~_hj_j~1#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~1#1, main_~_hj_j~1#1 / 8192))));main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_hj_j~1#1;main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_ha_hashv~1#1;main_~_hj_i~1#1 := (if 0 == main_~_hj_i~1#1 then main_~_ha_hashv~1#1 / 4096 else (if 0 == main_~_ha_hashv~1#1 / 4096 then main_~_hj_i~1#1 else (if main_~_hj_i~1#1 == main_~_ha_hashv~1#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~1#1, main_~_ha_hashv~1#1 / 4096))));main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_ha_hashv~1#1;main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_hj_i~1#1;main_~_hj_j~1#1 := (if 0 == main_~_hj_j~1#1 then 65536 * main_~_hj_i~1#1 else (if 0 == 65536 * main_~_hj_i~1#1 then main_~_hj_j~1#1 else (if main_~_hj_j~1#1 == 65536 * main_~_hj_i~1#1 then 0 else ~bitwiseXor(main_~_hj_j~1#1, 65536 * main_~_hj_i~1#1))));main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_i~1#1;main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_j~1#1;main_~_ha_hashv~1#1 := (if 0 == main_~_ha_hashv~1#1 then main_~_hj_j~1#1 / 32 else (if 0 == main_~_hj_j~1#1 / 32 then main_~_ha_hashv~1#1 else (if main_~_ha_hashv~1#1 == main_~_hj_j~1#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~1#1, main_~_hj_j~1#1 / 32))));main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_hj_j~1#1;main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_ha_hashv~1#1;main_~_hj_i~1#1 := (if 0 == main_~_hj_i~1#1 then main_~_ha_hashv~1#1 / 8 else (if 0 == main_~_ha_hashv~1#1 / 8 then main_~_hj_i~1#1 else (if main_~_hj_i~1#1 == main_~_ha_hashv~1#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~1#1, main_~_ha_hashv~1#1 / 8))));main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_ha_hashv~1#1;main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_hj_i~1#1;main_~_hj_j~1#1 := (if 0 == main_~_hj_j~1#1 then 1024 * main_~_hj_i~1#1 else (if 0 == 1024 * main_~_hj_i~1#1 then main_~_hj_j~1#1 else (if main_~_hj_j~1#1 == 1024 * main_~_hj_i~1#1 then 0 else ~bitwiseXor(main_~_hj_j~1#1, 1024 * main_~_hj_i~1#1))));main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_i~1#1;main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_j~1#1;main_~_ha_hashv~1#1 := (if 0 == main_~_ha_hashv~1#1 then main_~_hj_j~1#1 / 32768 else (if 0 == main_~_hj_j~1#1 / 32768 then main_~_ha_hashv~1#1 else (if main_~_ha_hashv~1#1 == main_~_hj_j~1#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~1#1, main_~_hj_j~1#1 / 32768)))); 1432#L743-43 goto; 1456#L743-45 goto; 1132#L743-47 goto; 1133#L743-118 call write~int(main_~_ha_hashv~1#1, main_~user~0#1.base, 68 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 60 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 64 + main_~user~0#1.offset, 4); 1315#L743-50 assume !(main_~altusers~0#1.base == 0 && main_~altusers~0#1.offset == 0);call main_#t~mem185#1.base, main_#t~mem185#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call write~$Pointer$(main_#t~mem185#1.base, main_#t~mem185#1.offset, main_~user~0#1.base, 40 + main_~user~0#1.offset, 4);havoc main_#t~mem185#1.base, main_#t~mem185#1.offset; 1385#L743-66 call write~$Pointer$(0, 0, main_~user~0#1.base, 48 + main_~user~0#1.offset, 4);call main_#t~mem186#1.base, main_#t~mem186#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem187#1.base, main_#t~mem187#1.offset := read~$Pointer$(main_#t~mem186#1.base, 16 + main_#t~mem186#1.offset, 4);call main_#t~mem188#1.base, main_#t~mem188#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem189#1 := read~int(main_#t~mem188#1.base, 20 + main_#t~mem188#1.offset, 4);call write~$Pointer$(main_#t~mem187#1.base, main_#t~mem187#1.offset - main_#t~mem189#1, main_~user~0#1.base, 44 + main_~user~0#1.offset, 4);havoc main_#t~mem186#1.base, main_#t~mem186#1.offset;havoc main_#t~mem187#1.base, main_#t~mem187#1.offset;havoc main_#t~mem188#1.base, main_#t~mem188#1.offset;havoc main_#t~mem189#1;call main_#t~mem190#1.base, main_#t~mem190#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem191#1.base, main_#t~mem191#1.offset := read~$Pointer$(main_#t~mem190#1.base, 16 + main_#t~mem190#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem191#1.base, 8 + main_#t~mem191#1.offset, 4);havoc main_#t~mem190#1.base, main_#t~mem190#1.offset;havoc main_#t~mem191#1.base, main_#t~mem191#1.offset;call main_#t~mem192#1.base, main_#t~mem192#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 40 + main_~user~0#1.offset, main_#t~mem192#1.base, 16 + main_#t~mem192#1.offset, 4);havoc main_#t~mem192#1.base, main_#t~mem192#1.offset; 1386#L743-65 goto; 1190#L743-116 havoc main_~_ha_bkt~1#1;call main_#t~mem193#1.base, main_#t~mem193#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem194#1 := read~int(main_#t~mem193#1.base, 12 + main_#t~mem193#1.offset, 4);main_#t~post195#1 := main_#t~mem194#1;call write~int(1 + main_#t~post195#1, main_#t~mem193#1.base, 12 + main_#t~mem193#1.offset, 4);havoc main_#t~mem193#1.base, main_#t~mem193#1.offset;havoc main_#t~mem194#1;havoc main_#t~post195#1; 1191#L743-70 call main_#t~mem196#1.base, main_#t~mem196#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem197#1 := read~int(main_#t~mem196#1.base, 4 + main_#t~mem196#1.offset, 4);main_~_ha_bkt~1#1 := (if 0 == main_~_ha_hashv~1#1 || 0 == main_#t~mem197#1 - 1 then 0 else (if main_~_ha_hashv~1#1 == main_#t~mem197#1 - 1 then main_~_ha_hashv~1#1 else ~bitwiseAnd(main_~_ha_hashv~1#1, main_#t~mem197#1 - 1)));havoc main_#t~mem196#1.base, main_#t~mem196#1.offset;havoc main_#t~mem197#1; 1123#L743-69 goto; 1124#L743-114 call main_#t~mem198#1.base, main_#t~mem198#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem199#1.base, main_#t~mem199#1.offset := read~$Pointer$(main_#t~mem198#1.base, main_#t~mem198#1.offset, 4);main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset := main_#t~mem199#1.base, main_#t~mem199#1.offset + 12 * (if main_~_ha_bkt~1#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~1#1 % 4294967296 % 4294967296 else main_~_ha_bkt~1#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem198#1.base, main_#t~mem198#1.offset;havoc main_#t~mem199#1.base, main_#t~mem199#1.offset;call main_#t~mem200#1 := read~int(main_~_ha_head~1#1.base, 4 + main_~_ha_head~1#1.offset, 4);main_#t~post201#1 := main_#t~mem200#1;call write~int(1 + main_#t~post201#1, main_~_ha_head~1#1.base, 4 + main_~_ha_head~1#1.offset, 4);havoc main_#t~mem200#1;havoc main_#t~post201#1;call main_#t~mem202#1.base, main_#t~mem202#1.offset := read~$Pointer$(main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, 4);call write~$Pointer$(main_#t~mem202#1.base, main_#t~mem202#1.offset, main_~user~0#1.base, 56 + main_~user~0#1.offset, 4);havoc main_#t~mem202#1.base, main_#t~mem202#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 52 + main_~user~0#1.offset, 4);call main_#t~mem203#1.base, main_#t~mem203#1.offset := read~$Pointer$(main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, 4); 1299#L743-72 assume main_#t~mem203#1.base != 0 || main_#t~mem203#1.offset != 0;havoc main_#t~mem203#1.base, main_#t~mem203#1.offset;call main_#t~mem204#1.base, main_#t~mem204#1.offset := read~$Pointer$(main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 40 + main_~user~0#1.offset, main_#t~mem204#1.base, 12 + main_#t~mem204#1.offset, 4);havoc main_#t~mem204#1.base, main_#t~mem204#1.offset; 1284#L743-74 call write~$Pointer$(main_~user~0#1.base, 40 + main_~user~0#1.offset, main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, 4);call main_#t~mem206#1 := read~int(main_~_ha_head~1#1.base, 4 + main_~_ha_head~1#1.offset, 4);call main_#t~mem205#1 := read~int(main_~_ha_head~1#1.base, 8 + main_~_ha_head~1#1.offset, 4);main_#t~short209#1 := main_#t~mem206#1 % 4294967296 >= 10 * (1 + main_#t~mem205#1) % 4294967296; 1197#L743-75 assume !main_#t~short209#1; 1198#L743-77 assume !main_#t~short209#1;havoc main_#t~mem206#1;havoc main_#t~mem205#1;havoc main_#t~mem207#1.base, main_#t~mem207#1.offset;havoc main_#t~mem208#1;havoc main_#t~short209#1; 1486#L743-113 goto; 1487#L743-115 goto; 1536#L743-117 goto; 1159#L743-119 goto; 1160#L733-3 call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post6#1 := main_#t~mem5#1;call write~int(1 + main_#t~post6#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem5#1;havoc main_#t~post6#1; 1169#L733-4 [2022-12-13 16:54:57,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:57,257 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 2 times [2022-12-13 16:54:57,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:57,258 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [22245900] [2022-12-13 16:54:57,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:57,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:57,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:57,278 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:54:57,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:57,300 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:54:57,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:57,301 INFO L85 PathProgramCache]: Analyzing trace with hash 1756007673, now seen corresponding path program 1 times [2022-12-13 16:54:57,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:57,301 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281771939] [2022-12-13 16:54:57,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:57,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:57,399 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-13 16:54:57,399 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1178342604] [2022-12-13 16:54:57,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:57,400 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 16:54:57,400 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 16:54:57,429 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 16:54:57,430 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-12-13 16:54:57,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:58,009 INFO L263 TraceCheckSpWp]: Trace formula consists of 1832 conjuncts, 3 conjunts are in the unsatisfiable core [2022-12-13 16:54:58,012 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-13 16:54:58,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:58,040 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-13 16:54:58,041 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:58,041 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281771939] [2022-12-13 16:54:58,041 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-13 16:54:58,041 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1178342604] [2022-12-13 16:54:58,041 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1178342604] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:58,042 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:58,042 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:54:58,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [687109058] [2022-12-13 16:54:58,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:58,043 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:54:58,043 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:54:58,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:54:58,043 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:54:58,044 INFO L87 Difference]: Start difference. First operand 501 states and 665 transitions. cyclomatic complexity: 175 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:58,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:54:58,121 INFO L93 Difference]: Finished difference Result 522 states and 686 transitions. [2022-12-13 16:54:58,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 522 states and 686 transitions. [2022-12-13 16:54:58,127 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 285 [2022-12-13 16:54:58,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 522 states to 522 states and 686 transitions. [2022-12-13 16:54:58,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 522 [2022-12-13 16:54:58,131 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 522 [2022-12-13 16:54:58,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 522 states and 686 transitions. [2022-12-13 16:54:58,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:54:58,134 INFO L218 hiAutomatonCegarLoop]: Abstraction has 522 states and 686 transitions. [2022-12-13 16:54:58,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states and 686 transitions. [2022-12-13 16:54:58,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 521. [2022-12-13 16:54:58,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 521 states, 514 states have (on average 1.3093385214007782) internal successors, (673), 513 states have internal predecessors, (673), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2022-12-13 16:54:58,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 685 transitions. [2022-12-13 16:54:58,151 INFO L240 hiAutomatonCegarLoop]: Abstraction has 521 states and 685 transitions. [2022-12-13 16:54:58,151 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:54:58,152 INFO L428 stractBuchiCegarLoop]: Abstraction has 521 states and 685 transitions. [2022-12-13 16:54:58,152 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 16:54:58,152 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 521 states and 685 transitions. [2022-12-13 16:54:58,156 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 284 [2022-12-13 16:54:58,156 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:58,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:58,157 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 16:54:58,157 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:58,157 INFO L748 eck$LassoCheckResult]: Stem: 2488#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);~count_int_int~0 := 0; 2489#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc8#1.base, main_#t~malloc8#1.offset, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem20#1, main_#t~mem22#1, main_#t~mem21#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~switch25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc37#1.base, main_#t~malloc37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~memset~res40#1.base, main_#t~memset~res40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~malloc46#1.base, main_#t~malloc46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~post70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem75#1, main_#t~mem74#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~short78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1, main_#t~malloc81#1.base, main_#t~malloc81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~memset~res86#1.base, main_#t~memset~res86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem91#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem95#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1, main_#t~pre109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1, main_#t~post114#1, main_#t~mem118#1, main_#t~mem116#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem117#1, main_#t~mem119#1, main_#t~post120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~post97#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~post130#1, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~ite140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem145#1, main_#t~mem144#1, main_#t~mem146#1, main_#t~mem147#1, main_#t~mem149#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem151#1, main_#t~mem153#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem155#1, main_#t~switch156#1, main_#t~mem157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~malloc168#1.base, main_#t~malloc168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~memset~res171#1.base, main_#t~memset~res171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~malloc177#1.base, main_#t~malloc177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~memset~res184#1.base, main_#t~memset~res184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1.base, main_#t~mem186#1.offset, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1, main_#t~post195#1, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_#t~mem200#1, main_#t~post201#1, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem206#1, main_#t~mem205#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1, main_#t~short209#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1, main_#t~malloc212#1.base, main_#t~malloc212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~memset~res217#1.base, main_#t~memset~res217#1.offset, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem222#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem226#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem237#1, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~pre240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1, main_#t~post245#1, main_#t~mem249#1, main_#t~mem247#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem248#1, main_#t~mem250#1, main_#t~post251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~post228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1, main_#t~post261#1, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem268#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1, main_#t~ite271#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_~_he_bkt~1#1, main_~_he_bkt_i~1#1, main_~_he_thh~1#1.base, main_~_he_thh~1#1.offset, main_~_he_hh_nxt~1#1.base, main_~_he_hh_nxt~1#1.offset, main_~#_he_new_buckets~1#1.base, main_~#_he_new_buckets~1#1.offset, main_~_he_newbkt~1#1.base, main_~_he_newbkt~1#1.offset, main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, main_~_ha_bkt~1#1, main_~_ha_hashv~1#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem276#1, main_#t~mem275#1, main_#t~mem277#1, main_#t~mem278#1, main_#t~mem280#1, main_#t~mem279#1, main_#t~mem281#1, main_#t~mem282#1, main_#t~mem284#1, main_#t~mem283#1, main_#t~mem285#1, main_#t~mem286#1, main_#t~switch287#1, main_#t~mem288#1, main_#t~mem289#1, main_#t~mem290#1, main_#t~mem291#1, main_#t~mem292#1, main_#t~mem293#1, main_#t~mem294#1, main_#t~mem295#1, main_#t~mem296#1, main_#t~mem297#1, main_#t~mem298#1, main_~_hj_i~2#1, main_~_hj_j~2#1, main_~_hj_k~2#1, main_~_hj_key~2#1.base, main_~_hj_key~2#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1.base, main_#t~mem302#1.offset, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1, main_#t~mem309#1, main_#t~mem310#1, main_#t~short311#1, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~ret313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem318#1, main_#t~mem320#1, main_#t~mem319#1, main_#t~mem321#1, main_#t~mem322#1, main_#t~mem324#1, main_#t~mem323#1, main_#t~mem325#1, main_#t~mem326#1, main_#t~mem328#1, main_#t~mem327#1, main_#t~mem329#1, main_#t~mem330#1, main_#t~switch331#1, main_#t~mem332#1, main_#t~mem333#1, main_#t~mem334#1, main_#t~mem335#1, main_#t~mem336#1, main_#t~mem337#1, main_#t~mem338#1, main_#t~mem339#1, main_#t~mem340#1, main_#t~mem341#1, main_#t~mem342#1, main_~_hj_i~3#1, main_~_hj_j~3#1, main_~_hj_k~3#1, main_~_hj_key~3#1.base, main_~_hj_key~3#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1.base, main_#t~mem349#1.offset, main_#t~mem350#1.base, main_#t~mem350#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_#t~mem352#1, main_#t~mem353#1, main_#t~mem354#1, main_#t~short355#1, main_#t~mem356#1.base, main_#t~mem356#1.offset, main_#t~ret357#1, main_#t~mem358#1.base, main_#t~mem358#1.offset, main_#t~mem359#1.base, main_#t~mem359#1.offset, main_#t~mem360#1.base, main_#t~mem360#1.offset, main_#t~mem361#1, main_~_hf_bkt~1#1, main_~_hf_hashv~1#1, main_#t~mem362#1, main_#t~mem364#1, main_#t~mem363#1, main_#t~mem365#1, main_#t~mem366#1, main_#t~mem368#1, main_#t~mem367#1, main_#t~mem369#1, main_#t~mem370#1, main_#t~mem372#1, main_#t~mem371#1, main_#t~mem373#1, main_#t~mem374#1, main_#t~switch375#1, main_#t~mem376#1, main_#t~mem377#1, main_#t~mem378#1, main_#t~mem379#1, main_#t~mem380#1, main_#t~mem381#1, main_#t~mem382#1, main_#t~mem383#1, main_#t~mem384#1, main_#t~mem385#1, main_#t~mem386#1, main_~_hj_i~4#1, main_~_hj_j~4#1, main_~_hj_k~4#1, main_~_hj_key~4#1.base, main_~_hj_key~4#1.offset, main_#t~mem387#1.base, main_#t~mem387#1.offset, main_#t~mem388#1, main_#t~mem389#1.base, main_#t~mem389#1.offset, main_#t~mem390#1.base, main_#t~mem390#1.offset, main_#t~mem391#1.base, main_#t~mem391#1.offset, main_#t~mem392#1.base, main_#t~mem392#1.offset, main_#t~mem393#1.base, main_#t~mem393#1.offset, main_#t~mem394#1.base, main_#t~mem394#1.offset, main_#t~mem395#1.base, main_#t~mem395#1.offset, main_#t~mem396#1, main_#t~mem397#1, main_#t~mem398#1, main_#t~short399#1, main_#t~mem400#1.base, main_#t~mem400#1.offset, main_#t~ret401#1, main_#t~mem402#1.base, main_#t~mem402#1.offset, main_#t~mem403#1.base, main_#t~mem403#1.offset, main_#t~mem404#1.base, main_#t~mem404#1.offset, main_#t~mem405#1, main_~_hf_bkt~2#1, main_~_hf_hashv~2#1, main_#t~mem406#1, main_#t~mem408#1, main_#t~mem407#1, main_#t~mem409#1, main_#t~mem410#1, main_#t~mem412#1, main_#t~mem411#1, main_#t~mem413#1, main_#t~mem414#1, main_#t~mem416#1, main_#t~mem415#1, main_#t~mem417#1, main_#t~mem418#1, main_#t~switch419#1, main_#t~mem420#1, main_#t~mem421#1, main_#t~mem422#1, main_#t~mem423#1, main_#t~mem424#1, main_#t~mem425#1, main_#t~mem426#1, main_#t~mem427#1, main_#t~mem428#1, main_#t~mem429#1, main_#t~mem430#1, main_~_hj_i~5#1, main_~_hj_j~5#1, main_~_hj_k~5#1, main_~_hj_key~5#1.base, main_~_hj_key~5#1.offset, main_#t~mem431#1.base, main_#t~mem431#1.offset, main_#t~mem432#1, main_#t~mem433#1.base, main_#t~mem433#1.offset, main_#t~mem434#1.base, main_#t~mem434#1.offset, main_#t~mem435#1.base, main_#t~mem435#1.offset, main_#t~mem436#1.base, main_#t~mem436#1.offset, main_#t~mem437#1.base, main_#t~mem437#1.offset, main_#t~mem438#1.base, main_#t~mem438#1.offset, main_#t~mem439#1.base, main_#t~mem439#1.offset, main_#t~mem440#1, main_#t~mem441#1, main_#t~mem442#1, main_#t~short443#1, main_#t~mem444#1.base, main_#t~mem444#1.offset, main_#t~ret445#1, main_#t~mem446#1.base, main_#t~mem446#1.offset, main_#t~mem447#1.base, main_#t~mem447#1.offset, main_#t~mem448#1.base, main_#t~mem448#1.offset, main_#t~mem449#1, main_~_hf_bkt~3#1, main_~_hf_hashv~3#1, main_#t~mem450#1, main_#t~ite452#1.base, main_#t~ite452#1.offset, main_#t~mem451#1.base, main_#t~mem451#1.offset, main_#t~mem455#1.base, main_#t~mem455#1.offset, main_#t~mem456#1.base, main_#t~mem456#1.offset, main_#t~short457#1, main_#t~mem458#1.base, main_#t~mem458#1.offset, main_#t~mem459#1.base, main_#t~mem459#1.offset, main_#t~mem460#1.base, main_#t~mem460#1.offset, main_#t~mem461#1.base, main_#t~mem461#1.offset, main_#t~mem462#1.base, main_#t~mem462#1.offset, main_#t~mem463#1.base, main_#t~mem463#1.offset, main_#t~mem464#1.base, main_#t~mem464#1.offset, main_#t~mem465#1.base, main_#t~mem465#1.offset, main_#t~mem466#1, main_#t~mem467#1.base, main_#t~mem467#1.offset, main_#t~mem468#1.base, main_#t~mem468#1.offset, main_#t~mem469#1.base, main_#t~mem469#1.offset, main_#t~mem470#1, main_#t~mem471#1.base, main_#t~mem471#1.offset, main_#t~mem472#1.base, main_#t~mem472#1.offset, main_#t~mem473#1.base, main_#t~mem473#1.offset, main_#t~mem474#1.base, main_#t~mem474#1.offset, main_#t~mem475#1.base, main_#t~mem475#1.offset, main_#t~mem476#1, main_#t~mem477#1.base, main_#t~mem477#1.offset, main_#t~mem480#1, main_#t~mem478#1.base, main_#t~mem478#1.offset, main_#t~mem479#1, main_#t~mem481#1.base, main_#t~mem481#1.offset, main_#t~mem482#1.base, main_#t~mem482#1.offset, main_#t~mem483#1, main_#t~post484#1, main_#t~mem485#1.base, main_#t~mem485#1.offset, main_#t~mem486#1.base, main_#t~mem486#1.offset, main_#t~mem487#1.base, main_#t~mem487#1.offset, main_#t~mem488#1.base, main_#t~mem488#1.offset, main_#t~mem489#1.base, main_#t~mem489#1.offset, main_#t~mem490#1.base, main_#t~mem490#1.offset, main_#t~mem491#1.base, main_#t~mem491#1.offset, main_#t~mem492#1.base, main_#t~mem492#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem493#1.base, main_#t~mem493#1.offset, main_#t~mem494#1, main_#t~post495#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem496#1.base, main_#t~mem496#1.offset, main_#t~mem497#1.base, main_#t~mem497#1.offset, main_#t~short498#1, main_#t~mem499#1.base, main_#t~mem499#1.offset, main_#t~mem500#1.base, main_#t~mem500#1.offset, main_#t~mem501#1.base, main_#t~mem501#1.offset, main_#t~mem502#1.base, main_#t~mem502#1.offset, main_#t~mem503#1.base, main_#t~mem503#1.offset, main_#t~mem504#1.base, main_#t~mem504#1.offset, main_#t~mem505#1.base, main_#t~mem505#1.offset, main_#t~mem506#1.base, main_#t~mem506#1.offset, main_#t~mem507#1, main_#t~mem508#1.base, main_#t~mem508#1.offset, main_#t~mem509#1.base, main_#t~mem509#1.offset, main_#t~mem510#1.base, main_#t~mem510#1.offset, main_#t~mem511#1, main_#t~mem512#1.base, main_#t~mem512#1.offset, main_#t~mem513#1.base, main_#t~mem513#1.offset, main_#t~mem514#1.base, main_#t~mem514#1.offset, main_#t~mem515#1.base, main_#t~mem515#1.offset, main_#t~mem516#1.base, main_#t~mem516#1.offset, main_#t~mem517#1, main_#t~mem518#1.base, main_#t~mem518#1.offset, main_#t~mem521#1, main_#t~mem519#1.base, main_#t~mem519#1.offset, main_#t~mem520#1, main_#t~mem522#1.base, main_#t~mem522#1.offset, main_#t~mem523#1.base, main_#t~mem523#1.offset, main_#t~mem524#1, main_#t~post525#1, main_#t~mem526#1.base, main_#t~mem526#1.offset, main_#t~mem527#1.base, main_#t~mem527#1.offset, main_#t~mem528#1.base, main_#t~mem528#1.offset, main_#t~mem529#1.base, main_#t~mem529#1.offset, main_#t~mem530#1.base, main_#t~mem530#1.offset, main_#t~mem531#1.base, main_#t~mem531#1.offset, main_#t~mem532#1.base, main_#t~mem532#1.offset, main_#t~mem533#1.base, main_#t~mem533#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem534#1.base, main_#t~mem534#1.offset, main_#t~mem535#1, main_#t~post536#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite454#1.base, main_#t~ite454#1.offset, main_#t~mem453#1.base, main_#t~mem453#1.offset, main_~usertmp~0#1.base, main_~usertmp~0#1.offset, main_~userstmp~0#1.base, main_~userstmp~0#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~altusers~0#1.base, main_~altusers~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~altusers~0#1.base, main_~altusers~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 2354#L733-4 [2022-12-13 16:54:58,157 INFO L750 eck$LassoCheckResult]: Loop: 2354#L733-4 call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 2221#L733-1 assume !!(main_#t~mem7#1 < 1000);havoc main_#t~mem7#1;call main_#t~malloc8#1.base, main_#t~malloc8#1.offset := #Ultimate.allocOnHeap(72);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc8#1.base, main_#t~malloc8#1.offset;havoc main_#t~malloc8#1.base, main_#t~malloc8#1.offset; 2223#L735 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 2433#L735-2 call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem9#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem9#1;call main_#t~mem10#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem11#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem10#1 * main_#t~mem11#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem10#1;havoc main_#t~mem11#1;call main_#t~mem12#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 2434#L740 assume !(main_#t~mem12#1 < 10);havoc main_#t~mem12#1; 2634#L743-120 havoc main_~_ha_hashv~1#1; 2612#L743-48 goto; 2277#L743-46 havoc main_~_hj_i~1#1;havoc main_~_hj_j~1#1;havoc main_~_hj_k~1#1;main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~1#1 := 4276993775;main_~_hj_j~1#1 := 2654435769;main_~_hj_i~1#1 := main_~_hj_j~1#1;main_~_hj_k~1#1 := 4; 2278#L743-7 assume !(main_~_hj_k~1#1 % 4294967296 >= 12); 2365#L743-8 main_~_ha_hashv~1#1 := 4 + main_~_ha_hashv~1#1;main_#t~switch156#1 := 11 == main_~_hj_k~1#1; 2366#L743-9 assume !main_#t~switch156#1; 2704#L743-11 main_#t~switch156#1 := main_#t~switch156#1 || 10 == main_~_hj_k~1#1; 2741#L743-12 assume !main_#t~switch156#1; 2560#L743-14 main_#t~switch156#1 := main_#t~switch156#1 || 9 == main_~_hj_k~1#1; 2561#L743-15 assume !main_#t~switch156#1; 2740#L743-17 main_#t~switch156#1 := main_#t~switch156#1 || 8 == main_~_hj_k~1#1; 2739#L743-18 assume main_#t~switch156#1;call main_#t~mem160#1 := read~int(main_~_hj_key~1#1.base, 7 + main_~_hj_key~1#1.offset, 1);main_~_hj_j~1#1 := main_~_hj_j~1#1 + 16777216 * (main_#t~mem160#1 % 256);havoc main_#t~mem160#1; 2693#L743-20 main_#t~switch156#1 := main_#t~switch156#1 || 7 == main_~_hj_k~1#1; 2714#L743-21 assume main_#t~switch156#1;call main_#t~mem161#1 := read~int(main_~_hj_key~1#1.base, 6 + main_~_hj_key~1#1.offset, 1);main_~_hj_j~1#1 := main_~_hj_j~1#1 + 65536 * (main_#t~mem161#1 % 256);havoc main_#t~mem161#1; 2513#L743-23 main_#t~switch156#1 := main_#t~switch156#1 || 6 == main_~_hj_k~1#1; 2514#L743-24 assume main_#t~switch156#1;call main_#t~mem162#1 := read~int(main_~_hj_key~1#1.base, 5 + main_~_hj_key~1#1.offset, 1);main_~_hj_j~1#1 := main_~_hj_j~1#1 + 256 * (main_#t~mem162#1 % 256);havoc main_#t~mem162#1; 2639#L743-26 main_#t~switch156#1 := main_#t~switch156#1 || 5 == main_~_hj_k~1#1; 2506#L743-27 assume main_#t~switch156#1;call main_#t~mem163#1 := read~int(main_~_hj_key~1#1.base, 4 + main_~_hj_key~1#1.offset, 1);main_~_hj_j~1#1 := main_~_hj_j~1#1 + main_#t~mem163#1 % 256;havoc main_#t~mem163#1; 2507#L743-29 main_#t~switch156#1 := main_#t~switch156#1 || 4 == main_~_hj_k~1#1; 2256#L743-30 assume main_#t~switch156#1;call main_#t~mem164#1 := read~int(main_~_hj_key~1#1.base, 3 + main_~_hj_key~1#1.offset, 1);main_~_hj_i~1#1 := main_~_hj_i~1#1 + 16777216 * (main_#t~mem164#1 % 256);havoc main_#t~mem164#1; 2257#L743-32 main_#t~switch156#1 := main_#t~switch156#1 || 3 == main_~_hj_k~1#1; 2674#L743-33 assume main_#t~switch156#1;call main_#t~mem165#1 := read~int(main_~_hj_key~1#1.base, 2 + main_~_hj_key~1#1.offset, 1);main_~_hj_i~1#1 := main_~_hj_i~1#1 + 65536 * (main_#t~mem165#1 % 256);havoc main_#t~mem165#1; 2675#L743-35 main_#t~switch156#1 := main_#t~switch156#1 || 2 == main_~_hj_k~1#1; 2586#L743-36 assume main_#t~switch156#1;call main_#t~mem166#1 := read~int(main_~_hj_key~1#1.base, 1 + main_~_hj_key~1#1.offset, 1);main_~_hj_i~1#1 := main_~_hj_i~1#1 + 256 * (main_#t~mem166#1 % 256);havoc main_#t~mem166#1; 2587#L743-38 main_#t~switch156#1 := main_#t~switch156#1 || 1 == main_~_hj_k~1#1; 2495#L743-39 assume main_#t~switch156#1;call main_#t~mem167#1 := read~int(main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, 1);main_~_hj_i~1#1 := main_~_hj_i~1#1 + main_#t~mem167#1 % 256;havoc main_#t~mem167#1; 2496#L743-41 havoc main_#t~switch156#1; 2618#L743-44 main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_hj_j~1#1;main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_ha_hashv~1#1;main_~_hj_i~1#1 := (if 0 == main_~_hj_i~1#1 then main_~_ha_hashv~1#1 / 8192 else (if 0 == main_~_ha_hashv~1#1 / 8192 then main_~_hj_i~1#1 else (if main_~_hj_i~1#1 == main_~_ha_hashv~1#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~1#1, main_~_ha_hashv~1#1 / 8192))));main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_ha_hashv~1#1;main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_hj_i~1#1;main_~_hj_j~1#1 := (if 0 == main_~_hj_j~1#1 then 256 * main_~_hj_i~1#1 else (if 0 == 256 * main_~_hj_i~1#1 then main_~_hj_j~1#1 else (if main_~_hj_j~1#1 == 256 * main_~_hj_i~1#1 then 0 else ~bitwiseXor(main_~_hj_j~1#1, 256 * main_~_hj_i~1#1))));main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_i~1#1;main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_j~1#1;main_~_ha_hashv~1#1 := (if 0 == main_~_ha_hashv~1#1 then main_~_hj_j~1#1 / 8192 else (if 0 == main_~_hj_j~1#1 / 8192 then main_~_ha_hashv~1#1 else (if main_~_ha_hashv~1#1 == main_~_hj_j~1#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~1#1, main_~_hj_j~1#1 / 8192))));main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_hj_j~1#1;main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_ha_hashv~1#1;main_~_hj_i~1#1 := (if 0 == main_~_hj_i~1#1 then main_~_ha_hashv~1#1 / 4096 else (if 0 == main_~_ha_hashv~1#1 / 4096 then main_~_hj_i~1#1 else (if main_~_hj_i~1#1 == main_~_ha_hashv~1#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~1#1, main_~_ha_hashv~1#1 / 4096))));main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_ha_hashv~1#1;main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_hj_i~1#1;main_~_hj_j~1#1 := (if 0 == main_~_hj_j~1#1 then 65536 * main_~_hj_i~1#1 else (if 0 == 65536 * main_~_hj_i~1#1 then main_~_hj_j~1#1 else (if main_~_hj_j~1#1 == 65536 * main_~_hj_i~1#1 then 0 else ~bitwiseXor(main_~_hj_j~1#1, 65536 * main_~_hj_i~1#1))));main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_i~1#1;main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_j~1#1;main_~_ha_hashv~1#1 := (if 0 == main_~_ha_hashv~1#1 then main_~_hj_j~1#1 / 32 else (if 0 == main_~_hj_j~1#1 / 32 then main_~_ha_hashv~1#1 else (if main_~_ha_hashv~1#1 == main_~_hj_j~1#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~1#1, main_~_hj_j~1#1 / 32))));main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_hj_j~1#1;main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_ha_hashv~1#1;main_~_hj_i~1#1 := (if 0 == main_~_hj_i~1#1 then main_~_ha_hashv~1#1 / 8 else (if 0 == main_~_ha_hashv~1#1 / 8 then main_~_hj_i~1#1 else (if main_~_hj_i~1#1 == main_~_ha_hashv~1#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~1#1, main_~_ha_hashv~1#1 / 8))));main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_ha_hashv~1#1;main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_hj_i~1#1;main_~_hj_j~1#1 := (if 0 == main_~_hj_j~1#1 then 1024 * main_~_hj_i~1#1 else (if 0 == 1024 * main_~_hj_i~1#1 then main_~_hj_j~1#1 else (if main_~_hj_j~1#1 == 1024 * main_~_hj_i~1#1 then 0 else ~bitwiseXor(main_~_hj_j~1#1, 1024 * main_~_hj_i~1#1))));main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_i~1#1;main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_j~1#1;main_~_ha_hashv~1#1 := (if 0 == main_~_ha_hashv~1#1 then main_~_hj_j~1#1 / 32768 else (if 0 == main_~_hj_j~1#1 / 32768 then main_~_ha_hashv~1#1 else (if main_~_ha_hashv~1#1 == main_~_hj_j~1#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~1#1, main_~_hj_j~1#1 / 32768)))); 2619#L743-43 goto; 2646#L743-45 goto; 2317#L743-47 goto; 2318#L743-118 call write~int(main_~_ha_hashv~1#1, main_~user~0#1.base, 68 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 60 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 64 + main_~user~0#1.offset, 4); 2501#L743-50 assume !(main_~altusers~0#1.base == 0 && main_~altusers~0#1.offset == 0);call main_#t~mem185#1.base, main_#t~mem185#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call write~$Pointer$(main_#t~mem185#1.base, main_#t~mem185#1.offset, main_~user~0#1.base, 40 + main_~user~0#1.offset, 4);havoc main_#t~mem185#1.base, main_#t~mem185#1.offset; 2572#L743-66 call write~$Pointer$(0, 0, main_~user~0#1.base, 48 + main_~user~0#1.offset, 4);call main_#t~mem186#1.base, main_#t~mem186#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem187#1.base, main_#t~mem187#1.offset := read~$Pointer$(main_#t~mem186#1.base, 16 + main_#t~mem186#1.offset, 4);call main_#t~mem188#1.base, main_#t~mem188#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem189#1 := read~int(main_#t~mem188#1.base, 20 + main_#t~mem188#1.offset, 4);call write~$Pointer$(main_#t~mem187#1.base, main_#t~mem187#1.offset - main_#t~mem189#1, main_~user~0#1.base, 44 + main_~user~0#1.offset, 4);havoc main_#t~mem186#1.base, main_#t~mem186#1.offset;havoc main_#t~mem187#1.base, main_#t~mem187#1.offset;havoc main_#t~mem188#1.base, main_#t~mem188#1.offset;havoc main_#t~mem189#1;call main_#t~mem190#1.base, main_#t~mem190#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem191#1.base, main_#t~mem191#1.offset := read~$Pointer$(main_#t~mem190#1.base, 16 + main_#t~mem190#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem191#1.base, 8 + main_#t~mem191#1.offset, 4);havoc main_#t~mem190#1.base, main_#t~mem190#1.offset;havoc main_#t~mem191#1.base, main_#t~mem191#1.offset;call main_#t~mem192#1.base, main_#t~mem192#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 40 + main_~user~0#1.offset, main_#t~mem192#1.base, 16 + main_#t~mem192#1.offset, 4);havoc main_#t~mem192#1.base, main_#t~mem192#1.offset; 2573#L743-65 goto; 2375#L743-116 havoc main_~_ha_bkt~1#1;call main_#t~mem193#1.base, main_#t~mem193#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem194#1 := read~int(main_#t~mem193#1.base, 12 + main_#t~mem193#1.offset, 4);main_#t~post195#1 := main_#t~mem194#1;call write~int(1 + main_#t~post195#1, main_#t~mem193#1.base, 12 + main_#t~mem193#1.offset, 4);havoc main_#t~mem193#1.base, main_#t~mem193#1.offset;havoc main_#t~mem194#1;havoc main_#t~post195#1; 2376#L743-70 call main_#t~mem196#1.base, main_#t~mem196#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem197#1 := read~int(main_#t~mem196#1.base, 4 + main_#t~mem196#1.offset, 4);main_~_ha_bkt~1#1 := (if 0 == main_~_ha_hashv~1#1 || 0 == main_#t~mem197#1 - 1 then 0 else (if main_~_ha_hashv~1#1 == main_#t~mem197#1 - 1 then main_~_ha_hashv~1#1 else ~bitwiseAnd(main_~_ha_hashv~1#1, main_#t~mem197#1 - 1)));havoc main_#t~mem196#1.base, main_#t~mem196#1.offset;havoc main_#t~mem197#1; 2308#L743-69 goto; 2309#L743-114 call main_#t~mem198#1.base, main_#t~mem198#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem199#1.base, main_#t~mem199#1.offset := read~$Pointer$(main_#t~mem198#1.base, main_#t~mem198#1.offset, 4);main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset := main_#t~mem199#1.base, main_#t~mem199#1.offset + 12 * (if main_~_ha_bkt~1#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~1#1 % 4294967296 % 4294967296 else main_~_ha_bkt~1#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem198#1.base, main_#t~mem198#1.offset;havoc main_#t~mem199#1.base, main_#t~mem199#1.offset;call main_#t~mem200#1 := read~int(main_~_ha_head~1#1.base, 4 + main_~_ha_head~1#1.offset, 4);main_#t~post201#1 := main_#t~mem200#1;call write~int(1 + main_#t~post201#1, main_~_ha_head~1#1.base, 4 + main_~_ha_head~1#1.offset, 4);havoc main_#t~mem200#1;havoc main_#t~post201#1;call main_#t~mem202#1.base, main_#t~mem202#1.offset := read~$Pointer$(main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, 4);call write~$Pointer$(main_#t~mem202#1.base, main_#t~mem202#1.offset, main_~user~0#1.base, 56 + main_~user~0#1.offset, 4);havoc main_#t~mem202#1.base, main_#t~mem202#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 52 + main_~user~0#1.offset, 4);call main_#t~mem203#1.base, main_#t~mem203#1.offset := read~$Pointer$(main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, 4); 2485#L743-72 assume main_#t~mem203#1.base != 0 || main_#t~mem203#1.offset != 0;havoc main_#t~mem203#1.base, main_#t~mem203#1.offset;call main_#t~mem204#1.base, main_#t~mem204#1.offset := read~$Pointer$(main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 40 + main_~user~0#1.offset, main_#t~mem204#1.base, 12 + main_#t~mem204#1.offset, 4);havoc main_#t~mem204#1.base, main_#t~mem204#1.offset; 2470#L743-74 call write~$Pointer$(main_~user~0#1.base, 40 + main_~user~0#1.offset, main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, 4);call main_#t~mem206#1 := read~int(main_~_ha_head~1#1.base, 4 + main_~_ha_head~1#1.offset, 4);call main_#t~mem205#1 := read~int(main_~_ha_head~1#1.base, 8 + main_~_ha_head~1#1.offset, 4);main_#t~short209#1 := main_#t~mem206#1 % 4294967296 >= 10 * (1 + main_#t~mem205#1) % 4294967296; 2382#L743-75 assume !main_#t~short209#1; 2383#L743-77 assume !main_#t~short209#1;havoc main_#t~mem206#1;havoc main_#t~mem205#1;havoc main_#t~mem207#1.base, main_#t~mem207#1.offset;havoc main_#t~mem208#1;havoc main_#t~short209#1; 2677#L743-113 goto; 2678#L743-115 goto; 2732#L743-117 goto; 2344#L743-119 goto; 2345#L733-3 call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post6#1 := main_#t~mem5#1;call write~int(1 + main_#t~post6#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem5#1;havoc main_#t~post6#1; 2354#L733-4 [2022-12-13 16:54:58,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:58,158 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 3 times [2022-12-13 16:54:58,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:58,158 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1860863827] [2022-12-13 16:54:58,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:58,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:58,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:58,179 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:54:58,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:58,203 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:54:58,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:58,203 INFO L85 PathProgramCache]: Analyzing trace with hash 1141712507, now seen corresponding path program 1 times [2022-12-13 16:54:58,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:58,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1284441578] [2022-12-13 16:54:58,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:58,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:58,299 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-13 16:54:58,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1920607869] [2022-12-13 16:54:58,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:58,300 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 16:54:58,300 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 16:54:58,301 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 16:54:58,302 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-12-13 16:54:58,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:54:58,835 INFO L263 TraceCheckSpWp]: Trace formula consists of 1826 conjuncts, 4 conjunts are in the unsatisfiable core [2022-12-13 16:54:58,839 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-13 16:54:58,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:54:58,875 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-13 16:54:58,875 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:54:58,875 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1284441578] [2022-12-13 16:54:58,875 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-13 16:54:58,875 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1920607869] [2022-12-13 16:54:58,876 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1920607869] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:54:58,876 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:54:58,876 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:54:58,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [908853323] [2022-12-13 16:54:58,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:54:58,877 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:54:58,877 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:54:58,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 16:54:58,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-12-13 16:54:58,878 INFO L87 Difference]: Start difference. First operand 521 states and 685 transitions. cyclomatic complexity: 175 Second operand has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:54:58,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:54:58,980 INFO L93 Difference]: Finished difference Result 923 states and 1218 transitions. [2022-12-13 16:54:58,980 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 923 states and 1218 transitions. [2022-12-13 16:54:58,988 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 382 [2022-12-13 16:54:58,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 923 states to 923 states and 1218 transitions. [2022-12-13 16:54:58,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 923 [2022-12-13 16:54:58,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 923 [2022-12-13 16:54:58,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 923 states and 1218 transitions. [2022-12-13 16:54:58,999 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:54:58,999 INFO L218 hiAutomatonCegarLoop]: Abstraction has 923 states and 1218 transitions. [2022-12-13 16:54:59,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 923 states and 1218 transitions. [2022-12-13 16:54:59,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 923 to 507. [2022-12-13 16:54:59,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 507 states, 500 states have (on average 1.304) internal successors, (652), 499 states have internal predecessors, (652), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2022-12-13 16:54:59,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 507 states to 507 states and 664 transitions. [2022-12-13 16:54:59,017 INFO L240 hiAutomatonCegarLoop]: Abstraction has 507 states and 664 transitions. [2022-12-13 16:54:59,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:54:59,018 INFO L428 stractBuchiCegarLoop]: Abstraction has 507 states and 664 transitions. [2022-12-13 16:54:59,018 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 16:54:59,018 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 507 states and 664 transitions. [2022-12-13 16:54:59,021 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 270 [2022-12-13 16:54:59,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:54:59,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:54:59,022 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 16:54:59,022 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:54:59,023 INFO L748 eck$LassoCheckResult]: Stem: 4096#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);~count_int_int~0 := 0; 4097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc8#1.base, main_#t~malloc8#1.offset, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem20#1, main_#t~mem22#1, main_#t~mem21#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~switch25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc37#1.base, main_#t~malloc37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~memset~res40#1.base, main_#t~memset~res40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~malloc46#1.base, main_#t~malloc46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~post70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem75#1, main_#t~mem74#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~short78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1, main_#t~malloc81#1.base, main_#t~malloc81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~memset~res86#1.base, main_#t~memset~res86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem91#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem95#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1, main_#t~pre109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1, main_#t~post114#1, main_#t~mem118#1, main_#t~mem116#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem117#1, main_#t~mem119#1, main_#t~post120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~post97#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~post130#1, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~ite140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem145#1, main_#t~mem144#1, main_#t~mem146#1, main_#t~mem147#1, main_#t~mem149#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem151#1, main_#t~mem153#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem155#1, main_#t~switch156#1, main_#t~mem157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~malloc168#1.base, main_#t~malloc168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~memset~res171#1.base, main_#t~memset~res171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~malloc177#1.base, main_#t~malloc177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~memset~res184#1.base, main_#t~memset~res184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1.base, main_#t~mem186#1.offset, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1, main_#t~post195#1, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_#t~mem200#1, main_#t~post201#1, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem206#1, main_#t~mem205#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1, main_#t~short209#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1, main_#t~malloc212#1.base, main_#t~malloc212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~memset~res217#1.base, main_#t~memset~res217#1.offset, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem222#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem226#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem237#1, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~pre240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1, main_#t~post245#1, main_#t~mem249#1, main_#t~mem247#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem248#1, main_#t~mem250#1, main_#t~post251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~post228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1, main_#t~post261#1, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem268#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1, main_#t~ite271#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_~_he_bkt~1#1, main_~_he_bkt_i~1#1, main_~_he_thh~1#1.base, main_~_he_thh~1#1.offset, main_~_he_hh_nxt~1#1.base, main_~_he_hh_nxt~1#1.offset, main_~#_he_new_buckets~1#1.base, main_~#_he_new_buckets~1#1.offset, main_~_he_newbkt~1#1.base, main_~_he_newbkt~1#1.offset, main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, main_~_ha_bkt~1#1, main_~_ha_hashv~1#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem276#1, main_#t~mem275#1, main_#t~mem277#1, main_#t~mem278#1, main_#t~mem280#1, main_#t~mem279#1, main_#t~mem281#1, main_#t~mem282#1, main_#t~mem284#1, main_#t~mem283#1, main_#t~mem285#1, main_#t~mem286#1, main_#t~switch287#1, main_#t~mem288#1, main_#t~mem289#1, main_#t~mem290#1, main_#t~mem291#1, main_#t~mem292#1, main_#t~mem293#1, main_#t~mem294#1, main_#t~mem295#1, main_#t~mem296#1, main_#t~mem297#1, main_#t~mem298#1, main_~_hj_i~2#1, main_~_hj_j~2#1, main_~_hj_k~2#1, main_~_hj_key~2#1.base, main_~_hj_key~2#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1.base, main_#t~mem302#1.offset, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1, main_#t~mem309#1, main_#t~mem310#1, main_#t~short311#1, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~ret313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem318#1, main_#t~mem320#1, main_#t~mem319#1, main_#t~mem321#1, main_#t~mem322#1, main_#t~mem324#1, main_#t~mem323#1, main_#t~mem325#1, main_#t~mem326#1, main_#t~mem328#1, main_#t~mem327#1, main_#t~mem329#1, main_#t~mem330#1, main_#t~switch331#1, main_#t~mem332#1, main_#t~mem333#1, main_#t~mem334#1, main_#t~mem335#1, main_#t~mem336#1, main_#t~mem337#1, main_#t~mem338#1, main_#t~mem339#1, main_#t~mem340#1, main_#t~mem341#1, main_#t~mem342#1, main_~_hj_i~3#1, main_~_hj_j~3#1, main_~_hj_k~3#1, main_~_hj_key~3#1.base, main_~_hj_key~3#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1.base, main_#t~mem349#1.offset, main_#t~mem350#1.base, main_#t~mem350#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_#t~mem352#1, main_#t~mem353#1, main_#t~mem354#1, main_#t~short355#1, main_#t~mem356#1.base, main_#t~mem356#1.offset, main_#t~ret357#1, main_#t~mem358#1.base, main_#t~mem358#1.offset, main_#t~mem359#1.base, main_#t~mem359#1.offset, main_#t~mem360#1.base, main_#t~mem360#1.offset, main_#t~mem361#1, main_~_hf_bkt~1#1, main_~_hf_hashv~1#1, main_#t~mem362#1, main_#t~mem364#1, main_#t~mem363#1, main_#t~mem365#1, main_#t~mem366#1, main_#t~mem368#1, main_#t~mem367#1, main_#t~mem369#1, main_#t~mem370#1, main_#t~mem372#1, main_#t~mem371#1, main_#t~mem373#1, main_#t~mem374#1, main_#t~switch375#1, main_#t~mem376#1, main_#t~mem377#1, main_#t~mem378#1, main_#t~mem379#1, main_#t~mem380#1, main_#t~mem381#1, main_#t~mem382#1, main_#t~mem383#1, main_#t~mem384#1, main_#t~mem385#1, main_#t~mem386#1, main_~_hj_i~4#1, main_~_hj_j~4#1, main_~_hj_k~4#1, main_~_hj_key~4#1.base, main_~_hj_key~4#1.offset, main_#t~mem387#1.base, main_#t~mem387#1.offset, main_#t~mem388#1, main_#t~mem389#1.base, main_#t~mem389#1.offset, main_#t~mem390#1.base, main_#t~mem390#1.offset, main_#t~mem391#1.base, main_#t~mem391#1.offset, main_#t~mem392#1.base, main_#t~mem392#1.offset, main_#t~mem393#1.base, main_#t~mem393#1.offset, main_#t~mem394#1.base, main_#t~mem394#1.offset, main_#t~mem395#1.base, main_#t~mem395#1.offset, main_#t~mem396#1, main_#t~mem397#1, main_#t~mem398#1, main_#t~short399#1, main_#t~mem400#1.base, main_#t~mem400#1.offset, main_#t~ret401#1, main_#t~mem402#1.base, main_#t~mem402#1.offset, main_#t~mem403#1.base, main_#t~mem403#1.offset, main_#t~mem404#1.base, main_#t~mem404#1.offset, main_#t~mem405#1, main_~_hf_bkt~2#1, main_~_hf_hashv~2#1, main_#t~mem406#1, main_#t~mem408#1, main_#t~mem407#1, main_#t~mem409#1, main_#t~mem410#1, main_#t~mem412#1, main_#t~mem411#1, main_#t~mem413#1, main_#t~mem414#1, main_#t~mem416#1, main_#t~mem415#1, main_#t~mem417#1, main_#t~mem418#1, main_#t~switch419#1, main_#t~mem420#1, main_#t~mem421#1, main_#t~mem422#1, main_#t~mem423#1, main_#t~mem424#1, main_#t~mem425#1, main_#t~mem426#1, main_#t~mem427#1, main_#t~mem428#1, main_#t~mem429#1, main_#t~mem430#1, main_~_hj_i~5#1, main_~_hj_j~5#1, main_~_hj_k~5#1, main_~_hj_key~5#1.base, main_~_hj_key~5#1.offset, main_#t~mem431#1.base, main_#t~mem431#1.offset, main_#t~mem432#1, main_#t~mem433#1.base, main_#t~mem433#1.offset, main_#t~mem434#1.base, main_#t~mem434#1.offset, main_#t~mem435#1.base, main_#t~mem435#1.offset, main_#t~mem436#1.base, main_#t~mem436#1.offset, main_#t~mem437#1.base, main_#t~mem437#1.offset, main_#t~mem438#1.base, main_#t~mem438#1.offset, main_#t~mem439#1.base, main_#t~mem439#1.offset, main_#t~mem440#1, main_#t~mem441#1, main_#t~mem442#1, main_#t~short443#1, main_#t~mem444#1.base, main_#t~mem444#1.offset, main_#t~ret445#1, main_#t~mem446#1.base, main_#t~mem446#1.offset, main_#t~mem447#1.base, main_#t~mem447#1.offset, main_#t~mem448#1.base, main_#t~mem448#1.offset, main_#t~mem449#1, main_~_hf_bkt~3#1, main_~_hf_hashv~3#1, main_#t~mem450#1, main_#t~ite452#1.base, main_#t~ite452#1.offset, main_#t~mem451#1.base, main_#t~mem451#1.offset, main_#t~mem455#1.base, main_#t~mem455#1.offset, main_#t~mem456#1.base, main_#t~mem456#1.offset, main_#t~short457#1, main_#t~mem458#1.base, main_#t~mem458#1.offset, main_#t~mem459#1.base, main_#t~mem459#1.offset, main_#t~mem460#1.base, main_#t~mem460#1.offset, main_#t~mem461#1.base, main_#t~mem461#1.offset, main_#t~mem462#1.base, main_#t~mem462#1.offset, main_#t~mem463#1.base, main_#t~mem463#1.offset, main_#t~mem464#1.base, main_#t~mem464#1.offset, main_#t~mem465#1.base, main_#t~mem465#1.offset, main_#t~mem466#1, main_#t~mem467#1.base, main_#t~mem467#1.offset, main_#t~mem468#1.base, main_#t~mem468#1.offset, main_#t~mem469#1.base, main_#t~mem469#1.offset, main_#t~mem470#1, main_#t~mem471#1.base, main_#t~mem471#1.offset, main_#t~mem472#1.base, main_#t~mem472#1.offset, main_#t~mem473#1.base, main_#t~mem473#1.offset, main_#t~mem474#1.base, main_#t~mem474#1.offset, main_#t~mem475#1.base, main_#t~mem475#1.offset, main_#t~mem476#1, main_#t~mem477#1.base, main_#t~mem477#1.offset, main_#t~mem480#1, main_#t~mem478#1.base, main_#t~mem478#1.offset, main_#t~mem479#1, main_#t~mem481#1.base, main_#t~mem481#1.offset, main_#t~mem482#1.base, main_#t~mem482#1.offset, main_#t~mem483#1, main_#t~post484#1, main_#t~mem485#1.base, main_#t~mem485#1.offset, main_#t~mem486#1.base, main_#t~mem486#1.offset, main_#t~mem487#1.base, main_#t~mem487#1.offset, main_#t~mem488#1.base, main_#t~mem488#1.offset, main_#t~mem489#1.base, main_#t~mem489#1.offset, main_#t~mem490#1.base, main_#t~mem490#1.offset, main_#t~mem491#1.base, main_#t~mem491#1.offset, main_#t~mem492#1.base, main_#t~mem492#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem493#1.base, main_#t~mem493#1.offset, main_#t~mem494#1, main_#t~post495#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem496#1.base, main_#t~mem496#1.offset, main_#t~mem497#1.base, main_#t~mem497#1.offset, main_#t~short498#1, main_#t~mem499#1.base, main_#t~mem499#1.offset, main_#t~mem500#1.base, main_#t~mem500#1.offset, main_#t~mem501#1.base, main_#t~mem501#1.offset, main_#t~mem502#1.base, main_#t~mem502#1.offset, main_#t~mem503#1.base, main_#t~mem503#1.offset, main_#t~mem504#1.base, main_#t~mem504#1.offset, main_#t~mem505#1.base, main_#t~mem505#1.offset, main_#t~mem506#1.base, main_#t~mem506#1.offset, main_#t~mem507#1, main_#t~mem508#1.base, main_#t~mem508#1.offset, main_#t~mem509#1.base, main_#t~mem509#1.offset, main_#t~mem510#1.base, main_#t~mem510#1.offset, main_#t~mem511#1, main_#t~mem512#1.base, main_#t~mem512#1.offset, main_#t~mem513#1.base, main_#t~mem513#1.offset, main_#t~mem514#1.base, main_#t~mem514#1.offset, main_#t~mem515#1.base, main_#t~mem515#1.offset, main_#t~mem516#1.base, main_#t~mem516#1.offset, main_#t~mem517#1, main_#t~mem518#1.base, main_#t~mem518#1.offset, main_#t~mem521#1, main_#t~mem519#1.base, main_#t~mem519#1.offset, main_#t~mem520#1, main_#t~mem522#1.base, main_#t~mem522#1.offset, main_#t~mem523#1.base, main_#t~mem523#1.offset, main_#t~mem524#1, main_#t~post525#1, main_#t~mem526#1.base, main_#t~mem526#1.offset, main_#t~mem527#1.base, main_#t~mem527#1.offset, main_#t~mem528#1.base, main_#t~mem528#1.offset, main_#t~mem529#1.base, main_#t~mem529#1.offset, main_#t~mem530#1.base, main_#t~mem530#1.offset, main_#t~mem531#1.base, main_#t~mem531#1.offset, main_#t~mem532#1.base, main_#t~mem532#1.offset, main_#t~mem533#1.base, main_#t~mem533#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem534#1.base, main_#t~mem534#1.offset, main_#t~mem535#1, main_#t~post536#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite454#1.base, main_#t~ite454#1.offset, main_#t~mem453#1.base, main_#t~mem453#1.offset, main_~usertmp~0#1.base, main_~usertmp~0#1.offset, main_~userstmp~0#1.base, main_~userstmp~0#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~altusers~0#1.base, main_~altusers~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~altusers~0#1.base, main_~altusers~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 3963#L733-4 [2022-12-13 16:54:59,023 INFO L750 eck$LassoCheckResult]: Loop: 3963#L733-4 call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 3829#L733-1 assume !!(main_#t~mem7#1 < 1000);havoc main_#t~mem7#1;call main_#t~malloc8#1.base, main_#t~malloc8#1.offset := #Ultimate.allocOnHeap(72);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc8#1.base, main_#t~malloc8#1.offset;havoc main_#t~malloc8#1.base, main_#t~malloc8#1.offset; 3831#L735 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 4042#L735-2 call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem9#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem9#1;call main_#t~mem10#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem11#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem10#1 * main_#t~mem11#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem10#1;havoc main_#t~mem11#1;call main_#t~mem12#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 4043#L740 assume !(main_#t~mem12#1 < 10);havoc main_#t~mem12#1; 4241#L743-120 havoc main_~_ha_hashv~1#1; 4219#L743-48 goto; 3884#L743-46 havoc main_~_hj_i~1#1;havoc main_~_hj_j~1#1;havoc main_~_hj_k~1#1;main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~1#1 := 4276993775;main_~_hj_j~1#1 := 2654435769;main_~_hj_i~1#1 := main_~_hj_j~1#1;main_~_hj_k~1#1 := 4; 3885#L743-7 assume !(main_~_hj_k~1#1 % 4294967296 >= 12); 3974#L743-8 main_~_ha_hashv~1#1 := 4 + main_~_ha_hashv~1#1;main_#t~switch156#1 := 11 == main_~_hj_k~1#1; 3975#L743-9 assume !main_#t~switch156#1; 4305#L743-11 main_#t~switch156#1 := main_#t~switch156#1 || 10 == main_~_hj_k~1#1; 4112#L743-12 assume !main_#t~switch156#1; 4113#L743-14 main_#t~switch156#1 := main_#t~switch156#1 || 9 == main_~_hj_k~1#1; 4168#L743-15 assume !main_#t~switch156#1; 4209#L743-17 main_#t~switch156#1 := main_#t~switch156#1 || 8 == main_~_hj_k~1#1; 4210#L743-18 assume !main_#t~switch156#1; 4175#L743-20 main_#t~switch156#1 := main_#t~switch156#1 || 7 == main_~_hj_k~1#1; 4176#L743-21 assume !main_#t~switch156#1; 4120#L743-23 main_#t~switch156#1 := main_#t~switch156#1 || 6 == main_~_hj_k~1#1; 4121#L743-24 assume !main_#t~switch156#1; 4246#L743-26 main_#t~switch156#1 := main_#t~switch156#1 || 5 == main_~_hj_k~1#1; 4114#L743-27 assume !main_#t~switch156#1; 4115#L743-29 main_#t~switch156#1 := main_#t~switch156#1 || 4 == main_~_hj_k~1#1; 3859#L743-30 assume main_#t~switch156#1;call main_#t~mem164#1 := read~int(main_~_hj_key~1#1.base, 3 + main_~_hj_key~1#1.offset, 1);main_~_hj_i~1#1 := main_~_hj_i~1#1 + 16777216 * (main_#t~mem164#1 % 256);havoc main_#t~mem164#1; 3860#L743-32 main_#t~switch156#1 := main_#t~switch156#1 || 3 == main_~_hj_k~1#1; 4066#L743-33 assume main_#t~switch156#1;call main_#t~mem165#1 := read~int(main_~_hj_key~1#1.base, 2 + main_~_hj_key~1#1.offset, 1);main_~_hj_i~1#1 := main_~_hj_i~1#1 + 65536 * (main_#t~mem165#1 % 256);havoc main_#t~mem165#1; 4280#L743-35 main_#t~switch156#1 := main_#t~switch156#1 || 2 == main_~_hj_k~1#1; 4191#L743-36 assume main_#t~switch156#1;call main_#t~mem166#1 := read~int(main_~_hj_key~1#1.base, 1 + main_~_hj_key~1#1.offset, 1);main_~_hj_i~1#1 := main_~_hj_i~1#1 + 256 * (main_#t~mem166#1 % 256);havoc main_#t~mem166#1; 4192#L743-38 main_#t~switch156#1 := main_#t~switch156#1 || 1 == main_~_hj_k~1#1; 4100#L743-39 assume main_#t~switch156#1;call main_#t~mem167#1 := read~int(main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, 1);main_~_hj_i~1#1 := main_~_hj_i~1#1 + main_#t~mem167#1 % 256;havoc main_#t~mem167#1; 4101#L743-41 havoc main_#t~switch156#1; 4225#L743-44 main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_hj_j~1#1;main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_ha_hashv~1#1;main_~_hj_i~1#1 := (if 0 == main_~_hj_i~1#1 then main_~_ha_hashv~1#1 / 8192 else (if 0 == main_~_ha_hashv~1#1 / 8192 then main_~_hj_i~1#1 else (if main_~_hj_i~1#1 == main_~_ha_hashv~1#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~1#1, main_~_ha_hashv~1#1 / 8192))));main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_ha_hashv~1#1;main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_hj_i~1#1;main_~_hj_j~1#1 := (if 0 == main_~_hj_j~1#1 then 256 * main_~_hj_i~1#1 else (if 0 == 256 * main_~_hj_i~1#1 then main_~_hj_j~1#1 else (if main_~_hj_j~1#1 == 256 * main_~_hj_i~1#1 then 0 else ~bitwiseXor(main_~_hj_j~1#1, 256 * main_~_hj_i~1#1))));main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_i~1#1;main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_j~1#1;main_~_ha_hashv~1#1 := (if 0 == main_~_ha_hashv~1#1 then main_~_hj_j~1#1 / 8192 else (if 0 == main_~_hj_j~1#1 / 8192 then main_~_ha_hashv~1#1 else (if main_~_ha_hashv~1#1 == main_~_hj_j~1#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~1#1, main_~_hj_j~1#1 / 8192))));main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_hj_j~1#1;main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_ha_hashv~1#1;main_~_hj_i~1#1 := (if 0 == main_~_hj_i~1#1 then main_~_ha_hashv~1#1 / 4096 else (if 0 == main_~_ha_hashv~1#1 / 4096 then main_~_hj_i~1#1 else (if main_~_hj_i~1#1 == main_~_ha_hashv~1#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~1#1, main_~_ha_hashv~1#1 / 4096))));main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_ha_hashv~1#1;main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_hj_i~1#1;main_~_hj_j~1#1 := (if 0 == main_~_hj_j~1#1 then 65536 * main_~_hj_i~1#1 else (if 0 == 65536 * main_~_hj_i~1#1 then main_~_hj_j~1#1 else (if main_~_hj_j~1#1 == 65536 * main_~_hj_i~1#1 then 0 else ~bitwiseXor(main_~_hj_j~1#1, 65536 * main_~_hj_i~1#1))));main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_i~1#1;main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_j~1#1;main_~_ha_hashv~1#1 := (if 0 == main_~_ha_hashv~1#1 then main_~_hj_j~1#1 / 32 else (if 0 == main_~_hj_j~1#1 / 32 then main_~_ha_hashv~1#1 else (if main_~_ha_hashv~1#1 == main_~_hj_j~1#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~1#1, main_~_hj_j~1#1 / 32))));main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_hj_j~1#1;main_~_hj_i~1#1 := main_~_hj_i~1#1 - main_~_ha_hashv~1#1;main_~_hj_i~1#1 := (if 0 == main_~_hj_i~1#1 then main_~_ha_hashv~1#1 / 8 else (if 0 == main_~_ha_hashv~1#1 / 8 then main_~_hj_i~1#1 else (if main_~_hj_i~1#1 == main_~_ha_hashv~1#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~1#1, main_~_ha_hashv~1#1 / 8))));main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_ha_hashv~1#1;main_~_hj_j~1#1 := main_~_hj_j~1#1 - main_~_hj_i~1#1;main_~_hj_j~1#1 := (if 0 == main_~_hj_j~1#1 then 1024 * main_~_hj_i~1#1 else (if 0 == 1024 * main_~_hj_i~1#1 then main_~_hj_j~1#1 else (if main_~_hj_j~1#1 == 1024 * main_~_hj_i~1#1 then 0 else ~bitwiseXor(main_~_hj_j~1#1, 1024 * main_~_hj_i~1#1))));main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_i~1#1;main_~_ha_hashv~1#1 := main_~_ha_hashv~1#1 - main_~_hj_j~1#1;main_~_ha_hashv~1#1 := (if 0 == main_~_ha_hashv~1#1 then main_~_hj_j~1#1 / 32768 else (if 0 == main_~_hj_j~1#1 / 32768 then main_~_ha_hashv~1#1 else (if main_~_ha_hashv~1#1 == main_~_hj_j~1#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~1#1, main_~_hj_j~1#1 / 32768)))); 4226#L743-43 goto; 4252#L743-45 goto; 3926#L743-47 goto; 3927#L743-118 call write~int(main_~_ha_hashv~1#1, main_~user~0#1.base, 68 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 60 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 64 + main_~user~0#1.offset, 4); 4109#L743-50 assume !(main_~altusers~0#1.base == 0 && main_~altusers~0#1.offset == 0);call main_#t~mem185#1.base, main_#t~mem185#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call write~$Pointer$(main_#t~mem185#1.base, main_#t~mem185#1.offset, main_~user~0#1.base, 40 + main_~user~0#1.offset, 4);havoc main_#t~mem185#1.base, main_#t~mem185#1.offset; 4179#L743-66 call write~$Pointer$(0, 0, main_~user~0#1.base, 48 + main_~user~0#1.offset, 4);call main_#t~mem186#1.base, main_#t~mem186#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem187#1.base, main_#t~mem187#1.offset := read~$Pointer$(main_#t~mem186#1.base, 16 + main_#t~mem186#1.offset, 4);call main_#t~mem188#1.base, main_#t~mem188#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem189#1 := read~int(main_#t~mem188#1.base, 20 + main_#t~mem188#1.offset, 4);call write~$Pointer$(main_#t~mem187#1.base, main_#t~mem187#1.offset - main_#t~mem189#1, main_~user~0#1.base, 44 + main_~user~0#1.offset, 4);havoc main_#t~mem186#1.base, main_#t~mem186#1.offset;havoc main_#t~mem187#1.base, main_#t~mem187#1.offset;havoc main_#t~mem188#1.base, main_#t~mem188#1.offset;havoc main_#t~mem189#1;call main_#t~mem190#1.base, main_#t~mem190#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem191#1.base, main_#t~mem191#1.offset := read~$Pointer$(main_#t~mem190#1.base, 16 + main_#t~mem190#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem191#1.base, 8 + main_#t~mem191#1.offset, 4);havoc main_#t~mem190#1.base, main_#t~mem190#1.offset;havoc main_#t~mem191#1.base, main_#t~mem191#1.offset;call main_#t~mem192#1.base, main_#t~mem192#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 40 + main_~user~0#1.offset, main_#t~mem192#1.base, 16 + main_#t~mem192#1.offset, 4);havoc main_#t~mem192#1.base, main_#t~mem192#1.offset; 4180#L743-65 goto; 3984#L743-116 havoc main_~_ha_bkt~1#1;call main_#t~mem193#1.base, main_#t~mem193#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem194#1 := read~int(main_#t~mem193#1.base, 12 + main_#t~mem193#1.offset, 4);main_#t~post195#1 := main_#t~mem194#1;call write~int(1 + main_#t~post195#1, main_#t~mem193#1.base, 12 + main_#t~mem193#1.offset, 4);havoc main_#t~mem193#1.base, main_#t~mem193#1.offset;havoc main_#t~mem194#1;havoc main_#t~post195#1; 3985#L743-70 call main_#t~mem196#1.base, main_#t~mem196#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem197#1 := read~int(main_#t~mem196#1.base, 4 + main_#t~mem196#1.offset, 4);main_~_ha_bkt~1#1 := (if 0 == main_~_ha_hashv~1#1 || 0 == main_#t~mem197#1 - 1 then 0 else (if main_~_ha_hashv~1#1 == main_#t~mem197#1 - 1 then main_~_ha_hashv~1#1 else ~bitwiseAnd(main_~_ha_hashv~1#1, main_#t~mem197#1 - 1)));havoc main_#t~mem196#1.base, main_#t~mem196#1.offset;havoc main_#t~mem197#1; 3917#L743-69 goto; 3918#L743-114 call main_#t~mem198#1.base, main_#t~mem198#1.offset := read~$Pointer$(main_~altusers~0#1.base, 40 + main_~altusers~0#1.offset, 4);call main_#t~mem199#1.base, main_#t~mem199#1.offset := read~$Pointer$(main_#t~mem198#1.base, main_#t~mem198#1.offset, 4);main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset := main_#t~mem199#1.base, main_#t~mem199#1.offset + 12 * (if main_~_ha_bkt~1#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~1#1 % 4294967296 % 4294967296 else main_~_ha_bkt~1#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem198#1.base, main_#t~mem198#1.offset;havoc main_#t~mem199#1.base, main_#t~mem199#1.offset;call main_#t~mem200#1 := read~int(main_~_ha_head~1#1.base, 4 + main_~_ha_head~1#1.offset, 4);main_#t~post201#1 := main_#t~mem200#1;call write~int(1 + main_#t~post201#1, main_~_ha_head~1#1.base, 4 + main_~_ha_head~1#1.offset, 4);havoc main_#t~mem200#1;havoc main_#t~post201#1;call main_#t~mem202#1.base, main_#t~mem202#1.offset := read~$Pointer$(main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, 4);call write~$Pointer$(main_#t~mem202#1.base, main_#t~mem202#1.offset, main_~user~0#1.base, 56 + main_~user~0#1.offset, 4);havoc main_#t~mem202#1.base, main_#t~mem202#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 52 + main_~user~0#1.offset, 4);call main_#t~mem203#1.base, main_#t~mem203#1.offset := read~$Pointer$(main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, 4); 4093#L743-72 assume main_#t~mem203#1.base != 0 || main_#t~mem203#1.offset != 0;havoc main_#t~mem203#1.base, main_#t~mem203#1.offset;call main_#t~mem204#1.base, main_#t~mem204#1.offset := read~$Pointer$(main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 40 + main_~user~0#1.offset, main_#t~mem204#1.base, 12 + main_#t~mem204#1.offset, 4);havoc main_#t~mem204#1.base, main_#t~mem204#1.offset; 4078#L743-74 call write~$Pointer$(main_~user~0#1.base, 40 + main_~user~0#1.offset, main_~_ha_head~1#1.base, main_~_ha_head~1#1.offset, 4);call main_#t~mem206#1 := read~int(main_~_ha_head~1#1.base, 4 + main_~_ha_head~1#1.offset, 4);call main_#t~mem205#1 := read~int(main_~_ha_head~1#1.base, 8 + main_~_ha_head~1#1.offset, 4);main_#t~short209#1 := main_#t~mem206#1 % 4294967296 >= 10 * (1 + main_#t~mem205#1) % 4294967296; 3991#L743-75 assume !main_#t~short209#1; 3992#L743-77 assume !main_#t~short209#1;havoc main_#t~mem206#1;havoc main_#t~mem205#1;havoc main_#t~mem207#1.base, main_#t~mem207#1.offset;havoc main_#t~mem208#1;havoc main_#t~short209#1; 4282#L743-113 goto; 4283#L743-115 goto; 4332#L743-117 goto; 3953#L743-119 goto; 3954#L733-3 call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post6#1 := main_#t~mem5#1;call write~int(1 + main_#t~post6#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem5#1;havoc main_#t~post6#1; 3963#L733-4 [2022-12-13 16:54:59,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:59,024 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 4 times [2022-12-13 16:54:59,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:59,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73749333] [2022-12-13 16:54:59,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:59,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:59,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:59,048 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:54:59,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:54:59,075 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:54:59,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:54:59,075 INFO L85 PathProgramCache]: Analyzing trace with hash 1586451843, now seen corresponding path program 1 times [2022-12-13 16:54:59,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:54:59,076 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1125885359] [2022-12-13 16:54:59,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:59,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:54:59,179 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-13 16:54:59,179 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1822813008] [2022-12-13 16:54:59,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:54:59,180 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 16:54:59,180 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 16:54:59,181 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 16:54:59,182 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58c47e53-dbf7-48f9-b29d-b7861e352c34/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process