./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test6-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test6-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 3012c2825f53c0db53d950c12df6540de859b34b2bef033c36a98846352dedd3 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 20:54:23,635 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 20:54:23,637 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 20:54:23,656 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 20:54:23,656 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 20:54:23,657 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 20:54:23,659 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 20:54:23,660 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 20:54:23,662 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 20:54:23,663 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 20:54:23,663 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 20:54:23,665 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 20:54:23,665 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 20:54:23,666 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 20:54:23,667 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 20:54:23,668 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 20:54:23,669 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 20:54:23,670 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 20:54:23,671 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 20:54:23,673 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 20:54:23,675 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 20:54:23,676 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 20:54:23,677 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 20:54:23,678 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 20:54:23,682 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 20:54:23,682 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 20:54:23,682 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 20:54:23,683 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 20:54:23,684 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 20:54:23,685 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 20:54:23,685 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 20:54:23,686 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 20:54:23,686 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 20:54:23,687 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 20:54:23,688 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 20:54:23,688 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 20:54:23,689 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 20:54:23,689 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 20:54:23,689 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 20:54:23,690 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 20:54:23,691 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 20:54:23,691 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 20:54:23,713 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 20:54:23,713 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 20:54:23,714 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 20:54:23,714 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 20:54:23,715 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 20:54:23,715 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 20:54:23,715 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 20:54:23,715 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 20:54:23,716 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 20:54:23,716 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 20:54:23,716 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 20:54:23,716 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 20:54:23,716 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 20:54:23,717 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 20:54:23,717 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 20:54:23,717 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 20:54:23,717 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 20:54:23,717 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 20:54:23,718 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 20:54:23,718 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 20:54:23,718 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 20:54:23,718 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 20:54:23,718 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 20:54:23,718 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 20:54:23,719 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 20:54:23,719 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 20:54:23,719 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 20:54:23,719 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 20:54:23,719 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 20:54:23,720 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 20:54:23,720 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 20:54:23,721 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 20:54:23,721 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 3012c2825f53c0db53d950c12df6540de859b34b2bef033c36a98846352dedd3 [2022-12-13 20:54:23,927 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 20:54:23,946 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 20:54:23,948 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 20:54:23,949 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 20:54:23,950 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 20:54:23,951 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test6-1.i [2022-12-13 20:54:26,503 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 20:54:26,764 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 20:54:26,764 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test6-1.i [2022-12-13 20:54:26,778 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/data/2d096f827/74b9802d6d174c2db907ee6359e44251/FLAG30e967a45 [2022-12-13 20:54:26,792 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/data/2d096f827/74b9802d6d174c2db907ee6359e44251 [2022-12-13 20:54:26,795 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 20:54:26,796 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 20:54:26,797 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 20:54:26,797 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 20:54:26,800 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 20:54:26,801 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 08:54:26" (1/1) ... [2022-12-13 20:54:26,802 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@e4247e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:26, skipping insertion in model container [2022-12-13 20:54:26,802 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 08:54:26" (1/1) ... [2022-12-13 20:54:26,808 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 20:54:26,850 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 20:54:27,304 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test6-1.i[44118,44131] [2022-12-13 20:54:27,315 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test6-1.i[44660,44673] [2022-12-13 20:54:27,317 WARN L623 FunctionHandler]: Unknown extern function memcmp [2022-12-13 20:54:27,407 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test6-1.i[56247,56260] [2022-12-13 20:54:27,408 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test6-1.i[56368,56381] [2022-12-13 20:54:27,413 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 20:54:27,422 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 20:54:27,447 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test6-1.i[44118,44131] [2022-12-13 20:54:27,450 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test6-1.i[44660,44673] [2022-12-13 20:54:27,450 WARN L623 FunctionHandler]: Unknown extern function memcmp [2022-12-13 20:54:27,488 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test6-1.i[56247,56260] [2022-12-13 20:54:27,489 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test6-1.i[56368,56381] [2022-12-13 20:54:27,492 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 20:54:27,553 INFO L208 MainTranslator]: Completed translation [2022-12-13 20:54:27,553 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:27 WrapperNode [2022-12-13 20:54:27,554 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 20:54:27,555 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 20:54:27,555 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 20:54:27,555 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 20:54:27,562 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:27" (1/1) ... [2022-12-13 20:54:27,599 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:27" (1/1) ... [2022-12-13 20:54:27,641 INFO L138 Inliner]: procedures = 282, calls = 294, calls flagged for inlining = 19, calls inlined = 21, statements flattened = 1139 [2022-12-13 20:54:27,641 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 20:54:27,642 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 20:54:27,642 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 20:54:27,642 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 20:54:27,650 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:27" (1/1) ... [2022-12-13 20:54:27,650 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:27" (1/1) ... [2022-12-13 20:54:27,665 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:27" (1/1) ... [2022-12-13 20:54:27,665 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:27" (1/1) ... [2022-12-13 20:54:27,717 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:27" (1/1) ... [2022-12-13 20:54:27,728 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:27" (1/1) ... [2022-12-13 20:54:27,738 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:27" (1/1) ... [2022-12-13 20:54:27,746 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:27" (1/1) ... [2022-12-13 20:54:27,759 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 20:54:27,760 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 20:54:27,761 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 20:54:27,761 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 20:54:27,761 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:27" (1/1) ... [2022-12-13 20:54:27,767 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 20:54:27,778 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 20:54:27,790 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 20:54:27,792 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 20:54:27,835 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2022-12-13 20:54:27,835 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2022-12-13 20:54:27,835 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-12-13 20:54:27,835 INFO L130 BoogieDeclarations]: Found specification of procedure memcmp [2022-12-13 20:54:27,835 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-12-13 20:54:27,835 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-12-13 20:54:27,836 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-12-13 20:54:27,836 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-12-13 20:54:27,836 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-12-13 20:54:27,836 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 20:54:27,836 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-12-13 20:54:27,836 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 20:54:27,836 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 20:54:27,837 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 20:54:28,005 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 20:54:28,007 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 20:54:28,011 WARN L816 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2022-12-13 20:54:29,234 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 20:54:29,243 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 20:54:29,243 INFO L300 CfgBuilder]: Removed 63 assume(true) statements. [2022-12-13 20:54:29,246 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 08:54:29 BoogieIcfgContainer [2022-12-13 20:54:29,246 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 20:54:29,247 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 20:54:29,247 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 20:54:29,250 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 20:54:29,251 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:54:29,251 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 08:54:26" (1/3) ... [2022-12-13 20:54:29,252 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@68f38517 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 08:54:29, skipping insertion in model container [2022-12-13 20:54:29,252 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:54:29,252 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:54:27" (2/3) ... [2022-12-13 20:54:29,253 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@68f38517 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 08:54:29, skipping insertion in model container [2022-12-13 20:54:29,253 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:54:29,253 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 08:54:29" (3/3) ... [2022-12-13 20:54:29,254 INFO L332 chiAutomizerObserver]: Analyzing ICFG uthash_JEN_test6-1.i [2022-12-13 20:54:29,307 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 20:54:29,307 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 20:54:29,308 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 20:54:29,308 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 20:54:29,308 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 20:54:29,308 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 20:54:29,308 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 20:54:29,308 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 20:54:29,313 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 220 states, 215 states have (on average 1.627906976744186) internal successors, (350), 215 states have internal predecessors, (350), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-13 20:54:29,345 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 202 [2022-12-13 20:54:29,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:54:29,345 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:54:29,351 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 20:54:29,351 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:54:29,352 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 20:54:29,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 220 states, 215 states have (on average 1.627906976744186) internal successors, (350), 215 states have internal predecessors, (350), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-13 20:54:29,364 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 202 [2022-12-13 20:54:29,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:54:29,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:54:29,365 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 20:54:29,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:54:29,372 INFO L748 eck$LassoCheckResult]: Stem: 128#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 135#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~pre140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1, main_#t~post145#1, main_#t~mem149#1, main_#t~mem147#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem148#1, main_#t~mem150#1, main_#t~post151#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1, main_#t~post163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~ite173#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem181#1, main_#t~mem180#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem185#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem189#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~switch192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1, main_#t~mem214#1, main_#t~mem215#1, main_#t~short216#1, main_#t~mem217#1.base, main_#t~mem217#1.offset, main_#t~ret218#1, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~short225#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem250#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem249#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem177#1, main_#t~post178#1, main_#t~mem179#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 10#L989-4true [2022-12-13 20:54:29,372 INFO L750 eck$LassoCheckResult]: Loop: 10#L989-4true call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 5#L989-1true assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 4#real_malloc_returnLabel#1true main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 11#L991true assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false; 82#L991-2true call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 196#L996-115true assume !true; 200#L989-3true call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 10#L989-4true [2022-12-13 20:54:29,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:54:29,377 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 1 times [2022-12-13 20:54:29,385 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:54:29,385 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615501015] [2022-12-13 20:54:29,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:29,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:54:29,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:54:29,484 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:54:29,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:54:29,528 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:54:29,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:54:29,531 INFO L85 PathProgramCache]: Analyzing trace with hash -1530816298, now seen corresponding path program 1 times [2022-12-13 20:54:29,531 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:54:29,531 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368139051] [2022-12-13 20:54:29,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:29,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:54:29,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:54:29,563 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:54:29,563 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [368139051] [2022-12-13 20:54:29,563 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2022-12-13 20:54:29,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2105413546] [2022-12-13 20:54:29,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:29,564 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 20:54:29,564 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 20:54:29,565 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 20:54:29,566 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-12-13 20:54:29,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:54:29,678 INFO L263 TraceCheckSpWp]: Trace formula consists of 82 conjuncts, 1 conjunts are in the unsatisfiable core [2022-12-13 20:54:29,679 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-13 20:54:29,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:54:29,696 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-13 20:54:29,696 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2105413546] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:54:29,697 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:54:29,697 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:54:29,698 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538321559] [2022-12-13 20:54:29,698 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:54:29,701 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:54:29,702 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:54:29,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 20:54:29,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 20:54:29,732 INFO L87 Difference]: Start difference. First operand has 220 states, 215 states have (on average 1.627906976744186) internal successors, (350), 215 states have internal predecessors, (350), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:54:29,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:54:29,753 INFO L93 Difference]: Finished difference Result 216 states and 273 transitions. [2022-12-13 20:54:29,754 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 216 states and 273 transitions. [2022-12-13 20:54:29,760 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 197 [2022-12-13 20:54:29,767 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 216 states to 204 states and 261 transitions. [2022-12-13 20:54:29,768 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 204 [2022-12-13 20:54:29,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 204 [2022-12-13 20:54:29,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 204 states and 261 transitions. [2022-12-13 20:54:29,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:54:29,773 INFO L218 hiAutomatonCegarLoop]: Abstraction has 204 states and 261 transitions. [2022-12-13 20:54:29,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states and 261 transitions. [2022-12-13 20:54:29,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 204. [2022-12-13 20:54:29,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 204 states, 200 states have (on average 1.275) internal successors, (255), 199 states have internal predecessors, (255), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-13 20:54:29,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 261 transitions. [2022-12-13 20:54:29,807 INFO L240 hiAutomatonCegarLoop]: Abstraction has 204 states and 261 transitions. [2022-12-13 20:54:29,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 20:54:29,810 INFO L428 stractBuchiCegarLoop]: Abstraction has 204 states and 261 transitions. [2022-12-13 20:54:29,810 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 20:54:29,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 261 transitions. [2022-12-13 20:54:29,811 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 197 [2022-12-13 20:54:29,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:54:29,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:54:29,812 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 20:54:29,812 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:54:29,812 INFO L748 eck$LassoCheckResult]: Stem: 638#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 639#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~pre140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1, main_#t~post145#1, main_#t~mem149#1, main_#t~mem147#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem148#1, main_#t~mem150#1, main_#t~post151#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1, main_#t~post163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~ite173#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem181#1, main_#t~mem180#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem185#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem189#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~switch192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1, main_#t~mem214#1, main_#t~mem215#1, main_#t~short216#1, main_#t~mem217#1.base, main_#t~mem217#1.offset, main_#t~ret218#1, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~short225#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem250#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem249#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem177#1, main_#t~post178#1, main_#t~mem179#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 476#L989-4 [2022-12-13 20:54:29,813 INFO L750 eck$LassoCheckResult]: Loop: 476#L989-4 call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 468#L989-1 assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 466#real_malloc_returnLabel#1 main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 467#L991 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 477#L991-2 call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 592#L996-115 havoc main_~_ha_hashv~0#1; 634#L996-49 goto; 635#L996-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 471#L996-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 497#L996-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch59#1 := 11 == main_~_hj_k~0#1; 660#L996-10 assume main_#t~switch59#1;call main_#t~mem60#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem60#1 % 256);havoc main_#t~mem60#1; 665#L996-12 main_#t~switch59#1 := main_#t~switch59#1 || 10 == main_~_hj_k~0#1; 568#L996-13 assume main_#t~switch59#1;call main_#t~mem61#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem61#1 % 256);havoc main_#t~mem61#1; 569#L996-15 main_#t~switch59#1 := main_#t~switch59#1 || 9 == main_~_hj_k~0#1; 661#L996-16 assume main_#t~switch59#1;call main_#t~mem62#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem62#1 % 256);havoc main_#t~mem62#1; 662#L996-18 main_#t~switch59#1 := main_#t~switch59#1 || 8 == main_~_hj_k~0#1; 653#L996-19 assume main_#t~switch59#1;call main_#t~mem63#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem63#1 % 256);havoc main_#t~mem63#1; 652#L996-21 main_#t~switch59#1 := main_#t~switch59#1 || 7 == main_~_hj_k~0#1; 630#L996-22 assume main_#t~switch59#1;call main_#t~mem64#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem64#1 % 256);havoc main_#t~mem64#1; 631#L996-24 main_#t~switch59#1 := main_#t~switch59#1 || 6 == main_~_hj_k~0#1; 649#L996-25 assume main_#t~switch59#1;call main_#t~mem65#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem65#1 % 256);havoc main_#t~mem65#1; 626#L996-27 main_#t~switch59#1 := main_#t~switch59#1 || 5 == main_~_hj_k~0#1; 472#L996-28 assume !main_#t~switch59#1; 473#L996-30 main_#t~switch59#1 := main_#t~switch59#1 || 4 == main_~_hj_k~0#1; 600#L996-31 assume main_#t~switch59#1;call main_#t~mem67#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem67#1 % 256);havoc main_#t~mem67#1; 618#L996-33 main_#t~switch59#1 := main_#t~switch59#1 || 3 == main_~_hj_k~0#1; 588#L996-34 assume main_#t~switch59#1;call main_#t~mem68#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem68#1 % 256);havoc main_#t~mem68#1; 589#L996-36 main_#t~switch59#1 := main_#t~switch59#1 || 2 == main_~_hj_k~0#1; 550#L996-37 assume main_#t~switch59#1;call main_#t~mem69#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem69#1 % 256);havoc main_#t~mem69#1; 551#L996-39 main_#t~switch59#1 := main_#t~switch59#1 || 1 == main_~_hj_k~0#1; 572#L996-40 assume main_#t~switch59#1;call main_#t~mem70#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem70#1 % 256;havoc main_#t~mem70#1; 601#L996-42 havoc main_#t~switch59#1; 530#L996-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 531#L996-44 goto; 613#L996-46 goto; 627#L996-48 goto; 517#L996-113 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 518#L996-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem86#1.base, main_#t~mem86#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset; 578#L996-63 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$(main_#t~mem87#1.base, 16 + main_#t~mem87#1.offset, 4);call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem90#1 := read~int(main_#t~mem89#1.base, 20 + main_#t~mem89#1.offset, 4);call write~$Pointer$(main_#t~mem88#1.base, main_#t~mem88#1.offset - main_#t~mem90#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;call main_#t~mem91#1.base, main_#t~mem91#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$(main_#t~mem91#1.base, 16 + main_#t~mem91#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem92#1.base, 8 + main_#t~mem92#1.offset, 4);havoc main_#t~mem91#1.base, main_#t~mem91#1.offset;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;call main_#t~mem93#1.base, main_#t~mem93#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem93#1.base, 16 + main_#t~mem93#1.offset, 4);havoc main_#t~mem93#1.base, main_#t~mem93#1.offset; 579#L996-62 goto; 533#L996-111 havoc main_~_ha_bkt~0#1;call main_#t~mem94#1.base, main_#t~mem94#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem95#1 := read~int(main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);main_#t~post96#1 := main_#t~mem95#1;call write~int(1 + main_#t~post96#1, main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);havoc main_#t~mem94#1.base, main_#t~mem94#1.offset;havoc main_#t~mem95#1;havoc main_#t~post96#1; 622#L996-67 call main_#t~mem97#1.base, main_#t~mem97#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem98#1 := read~int(main_#t~mem97#1.base, 4 + main_#t~mem97#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem98#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem98#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1)));havoc main_#t~mem97#1.base, main_#t~mem97#1.offset;havoc main_#t~mem98#1; 623#L996-66 goto; 656#L996-109 call main_#t~mem99#1.base, main_#t~mem99#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem100#1.base, main_#t~mem100#1.offset := read~$Pointer$(main_#t~mem99#1.base, main_#t~mem99#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem100#1.base, main_#t~mem100#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem99#1.base, main_#t~mem99#1.offset;havoc main_#t~mem100#1.base, main_#t~mem100#1.offset;call main_#t~mem101#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post102#1 := main_#t~mem101#1;call write~int(1 + main_#t~post102#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem101#1;havoc main_#t~post102#1;call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem103#1.base, main_#t~mem103#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 650#L996-69 assume main_#t~mem104#1.base != 0 || main_#t~mem104#1.offset != 0;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem105#1.base, 12 + main_#t~mem105#1.offset, 4);havoc main_#t~mem105#1.base, main_#t~mem105#1.offset; 498#L996-71 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem107#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem106#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short110#1 := main_#t~mem107#1 % 4294967296 >= 10 * (1 + main_#t~mem106#1) % 4294967296; 499#L996-72 assume main_#t~short110#1;call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem109#1 := read~int(main_#t~mem108#1.base, 36 + main_#t~mem108#1.offset, 4);main_#t~short110#1 := 0 == main_#t~mem109#1 % 4294967296; 554#L996-74 assume !main_#t~short110#1;havoc main_#t~mem107#1;havoc main_#t~mem106#1;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;havoc main_#t~mem109#1;havoc main_#t~short110#1; 521#L996-108 goto; 515#L996-110 goto; 516#L996-112 goto; 566#L996-114 goto; 567#L989-3 call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 476#L989-4 [2022-12-13 20:54:29,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:54:29,813 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 2 times [2022-12-13 20:54:29,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:54:29,814 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328720886] [2022-12-13 20:54:29,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:29,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:54:29,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:54:29,827 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:54:29,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:54:29,841 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:54:29,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:54:29,841 INFO L85 PathProgramCache]: Analyzing trace with hash 1735500791, now seen corresponding path program 1 times [2022-12-13 20:54:29,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:54:29,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930325761] [2022-12-13 20:54:29,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:29,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:54:29,989 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-13 20:54:29,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1248661825] [2022-12-13 20:54:29,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:29,990 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 20:54:29,990 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 20:54:30,004 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 20:54:30,005 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-12-13 20:54:30,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:54:30,532 INFO L263 TraceCheckSpWp]: Trace formula consists of 1858 conjuncts, 3 conjunts are in the unsatisfiable core [2022-12-13 20:54:30,535 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-13 20:54:30,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:54:30,567 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-13 20:54:30,567 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:54:30,567 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930325761] [2022-12-13 20:54:30,567 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-13 20:54:30,567 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1248661825] [2022-12-13 20:54:30,568 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1248661825] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:54:30,568 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:54:30,568 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:54:30,568 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1783493741] [2022-12-13 20:54:30,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:54:30,569 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:54:30,569 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:54:30,569 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:54:30,570 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:54:30,570 INFO L87 Difference]: Start difference. First operand 204 states and 261 transitions. cyclomatic complexity: 60 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:54:30,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:54:30,650 INFO L93 Difference]: Finished difference Result 225 states and 282 transitions. [2022-12-13 20:54:30,651 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 225 states and 282 transitions. [2022-12-13 20:54:30,653 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 218 [2022-12-13 20:54:30,655 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 225 states to 225 states and 282 transitions. [2022-12-13 20:54:30,655 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 225 [2022-12-13 20:54:30,655 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 225 [2022-12-13 20:54:30,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 225 states and 282 transitions. [2022-12-13 20:54:30,656 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:54:30,656 INFO L218 hiAutomatonCegarLoop]: Abstraction has 225 states and 282 transitions. [2022-12-13 20:54:30,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states and 282 transitions. [2022-12-13 20:54:30,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 224. [2022-12-13 20:54:30,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224 states, 220 states have (on average 1.25) internal successors, (275), 219 states have internal predecessors, (275), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-13 20:54:30,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 281 transitions. [2022-12-13 20:54:30,665 INFO L240 hiAutomatonCegarLoop]: Abstraction has 224 states and 281 transitions. [2022-12-13 20:54:30,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:54:30,666 INFO L428 stractBuchiCegarLoop]: Abstraction has 224 states and 281 transitions. [2022-12-13 20:54:30,666 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 20:54:30,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 224 states and 281 transitions. [2022-12-13 20:54:30,668 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 217 [2022-12-13 20:54:30,668 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:54:30,668 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:54:30,669 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 20:54:30,669 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:54:30,669 INFO L748 eck$LassoCheckResult]: Stem: 1231#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 1232#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~pre140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1, main_#t~post145#1, main_#t~mem149#1, main_#t~mem147#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem148#1, main_#t~mem150#1, main_#t~post151#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1, main_#t~post163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~ite173#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem181#1, main_#t~mem180#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem185#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem189#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~switch192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1, main_#t~mem214#1, main_#t~mem215#1, main_#t~short216#1, main_#t~mem217#1.base, main_#t~mem217#1.offset, main_#t~ret218#1, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~short225#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem250#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem249#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem177#1, main_#t~post178#1, main_#t~mem179#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1067#L989-4 [2022-12-13 20:54:30,670 INFO L750 eck$LassoCheckResult]: Loop: 1067#L989-4 call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1059#L989-1 assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 1057#real_malloc_returnLabel#1 main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 1058#L991 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1068#L991-2 call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 1184#L996-115 havoc main_~_ha_hashv~0#1; 1227#L996-49 goto; 1228#L996-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 1062#L996-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 1090#L996-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch59#1 := 11 == main_~_hj_k~0#1; 1254#L996-10 assume main_#t~switch59#1;call main_#t~mem60#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem60#1 % 256);havoc main_#t~mem60#1; 1260#L996-12 main_#t~switch59#1 := main_#t~switch59#1 || 10 == main_~_hj_k~0#1; 1159#L996-13 assume main_#t~switch59#1;call main_#t~mem61#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem61#1 % 256);havoc main_#t~mem61#1; 1160#L996-15 main_#t~switch59#1 := main_#t~switch59#1 || 9 == main_~_hj_k~0#1; 1256#L996-16 assume main_#t~switch59#1;call main_#t~mem62#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem62#1 % 256);havoc main_#t~mem62#1; 1257#L996-18 main_#t~switch59#1 := main_#t~switch59#1 || 8 == main_~_hj_k~0#1; 1246#L996-19 assume main_#t~switch59#1;call main_#t~mem63#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem63#1 % 256);havoc main_#t~mem63#1; 1245#L996-21 main_#t~switch59#1 := main_#t~switch59#1 || 7 == main_~_hj_k~0#1; 1223#L996-22 assume main_#t~switch59#1;call main_#t~mem64#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem64#1 % 256);havoc main_#t~mem64#1; 1224#L996-24 main_#t~switch59#1 := main_#t~switch59#1 || 6 == main_~_hj_k~0#1; 1242#L996-25 assume main_#t~switch59#1;call main_#t~mem65#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem65#1 % 256);havoc main_#t~mem65#1; 1219#L996-27 main_#t~switch59#1 := main_#t~switch59#1 || 5 == main_~_hj_k~0#1; 1063#L996-28 assume main_#t~switch59#1;call main_#t~mem66#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem66#1 % 256;havoc main_#t~mem66#1; 1064#L996-30 main_#t~switch59#1 := main_#t~switch59#1 || 4 == main_~_hj_k~0#1; 1192#L996-31 assume main_#t~switch59#1;call main_#t~mem67#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem67#1 % 256);havoc main_#t~mem67#1; 1255#L996-33 main_#t~switch59#1 := main_#t~switch59#1 || 3 == main_~_hj_k~0#1; 1180#L996-34 assume main_#t~switch59#1;call main_#t~mem68#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem68#1 % 256);havoc main_#t~mem68#1; 1181#L996-36 main_#t~switch59#1 := main_#t~switch59#1 || 2 == main_~_hj_k~0#1; 1141#L996-37 assume main_#t~switch59#1;call main_#t~mem69#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem69#1 % 256);havoc main_#t~mem69#1; 1142#L996-39 main_#t~switch59#1 := main_#t~switch59#1 || 1 == main_~_hj_k~0#1; 1248#L996-40 assume main_#t~switch59#1;call main_#t~mem70#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem70#1 % 256;havoc main_#t~mem70#1; 1193#L996-42 havoc main_#t~switch59#1; 1121#L996-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1122#L996-44 goto; 1205#L996-46 goto; 1220#L996-48 goto; 1108#L996-113 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1109#L996-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem86#1.base, main_#t~mem86#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset; 1171#L996-63 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$(main_#t~mem87#1.base, 16 + main_#t~mem87#1.offset, 4);call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem90#1 := read~int(main_#t~mem89#1.base, 20 + main_#t~mem89#1.offset, 4);call write~$Pointer$(main_#t~mem88#1.base, main_#t~mem88#1.offset - main_#t~mem90#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;call main_#t~mem91#1.base, main_#t~mem91#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$(main_#t~mem91#1.base, 16 + main_#t~mem91#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem92#1.base, 8 + main_#t~mem92#1.offset, 4);havoc main_#t~mem91#1.base, main_#t~mem91#1.offset;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;call main_#t~mem93#1.base, main_#t~mem93#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem93#1.base, 16 + main_#t~mem93#1.offset, 4);havoc main_#t~mem93#1.base, main_#t~mem93#1.offset; 1172#L996-62 goto; 1124#L996-111 havoc main_~_ha_bkt~0#1;call main_#t~mem94#1.base, main_#t~mem94#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem95#1 := read~int(main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);main_#t~post96#1 := main_#t~mem95#1;call write~int(1 + main_#t~post96#1, main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);havoc main_#t~mem94#1.base, main_#t~mem94#1.offset;havoc main_#t~mem95#1;havoc main_#t~post96#1; 1215#L996-67 call main_#t~mem97#1.base, main_#t~mem97#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem98#1 := read~int(main_#t~mem97#1.base, 4 + main_#t~mem97#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem98#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem98#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1)));havoc main_#t~mem97#1.base, main_#t~mem97#1.offset;havoc main_#t~mem98#1; 1216#L996-66 goto; 1251#L996-109 call main_#t~mem99#1.base, main_#t~mem99#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem100#1.base, main_#t~mem100#1.offset := read~$Pointer$(main_#t~mem99#1.base, main_#t~mem99#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem100#1.base, main_#t~mem100#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem99#1.base, main_#t~mem99#1.offset;havoc main_#t~mem100#1.base, main_#t~mem100#1.offset;call main_#t~mem101#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post102#1 := main_#t~mem101#1;call write~int(1 + main_#t~post102#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem101#1;havoc main_#t~post102#1;call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem103#1.base, main_#t~mem103#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 1243#L996-69 assume main_#t~mem104#1.base != 0 || main_#t~mem104#1.offset != 0;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem105#1.base, 12 + main_#t~mem105#1.offset, 4);havoc main_#t~mem105#1.base, main_#t~mem105#1.offset; 1091#L996-71 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem107#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem106#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short110#1 := main_#t~mem107#1 % 4294967296 >= 10 * (1 + main_#t~mem106#1) % 4294967296; 1092#L996-72 assume main_#t~short110#1;call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem109#1 := read~int(main_#t~mem108#1.base, 36 + main_#t~mem108#1.offset, 4);main_#t~short110#1 := 0 == main_#t~mem109#1 % 4294967296; 1145#L996-74 assume !main_#t~short110#1;havoc main_#t~mem107#1;havoc main_#t~mem106#1;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;havoc main_#t~mem109#1;havoc main_#t~short110#1; 1112#L996-108 goto; 1106#L996-110 goto; 1107#L996-112 goto; 1157#L996-114 goto; 1158#L989-3 call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 1067#L989-4 [2022-12-13 20:54:30,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:54:30,670 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 3 times [2022-12-13 20:54:30,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:54:30,671 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1202504128] [2022-12-13 20:54:30,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:30,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:54:30,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:54:30,703 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:54:30,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:54:30,726 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:54:30,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:54:30,727 INFO L85 PathProgramCache]: Analyzing trace with hash 1033900917, now seen corresponding path program 1 times [2022-12-13 20:54:30,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:54:30,727 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864750818] [2022-12-13 20:54:30,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:30,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:54:30,828 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-13 20:54:30,828 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1228779487] [2022-12-13 20:54:30,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:30,829 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 20:54:30,829 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 20:54:30,830 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 20:54:30,832 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-12-13 20:54:31,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:54:31,409 INFO L263 TraceCheckSpWp]: Trace formula consists of 1864 conjuncts, 3 conjunts are in the unsatisfiable core [2022-12-13 20:54:31,411 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-13 20:54:31,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:54:31,432 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-13 20:54:31,433 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:54:31,433 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864750818] [2022-12-13 20:54:31,433 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-13 20:54:31,433 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1228779487] [2022-12-13 20:54:31,433 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1228779487] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:54:31,433 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:54:31,433 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-13 20:54:31,434 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213988035] [2022-12-13 20:54:31,434 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:54:31,434 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:54:31,434 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:54:31,435 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:54:31,435 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:54:31,435 INFO L87 Difference]: Start difference. First operand 224 states and 281 transitions. cyclomatic complexity: 60 Second operand has 4 states, 4 states have (on average 13.25) internal successors, (53), 4 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:54:31,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:54:31,501 INFO L93 Difference]: Finished difference Result 308 states and 386 transitions. [2022-12-13 20:54:31,502 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 386 transitions. [2022-12-13 20:54:31,505 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 292 [2022-12-13 20:54:31,508 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 308 states and 386 transitions. [2022-12-13 20:54:31,509 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 308 [2022-12-13 20:54:31,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 308 [2022-12-13 20:54:31,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 308 states and 386 transitions. [2022-12-13 20:54:31,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:54:31,511 INFO L218 hiAutomatonCegarLoop]: Abstraction has 308 states and 386 transitions. [2022-12-13 20:54:31,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states and 386 transitions. [2022-12-13 20:54:31,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 210. [2022-12-13 20:54:31,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 210 states, 206 states have (on average 1.233009708737864) internal successors, (254), 205 states have internal predecessors, (254), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-13 20:54:31,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 260 transitions. [2022-12-13 20:54:31,524 INFO L240 hiAutomatonCegarLoop]: Abstraction has 210 states and 260 transitions. [2022-12-13 20:54:31,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:54:31,525 INFO L428 stractBuchiCegarLoop]: Abstraction has 210 states and 260 transitions. [2022-12-13 20:54:31,525 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 20:54:31,525 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 210 states and 260 transitions. [2022-12-13 20:54:31,527 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 203 [2022-12-13 20:54:31,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:54:31,527 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:54:31,528 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 20:54:31,528 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:54:31,528 INFO L748 eck$LassoCheckResult]: Stem: 1928#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 1929#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~pre140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1, main_#t~post145#1, main_#t~mem149#1, main_#t~mem147#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem148#1, main_#t~mem150#1, main_#t~post151#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1, main_#t~post163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~ite173#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem181#1, main_#t~mem180#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem185#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem189#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~switch192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1, main_#t~mem214#1, main_#t~mem215#1, main_#t~short216#1, main_#t~mem217#1.base, main_#t~mem217#1.offset, main_#t~ret218#1, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~short225#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem250#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem249#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem177#1, main_#t~post178#1, main_#t~mem179#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1764#L989-4 [2022-12-13 20:54:31,529 INFO L750 eck$LassoCheckResult]: Loop: 1764#L989-4 call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1756#L989-1 assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 1754#real_malloc_returnLabel#1 main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 1755#L991 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1765#L991-2 call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 1880#L996-115 havoc main_~_ha_hashv~0#1; 1923#L996-49 goto; 1924#L996-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 1759#L996-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 1789#L996-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch59#1 := 11 == main_~_hj_k~0#1; 1949#L996-10 assume !main_#t~switch59#1; 1955#L996-12 main_#t~switch59#1 := main_#t~switch59#1 || 10 == main_~_hj_k~0#1; 1856#L996-13 assume !main_#t~switch59#1; 1857#L996-15 main_#t~switch59#1 := main_#t~switch59#1 || 9 == main_~_hj_k~0#1; 1951#L996-16 assume !main_#t~switch59#1; 1952#L996-18 main_#t~switch59#1 := main_#t~switch59#1 || 8 == main_~_hj_k~0#1; 1942#L996-19 assume !main_#t~switch59#1; 1941#L996-21 main_#t~switch59#1 := main_#t~switch59#1 || 7 == main_~_hj_k~0#1; 1919#L996-22 assume !main_#t~switch59#1; 1920#L996-24 main_#t~switch59#1 := main_#t~switch59#1 || 6 == main_~_hj_k~0#1; 1938#L996-25 assume !main_#t~switch59#1; 1915#L996-27 main_#t~switch59#1 := main_#t~switch59#1 || 5 == main_~_hj_k~0#1; 1760#L996-28 assume !main_#t~switch59#1; 1761#L996-30 main_#t~switch59#1 := main_#t~switch59#1 || 4 == main_~_hj_k~0#1; 1888#L996-31 assume !main_#t~switch59#1; 1906#L996-33 main_#t~switch59#1 := main_#t~switch59#1 || 3 == main_~_hj_k~0#1; 1907#L996-34 assume main_#t~switch59#1;call main_#t~mem68#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem68#1 % 256);havoc main_#t~mem68#1; 1877#L996-36 main_#t~switch59#1 := main_#t~switch59#1 || 2 == main_~_hj_k~0#1; 1838#L996-37 assume main_#t~switch59#1;call main_#t~mem69#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem69#1 % 256);havoc main_#t~mem69#1; 1839#L996-39 main_#t~switch59#1 := main_#t~switch59#1 || 1 == main_~_hj_k~0#1; 1860#L996-40 assume main_#t~switch59#1;call main_#t~mem70#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem70#1 % 256;havoc main_#t~mem70#1; 1889#L996-42 havoc main_#t~switch59#1; 1818#L996-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1819#L996-44 goto; 1903#L996-46 goto; 1916#L996-48 goto; 1805#L996-113 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1806#L996-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem86#1.base, main_#t~mem86#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset; 1867#L996-63 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$(main_#t~mem87#1.base, 16 + main_#t~mem87#1.offset, 4);call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem90#1 := read~int(main_#t~mem89#1.base, 20 + main_#t~mem89#1.offset, 4);call write~$Pointer$(main_#t~mem88#1.base, main_#t~mem88#1.offset - main_#t~mem90#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;call main_#t~mem91#1.base, main_#t~mem91#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$(main_#t~mem91#1.base, 16 + main_#t~mem91#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem92#1.base, 8 + main_#t~mem92#1.offset, 4);havoc main_#t~mem91#1.base, main_#t~mem91#1.offset;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;call main_#t~mem93#1.base, main_#t~mem93#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem93#1.base, 16 + main_#t~mem93#1.offset, 4);havoc main_#t~mem93#1.base, main_#t~mem93#1.offset; 1868#L996-62 goto; 1821#L996-111 havoc main_~_ha_bkt~0#1;call main_#t~mem94#1.base, main_#t~mem94#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem95#1 := read~int(main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);main_#t~post96#1 := main_#t~mem95#1;call write~int(1 + main_#t~post96#1, main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);havoc main_#t~mem94#1.base, main_#t~mem94#1.offset;havoc main_#t~mem95#1;havoc main_#t~post96#1; 1911#L996-67 call main_#t~mem97#1.base, main_#t~mem97#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem98#1 := read~int(main_#t~mem97#1.base, 4 + main_#t~mem97#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem98#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem98#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1)));havoc main_#t~mem97#1.base, main_#t~mem97#1.offset;havoc main_#t~mem98#1; 1912#L996-66 goto; 1944#L996-109 call main_#t~mem99#1.base, main_#t~mem99#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem100#1.base, main_#t~mem100#1.offset := read~$Pointer$(main_#t~mem99#1.base, main_#t~mem99#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem100#1.base, main_#t~mem100#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem99#1.base, main_#t~mem99#1.offset;havoc main_#t~mem100#1.base, main_#t~mem100#1.offset;call main_#t~mem101#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post102#1 := main_#t~mem101#1;call write~int(1 + main_#t~post102#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem101#1;havoc main_#t~post102#1;call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem103#1.base, main_#t~mem103#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 1939#L996-69 assume main_#t~mem104#1.base != 0 || main_#t~mem104#1.offset != 0;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem105#1.base, 12 + main_#t~mem105#1.offset, 4);havoc main_#t~mem105#1.base, main_#t~mem105#1.offset; 1784#L996-71 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem107#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem106#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short110#1 := main_#t~mem107#1 % 4294967296 >= 10 * (1 + main_#t~mem106#1) % 4294967296; 1785#L996-72 assume main_#t~short110#1;call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem109#1 := read~int(main_#t~mem108#1.base, 36 + main_#t~mem108#1.offset, 4);main_#t~short110#1 := 0 == main_#t~mem109#1 % 4294967296; 1842#L996-74 assume !main_#t~short110#1;havoc main_#t~mem107#1;havoc main_#t~mem106#1;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;havoc main_#t~mem109#1;havoc main_#t~short110#1; 1807#L996-108 goto; 1803#L996-110 goto; 1804#L996-112 goto; 1852#L996-114 goto; 1853#L989-3 call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 1764#L989-4 [2022-12-13 20:54:31,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:54:31,529 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 4 times [2022-12-13 20:54:31,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:54:31,530 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45988784] [2022-12-13 20:54:31,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:31,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:54:31,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:54:31,549 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:54:31,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:54:31,575 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:54:31,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:54:31,575 INFO L85 PathProgramCache]: Analyzing trace with hash 545729925, now seen corresponding path program 1 times [2022-12-13 20:54:31,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:54:31,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1639231998] [2022-12-13 20:54:31,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:31,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:54:31,681 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-13 20:54:31,681 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [673721170] [2022-12-13 20:54:31,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:31,681 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 20:54:31,681 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 20:54:31,683 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 20:54:31,683 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-12-13 20:54:32,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:54:32,308 INFO L263 TraceCheckSpWp]: Trace formula consists of 1816 conjuncts, 4 conjunts are in the unsatisfiable core [2022-12-13 20:54:32,311 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-13 20:54:32,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:54:32,344 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-13 20:54:32,344 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:54:32,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1639231998] [2022-12-13 20:54:32,345 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-13 20:54:32,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [673721170] [2022-12-13 20:54:32,345 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [673721170] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:54:32,345 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:54:32,345 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:54:32,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421330680] [2022-12-13 20:54:32,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:54:32,346 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:54:32,346 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:54:32,346 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 20:54:32,346 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-12-13 20:54:32,346 INFO L87 Difference]: Start difference. First operand 210 states and 260 transitions. cyclomatic complexity: 53 Second operand has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:54:32,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:54:32,466 INFO L93 Difference]: Finished difference Result 415 states and 512 transitions. [2022-12-13 20:54:32,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 415 states and 512 transitions. [2022-12-13 20:54:32,469 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 407 [2022-12-13 20:54:32,472 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 415 states to 415 states and 512 transitions. [2022-12-13 20:54:32,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 415 [2022-12-13 20:54:32,473 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 415 [2022-12-13 20:54:32,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 415 states and 512 transitions. [2022-12-13 20:54:32,474 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:54:32,474 INFO L218 hiAutomatonCegarLoop]: Abstraction has 415 states and 512 transitions. [2022-12-13 20:54:32,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 415 states and 512 transitions. [2022-12-13 20:54:32,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 415 to 233. [2022-12-13 20:54:32,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 233 states, 229 states have (on average 1.2183406113537119) internal successors, (279), 228 states have internal predecessors, (279), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-13 20:54:32,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233 states to 233 states and 285 transitions. [2022-12-13 20:54:32,482 INFO L240 hiAutomatonCegarLoop]: Abstraction has 233 states and 285 transitions. [2022-12-13 20:54:32,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-12-13 20:54:32,483 INFO L428 stractBuchiCegarLoop]: Abstraction has 233 states and 285 transitions. [2022-12-13 20:54:32,483 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 20:54:32,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 233 states and 285 transitions. [2022-12-13 20:54:32,485 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 226 [2022-12-13 20:54:32,485 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:54:32,485 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:54:32,485 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 20:54:32,485 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:54:32,486 INFO L748 eck$LassoCheckResult]: Stem: 2719#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 2720#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~pre140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1, main_#t~post145#1, main_#t~mem149#1, main_#t~mem147#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem148#1, main_#t~mem150#1, main_#t~post151#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1, main_#t~post163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~ite173#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem181#1, main_#t~mem180#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem185#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem189#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~switch192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1, main_#t~mem214#1, main_#t~mem215#1, main_#t~short216#1, main_#t~mem217#1.base, main_#t~mem217#1.offset, main_#t~ret218#1, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~short225#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem250#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem249#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem177#1, main_#t~post178#1, main_#t~mem179#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 2553#L989-4 [2022-12-13 20:54:32,486 INFO L750 eck$LassoCheckResult]: Loop: 2553#L989-4 call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 2545#L989-1 assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 2543#real_malloc_returnLabel#1 main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 2544#L991 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 2554#L991-2 call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 2671#L996-115 havoc main_~_ha_hashv~0#1; 2715#L996-49 goto; 2716#L996-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 2573#L996-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 2575#L996-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch59#1 := 11 == main_~_hj_k~0#1; 2759#L996-10 assume !main_#t~switch59#1; 2760#L996-12 main_#t~switch59#1 := main_#t~switch59#1 || 10 == main_~_hj_k~0#1; 2646#L996-13 assume !main_#t~switch59#1; 2647#L996-15 main_#t~switch59#1 := main_#t~switch59#1 || 9 == main_~_hj_k~0#1; 2751#L996-16 assume !main_#t~switch59#1; 2752#L996-18 main_#t~switch59#1 := main_#t~switch59#1 || 8 == main_~_hj_k~0#1; 2738#L996-19 assume !main_#t~switch59#1; 2739#L996-21 main_#t~switch59#1 := main_#t~switch59#1 || 7 == main_~_hj_k~0#1; 2711#L996-22 assume !main_#t~switch59#1; 2712#L996-24 main_#t~switch59#1 := main_#t~switch59#1 || 6 == main_~_hj_k~0#1; 2734#L996-25 assume !main_#t~switch59#1; 2735#L996-27 main_#t~switch59#1 := main_#t~switch59#1 || 5 == main_~_hj_k~0#1; 2549#L996-28 assume !main_#t~switch59#1; 2550#L996-30 main_#t~switch59#1 := main_#t~switch59#1 || 4 == main_~_hj_k~0#1; 2749#L996-31 assume main_#t~switch59#1;call main_#t~mem67#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem67#1 % 256);havoc main_#t~mem67#1; 2698#L996-33 main_#t~switch59#1 := main_#t~switch59#1 || 3 == main_~_hj_k~0#1; 2667#L996-34 assume main_#t~switch59#1;call main_#t~mem68#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem68#1 % 256);havoc main_#t~mem68#1; 2668#L996-36 main_#t~switch59#1 := main_#t~switch59#1 || 2 == main_~_hj_k~0#1; 2763#L996-37 assume main_#t~switch59#1;call main_#t~mem69#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem69#1 % 256);havoc main_#t~mem69#1; 2650#L996-39 main_#t~switch59#1 := main_#t~switch59#1 || 1 == main_~_hj_k~0#1; 2651#L996-40 assume main_#t~switch59#1;call main_#t~mem70#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem70#1 % 256;havoc main_#t~mem70#1; 2681#L996-42 havoc main_#t~switch59#1; 2608#L996-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 2609#L996-44 goto; 2693#L996-46 goto; 2708#L996-48 goto; 2595#L996-113 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 2596#L996-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem86#1.base, main_#t~mem86#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset; 2657#L996-63 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$(main_#t~mem87#1.base, 16 + main_#t~mem87#1.offset, 4);call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem90#1 := read~int(main_#t~mem89#1.base, 20 + main_#t~mem89#1.offset, 4);call write~$Pointer$(main_#t~mem88#1.base, main_#t~mem88#1.offset - main_#t~mem90#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;call main_#t~mem91#1.base, main_#t~mem91#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$(main_#t~mem91#1.base, 16 + main_#t~mem91#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem92#1.base, 8 + main_#t~mem92#1.offset, 4);havoc main_#t~mem91#1.base, main_#t~mem91#1.offset;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;call main_#t~mem93#1.base, main_#t~mem93#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem93#1.base, 16 + main_#t~mem93#1.offset, 4);havoc main_#t~mem93#1.base, main_#t~mem93#1.offset; 2658#L996-62 goto; 2611#L996-111 havoc main_~_ha_bkt~0#1;call main_#t~mem94#1.base, main_#t~mem94#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem95#1 := read~int(main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);main_#t~post96#1 := main_#t~mem95#1;call write~int(1 + main_#t~post96#1, main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);havoc main_#t~mem94#1.base, main_#t~mem94#1.offset;havoc main_#t~mem95#1;havoc main_#t~post96#1; 2702#L996-67 call main_#t~mem97#1.base, main_#t~mem97#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem98#1 := read~int(main_#t~mem97#1.base, 4 + main_#t~mem97#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem98#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem98#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1)));havoc main_#t~mem97#1.base, main_#t~mem97#1.offset;havoc main_#t~mem98#1; 2703#L996-66 goto; 2743#L996-109 call main_#t~mem99#1.base, main_#t~mem99#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem100#1.base, main_#t~mem100#1.offset := read~$Pointer$(main_#t~mem99#1.base, main_#t~mem99#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem100#1.base, main_#t~mem100#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem99#1.base, main_#t~mem99#1.offset;havoc main_#t~mem100#1.base, main_#t~mem100#1.offset;call main_#t~mem101#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post102#1 := main_#t~mem101#1;call write~int(1 + main_#t~post102#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem101#1;havoc main_#t~post102#1;call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem103#1.base, main_#t~mem103#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 2732#L996-69 assume main_#t~mem104#1.base != 0 || main_#t~mem104#1.offset != 0;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem105#1.base, 12 + main_#t~mem105#1.offset, 4);havoc main_#t~mem105#1.base, main_#t~mem105#1.offset; 2576#L996-71 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem107#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem106#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short110#1 := main_#t~mem107#1 % 4294967296 >= 10 * (1 + main_#t~mem106#1) % 4294967296; 2577#L996-72 assume main_#t~short110#1;call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem109#1 := read~int(main_#t~mem108#1.base, 36 + main_#t~mem108#1.offset, 4);main_#t~short110#1 := 0 == main_#t~mem109#1 % 4294967296; 2632#L996-74 assume !main_#t~short110#1;havoc main_#t~mem107#1;havoc main_#t~mem106#1;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;havoc main_#t~mem109#1;havoc main_#t~short110#1; 2599#L996-108 goto; 2593#L996-110 goto; 2594#L996-112 goto; 2644#L996-114 goto; 2645#L989-3 call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 2553#L989-4 [2022-12-13 20:54:32,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:54:32,486 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 5 times [2022-12-13 20:54:32,486 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:54:32,487 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075392242] [2022-12-13 20:54:32,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:32,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:54:32,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:54:32,503 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:54:32,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:54:32,523 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:54:32,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:54:32,523 INFO L85 PathProgramCache]: Analyzing trace with hash -840473469, now seen corresponding path program 1 times [2022-12-13 20:54:32,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:54:32,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [904673361] [2022-12-13 20:54:32,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:32,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:54:32,611 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-13 20:54:32,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [381335948] [2022-12-13 20:54:32,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:54:32,612 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 20:54:32,612 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 20:54:32,613 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 20:54:32,614 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f27e8073-83bc-40f6-b662-7e6ff64e54eb/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process