./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test1-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test1-2.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bfb70cce6cd508003f6161c30aa2ac99ac8ddeb6209ddd86b65ca0c623c2fb1c --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 18:53:55,381 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 18:53:55,382 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 18:53:55,394 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 18:53:55,395 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 18:53:55,395 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 18:53:55,396 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 18:53:55,397 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 18:53:55,398 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 18:53:55,399 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 18:53:55,399 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 18:53:55,400 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 18:53:55,400 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 18:53:55,401 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 18:53:55,401 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 18:53:55,402 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 18:53:55,403 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 18:53:55,403 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 18:53:55,404 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 18:53:55,406 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 18:53:55,407 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 18:53:55,407 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 18:53:55,408 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 18:53:55,409 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 18:53:55,411 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 18:53:55,411 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 18:53:55,411 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 18:53:55,412 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 18:53:55,412 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 18:53:55,413 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 18:53:55,413 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 18:53:55,414 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 18:53:55,414 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 18:53:55,415 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 18:53:55,415 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 18:53:55,415 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 18:53:55,416 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 18:53:55,416 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 18:53:55,416 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 18:53:55,417 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 18:53:55,417 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 18:53:55,418 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 18:53:55,433 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 18:53:55,434 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 18:53:55,434 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 18:53:55,434 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 18:53:55,435 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 18:53:55,435 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 18:53:55,435 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 18:53:55,435 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 18:53:55,435 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 18:53:55,435 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 18:53:55,435 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 18:53:55,436 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 18:53:55,436 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 18:53:55,436 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 18:53:55,436 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 18:53:55,436 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 18:53:55,436 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 18:53:55,436 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 18:53:55,436 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 18:53:55,437 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 18:53:55,437 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 18:53:55,437 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 18:53:55,437 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 18:53:55,437 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 18:53:55,437 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 18:53:55,437 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 18:53:55,437 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 18:53:55,438 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 18:53:55,438 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 18:53:55,438 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 18:53:55,438 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 18:53:55,439 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 18:53:55,439 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bfb70cce6cd508003f6161c30aa2ac99ac8ddeb6209ddd86b65ca0c623c2fb1c [2022-12-13 18:53:55,597 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 18:53:55,616 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 18:53:55,618 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 18:53:55,619 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 18:53:55,619 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 18:53:55,620 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test1-2.i [2022-12-13 18:53:58,143 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 18:53:58,351 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 18:53:58,351 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test1-2.i [2022-12-13 18:53:58,360 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/data/58ad26d1a/c956f8eb22484f898912ed7c5cb61c2b/FLAG8822db505 [2022-12-13 18:53:58,700 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/data/58ad26d1a/c956f8eb22484f898912ed7c5cb61c2b [2022-12-13 18:53:58,703 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 18:53:58,704 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 18:53:58,705 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 18:53:58,705 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 18:53:58,709 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 18:53:58,710 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 06:53:58" (1/1) ... [2022-12-13 18:53:58,711 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7ae8b11d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:58, skipping insertion in model container [2022-12-13 18:53:58,711 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 06:53:58" (1/1) ... [2022-12-13 18:53:58,719 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 18:53:58,751 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 18:53:58,975 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test1-2.i[33021,33034] [2022-12-13 18:53:59,026 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 18:53:59,035 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 18:53:59,056 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test1-2.i[33021,33034] [2022-12-13 18:53:59,085 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 18:53:59,104 INFO L208 MainTranslator]: Completed translation [2022-12-13 18:53:59,105 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:59 WrapperNode [2022-12-13 18:53:59,105 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 18:53:59,105 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 18:53:59,106 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 18:53:59,106 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 18:53:59,111 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:59" (1/1) ... [2022-12-13 18:53:59,131 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:59" (1/1) ... [2022-12-13 18:53:59,173 INFO L138 Inliner]: procedures = 177, calls = 237, calls flagged for inlining = 13, calls inlined = 13, statements flattened = 803 [2022-12-13 18:53:59,173 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 18:53:59,174 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 18:53:59,174 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 18:53:59,174 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 18:53:59,182 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:59" (1/1) ... [2022-12-13 18:53:59,182 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:59" (1/1) ... [2022-12-13 18:53:59,189 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:59" (1/1) ... [2022-12-13 18:53:59,189 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:59" (1/1) ... [2022-12-13 18:53:59,223 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:59" (1/1) ... [2022-12-13 18:53:59,231 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:59" (1/1) ... [2022-12-13 18:53:59,234 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:59" (1/1) ... [2022-12-13 18:53:59,236 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:59" (1/1) ... [2022-12-13 18:53:59,241 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 18:53:59,241 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 18:53:59,241 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 18:53:59,241 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 18:53:59,242 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:59" (1/1) ... [2022-12-13 18:53:59,247 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 18:53:59,256 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 18:53:59,267 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 18:53:59,269 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 18:53:59,303 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-12-13 18:53:59,303 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-12-13 18:53:59,303 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2022-12-13 18:53:59,304 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2022-12-13 18:53:59,304 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-12-13 18:53:59,304 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 18:53:59,304 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-12-13 18:53:59,304 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-12-13 18:53:59,304 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-12-13 18:53:59,304 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-12-13 18:53:59,304 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 18:53:59,305 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 18:53:59,305 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 18:53:59,471 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 18:53:59,473 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 18:53:59,476 WARN L816 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2022-12-13 18:54:00,482 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 18:54:00,487 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 18:54:00,488 INFO L300 CfgBuilder]: Removed 40 assume(true) statements. [2022-12-13 18:54:00,489 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 06:54:00 BoogieIcfgContainer [2022-12-13 18:54:00,489 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 18:54:00,490 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 18:54:00,490 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 18:54:00,493 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 18:54:00,493 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 18:54:00,493 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 06:53:58" (1/3) ... [2022-12-13 18:54:00,494 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@443eab32 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 06:54:00, skipping insertion in model container [2022-12-13 18:54:00,494 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 18:54:00,494 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:53:59" (2/3) ... [2022-12-13 18:54:00,494 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@443eab32 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 06:54:00, skipping insertion in model container [2022-12-13 18:54:00,495 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 18:54:00,495 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 06:54:00" (3/3) ... [2022-12-13 18:54:00,496 INFO L332 chiAutomizerObserver]: Analyzing ICFG uthash_OAT_test1-2.i [2022-12-13 18:54:00,536 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 18:54:00,536 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 18:54:00,536 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 18:54:00,536 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 18:54:00,536 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 18:54:00,536 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 18:54:00,536 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 18:54:00,536 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 18:54:00,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 160 states, 155 states have (on average 1.6516129032258065) internal successors, (256), 155 states have internal predecessors, (256), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-13 18:54:00,560 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 146 [2022-12-13 18:54:00,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:54:00,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:54:00,565 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 18:54:00,565 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-12-13 18:54:00,565 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 18:54:00,566 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 160 states, 155 states have (on average 1.6516129032258065) internal successors, (256), 155 states have internal predecessors, (256), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-13 18:54:00,571 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 146 [2022-12-13 18:54:00,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:54:00,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:54:00,571 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 18:54:00,571 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-12-13 18:54:00,577 INFO L748 eck$LassoCheckResult]: Stem: 42#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 52#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~ite142#1.base, main_#t~ite142#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~short147#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1.base, main_#t~mem163#1.offset, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~post174#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1, main_#t~post185#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite144#1.base, main_#t~ite144#1.offset, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 129#L750-3true [2022-12-13 18:54:00,577 INFO L750 eck$LassoCheckResult]: Loop: 129#L750-3true assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 88#L752true assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false; 90#L752-2true call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 34#L757-121true assume !true; 63#L750-2true main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 129#L750-3true [2022-12-13 18:54:00,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:54:00,581 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 1 times [2022-12-13 18:54:00,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:54:00,588 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368805234] [2022-12-13 18:54:00,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:00,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:54:00,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:54:00,651 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 18:54:00,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:54:00,675 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 18:54:00,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:54:00,677 INFO L85 PathProgramCache]: Analyzing trace with hash 46868248, now seen corresponding path program 1 times [2022-12-13 18:54:00,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:54:00,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623600984] [2022-12-13 18:54:00,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:00,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:54:00,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:54:00,705 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:54:00,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [623600984] [2022-12-13 18:54:00,706 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2022-12-13 18:54:00,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1772517768] [2022-12-13 18:54:00,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:00,706 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 18:54:00,706 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 18:54:00,707 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 18:54:00,709 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-12-13 18:54:00,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:54:00,786 INFO L263 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 1 conjunts are in the unsatisfiable core [2022-12-13 18:54:00,787 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-13 18:54:00,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:54:00,800 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-13 18:54:00,801 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1772517768] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:54:00,801 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:54:00,801 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 18:54:00,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1643377855] [2022-12-13 18:54:00,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:54:00,805 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:54:00,805 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:54:00,828 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 18:54:00,829 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 18:54:00,830 INFO L87 Difference]: Start difference. First operand has 160 states, 155 states have (on average 1.6516129032258065) internal successors, (256), 155 states have internal predecessors, (256), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 2.5) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:54:00,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:54:00,843 INFO L93 Difference]: Finished difference Result 160 states and 208 transitions. [2022-12-13 18:54:00,844 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 160 states and 208 transitions. [2022-12-13 18:54:00,847 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 146 [2022-12-13 18:54:00,851 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 160 states to 156 states and 204 transitions. [2022-12-13 18:54:00,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 156 [2022-12-13 18:54:00,853 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 156 [2022-12-13 18:54:00,853 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156 states and 204 transitions. [2022-12-13 18:54:00,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:54:00,855 INFO L218 hiAutomatonCegarLoop]: Abstraction has 156 states and 204 transitions. [2022-12-13 18:54:00,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states and 204 transitions. [2022-12-13 18:54:00,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 156. [2022-12-13 18:54:00,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 156 states, 152 states have (on average 1.3026315789473684) internal successors, (198), 151 states have internal predecessors, (198), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-13 18:54:00,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 204 transitions. [2022-12-13 18:54:00,880 INFO L240 hiAutomatonCegarLoop]: Abstraction has 156 states and 204 transitions. [2022-12-13 18:54:00,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 18:54:00,883 INFO L428 stractBuchiCegarLoop]: Abstraction has 156 states and 204 transitions. [2022-12-13 18:54:00,883 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 18:54:00,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156 states and 204 transitions. [2022-12-13 18:54:00,884 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 146 [2022-12-13 18:54:00,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:54:00,885 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:54:00,885 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 18:54:00,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:54:00,885 INFO L748 eck$LassoCheckResult]: Stem: 411#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~ite142#1.base, main_#t~ite142#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~short147#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1.base, main_#t~mem163#1.offset, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~post174#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1, main_#t~post185#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite144#1.base, main_#t~ite144#1.offset, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 425#L750-3 [2022-12-13 18:54:00,886 INFO L750 eck$LassoCheckResult]: Loop: 425#L750-3 assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 466#L752 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 467#L752-2 call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 404#L757-121 havoc main_~_ha_hashv~0#1; 405#L757-49 goto; 453#L757-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 344#L757-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 345#L757-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch19#1 := 11 == main_~_hj_k~0#1; 413#L757-10 assume main_#t~switch19#1;call main_#t~mem20#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem20#1 % 256);havoc main_#t~mem20#1; 493#L757-12 main_#t~switch19#1 := main_#t~switch19#1 || 10 == main_~_hj_k~0#1; 393#L757-13 assume main_#t~switch19#1;call main_#t~mem21#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem21#1 % 256);havoc main_#t~mem21#1; 342#L757-15 main_#t~switch19#1 := main_#t~switch19#1 || 9 == main_~_hj_k~0#1; 343#L757-16 assume main_#t~switch19#1;call main_#t~mem22#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem22#1 % 256);havoc main_#t~mem22#1; 486#L757-18 main_#t~switch19#1 := main_#t~switch19#1 || 8 == main_~_hj_k~0#1; 470#L757-19 assume main_#t~switch19#1;call main_#t~mem23#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem23#1 % 256);havoc main_#t~mem23#1; 381#L757-21 main_#t~switch19#1 := main_#t~switch19#1 || 7 == main_~_hj_k~0#1; 382#L757-22 assume !main_#t~switch19#1; 451#L757-24 main_#t~switch19#1 := main_#t~switch19#1 || 6 == main_~_hj_k~0#1; 417#L757-25 assume main_#t~switch19#1;call main_#t~mem25#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem25#1 % 256);havoc main_#t~mem25#1; 418#L757-27 main_#t~switch19#1 := main_#t~switch19#1 || 5 == main_~_hj_k~0#1; 492#L757-28 assume main_#t~switch19#1;call main_#t~mem26#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem26#1 % 256;havoc main_#t~mem26#1; 490#L757-30 main_#t~switch19#1 := main_#t~switch19#1 || 4 == main_~_hj_k~0#1; 489#L757-31 assume main_#t~switch19#1;call main_#t~mem27#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem27#1 % 256);havoc main_#t~mem27#1; 357#L757-33 main_#t~switch19#1 := main_#t~switch19#1 || 3 == main_~_hj_k~0#1; 358#L757-34 assume main_#t~switch19#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 449#L757-36 main_#t~switch19#1 := main_#t~switch19#1 || 2 == main_~_hj_k~0#1; 428#L757-37 assume main_#t~switch19#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem29#1 % 256);havoc main_#t~mem29#1; 429#L757-39 main_#t~switch19#1 := main_#t~switch19#1 || 1 == main_~_hj_k~0#1; 385#L757-40 assume main_#t~switch19#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem30#1 % 256;havoc main_#t~mem30#1; 366#L757-42 havoc main_#t~switch19#1; 367#L757-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 423#L757-44 goto; 475#L757-46 goto; 476#L757-48 goto; 447#L757-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 448#L757-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem48#1.base, main_#t~mem48#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem48#1.base, main_#t~mem48#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem48#1.base, main_#t~mem48#1.offset; 482#L757-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem49#1.base, main_#t~mem49#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem50#1.base, main_#t~mem50#1.offset := read~$Pointer$(main_#t~mem49#1.base, 16 + main_#t~mem49#1.offset, 4);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem52#1 := read~int(main_#t~mem51#1.base, 20 + main_#t~mem51#1.offset, 4);call write~$Pointer$(main_#t~mem50#1.base, main_#t~mem50#1.offset - main_#t~mem52#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem49#1.base, main_#t~mem49#1.offset;havoc main_#t~mem50#1.base, main_#t~mem50#1.offset;havoc main_#t~mem51#1.base, main_#t~mem51#1.offset;havoc main_#t~mem52#1;call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_#t~mem53#1.base, 16 + main_#t~mem53#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem54#1.base, 8 + main_#t~mem54#1.offset, 4);havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;call main_#t~mem55#1.base, main_#t~mem55#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem55#1.base, 16 + main_#t~mem55#1.offset, 4);havoc main_#t~mem55#1.base, main_#t~mem55#1.offset; 483#L757-66 goto; 386#L757-117 havoc main_~_ha_bkt~0#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1 := read~int(main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);main_#t~post58#1 := main_#t~mem57#1;call write~int(1 + main_#t~post58#1, main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1;havoc main_#t~post58#1; 390#L757-71 call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 4 + main_#t~mem59#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem60#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem60#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem60#1 - 1)));havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1; 452#L757-70 goto; 463#L757-115 call main_#t~mem61#1.base, main_#t~mem61#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_#t~mem61#1.base, main_#t~mem61#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem62#1.base, main_#t~mem62#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem61#1.base, main_#t~mem61#1.offset;havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;call main_#t~mem63#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post64#1 := main_#t~mem63#1;call write~int(1 + main_#t~post64#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem63#1;havoc main_#t~post64#1;call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 495#L757-73 assume main_#t~mem66#1.base != 0 || main_#t~mem66#1.offset != 0;havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem67#1.base, 12 + main_#t~mem67#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset; 406#L757-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem69#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem68#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short72#1 := main_#t~mem69#1 % 4294967296 >= 10 * (1 + main_#t~mem68#1) % 4294967296; 407#L757-76 assume main_#t~short72#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_#t~mem70#1.base, 36 + main_#t~mem70#1.offset, 4);main_#t~short72#1 := 0 == main_#t~mem71#1 % 4294967296; 485#L757-78 assume !main_#t~short72#1;havoc main_#t~mem69#1;havoc main_#t~mem68#1;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;havoc main_#t~short72#1; 430#L757-114 goto; 431#L757-116 goto; 468#L757-118 goto; 469#L757-120 goto; 439#L750-2 main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 425#L750-3 [2022-12-13 18:54:00,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:54:00,887 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 2 times [2022-12-13 18:54:00,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:54:00,887 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085777047] [2022-12-13 18:54:00,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:00,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:54:00,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:54:00,893 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 18:54:00,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:54:00,901 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 18:54:00,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:54:00,902 INFO L85 PathProgramCache]: Analyzing trace with hash -51894535, now seen corresponding path program 1 times [2022-12-13 18:54:00,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:54:00,902 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183973039] [2022-12-13 18:54:00,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:00,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:54:01,026 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-13 18:54:01,027 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [587303531] [2022-12-13 18:54:01,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:01,027 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 18:54:01,027 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 18:54:01,055 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 18:54:01,056 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-12-13 18:54:01,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:54:01,560 INFO L263 TraceCheckSpWp]: Trace formula consists of 1823 conjuncts, 3 conjunts are in the unsatisfiable core [2022-12-13 18:54:01,562 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-13 18:54:01,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:54:01,588 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-13 18:54:01,588 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:54:01,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1183973039] [2022-12-13 18:54:01,589 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-13 18:54:01,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [587303531] [2022-12-13 18:54:01,589 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [587303531] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:54:01,589 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:54:01,589 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:54:01,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575178983] [2022-12-13 18:54:01,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:54:01,590 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:54:01,590 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:54:01,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:54:01,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:54:01,591 INFO L87 Difference]: Start difference. First operand 156 states and 204 transitions. cyclomatic complexity: 52 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:54:01,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:54:01,661 INFO L93 Difference]: Finished difference Result 177 states and 225 transitions. [2022-12-13 18:54:01,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 177 states and 225 transitions. [2022-12-13 18:54:01,663 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 167 [2022-12-13 18:54:01,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 177 states to 177 states and 225 transitions. [2022-12-13 18:54:01,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 177 [2022-12-13 18:54:01,664 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 177 [2022-12-13 18:54:01,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 177 states and 225 transitions. [2022-12-13 18:54:01,665 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:54:01,666 INFO L218 hiAutomatonCegarLoop]: Abstraction has 177 states and 225 transitions. [2022-12-13 18:54:01,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states and 225 transitions. [2022-12-13 18:54:01,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 176. [2022-12-13 18:54:01,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 176 states, 172 states have (on average 1.2674418604651163) internal successors, (218), 171 states have internal predecessors, (218), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-13 18:54:01,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 224 transitions. [2022-12-13 18:54:01,675 INFO L240 hiAutomatonCegarLoop]: Abstraction has 176 states and 224 transitions. [2022-12-13 18:54:01,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:54:01,676 INFO L428 stractBuchiCegarLoop]: Abstraction has 176 states and 224 transitions. [2022-12-13 18:54:01,676 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 18:54:01,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 176 states and 224 transitions. [2022-12-13 18:54:01,678 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 166 [2022-12-13 18:54:01,678 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:54:01,678 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:54:01,679 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 18:54:01,679 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:54:01,679 INFO L748 eck$LassoCheckResult]: Stem: 901#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 902#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~ite142#1.base, main_#t~ite142#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~short147#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1.base, main_#t~mem163#1.offset, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~post174#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1, main_#t~post185#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite144#1.base, main_#t~ite144#1.offset, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 915#L750-3 [2022-12-13 18:54:01,680 INFO L750 eck$LassoCheckResult]: Loop: 915#L750-3 assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 958#L752 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 959#L752-2 call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 892#L757-121 havoc main_~_ha_hashv~0#1; 893#L757-49 goto; 945#L757-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 833#L757-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 834#L757-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch19#1 := 11 == main_~_hj_k~0#1; 903#L757-10 assume main_#t~switch19#1;call main_#t~mem20#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem20#1 % 256);havoc main_#t~mem20#1; 988#L757-12 main_#t~switch19#1 := main_#t~switch19#1 || 10 == main_~_hj_k~0#1; 882#L757-13 assume main_#t~switch19#1;call main_#t~mem21#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem21#1 % 256);havoc main_#t~mem21#1; 883#L757-15 main_#t~switch19#1 := main_#t~switch19#1 || 9 == main_~_hj_k~0#1; 979#L757-16 assume main_#t~switch19#1;call main_#t~mem22#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem22#1 % 256);havoc main_#t~mem22#1; 980#L757-18 main_#t~switch19#1 := main_#t~switch19#1 || 8 == main_~_hj_k~0#1; 962#L757-19 assume main_#t~switch19#1;call main_#t~mem23#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem23#1 % 256);havoc main_#t~mem23#1; 963#L757-21 main_#t~switch19#1 := main_#t~switch19#1 || 7 == main_~_hj_k~0#1; 944#L757-22 assume main_#t~switch19#1;call main_#t~mem24#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem24#1 % 256);havoc main_#t~mem24#1; 943#L757-24 main_#t~switch19#1 := main_#t~switch19#1 || 6 == main_~_hj_k~0#1; 907#L757-25 assume main_#t~switch19#1;call main_#t~mem25#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem25#1 % 256);havoc main_#t~mem25#1; 908#L757-27 main_#t~switch19#1 := main_#t~switch19#1 || 5 == main_~_hj_k~0#1; 987#L757-28 assume main_#t~switch19#1;call main_#t~mem26#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem26#1 % 256;havoc main_#t~mem26#1; 985#L757-30 main_#t~switch19#1 := main_#t~switch19#1 || 4 == main_~_hj_k~0#1; 983#L757-31 assume main_#t~switch19#1;call main_#t~mem27#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem27#1 % 256);havoc main_#t~mem27#1; 984#L757-33 main_#t~switch19#1 := main_#t~switch19#1 || 3 == main_~_hj_k~0#1; 939#L757-34 assume main_#t~switch19#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 940#L757-36 main_#t~switch19#1 := main_#t~switch19#1 || 2 == main_~_hj_k~0#1; 918#L757-37 assume main_#t~switch19#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem29#1 % 256);havoc main_#t~mem29#1; 919#L757-39 main_#t~switch19#1 := main_#t~switch19#1 || 1 == main_~_hj_k~0#1; 872#L757-40 assume main_#t~switch19#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem30#1 % 256;havoc main_#t~mem30#1; 855#L757-42 havoc main_#t~switch19#1; 856#L757-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 913#L757-44 goto; 968#L757-46 goto; 969#L757-48 goto; 937#L757-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 938#L757-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem48#1.base, main_#t~mem48#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem48#1.base, main_#t~mem48#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem48#1.base, main_#t~mem48#1.offset; 975#L757-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem49#1.base, main_#t~mem49#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem50#1.base, main_#t~mem50#1.offset := read~$Pointer$(main_#t~mem49#1.base, 16 + main_#t~mem49#1.offset, 4);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem52#1 := read~int(main_#t~mem51#1.base, 20 + main_#t~mem51#1.offset, 4);call write~$Pointer$(main_#t~mem50#1.base, main_#t~mem50#1.offset - main_#t~mem52#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem49#1.base, main_#t~mem49#1.offset;havoc main_#t~mem50#1.base, main_#t~mem50#1.offset;havoc main_#t~mem51#1.base, main_#t~mem51#1.offset;havoc main_#t~mem52#1;call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_#t~mem53#1.base, 16 + main_#t~mem53#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem54#1.base, 8 + main_#t~mem54#1.offset, 4);havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;call main_#t~mem55#1.base, main_#t~mem55#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem55#1.base, 16 + main_#t~mem55#1.offset, 4);havoc main_#t~mem55#1.base, main_#t~mem55#1.offset; 976#L757-66 goto; 875#L757-117 havoc main_~_ha_bkt~0#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1 := read~int(main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);main_#t~post58#1 := main_#t~mem57#1;call write~int(1 + main_#t~post58#1, main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1;havoc main_#t~post58#1; 879#L757-71 call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 4 + main_#t~mem59#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem60#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem60#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem60#1 - 1)));havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1; 942#L757-70 goto; 955#L757-115 call main_#t~mem61#1.base, main_#t~mem61#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_#t~mem61#1.base, main_#t~mem61#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem62#1.base, main_#t~mem62#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem61#1.base, main_#t~mem61#1.offset;havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;call main_#t~mem63#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post64#1 := main_#t~mem63#1;call write~int(1 + main_#t~post64#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem63#1;havoc main_#t~post64#1;call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 991#L757-73 assume main_#t~mem66#1.base != 0 || main_#t~mem66#1.offset != 0;havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem67#1.base, 12 + main_#t~mem67#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset; 896#L757-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem69#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem68#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short72#1 := main_#t~mem69#1 % 4294967296 >= 10 * (1 + main_#t~mem68#1) % 4294967296; 897#L757-76 assume main_#t~short72#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_#t~mem70#1.base, 36 + main_#t~mem70#1.offset, 4);main_#t~short72#1 := 0 == main_#t~mem71#1 % 4294967296; 978#L757-78 assume !main_#t~short72#1;havoc main_#t~mem69#1;havoc main_#t~mem68#1;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;havoc main_#t~short72#1; 920#L757-114 goto; 921#L757-116 goto; 960#L757-118 goto; 961#L757-120 goto; 929#L750-2 main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 915#L750-3 [2022-12-13 18:54:01,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:54:01,680 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 3 times [2022-12-13 18:54:01,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:54:01,681 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872007390] [2022-12-13 18:54:01,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:01,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:54:01,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:54:01,692 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 18:54:01,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:54:01,706 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 18:54:01,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:54:01,707 INFO L85 PathProgramCache]: Analyzing trace with hash 792110967, now seen corresponding path program 1 times [2022-12-13 18:54:01,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:54:01,708 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962811559] [2022-12-13 18:54:01,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:01,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:54:01,799 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-13 18:54:01,799 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2033191840] [2022-12-13 18:54:01,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:01,799 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 18:54:01,800 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 18:54:01,801 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 18:54:01,802 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-12-13 18:54:02,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:54:02,321 INFO L263 TraceCheckSpWp]: Trace formula consists of 1829 conjuncts, 3 conjunts are in the unsatisfiable core [2022-12-13 18:54:02,323 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-13 18:54:02,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:54:02,347 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-13 18:54:02,348 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:54:02,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [962811559] [2022-12-13 18:54:02,348 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-13 18:54:02,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2033191840] [2022-12-13 18:54:02,348 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2033191840] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:54:02,349 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:54:02,349 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-13 18:54:02,349 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1991570317] [2022-12-13 18:54:02,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:54:02,350 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:54:02,350 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:54:02,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 18:54:02,350 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 18:54:02,351 INFO L87 Difference]: Start difference. First operand 176 states and 224 transitions. cyclomatic complexity: 52 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 4 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:54:02,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:54:02,427 INFO L93 Difference]: Finished difference Result 233 states and 296 transitions. [2022-12-13 18:54:02,427 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 233 states and 296 transitions. [2022-12-13 18:54:02,430 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 213 [2022-12-13 18:54:02,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 233 states to 233 states and 296 transitions. [2022-12-13 18:54:02,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 233 [2022-12-13 18:54:02,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 233 [2022-12-13 18:54:02,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 233 states and 296 transitions. [2022-12-13 18:54:02,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:54:02,433 INFO L218 hiAutomatonCegarLoop]: Abstraction has 233 states and 296 transitions. [2022-12-13 18:54:02,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states and 296 transitions. [2022-12-13 18:54:02,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 162. [2022-12-13 18:54:02,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 162 states, 158 states have (on average 1.2468354430379747) internal successors, (197), 157 states have internal predecessors, (197), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-13 18:54:02,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 203 transitions. [2022-12-13 18:54:02,442 INFO L240 hiAutomatonCegarLoop]: Abstraction has 162 states and 203 transitions. [2022-12-13 18:54:02,443 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 18:54:02,443 INFO L428 stractBuchiCegarLoop]: Abstraction has 162 states and 203 transitions. [2022-12-13 18:54:02,444 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 18:54:02,444 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 162 states and 203 transitions. [2022-12-13 18:54:02,445 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 152 [2022-12-13 18:54:02,445 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:54:02,446 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:54:02,446 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 18:54:02,446 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:54:02,447 INFO L748 eck$LassoCheckResult]: Stem: 1468#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 1469#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~ite142#1.base, main_#t~ite142#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~short147#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1.base, main_#t~mem163#1.offset, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~post174#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1, main_#t~post185#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite144#1.base, main_#t~ite144#1.offset, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 1482#L750-3 [2022-12-13 18:54:02,447 INFO L750 eck$LassoCheckResult]: Loop: 1482#L750-3 assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 1524#L752 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1525#L752-2 call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 1455#L757-121 havoc main_~_ha_hashv~0#1; 1456#L757-49 goto; 1511#L757-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 1401#L757-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 1402#L757-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch19#1 := 11 == main_~_hj_k~0#1; 1470#L757-10 assume !main_#t~switch19#1; 1552#L757-12 main_#t~switch19#1 := main_#t~switch19#1 || 10 == main_~_hj_k~0#1; 1450#L757-13 assume !main_#t~switch19#1; 1399#L757-15 main_#t~switch19#1 := main_#t~switch19#1 || 9 == main_~_hj_k~0#1; 1400#L757-16 assume !main_#t~switch19#1; 1543#L757-18 main_#t~switch19#1 := main_#t~switch19#1 || 8 == main_~_hj_k~0#1; 1528#L757-19 assume !main_#t~switch19#1; 1438#L757-21 main_#t~switch19#1 := main_#t~switch19#1 || 7 == main_~_hj_k~0#1; 1439#L757-22 assume !main_#t~switch19#1; 1509#L757-24 main_#t~switch19#1 := main_#t~switch19#1 || 6 == main_~_hj_k~0#1; 1474#L757-25 assume !main_#t~switch19#1; 1475#L757-27 main_#t~switch19#1 := main_#t~switch19#1 || 5 == main_~_hj_k~0#1; 1551#L757-28 assume !main_#t~switch19#1; 1549#L757-30 main_#t~switch19#1 := main_#t~switch19#1 || 4 == main_~_hj_k~0#1; 1547#L757-31 assume !main_#t~switch19#1; 1414#L757-33 main_#t~switch19#1 := main_#t~switch19#1 || 3 == main_~_hj_k~0#1; 1415#L757-34 assume main_#t~switch19#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 1507#L757-36 main_#t~switch19#1 := main_#t~switch19#1 || 2 == main_~_hj_k~0#1; 1485#L757-37 assume main_#t~switch19#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem29#1 % 256);havoc main_#t~mem29#1; 1486#L757-39 main_#t~switch19#1 := main_#t~switch19#1 || 1 == main_~_hj_k~0#1; 1442#L757-40 assume main_#t~switch19#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem30#1 % 256;havoc main_#t~mem30#1; 1423#L757-42 havoc main_#t~switch19#1; 1424#L757-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1480#L757-44 goto; 1535#L757-46 goto; 1536#L757-48 goto; 1504#L757-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1505#L757-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem48#1.base, main_#t~mem48#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem48#1.base, main_#t~mem48#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem48#1.base, main_#t~mem48#1.offset; 1540#L757-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem49#1.base, main_#t~mem49#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem50#1.base, main_#t~mem50#1.offset := read~$Pointer$(main_#t~mem49#1.base, 16 + main_#t~mem49#1.offset, 4);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem52#1 := read~int(main_#t~mem51#1.base, 20 + main_#t~mem51#1.offset, 4);call write~$Pointer$(main_#t~mem50#1.base, main_#t~mem50#1.offset - main_#t~mem52#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem49#1.base, main_#t~mem49#1.offset;havoc main_#t~mem50#1.base, main_#t~mem50#1.offset;havoc main_#t~mem51#1.base, main_#t~mem51#1.offset;havoc main_#t~mem52#1;call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_#t~mem53#1.base, 16 + main_#t~mem53#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem54#1.base, 8 + main_#t~mem54#1.offset, 4);havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;call main_#t~mem55#1.base, main_#t~mem55#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem55#1.base, 16 + main_#t~mem55#1.offset, 4);havoc main_#t~mem55#1.base, main_#t~mem55#1.offset; 1541#L757-66 goto; 1445#L757-117 havoc main_~_ha_bkt~0#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1 := read~int(main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);main_#t~post58#1 := main_#t~mem57#1;call write~int(1 + main_#t~post58#1, main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1;havoc main_#t~post58#1; 1448#L757-71 call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 4 + main_#t~mem59#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem60#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem60#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem60#1 - 1)));havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1; 1510#L757-70 goto; 1523#L757-115 call main_#t~mem61#1.base, main_#t~mem61#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_#t~mem61#1.base, main_#t~mem61#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem62#1.base, main_#t~mem62#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem61#1.base, main_#t~mem61#1.offset;havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;call main_#t~mem63#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post64#1 := main_#t~mem63#1;call write~int(1 + main_#t~post64#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem63#1;havoc main_#t~post64#1;call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 1558#L757-73 assume main_#t~mem66#1.base != 0 || main_#t~mem66#1.offset != 0;havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem67#1.base, 12 + main_#t~mem67#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset; 1465#L757-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem69#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem68#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short72#1 := main_#t~mem69#1 % 4294967296 >= 10 * (1 + main_#t~mem68#1) % 4294967296; 1466#L757-76 assume main_#t~short72#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_#t~mem70#1.base, 36 + main_#t~mem70#1.offset, 4);main_#t~short72#1 := 0 == main_#t~mem71#1 % 4294967296; 1544#L757-78 assume !main_#t~short72#1;havoc main_#t~mem69#1;havoc main_#t~mem68#1;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;havoc main_#t~short72#1; 1489#L757-114 goto; 1490#L757-116 goto; 1526#L757-118 goto; 1527#L757-120 goto; 1498#L750-2 main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1482#L750-3 [2022-12-13 18:54:02,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:54:02,448 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 4 times [2022-12-13 18:54:02,448 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:54:02,448 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [200393213] [2022-12-13 18:54:02,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:02,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:54:02,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:54:02,462 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 18:54:02,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:54:02,477 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 18:54:02,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:54:02,478 INFO L85 PathProgramCache]: Analyzing trace with hash 303939975, now seen corresponding path program 1 times [2022-12-13 18:54:02,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:54:02,478 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1268671763] [2022-12-13 18:54:02,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:02,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:54:02,564 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-13 18:54:02,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [909274109] [2022-12-13 18:54:02,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:02,564 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 18:54:02,564 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 18:54:02,566 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 18:54:02,566 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-12-13 18:54:03,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:54:03,118 INFO L263 TraceCheckSpWp]: Trace formula consists of 1781 conjuncts, 4 conjunts are in the unsatisfiable core [2022-12-13 18:54:03,120 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-13 18:54:03,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:54:03,157 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-13 18:54:03,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:54:03,157 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1268671763] [2022-12-13 18:54:03,157 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-13 18:54:03,158 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [909274109] [2022-12-13 18:54:03,158 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [909274109] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:54:03,158 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:54:03,158 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 18:54:03,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [763610644] [2022-12-13 18:54:03,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:54:03,159 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:54:03,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:54:03,159 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 18:54:03,159 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-12-13 18:54:03,159 INFO L87 Difference]: Start difference. First operand 162 states and 203 transitions. cyclomatic complexity: 45 Second operand has 5 states, 5 states have (on average 10.2) internal successors, (51), 5 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:54:03,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:54:03,242 INFO L93 Difference]: Finished difference Result 319 states and 398 transitions. [2022-12-13 18:54:03,243 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 319 states and 398 transitions. [2022-12-13 18:54:03,244 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 305 [2022-12-13 18:54:03,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 319 states to 319 states and 398 transitions. [2022-12-13 18:54:03,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 319 [2022-12-13 18:54:03,246 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 319 [2022-12-13 18:54:03,246 INFO L73 IsDeterministic]: Start isDeterministic. Operand 319 states and 398 transitions. [2022-12-13 18:54:03,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:54:03,247 INFO L218 hiAutomatonCegarLoop]: Abstraction has 319 states and 398 transitions. [2022-12-13 18:54:03,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states and 398 transitions. [2022-12-13 18:54:03,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 185. [2022-12-13 18:54:03,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 185 states, 181 states have (on average 1.2265193370165746) internal successors, (222), 180 states have internal predecessors, (222), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-13 18:54:03,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 228 transitions. [2022-12-13 18:54:03,253 INFO L240 hiAutomatonCegarLoop]: Abstraction has 185 states and 228 transitions. [2022-12-13 18:54:03,253 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-12-13 18:54:03,254 INFO L428 stractBuchiCegarLoop]: Abstraction has 185 states and 228 transitions. [2022-12-13 18:54:03,254 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 18:54:03,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 185 states and 228 transitions. [2022-12-13 18:54:03,255 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 175 [2022-12-13 18:54:03,255 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:54:03,255 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:54:03,255 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 18:54:03,255 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:54:03,256 INFO L748 eck$LassoCheckResult]: Stem: 2107#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 2108#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~ite142#1.base, main_#t~ite142#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~short147#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1.base, main_#t~mem163#1.offset, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~post174#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1, main_#t~post185#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite144#1.base, main_#t~ite144#1.offset, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 2121#L750-3 [2022-12-13 18:54:03,256 INFO L750 eck$LassoCheckResult]: Loop: 2121#L750-3 assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 2162#L752 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 2163#L752-2 call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 2094#L757-121 havoc main_~_ha_hashv~0#1; 2095#L757-49 goto; 2149#L757-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 2040#L757-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 2041#L757-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch19#1 := 11 == main_~_hj_k~0#1; 2109#L757-10 assume !main_#t~switch19#1; 2190#L757-12 main_#t~switch19#1 := main_#t~switch19#1 || 10 == main_~_hj_k~0#1; 2089#L757-13 assume !main_#t~switch19#1; 2038#L757-15 main_#t~switch19#1 := main_#t~switch19#1 || 9 == main_~_hj_k~0#1; 2039#L757-16 assume !main_#t~switch19#1; 2181#L757-18 main_#t~switch19#1 := main_#t~switch19#1 || 8 == main_~_hj_k~0#1; 2166#L757-19 assume !main_#t~switch19#1; 2077#L757-21 main_#t~switch19#1 := main_#t~switch19#1 || 7 == main_~_hj_k~0#1; 2078#L757-22 assume !main_#t~switch19#1; 2147#L757-24 main_#t~switch19#1 := main_#t~switch19#1 || 6 == main_~_hj_k~0#1; 2113#L757-25 assume !main_#t~switch19#1; 2114#L757-27 main_#t~switch19#1 := main_#t~switch19#1 || 5 == main_~_hj_k~0#1; 2189#L757-28 assume !main_#t~switch19#1; 2187#L757-30 main_#t~switch19#1 := main_#t~switch19#1 || 4 == main_~_hj_k~0#1; 2185#L757-31 assume !main_#t~switch19#1; 2053#L757-33 main_#t~switch19#1 := main_#t~switch19#1 || 3 == main_~_hj_k~0#1; 2054#L757-34 assume !main_#t~switch19#1; 2145#L757-36 main_#t~switch19#1 := main_#t~switch19#1 || 2 == main_~_hj_k~0#1; 2219#L757-37 assume !main_#t~switch19#1; 2217#L757-39 main_#t~switch19#1 := main_#t~switch19#1 || 1 == main_~_hj_k~0#1; 2081#L757-40 assume !main_#t~switch19#1; 2062#L757-42 havoc main_#t~switch19#1; 2063#L757-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 2119#L757-44 goto; 2173#L757-46 goto; 2174#L757-48 goto; 2143#L757-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 2144#L757-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem48#1.base, main_#t~mem48#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem48#1.base, main_#t~mem48#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem48#1.base, main_#t~mem48#1.offset; 2178#L757-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem49#1.base, main_#t~mem49#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem50#1.base, main_#t~mem50#1.offset := read~$Pointer$(main_#t~mem49#1.base, 16 + main_#t~mem49#1.offset, 4);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem52#1 := read~int(main_#t~mem51#1.base, 20 + main_#t~mem51#1.offset, 4);call write~$Pointer$(main_#t~mem50#1.base, main_#t~mem50#1.offset - main_#t~mem52#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem49#1.base, main_#t~mem49#1.offset;havoc main_#t~mem50#1.base, main_#t~mem50#1.offset;havoc main_#t~mem51#1.base, main_#t~mem51#1.offset;havoc main_#t~mem52#1;call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_#t~mem53#1.base, 16 + main_#t~mem53#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem54#1.base, 8 + main_#t~mem54#1.offset, 4);havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;call main_#t~mem55#1.base, main_#t~mem55#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem55#1.base, 16 + main_#t~mem55#1.offset, 4);havoc main_#t~mem55#1.base, main_#t~mem55#1.offset; 2179#L757-66 goto; 2084#L757-117 havoc main_~_ha_bkt~0#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1 := read~int(main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);main_#t~post58#1 := main_#t~mem57#1;call write~int(1 + main_#t~post58#1, main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1;havoc main_#t~post58#1; 2087#L757-71 call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 4 + main_#t~mem59#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem60#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem60#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem60#1 - 1)));havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1; 2148#L757-70 goto; 2161#L757-115 call main_#t~mem61#1.base, main_#t~mem61#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_#t~mem61#1.base, main_#t~mem61#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem62#1.base, main_#t~mem62#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem61#1.base, main_#t~mem61#1.offset;havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;call main_#t~mem63#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post64#1 := main_#t~mem63#1;call write~int(1 + main_#t~post64#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem63#1;havoc main_#t~post64#1;call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 2194#L757-73 assume main_#t~mem66#1.base != 0 || main_#t~mem66#1.offset != 0;havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem67#1.base, 12 + main_#t~mem67#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset; 2104#L757-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem69#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem68#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short72#1 := main_#t~mem69#1 % 4294967296 >= 10 * (1 + main_#t~mem68#1) % 4294967296; 2105#L757-76 assume main_#t~short72#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_#t~mem70#1.base, 36 + main_#t~mem70#1.offset, 4);main_#t~short72#1 := 0 == main_#t~mem71#1 % 4294967296; 2182#L757-78 assume !main_#t~short72#1;havoc main_#t~mem69#1;havoc main_#t~mem68#1;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;havoc main_#t~short72#1; 2128#L757-114 goto; 2129#L757-116 goto; 2164#L757-118 goto; 2165#L757-120 goto; 2137#L750-2 main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2121#L750-3 [2022-12-13 18:54:03,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:54:03,256 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 5 times [2022-12-13 18:54:03,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:54:03,257 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290057304] [2022-12-13 18:54:03,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:03,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:54:03,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:54:03,264 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 18:54:03,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:54:03,273 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 18:54:03,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:54:03,273 INFO L85 PathProgramCache]: Analyzing trace with hash 562278285, now seen corresponding path program 1 times [2022-12-13 18:54:03,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:54:03,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [644893031] [2022-12-13 18:54:03,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:03,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:54:03,359 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-13 18:54:03,359 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1000438142] [2022-12-13 18:54:03,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:03,359 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 18:54:03,359 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 18:54:03,360 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 18:54:03,361 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-12-13 18:54:03,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:54:03,946 INFO L263 TraceCheckSpWp]: Trace formula consists of 1763 conjuncts, 4 conjunts are in the unsatisfiable core [2022-12-13 18:54:03,949 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-13 18:54:03,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:54:03,976 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-13 18:54:03,976 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:54:03,976 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [644893031] [2022-12-13 18:54:03,976 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-13 18:54:03,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1000438142] [2022-12-13 18:54:03,977 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1000438142] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:54:03,977 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:54:03,977 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-13 18:54:03,977 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805171102] [2022-12-13 18:54:03,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:54:03,978 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:54:03,978 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:54:03,978 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 18:54:03,978 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 18:54:03,978 INFO L87 Difference]: Start difference. First operand 185 states and 228 transitions. cyclomatic complexity: 47 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 4 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:54:04,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:54:04,016 INFO L93 Difference]: Finished difference Result 223 states and 281 transitions. [2022-12-13 18:54:04,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 223 states and 281 transitions. [2022-12-13 18:54:04,019 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 203 [2022-12-13 18:54:04,020 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 223 states to 223 states and 281 transitions. [2022-12-13 18:54:04,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 223 [2022-12-13 18:54:04,020 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 223 [2022-12-13 18:54:04,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223 states and 281 transitions. [2022-12-13 18:54:04,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:54:04,021 INFO L218 hiAutomatonCegarLoop]: Abstraction has 223 states and 281 transitions. [2022-12-13 18:54:04,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states and 281 transitions. [2022-12-13 18:54:04,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 153. [2022-12-13 18:54:04,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 153 states, 149 states have (on average 1.2281879194630871) internal successors, (183), 148 states have internal predecessors, (183), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-13 18:54:04,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 189 transitions. [2022-12-13 18:54:04,025 INFO L240 hiAutomatonCegarLoop]: Abstraction has 153 states and 189 transitions. [2022-12-13 18:54:04,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 18:54:04,026 INFO L428 stractBuchiCegarLoop]: Abstraction has 153 states and 189 transitions. [2022-12-13 18:54:04,026 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 18:54:04,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 153 states and 189 transitions. [2022-12-13 18:54:04,026 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 143 [2022-12-13 18:54:04,026 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:54:04,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:54:04,027 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-12-13 18:54:04,027 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:54:04,027 INFO L748 eck$LassoCheckResult]: Stem: 2671#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 2672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~ite142#1.base, main_#t~ite142#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~short147#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1.base, main_#t~mem163#1.offset, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~post174#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1, main_#t~post185#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite144#1.base, main_#t~ite144#1.offset, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 2685#L750-3 [2022-12-13 18:54:04,027 INFO L750 eck$LassoCheckResult]: Loop: 2685#L750-3 assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 2726#L752 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 2727#L752-2 call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 2662#L757-121 havoc main_~_ha_hashv~0#1; 2663#L757-49 goto; 2713#L757-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 2605#L757-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 2606#L757-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch19#1 := 11 == main_~_hj_k~0#1; 2673#L757-10 assume !main_#t~switch19#1; 2753#L757-12 main_#t~switch19#1 := main_#t~switch19#1 || 10 == main_~_hj_k~0#1; 2653#L757-13 assume !main_#t~switch19#1; 2603#L757-15 main_#t~switch19#1 := main_#t~switch19#1 || 9 == main_~_hj_k~0#1; 2604#L757-16 assume !main_#t~switch19#1; 2745#L757-18 main_#t~switch19#1 := main_#t~switch19#1 || 8 == main_~_hj_k~0#1; 2730#L757-19 assume !main_#t~switch19#1; 2641#L757-21 main_#t~switch19#1 := main_#t~switch19#1 || 7 == main_~_hj_k~0#1; 2642#L757-22 assume !main_#t~switch19#1; 2711#L757-24 main_#t~switch19#1 := main_#t~switch19#1 || 6 == main_~_hj_k~0#1; 2677#L757-25 assume !main_#t~switch19#1; 2678#L757-27 main_#t~switch19#1 := main_#t~switch19#1 || 5 == main_~_hj_k~0#1; 2752#L757-28 assume !main_#t~switch19#1; 2750#L757-30 main_#t~switch19#1 := main_#t~switch19#1 || 4 == main_~_hj_k~0#1; 2749#L757-31 assume main_#t~switch19#1;call main_#t~mem27#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem27#1 % 256);havoc main_#t~mem27#1; 2617#L757-33 main_#t~switch19#1 := main_#t~switch19#1 || 3 == main_~_hj_k~0#1; 2618#L757-34 assume main_#t~switch19#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 2709#L757-36 main_#t~switch19#1 := main_#t~switch19#1 || 2 == main_~_hj_k~0#1; 2688#L757-37 assume main_#t~switch19#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem29#1 % 256);havoc main_#t~mem29#1; 2689#L757-39 main_#t~switch19#1 := main_#t~switch19#1 || 1 == main_~_hj_k~0#1; 2645#L757-40 assume main_#t~switch19#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem30#1 % 256;havoc main_#t~mem30#1; 2626#L757-42 havoc main_#t~switch19#1; 2627#L757-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 2684#L757-44 goto; 2737#L757-46 goto; 2738#L757-48 goto; 2707#L757-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 2708#L757-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem48#1.base, main_#t~mem48#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem48#1.base, main_#t~mem48#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem48#1.base, main_#t~mem48#1.offset; 2742#L757-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem49#1.base, main_#t~mem49#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem50#1.base, main_#t~mem50#1.offset := read~$Pointer$(main_#t~mem49#1.base, 16 + main_#t~mem49#1.offset, 4);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem52#1 := read~int(main_#t~mem51#1.base, 20 + main_#t~mem51#1.offset, 4);call write~$Pointer$(main_#t~mem50#1.base, main_#t~mem50#1.offset - main_#t~mem52#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem49#1.base, main_#t~mem49#1.offset;havoc main_#t~mem50#1.base, main_#t~mem50#1.offset;havoc main_#t~mem51#1.base, main_#t~mem51#1.offset;havoc main_#t~mem52#1;call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_#t~mem53#1.base, 16 + main_#t~mem53#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem54#1.base, 8 + main_#t~mem54#1.offset, 4);havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;call main_#t~mem55#1.base, main_#t~mem55#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem55#1.base, 16 + main_#t~mem55#1.offset, 4);havoc main_#t~mem55#1.base, main_#t~mem55#1.offset; 2743#L757-66 goto; 2648#L757-117 havoc main_~_ha_bkt~0#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1 := read~int(main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);main_#t~post58#1 := main_#t~mem57#1;call write~int(1 + main_#t~post58#1, main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1;havoc main_#t~post58#1; 2651#L757-71 call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 4 + main_#t~mem59#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem60#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem60#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem60#1 - 1)));havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1; 2712#L757-70 goto; 2725#L757-115 call main_#t~mem61#1.base, main_#t~mem61#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_#t~mem61#1.base, main_#t~mem61#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem62#1.base, main_#t~mem62#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem61#1.base, main_#t~mem61#1.offset;havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;call main_#t~mem63#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post64#1 := main_#t~mem63#1;call write~int(1 + main_#t~post64#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem63#1;havoc main_#t~post64#1;call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 2755#L757-73 assume main_#t~mem66#1.base != 0 || main_#t~mem66#1.offset != 0;havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem67#1.base, 12 + main_#t~mem67#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset; 2668#L757-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem69#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem68#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short72#1 := main_#t~mem69#1 % 4294967296 >= 10 * (1 + main_#t~mem68#1) % 4294967296; 2669#L757-76 assume main_#t~short72#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_#t~mem70#1.base, 36 + main_#t~mem70#1.offset, 4);main_#t~short72#1 := 0 == main_#t~mem71#1 % 4294967296; 2746#L757-78 assume !main_#t~short72#1;havoc main_#t~mem69#1;havoc main_#t~mem68#1;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;havoc main_#t~short72#1; 2692#L757-114 goto; 2693#L757-116 goto; 2728#L757-118 goto; 2729#L757-120 goto; 2701#L750-2 main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2685#L750-3 [2022-12-13 18:54:04,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:54:04,028 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 6 times [2022-12-13 18:54:04,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:54:04,028 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607184077] [2022-12-13 18:54:04,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:04,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:54:04,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:54:04,038 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 18:54:04,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:54:04,046 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 18:54:04,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:54:04,047 INFO L85 PathProgramCache]: Analyzing trace with hash -1082263419, now seen corresponding path program 1 times [2022-12-13 18:54:04,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:54:04,047 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851906330] [2022-12-13 18:54:04,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:04,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:54:04,139 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-13 18:54:04,139 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1362992962] [2022-12-13 18:54:04,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:54:04,140 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 18:54:04,140 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 18:54:04,141 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 18:54:04,142 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-12-13 18:57:25,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:57:25,441 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 18:57:30,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 18:57:30,197 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 18:57:30,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:57:30,197 INFO L85 PathProgramCache]: Analyzing trace with hash -1692418973, now seen corresponding path program 1 times [2022-12-13 18:57:30,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:57:30,198 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350031044] [2022-12-13 18:57:30,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:57:30,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:57:30,285 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-13 18:57:30,285 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1129153386] [2022-12-13 18:57:30,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:57:30,285 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-13 18:57:30,285 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 18:57:30,287 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-13 18:57:30,287 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5789f37d-7259-4e74-93fd-95d493f7a3e3/bin/uautomizer-uyxdKDjOR8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-12-13 18:57:31,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:57:31,025 INFO L263 TraceCheckSpWp]: Trace formula consists of 1814 conjuncts, 5 conjunts are in the unsatisfiable core [2022-12-13 18:57:31,027 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-13 18:57:31,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:57:31,123 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-13 18:57:31,123 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:57:31,123 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350031044] [2022-12-13 18:57:31,123 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-13 18:57:31,124 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1129153386] [2022-12-13 18:57:31,124 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1129153386] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:57:31,124 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:57:31,124 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:57:31,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [614236181] [2022-12-13 18:57:31,124 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton