./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pc_sfifo_1.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pc_sfifo_1.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c74d959057dcef9924c2fba34a5baac5be90cef6ad1eac335d6f9d2397fc60bb --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 19:16:21,387 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 19:16:21,389 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 19:16:21,408 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 19:16:21,408 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 19:16:21,409 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 19:16:21,411 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 19:16:21,412 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 19:16:21,414 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 19:16:21,415 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 19:16:21,416 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 19:16:21,417 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 19:16:21,417 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 19:16:21,418 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 19:16:21,419 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 19:16:21,421 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 19:16:21,421 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 19:16:21,422 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 19:16:21,424 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 19:16:21,426 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 19:16:21,427 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 19:16:21,429 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 19:16:21,430 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 19:16:21,431 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 19:16:21,435 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 19:16:21,435 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 19:16:21,435 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 19:16:21,436 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 19:16:21,437 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 19:16:21,438 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 19:16:21,438 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 19:16:21,439 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 19:16:21,440 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 19:16:21,440 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 19:16:21,441 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 19:16:21,441 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 19:16:21,442 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 19:16:21,442 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 19:16:21,442 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 19:16:21,443 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 19:16:21,444 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 19:16:21,445 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 19:16:21,466 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 19:16:21,467 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 19:16:21,467 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 19:16:21,467 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 19:16:21,468 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 19:16:21,468 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 19:16:21,469 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 19:16:21,469 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 19:16:21,469 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 19:16:21,469 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 19:16:21,469 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 19:16:21,469 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 19:16:21,469 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 19:16:21,470 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 19:16:21,470 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 19:16:21,470 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 19:16:21,470 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 19:16:21,470 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 19:16:21,471 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 19:16:21,471 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 19:16:21,471 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 19:16:21,471 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 19:16:21,471 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 19:16:21,471 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 19:16:21,472 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 19:16:21,472 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 19:16:21,472 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 19:16:21,472 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 19:16:21,472 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 19:16:21,473 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 19:16:21,473 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 19:16:21,474 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 19:16:21,474 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c74d959057dcef9924c2fba34a5baac5be90cef6ad1eac335d6f9d2397fc60bb [2022-12-13 19:16:21,657 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 19:16:21,673 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 19:16:21,675 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 19:16:21,676 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 19:16:21,676 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 19:16:21,677 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/pc_sfifo_1.cil-1.c [2022-12-13 19:16:24,214 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 19:16:24,371 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 19:16:24,371 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/sv-benchmarks/c/systemc/pc_sfifo_1.cil-1.c [2022-12-13 19:16:24,377 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/data/ca0332cfb/65f9f3646ea542eaa9c728cc79752fdd/FLAG4f045a433 [2022-12-13 19:16:24,787 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/data/ca0332cfb/65f9f3646ea542eaa9c728cc79752fdd [2022-12-13 19:16:24,789 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 19:16:24,790 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 19:16:24,791 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 19:16:24,791 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 19:16:24,793 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 19:16:24,794 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 07:16:24" (1/1) ... [2022-12-13 19:16:24,794 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@58ab7e38 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24, skipping insertion in model container [2022-12-13 19:16:24,795 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 07:16:24" (1/1) ... [2022-12-13 19:16:24,799 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 19:16:24,815 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 19:16:24,901 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/sv-benchmarks/c/systemc/pc_sfifo_1.cil-1.c[642,655] [2022-12-13 19:16:24,924 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 19:16:24,933 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 19:16:24,941 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/sv-benchmarks/c/systemc/pc_sfifo_1.cil-1.c[642,655] [2022-12-13 19:16:24,952 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 19:16:24,963 INFO L208 MainTranslator]: Completed translation [2022-12-13 19:16:24,963 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24 WrapperNode [2022-12-13 19:16:24,963 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 19:16:24,964 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 19:16:24,964 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 19:16:24,964 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 19:16:24,969 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24" (1/1) ... [2022-12-13 19:16:24,974 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24" (1/1) ... [2022-12-13 19:16:24,989 INFO L138 Inliner]: procedures = 24, calls = 23, calls flagged for inlining = 18, calls inlined = 20, statements flattened = 260 [2022-12-13 19:16:24,990 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 19:16:24,990 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 19:16:24,990 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 19:16:24,990 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 19:16:24,996 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24" (1/1) ... [2022-12-13 19:16:24,996 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24" (1/1) ... [2022-12-13 19:16:24,997 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24" (1/1) ... [2022-12-13 19:16:24,998 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24" (1/1) ... [2022-12-13 19:16:25,000 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24" (1/1) ... [2022-12-13 19:16:25,003 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24" (1/1) ... [2022-12-13 19:16:25,004 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24" (1/1) ... [2022-12-13 19:16:25,005 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24" (1/1) ... [2022-12-13 19:16:25,006 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 19:16:25,007 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 19:16:25,007 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 19:16:25,007 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 19:16:25,008 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24" (1/1) ... [2022-12-13 19:16:25,013 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 19:16:25,022 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 19:16:25,030 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 19:16:25,032 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 19:16:25,061 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 19:16:25,061 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 19:16:25,061 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 19:16:25,061 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 19:16:25,118 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 19:16:25,119 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 19:16:25,302 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 19:16:25,307 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 19:16:25,307 INFO L300 CfgBuilder]: Removed 4 assume(true) statements. [2022-12-13 19:16:25,309 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:16:25 BoogieIcfgContainer [2022-12-13 19:16:25,309 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 19:16:25,310 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 19:16:25,310 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 19:16:25,313 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 19:16:25,313 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:16:25,313 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 07:16:24" (1/3) ... [2022-12-13 19:16:25,314 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5fa58447 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 07:16:25, skipping insertion in model container [2022-12-13 19:16:25,314 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:16:25,314 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:16:24" (2/3) ... [2022-12-13 19:16:25,314 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5fa58447 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 07:16:25, skipping insertion in model container [2022-12-13 19:16:25,314 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:16:25,315 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:16:25" (3/3) ... [2022-12-13 19:16:25,316 INFO L332 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_1.cil-1.c [2022-12-13 19:16:25,355 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 19:16:25,355 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 19:16:25,355 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 19:16:25,355 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 19:16:25,355 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 19:16:25,355 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 19:16:25,356 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 19:16:25,356 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 19:16:25,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 81 states, 80 states have (on average 1.5125) internal successors, (121), 80 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:25,374 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-12-13 19:16:25,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:25,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:25,379 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-12-13 19:16:25,379 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:25,379 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 19:16:25,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 81 states, 80 states have (on average 1.5125) internal successors, (121), 80 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:25,382 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-12-13 19:16:25,382 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:25,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:25,383 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-12-13 19:16:25,383 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:25,389 INFO L748 eck$LassoCheckResult]: Stem: 32#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 45#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 68#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 38#L206true assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 3#L206-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 46#L211-1true assume { :end_inline_init_threads } true; 66#L323-2true [2022-12-13 19:16:25,390 INFO L750 eck$LassoCheckResult]: Loop: 66#L323-2true assume !false; 13#L324true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 50#L272true assume false; 16#eval_returnLabel#1true assume { :end_inline_eval } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 59#L224-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 77#L236-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 29#exists_runnable_thread_returnLabel#2true stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 14#L302true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15#L309true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 74#stop_simulation_returnLabel#1true start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 55#L330true assume !(0 != start_simulation_~tmp~3#1); 66#L323-2true [2022-12-13 19:16:25,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:25,394 INFO L85 PathProgramCache]: Analyzing trace with hash 889479019, now seen corresponding path program 1 times [2022-12-13 19:16:25,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:25,401 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187055151] [2022-12-13 19:16:25,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:25,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:25,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:25,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:25,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:25,522 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1187055151] [2022-12-13 19:16:25,523 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1187055151] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:25,523 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:25,523 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:16:25,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [352032376] [2022-12-13 19:16:25,525 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:25,528 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:16:25,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:25,529 INFO L85 PathProgramCache]: Analyzing trace with hash -1504754769, now seen corresponding path program 1 times [2022-12-13 19:16:25,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:25,529 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228441496] [2022-12-13 19:16:25,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:25,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:25,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:25,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:25,539 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:25,539 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228441496] [2022-12-13 19:16:25,539 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1228441496] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:25,540 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:25,540 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:16:25,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1338114051] [2022-12-13 19:16:25,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:25,541 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:25,542 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:25,584 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:16:25,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:16:25,586 INFO L87 Difference]: Start difference. First operand has 81 states, 80 states have (on average 1.5125) internal successors, (121), 80 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:25,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:25,607 INFO L93 Difference]: Finished difference Result 78 states and 106 transitions. [2022-12-13 19:16:25,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78 states and 106 transitions. [2022-12-13 19:16:25,616 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 65 [2022-12-13 19:16:25,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78 states to 71 states and 99 transitions. [2022-12-13 19:16:25,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71 [2022-12-13 19:16:25,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71 [2022-12-13 19:16:25,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71 states and 99 transitions. [2022-12-13 19:16:25,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:25,621 INFO L218 hiAutomatonCegarLoop]: Abstraction has 71 states and 99 transitions. [2022-12-13 19:16:25,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states and 99 transitions. [2022-12-13 19:16:25,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71. [2022-12-13 19:16:25,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71 states, 71 states have (on average 1.3943661971830985) internal successors, (99), 70 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:25,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 99 transitions. [2022-12-13 19:16:25,644 INFO L240 hiAutomatonCegarLoop]: Abstraction has 71 states and 99 transitions. [2022-12-13 19:16:25,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:16:25,647 INFO L428 stractBuchiCegarLoop]: Abstraction has 71 states and 99 transitions. [2022-12-13 19:16:25,648 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 19:16:25,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71 states and 99 transitions. [2022-12-13 19:16:25,649 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 65 [2022-12-13 19:16:25,649 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:25,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:25,649 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-12-13 19:16:25,649 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:25,650 INFO L748 eck$LassoCheckResult]: Stem: 212#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 213#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 223#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 218#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 172#L206-2 assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 173#L211-1 assume { :end_inline_init_threads } true; 224#L323-2 [2022-12-13 19:16:25,650 INFO L750 eck$LassoCheckResult]: Loop: 224#L323-2 assume !false; 189#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 176#L272 assume !false; 228#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 180#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 181#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 183#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 184#L252 assume !(0 != eval_~tmp___1~0#1); 193#eval_returnLabel#1 assume { :end_inline_eval } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 194#L224-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 233#L236-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 209#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 190#L302 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 191#L309 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 192#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 230#L330 assume !(0 != start_simulation_~tmp~3#1); 224#L323-2 [2022-12-13 19:16:25,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:25,650 INFO L85 PathProgramCache]: Analyzing trace with hash 889477097, now seen corresponding path program 1 times [2022-12-13 19:16:25,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:25,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965973774] [2022-12-13 19:16:25,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:25,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:25,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:25,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:25,679 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:25,680 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1965973774] [2022-12-13 19:16:25,680 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1965973774] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:25,680 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:25,680 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:16:25,680 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247352297] [2022-12-13 19:16:25,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:25,681 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:16:25,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:25,682 INFO L85 PathProgramCache]: Analyzing trace with hash -1251467551, now seen corresponding path program 1 times [2022-12-13 19:16:25,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:25,682 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29209755] [2022-12-13 19:16:25,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:25,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:25,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:25,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:25,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:25,734 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [29209755] [2022-12-13 19:16:25,734 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [29209755] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:25,734 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:25,734 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:16:25,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1586697380] [2022-12-13 19:16:25,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:25,735 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:25,735 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:25,735 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:16:25,736 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:16:25,736 INFO L87 Difference]: Start difference. First operand 71 states and 99 transitions. cyclomatic complexity: 29 Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:25,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:25,745 INFO L93 Difference]: Finished difference Result 71 states and 98 transitions. [2022-12-13 19:16:25,745 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 98 transitions. [2022-12-13 19:16:25,746 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 65 [2022-12-13 19:16:25,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 71 states and 98 transitions. [2022-12-13 19:16:25,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71 [2022-12-13 19:16:25,747 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71 [2022-12-13 19:16:25,747 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71 states and 98 transitions. [2022-12-13 19:16:25,748 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:25,748 INFO L218 hiAutomatonCegarLoop]: Abstraction has 71 states and 98 transitions. [2022-12-13 19:16:25,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states and 98 transitions. [2022-12-13 19:16:25,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71. [2022-12-13 19:16:25,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71 states, 71 states have (on average 1.380281690140845) internal successors, (98), 70 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:25,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 98 transitions. [2022-12-13 19:16:25,751 INFO L240 hiAutomatonCegarLoop]: Abstraction has 71 states and 98 transitions. [2022-12-13 19:16:25,751 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:16:25,752 INFO L428 stractBuchiCegarLoop]: Abstraction has 71 states and 98 transitions. [2022-12-13 19:16:25,752 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 19:16:25,752 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71 states and 98 transitions. [2022-12-13 19:16:25,753 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 65 [2022-12-13 19:16:25,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:25,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:25,753 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-12-13 19:16:25,753 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:25,754 INFO L748 eck$LassoCheckResult]: Stem: 364#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 365#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 374#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 371#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 323#L206-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 324#L211-1 assume { :end_inline_init_threads } true; 375#L323-2 [2022-12-13 19:16:25,754 INFO L750 eck$LassoCheckResult]: Loop: 375#L323-2 assume !false; 342#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 327#L272 assume !false; 378#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 331#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 332#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 334#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 335#L252 assume !(0 != eval_~tmp___1~0#1); 344#eval_returnLabel#1 assume { :end_inline_eval } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 345#L224-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 384#L236-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 358#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 340#L302 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 341#L309 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 343#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 382#L330 assume !(0 != start_simulation_~tmp~3#1); 375#L323-2 [2022-12-13 19:16:25,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:25,754 INFO L85 PathProgramCache]: Analyzing trace with hash 889477035, now seen corresponding path program 1 times [2022-12-13 19:16:25,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:25,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251223359] [2022-12-13 19:16:25,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:25,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:25,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:25,763 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:25,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:25,782 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:16:25,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:25,782 INFO L85 PathProgramCache]: Analyzing trace with hash -1251467551, now seen corresponding path program 2 times [2022-12-13 19:16:25,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:25,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575635322] [2022-12-13 19:16:25,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:25,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:25,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:25,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:25,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:25,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [575635322] [2022-12-13 19:16:25,823 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [575635322] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:25,823 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:25,823 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:16:25,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170008515] [2022-12-13 19:16:25,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:25,824 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:25,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:25,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:16:25,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:16:25,825 INFO L87 Difference]: Start difference. First operand 71 states and 98 transitions. cyclomatic complexity: 28 Second operand has 5 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:25,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:25,896 INFO L93 Difference]: Finished difference Result 139 states and 190 transitions. [2022-12-13 19:16:25,896 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 139 states and 190 transitions. [2022-12-13 19:16:25,897 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 133 [2022-12-13 19:16:25,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 139 states to 139 states and 190 transitions. [2022-12-13 19:16:25,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 139 [2022-12-13 19:16:25,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 139 [2022-12-13 19:16:25,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 139 states and 190 transitions. [2022-12-13 19:16:25,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:25,899 INFO L218 hiAutomatonCegarLoop]: Abstraction has 139 states and 190 transitions. [2022-12-13 19:16:25,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states and 190 transitions. [2022-12-13 19:16:25,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 74. [2022-12-13 19:16:25,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.364864864864865) internal successors, (101), 73 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:25,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 101 transitions. [2022-12-13 19:16:25,903 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 101 transitions. [2022-12-13 19:16:25,903 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 19:16:25,904 INFO L428 stractBuchiCegarLoop]: Abstraction has 74 states and 101 transitions. [2022-12-13 19:16:25,904 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 19:16:25,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 101 transitions. [2022-12-13 19:16:25,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 68 [2022-12-13 19:16:25,904 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:25,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:25,905 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-12-13 19:16:25,905 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:25,905 INFO L748 eck$LassoCheckResult]: Stem: 590#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 591#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 601#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 596#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 549#L206-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 550#L211-1 assume { :end_inline_init_threads } true; 602#L323-2 [2022-12-13 19:16:25,905 INFO L750 eck$LassoCheckResult]: Loop: 602#L323-2 assume !false; 566#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 553#L272 assume !false; 606#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 557#L224 assume !(0 == ~p_dw_st~0); 559#L228 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 572#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 616#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 618#L252 assume !(0 != eval_~tmp___1~0#1); 570#eval_returnLabel#1 assume { :end_inline_eval } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 571#L224-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 611#L236-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 585#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 567#L302 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 568#L309 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 569#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 609#L330 assume !(0 != start_simulation_~tmp~3#1); 602#L323-2 [2022-12-13 19:16:25,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:25,906 INFO L85 PathProgramCache]: Analyzing trace with hash 889477035, now seen corresponding path program 2 times [2022-12-13 19:16:25,906 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:25,906 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344752179] [2022-12-13 19:16:25,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:25,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:25,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:25,912 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:25,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:25,918 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:16:25,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:25,919 INFO L85 PathProgramCache]: Analyzing trace with hash 960183933, now seen corresponding path program 1 times [2022-12-13 19:16:25,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:25,919 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387777662] [2022-12-13 19:16:25,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:25,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:25,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:25,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:25,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:25,937 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387777662] [2022-12-13 19:16:25,937 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387777662] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:25,937 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:25,937 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:16:25,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324228458] [2022-12-13 19:16:25,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:25,938 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:25,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:25,938 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:16:25,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:16:25,938 INFO L87 Difference]: Start difference. First operand 74 states and 101 transitions. cyclomatic complexity: 28 Second operand has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:25,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:25,959 INFO L93 Difference]: Finished difference Result 120 states and 160 transitions. [2022-12-13 19:16:25,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120 states and 160 transitions. [2022-12-13 19:16:25,960 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 112 [2022-12-13 19:16:25,961 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120 states to 120 states and 160 transitions. [2022-12-13 19:16:25,961 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120 [2022-12-13 19:16:25,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120 [2022-12-13 19:16:25,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120 states and 160 transitions. [2022-12-13 19:16:25,962 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:25,962 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120 states and 160 transitions. [2022-12-13 19:16:25,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states and 160 transitions. [2022-12-13 19:16:25,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 103. [2022-12-13 19:16:25,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103 states, 103 states have (on average 1.3203883495145632) internal successors, (136), 102 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:25,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 136 transitions. [2022-12-13 19:16:25,966 INFO L240 hiAutomatonCegarLoop]: Abstraction has 103 states and 136 transitions. [2022-12-13 19:16:25,966 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:16:25,967 INFO L428 stractBuchiCegarLoop]: Abstraction has 103 states and 136 transitions. [2022-12-13 19:16:25,967 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 19:16:25,967 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103 states and 136 transitions. [2022-12-13 19:16:25,967 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 95 [2022-12-13 19:16:25,967 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:25,967 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:25,968 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:25,968 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:25,968 INFO L748 eck$LassoCheckResult]: Stem: 793#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 794#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 803#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 799#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 745#L206-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 746#L211-1 assume { :end_inline_init_threads } true; 804#L323-2 assume !false; 821#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 830#L272 [2022-12-13 19:16:25,968 INFO L750 eck$LassoCheckResult]: Loop: 830#L272 assume !false; 829#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 828#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 827#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 826#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 814#L252 assume 0 != eval_~tmp___1~0#1; 815#L252-1 assume !(0 == ~p_dw_st~0); 795#L257 assume 0 == ~c_dr_st~0;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 751#L276 assume 0 != eval_~tmp___0~1#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 752#L149 assume 0 == ~c_dr_pc~0; 781#L182-1 assume !false; 831#L161 assume !(1 == ~q_free~0); 765#L162-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_read_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 847#L42-3 assume 1 == ~p_dw_pc~0; 845#L43-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 844#L53-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 843#is_do_write_p_triggered_returnLabel#2 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 842#L84-3 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 748#L84-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 805#L61-3 assume 1 == ~c_dr_pc~0; 813#L62-1 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 749#L72-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 750#is_do_read_c_triggered_returnLabel#2 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 802#L92-3 assume 0 != immediate_notify_threads_~tmp___0~0#1;~c_dr_st~0 := 0; 791#L92-5 assume { :end_inline_immediate_notify_threads } true;~q_read_ev~0 := 2; 792#L182 assume ~p_last_write~0 == ~c_last_read~0; 786#L183 assume ~p_num_write~0 == ~c_num_read~0; 787#L182-1 assume !false; 761#L161 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 762#do_read_c_returnLabel#1 assume { :end_inline_do_read_c } true; 830#L272 [2022-12-13 19:16:25,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:25,969 INFO L85 PathProgramCache]: Analyzing trace with hash 88939597, now seen corresponding path program 1 times [2022-12-13 19:16:25,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:25,969 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374556235] [2022-12-13 19:16:25,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:25,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:25,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:25,974 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:25,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:25,980 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:16:25,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:25,981 INFO L85 PathProgramCache]: Analyzing trace with hash 1842572908, now seen corresponding path program 1 times [2022-12-13 19:16:25,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:25,981 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222808124] [2022-12-13 19:16:25,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:25,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:25,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:25,999 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-13 19:16:25,999 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:25,999 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1222808124] [2022-12-13 19:16:25,999 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1222808124] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:26,000 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:26,000 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:16:26,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1262194364] [2022-12-13 19:16:26,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:26,000 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:26,001 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:26,001 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:16:26,001 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:16:26,001 INFO L87 Difference]: Start difference. First operand 103 states and 136 transitions. cyclomatic complexity: 34 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:26,018 INFO L93 Difference]: Finished difference Result 120 states and 158 transitions. [2022-12-13 19:16:26,018 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120 states and 158 transitions. [2022-12-13 19:16:26,020 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 112 [2022-12-13 19:16:26,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120 states to 120 states and 158 transitions. [2022-12-13 19:16:26,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120 [2022-12-13 19:16:26,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120 [2022-12-13 19:16:26,022 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120 states and 158 transitions. [2022-12-13 19:16:26,023 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:26,023 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120 states and 158 transitions. [2022-12-13 19:16:26,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states and 158 transitions. [2022-12-13 19:16:26,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 103. [2022-12-13 19:16:26,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103 states, 103 states have (on average 1.3009708737864079) internal successors, (134), 102 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 134 transitions. [2022-12-13 19:16:26,027 INFO L240 hiAutomatonCegarLoop]: Abstraction has 103 states and 134 transitions. [2022-12-13 19:16:26,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:16:26,028 INFO L428 stractBuchiCegarLoop]: Abstraction has 103 states and 134 transitions. [2022-12-13 19:16:26,028 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 19:16:26,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103 states and 134 transitions. [2022-12-13 19:16:26,028 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 95 [2022-12-13 19:16:26,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:26,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:26,029 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,029 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,029 INFO L748 eck$LassoCheckResult]: Stem: 1023#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1024#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1033#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 1029#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 974#L206-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 975#L211-1 assume { :end_inline_init_threads } true; 1034#L323-2 assume !false; 995#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 996#L272 [2022-12-13 19:16:26,029 INFO L750 eck$LassoCheckResult]: Loop: 996#L272 assume !false; 1037#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 986#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 987#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1056#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 1044#L252 assume 0 != eval_~tmp___1~0#1; 1045#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1052#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 1040#L106 assume 0 == ~p_dw_pc~0; 1015#L117-1 assume !false; 1008#L118 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 1009#do_write_p_returnLabel#1 assume { :end_inline_do_write_p } true; 1025#L257 assume 0 == ~c_dr_st~0;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 980#L276 assume 0 != eval_~tmp___0~1#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 981#L149 assume 0 == ~c_dr_pc~0; 1011#L182-1 assume !false; 1060#L161 assume !(1 == ~q_free~0); 994#L162-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_read_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1076#L42-3 assume 1 == ~p_dw_pc~0; 1074#L43-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 1073#L53-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1072#is_do_write_p_triggered_returnLabel#2 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 1071#L84-3 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 977#L84-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1035#L61-3 assume 1 == ~c_dr_pc~0; 1043#L62-1 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 978#L72-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 979#is_do_read_c_triggered_returnLabel#2 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 1032#L92-3 assume 0 != immediate_notify_threads_~tmp___0~0#1;~c_dr_st~0 := 0; 1021#L92-5 assume { :end_inline_immediate_notify_threads } true;~q_read_ev~0 := 2; 1022#L182 assume ~p_last_write~0 == ~c_last_read~0; 1016#L183 assume ~p_num_write~0 == ~c_num_read~0; 1017#L182-1 assume !false; 990#L161 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 991#do_read_c_returnLabel#1 assume { :end_inline_do_read_c } true; 996#L272 [2022-12-13 19:16:26,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,030 INFO L85 PathProgramCache]: Analyzing trace with hash 88939597, now seen corresponding path program 2 times [2022-12-13 19:16:26,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,030 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562644115] [2022-12-13 19:16:26,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,035 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:26,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,040 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:16:26,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,041 INFO L85 PathProgramCache]: Analyzing trace with hash -337282307, now seen corresponding path program 1 times [2022-12-13 19:16:26,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795085761] [2022-12-13 19:16:26,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:26,089 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:26,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:26,090 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [795085761] [2022-12-13 19:16:26,090 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [795085761] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:26,090 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:26,090 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:16:26,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [573095735] [2022-12-13 19:16:26,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:26,091 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:26,091 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:26,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:16:26,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:16:26,092 INFO L87 Difference]: Start difference. First operand 103 states and 134 transitions. cyclomatic complexity: 32 Second operand has 5 states, 5 states have (on average 7.0) internal successors, (35), 5 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:26,169 INFO L93 Difference]: Finished difference Result 260 states and 329 transitions. [2022-12-13 19:16:26,169 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 260 states and 329 transitions. [2022-12-13 19:16:26,172 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2022-12-13 19:16:26,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 260 states to 260 states and 329 transitions. [2022-12-13 19:16:26,174 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 260 [2022-12-13 19:16:26,175 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 260 [2022-12-13 19:16:26,175 INFO L73 IsDeterministic]: Start isDeterministic. Operand 260 states and 329 transitions. [2022-12-13 19:16:26,176 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:26,176 INFO L218 hiAutomatonCegarLoop]: Abstraction has 260 states and 329 transitions. [2022-12-13 19:16:26,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 260 states and 329 transitions. [2022-12-13 19:16:26,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 260 to 224. [2022-12-13 19:16:26,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224 states, 224 states have (on average 1.2723214285714286) internal successors, (285), 223 states have internal predecessors, (285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 285 transitions. [2022-12-13 19:16:26,184 INFO L240 hiAutomatonCegarLoop]: Abstraction has 224 states and 285 transitions. [2022-12-13 19:16:26,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-12-13 19:16:26,184 INFO L428 stractBuchiCegarLoop]: Abstraction has 224 states and 285 transitions. [2022-12-13 19:16:26,185 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 19:16:26,185 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 224 states and 285 transitions. [2022-12-13 19:16:26,185 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 195 [2022-12-13 19:16:26,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:26,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:26,186 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,186 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,186 INFO L748 eck$LassoCheckResult]: Stem: 1398#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1399#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1415#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 1406#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1353#L206-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1354#L211-1 assume { :end_inline_init_threads } true; 1416#L323-2 assume !false; 1490#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 1488#L272 assume !false; 1486#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1484#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1482#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1480#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 1467#L252 assume 0 != eval_~tmp___1~0#1; 1464#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1452#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 1453#L106 assume 0 == ~p_dw_pc~0; 1422#L117-1 assume !false; 1465#L118 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 1466#do_write_p_returnLabel#1 [2022-12-13 19:16:26,187 INFO L750 eck$LassoCheckResult]: Loop: 1466#do_write_p_returnLabel#1 assume { :end_inline_do_write_p } true; 1472#L257 assume 0 == ~c_dr_st~0;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1470#L276 assume 0 != eval_~tmp___0~1#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 1469#L149 assume 0 == ~c_dr_pc~0; 1387#L182-1 assume !false; 1368#L161 assume !(1 == ~q_free~0); 1369#L162-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_read_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1382#L42-3 assume 1 == ~p_dw_pc~0; 1383#L43-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 1549#L53-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1548#is_do_write_p_triggered_returnLabel#2 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 1547#L84-3 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 1356#L84-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1545#L61-3 assume !(1 == ~c_dr_pc~0); 1388#L61-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 1357#L72-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1358#is_do_read_c_triggered_returnLabel#2 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 1417#L92-3 assume 0 != immediate_notify_threads_~tmp___0~0#1;~c_dr_st~0 := 0; 1396#L92-5 assume { :end_inline_immediate_notify_threads } true;~q_read_ev~0 := 2; 1397#L182 assume ~p_last_write~0 == ~c_last_read~0; 1391#L183 assume ~p_num_write~0 == ~c_num_read~0; 1392#L182-1 assume !false; 1461#L161 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 1462#do_read_c_returnLabel#1 assume { :end_inline_do_read_c } true; 1489#L272 assume !false; 1487#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1485#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1483#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1481#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 1476#L252 assume 0 != eval_~tmp___1~0#1; 1475#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1474#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 1430#L106 assume !(0 == ~p_dw_pc~0); 1432#L109 assume 1 == ~p_dw_pc~0; 1439#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1440#L42 assume 1 == ~p_dw_pc~0; 1459#L43 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 1458#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1457#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 1456#L84 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 1455#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1454#L61 assume !(1 == ~c_dr_pc~0); 1363#L61-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1450#L72 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1451#is_do_read_c_triggered_returnLabel#1 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 1424#L92 assume 0 != immediate_notify_threads_~tmp___0~0#1;~c_dr_st~0 := 0; 1425#L92-2 assume { :end_inline_immediate_notify_threads } true;~q_write_ev~0 := 2; 1479#L117-1 assume !false; 1477#L118 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 1466#do_write_p_returnLabel#1 [2022-12-13 19:16:26,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,187 INFO L85 PathProgramCache]: Analyzing trace with hash 724282251, now seen corresponding path program 1 times [2022-12-13 19:16:26,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,187 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814146436] [2022-12-13 19:16:26,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:26,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:26,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:26,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814146436] [2022-12-13 19:16:26,249 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [814146436] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:26,249 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:26,249 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-12-13 19:16:26,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1451063204] [2022-12-13 19:16:26,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:26,250 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:16:26,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,250 INFO L85 PathProgramCache]: Analyzing trace with hash -1507672840, now seen corresponding path program 1 times [2022-12-13 19:16:26,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [869042039] [2022-12-13 19:16:26,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:26,290 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:26,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:26,290 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [869042039] [2022-12-13 19:16:26,290 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [869042039] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:26,290 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:26,290 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:16:26,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [13010225] [2022-12-13 19:16:26,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:26,291 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:26,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:26,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-12-13 19:16:26,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2022-12-13 19:16:26,292 INFO L87 Difference]: Start difference. First operand 224 states and 285 transitions. cyclomatic complexity: 62 Second operand has 7 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 7 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:26,383 INFO L93 Difference]: Finished difference Result 296 states and 362 transitions. [2022-12-13 19:16:26,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 296 states and 362 transitions. [2022-12-13 19:16:26,386 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2022-12-13 19:16:26,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 296 states to 292 states and 356 transitions. [2022-12-13 19:16:26,388 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 292 [2022-12-13 19:16:26,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 292 [2022-12-13 19:16:26,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 292 states and 356 transitions. [2022-12-13 19:16:26,389 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:26,389 INFO L218 hiAutomatonCegarLoop]: Abstraction has 292 states and 356 transitions. [2022-12-13 19:16:26,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292 states and 356 transitions. [2022-12-13 19:16:26,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292 to 192. [2022-12-13 19:16:26,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 192 states, 192 states have (on average 1.2447916666666667) internal successors, (239), 191 states have internal predecessors, (239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 239 transitions. [2022-12-13 19:16:26,395 INFO L240 hiAutomatonCegarLoop]: Abstraction has 192 states and 239 transitions. [2022-12-13 19:16:26,396 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-12-13 19:16:26,396 INFO L428 stractBuchiCegarLoop]: Abstraction has 192 states and 239 transitions. [2022-12-13 19:16:26,396 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 19:16:26,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 192 states and 239 transitions. [2022-12-13 19:16:26,397 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 163 [2022-12-13 19:16:26,397 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:26,397 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:26,398 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,398 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,398 INFO L748 eck$LassoCheckResult]: Stem: 1944#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1945#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1957#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 1951#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1896#L206-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1897#L211-1 assume { :end_inline_init_threads } true; 1958#L323-2 assume !false; 2014#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 2013#L272 assume !false; 2012#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2011#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2010#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2008#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 2006#L252 assume 0 != eval_~tmp___1~0#1; 2004#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2003#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 1968#L106 assume !(0 == ~p_dw_pc~0); 1970#L109 assume 1 == ~p_dw_pc~0; 1974#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1975#L42 assume 1 == ~p_dw_pc~0; 1978#L43 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 1950#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1939#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 1940#L84 assume !(0 != immediate_notify_threads_~tmp~0#1); 1934#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1906#L61 assume !(1 == ~c_dr_pc~0); 1907#L61-2 [2022-12-13 19:16:26,398 INFO L750 eck$LassoCheckResult]: Loop: 1907#L61-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1987#L72 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1988#is_do_read_c_triggered_returnLabel#1 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 1964#L92 assume 0 != immediate_notify_threads_~tmp___0~0#1;~c_dr_st~0 := 0; 1965#L92-2 assume { :end_inline_immediate_notify_threads } true;~q_write_ev~0 := 2; 2030#L117-1 assume !false; 1928#L118 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 1929#do_write_p_returnLabel#1 assume { :end_inline_do_write_p } true; 2025#L257 assume 0 == ~c_dr_st~0;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 2023#L276 assume 0 != eval_~tmp___0~1#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 1930#L149 assume 0 == ~c_dr_pc~0; 1931#L182-1 assume !false; 1912#L161 assume !(1 == ~q_free~0); 1913#L162-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_read_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2081#L42-3 assume !(1 == ~p_dw_pc~0); 2080#L42-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 2078#L53-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2077#is_do_write_p_triggered_returnLabel#2 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 2075#L84-3 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 2076#L84-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1980#L61-3 assume !(1 == ~c_dr_pc~0); 1933#L61-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 1901#L72-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1902#is_do_read_c_triggered_returnLabel#2 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 1956#L92-3 assume 0 != immediate_notify_threads_~tmp___0~0#1;~c_dr_st~0 := 0; 1942#L92-5 assume { :end_inline_immediate_notify_threads } true;~q_read_ev~0 := 2; 1943#L182 assume ~p_last_write~0 == ~c_last_read~0; 1954#L183 assume ~p_num_write~0 == ~c_num_read~0; 1989#L182-1 assume !false; 1990#L161 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 2019#do_read_c_returnLabel#1 assume { :end_inline_do_read_c } true; 2018#L272 assume !false; 2017#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2016#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2015#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2009#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 2007#L252 assume 0 != eval_~tmp___1~0#1; 2005#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1991#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 1992#L106 assume !(0 == ~p_dw_pc~0); 1960#L109 assume 1 == ~p_dw_pc~0; 1961#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2000#L42 assume 1 == ~p_dw_pc~0; 1998#L43 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 1997#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1996#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 1995#L84 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 1994#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1993#L61 assume !(1 == ~c_dr_pc~0); 1907#L61-2 [2022-12-13 19:16:26,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,398 INFO L85 PathProgramCache]: Analyzing trace with hash 465570555, now seen corresponding path program 1 times [2022-12-13 19:16:26,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,399 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1519909214] [2022-12-13 19:16:26,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:26,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:26,417 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:26,417 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1519909214] [2022-12-13 19:16:26,417 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1519909214] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:26,418 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:26,418 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:16:26,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732609066] [2022-12-13 19:16:26,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:26,418 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:16:26,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,419 INFO L85 PathProgramCache]: Analyzing trace with hash -1283582209, now seen corresponding path program 1 times [2022-12-13 19:16:26,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940966061] [2022-12-13 19:16:26,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:26,444 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:26,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:26,445 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [940966061] [2022-12-13 19:16:26,445 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [940966061] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:26,445 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:26,445 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:16:26,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [237578152] [2022-12-13 19:16:26,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:26,446 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:26,446 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:26,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:16:26,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:16:26,447 INFO L87 Difference]: Start difference. First operand 192 states and 239 transitions. cyclomatic complexity: 48 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:26,461 INFO L93 Difference]: Finished difference Result 215 states and 263 transitions. [2022-12-13 19:16:26,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 215 states and 263 transitions. [2022-12-13 19:16:26,463 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 188 [2022-12-13 19:16:26,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 215 states to 215 states and 263 transitions. [2022-12-13 19:16:26,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 215 [2022-12-13 19:16:26,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 215 [2022-12-13 19:16:26,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 215 states and 263 transitions. [2022-12-13 19:16:26,465 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:26,465 INFO L218 hiAutomatonCegarLoop]: Abstraction has 215 states and 263 transitions. [2022-12-13 19:16:26,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states and 263 transitions. [2022-12-13 19:16:26,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 194. [2022-12-13 19:16:26,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 194 states, 194 states have (on average 1.2216494845360826) internal successors, (237), 193 states have internal predecessors, (237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 237 transitions. [2022-12-13 19:16:26,472 INFO L240 hiAutomatonCegarLoop]: Abstraction has 194 states and 237 transitions. [2022-12-13 19:16:26,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:16:26,474 INFO L428 stractBuchiCegarLoop]: Abstraction has 194 states and 237 transitions. [2022-12-13 19:16:26,474 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 19:16:26,474 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 194 states and 237 transitions. [2022-12-13 19:16:26,475 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 167 [2022-12-13 19:16:26,475 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:26,475 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:26,476 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,476 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,477 INFO L748 eck$LassoCheckResult]: Stem: 2356#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 2357#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2371#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 2364#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2310#L206-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2311#L211-1 assume { :end_inline_init_threads } true; 2372#L323-2 assume !false; 2436#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 2434#L272 assume !false; 2432#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2430#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2426#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2422#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 2418#L252 assume 0 != eval_~tmp___1~0#1; 2414#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2407#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 2383#L106 assume 0 == ~p_dw_pc~0; 2384#L117-1 assume !false; 2465#L118 assume !(0 == ~q_free~0); 2390#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2391#L42 assume !(1 == ~p_dw_pc~0); 2400#L42-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 2363#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2351#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 2352#L84 assume !(0 != immediate_notify_threads_~tmp~0#1); 2347#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2320#L61 assume !(1 == ~c_dr_pc~0); 2321#L61-2 [2022-12-13 19:16:26,477 INFO L750 eck$LassoCheckResult]: Loop: 2321#L61-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 2452#L72 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2450#is_do_read_c_triggered_returnLabel#1 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 2447#L92 assume 0 != immediate_notify_threads_~tmp___0~0#1;~c_dr_st~0 := 0; 2445#L92-2 assume { :end_inline_immediate_notify_threads } true;~q_write_ev~0 := 2; 2442#L117-1 assume !false; 2428#L118 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 2424#do_write_p_returnLabel#1 assume { :end_inline_do_write_p } true; 2421#L257 assume 0 == ~c_dr_st~0;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 2416#L276 assume 0 != eval_~tmp___0~1#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 2413#L149 assume 0 == ~c_dr_pc~0; 2360#L182-1 assume !false; 2406#L161 assume !(1 == ~q_free~0); 2380#L162-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_read_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2339#L42-3 assume 1 == ~p_dw_pc~0; 2340#L43-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 2368#L53-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2402#is_do_write_p_triggered_returnLabel#2 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 2312#L84-3 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 2313#L84-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2374#L61-3 assume !(1 == ~c_dr_pc~0); 2468#L61-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 2467#L72-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2369#is_do_read_c_triggered_returnLabel#2 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 2370#L92-3 assume 0 != immediate_notify_threads_~tmp___0~0#1;~c_dr_st~0 := 0; 2466#L92-5 assume { :end_inline_immediate_notify_threads } true;~q_read_ev~0 := 2; 2366#L182 assume ~p_last_write~0 == ~c_last_read~0; 2367#L183 assume ~p_num_write~0 == ~c_num_read~0; 2438#L182-1 assume !false; 2437#L161 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 2435#do_read_c_returnLabel#1 assume { :end_inline_do_read_c } true; 2433#L272 assume !false; 2431#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2427#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2423#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2420#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 2415#L252 assume 0 != eval_~tmp___1~0#1; 2412#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2410#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 2408#L106 assume !(0 == ~p_dw_pc~0); 2375#L109 assume 1 == ~p_dw_pc~0; 2376#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2411#L42 assume 1 == ~p_dw_pc~0; 2393#L43 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 2394#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2451#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 2441#L84 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 2440#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2439#L61 assume !(1 == ~c_dr_pc~0); 2321#L61-2 [2022-12-13 19:16:26,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,477 INFO L85 PathProgramCache]: Analyzing trace with hash 562308425, now seen corresponding path program 1 times [2022-12-13 19:16:26,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,478 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [266512247] [2022-12-13 19:16:26,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,486 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:26,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,496 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:16:26,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,497 INFO L85 PathProgramCache]: Analyzing trace with hash 1959935998, now seen corresponding path program 2 times [2022-12-13 19:16:26,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,498 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349172092] [2022-12-13 19:16:26,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:26,545 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:26,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:26,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [349172092] [2022-12-13 19:16:26,546 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [349172092] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:26,546 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:26,546 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:16:26,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2023716051] [2022-12-13 19:16:26,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:26,547 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:26,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:26,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:16:26,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:16:26,548 INFO L87 Difference]: Start difference. First operand 194 states and 237 transitions. cyclomatic complexity: 44 Second operand has 5 states, 5 states have (on average 9.8) internal successors, (49), 5 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:26,591 INFO L93 Difference]: Finished difference Result 405 states and 488 transitions. [2022-12-13 19:16:26,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 405 states and 488 transitions. [2022-12-13 19:16:26,594 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 378 [2022-12-13 19:16:26,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 405 states to 405 states and 488 transitions. [2022-12-13 19:16:26,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 405 [2022-12-13 19:16:26,597 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 405 [2022-12-13 19:16:26,597 INFO L73 IsDeterministic]: Start isDeterministic. Operand 405 states and 488 transitions. [2022-12-13 19:16:26,597 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:26,597 INFO L218 hiAutomatonCegarLoop]: Abstraction has 405 states and 488 transitions. [2022-12-13 19:16:26,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 405 states and 488 transitions. [2022-12-13 19:16:26,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 405 to 203. [2022-12-13 19:16:26,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 203 states, 203 states have (on average 1.206896551724138) internal successors, (245), 202 states have internal predecessors, (245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 245 transitions. [2022-12-13 19:16:26,604 INFO L240 hiAutomatonCegarLoop]: Abstraction has 203 states and 245 transitions. [2022-12-13 19:16:26,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 19:16:26,605 INFO L428 stractBuchiCegarLoop]: Abstraction has 203 states and 245 transitions. [2022-12-13 19:16:26,605 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 19:16:26,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 203 states and 245 transitions. [2022-12-13 19:16:26,606 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 176 [2022-12-13 19:16:26,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:26,606 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:26,608 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,608 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,608 INFO L748 eck$LassoCheckResult]: Stem: 2973#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 2974#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2986#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 2981#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2923#L206-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2924#L211-1 assume { :end_inline_init_threads } true; 2987#L323-2 assume !false; 3041#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 3040#L272 assume !false; 3039#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3038#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3037#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3036#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 3035#L252 assume 0 != eval_~tmp___1~0#1; 3034#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 3033#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 3032#L106 assume 0 == ~p_dw_pc~0; 3031#L117-1 assume !false; 3030#L118 assume !(0 == ~q_free~0); 3029#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3028#L42 assume !(1 == ~p_dw_pc~0); 3027#L42-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3026#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3025#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 3024#L84 assume !(0 != immediate_notify_threads_~tmp~0#1); 3023#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2933#L61 assume !(1 == ~c_dr_pc~0); 2934#L61-2 [2022-12-13 19:16:26,608 INFO L750 eck$LassoCheckResult]: Loop: 2934#L61-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3064#L72 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3063#is_do_read_c_triggered_returnLabel#1 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 3062#L92 assume !(0 != immediate_notify_threads_~tmp___0~0#1); 3061#L92-2 assume { :end_inline_immediate_notify_threads } true;~q_write_ev~0 := 2; 3060#L117-1 assume !false; 3058#L118 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 3056#do_write_p_returnLabel#1 assume { :end_inline_do_write_p } true; 3055#L257 assume 0 == ~c_dr_st~0;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 3053#L276 assume 0 != eval_~tmp___0~1#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 3052#L149 assume 0 == ~c_dr_pc~0; 2977#L182-1 assume !false; 2939#L161 assume !(1 == ~q_free~0); 2940#L162-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_read_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2954#L42-3 assume 1 == ~p_dw_pc~0; 2955#L43-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 2983#L53-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3015#is_do_write_p_triggered_returnLabel#2 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 3100#L84-3 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 3099#L84-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3010#L61-3 assume !(1 == ~c_dr_pc~0); 3011#L61-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 3098#L72-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3096#is_do_read_c_triggered_returnLabel#2 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 3094#L92-3 assume !(0 != immediate_notify_threads_~tmp___0~0#1); 3092#L92-5 assume { :end_inline_immediate_notify_threads } true;~q_read_ev~0 := 2; 3091#L182 assume ~p_last_write~0 == ~c_last_read~0; 3090#L183 assume ~p_num_write~0 == ~c_num_read~0; 3089#L182-1 assume !false; 3088#L161 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 3087#do_read_c_returnLabel#1 assume { :end_inline_do_read_c } true; 3086#L272 assume !false; 3085#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3084#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3051#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3049#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 3047#L252 assume 0 != eval_~tmp___1~0#1; 3046#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 3022#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 2999#L106 assume !(0 == ~p_dw_pc~0); 2991#L109 assume 1 == ~p_dw_pc~0; 2992#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3044#L42 assume 1 == ~p_dw_pc~0; 3008#L43 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 2980#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2967#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 2968#L84 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 2962#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2963#L61 assume !(1 == ~c_dr_pc~0); 2934#L61-2 [2022-12-13 19:16:26,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,609 INFO L85 PathProgramCache]: Analyzing trace with hash 562308425, now seen corresponding path program 2 times [2022-12-13 19:16:26,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1166366560] [2022-12-13 19:16:26,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,616 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:26,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,626 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:16:26,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,626 INFO L85 PathProgramCache]: Analyzing trace with hash -266209986, now seen corresponding path program 1 times [2022-12-13 19:16:26,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,627 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650152602] [2022-12-13 19:16:26,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:26,660 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:26,660 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:26,661 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650152602] [2022-12-13 19:16:26,661 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1650152602] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:26,661 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:26,661 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:16:26,661 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786880095] [2022-12-13 19:16:26,661 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:26,661 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:26,662 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:26,662 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:16:26,662 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:16:26,662 INFO L87 Difference]: Start difference. First operand 203 states and 245 transitions. cyclomatic complexity: 43 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:26,671 INFO L93 Difference]: Finished difference Result 203 states and 244 transitions. [2022-12-13 19:16:26,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 203 states and 244 transitions. [2022-12-13 19:16:26,673 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 176 [2022-12-13 19:16:26,674 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 203 states to 203 states and 244 transitions. [2022-12-13 19:16:26,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 203 [2022-12-13 19:16:26,674 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 203 [2022-12-13 19:16:26,674 INFO L73 IsDeterministic]: Start isDeterministic. Operand 203 states and 244 transitions. [2022-12-13 19:16:26,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:26,675 INFO L218 hiAutomatonCegarLoop]: Abstraction has 203 states and 244 transitions. [2022-12-13 19:16:26,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203 states and 244 transitions. [2022-12-13 19:16:26,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203 to 203. [2022-12-13 19:16:26,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 203 states, 203 states have (on average 1.2019704433497538) internal successors, (244), 202 states have internal predecessors, (244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 244 transitions. [2022-12-13 19:16:26,679 INFO L240 hiAutomatonCegarLoop]: Abstraction has 203 states and 244 transitions. [2022-12-13 19:16:26,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:16:26,680 INFO L428 stractBuchiCegarLoop]: Abstraction has 203 states and 244 transitions. [2022-12-13 19:16:26,680 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 19:16:26,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 203 states and 244 transitions. [2022-12-13 19:16:26,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 176 [2022-12-13 19:16:26,682 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:26,682 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:26,683 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,683 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,683 INFO L748 eck$LassoCheckResult]: Stem: 3383#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3384#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3396#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 3391#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3335#L206-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3336#L211-1 assume { :end_inline_init_threads } true; 3397#L323-2 assume !false; 3464#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 3462#L272 assume !false; 3458#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3455#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3450#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3445#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 3440#L252 assume 0 != eval_~tmp___1~0#1; 3435#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 3427#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 3406#L106 assume 0 == ~p_dw_pc~0; 3407#L117-1 assume !false; 3495#L118 assume !(0 == ~q_free~0); 3414#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3415#L42 assume !(1 == ~p_dw_pc~0); 3421#L42-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3390#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3377#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 3378#L84 assume !(0 != immediate_notify_threads_~tmp~0#1); 3373#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3345#L61 assume !(1 == ~c_dr_pc~0); 3346#L61-2 [2022-12-13 19:16:26,683 INFO L750 eck$LassoCheckResult]: Loop: 3346#L61-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3472#L72 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3470#is_do_read_c_triggered_returnLabel#1 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 3468#L92 assume !(0 != immediate_notify_threads_~tmp___0~0#1); 3460#L92-2 assume { :end_inline_immediate_notify_threads } true;~q_write_ev~0 := 2; 3457#L117-1 assume !false; 3452#L118 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 3447#do_write_p_returnLabel#1 assume { :end_inline_do_write_p } true; 3443#L257 assume 0 == ~c_dr_st~0;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 3437#L276 assume 0 != eval_~tmp___0~1#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 3433#L149 assume 0 == ~c_dr_pc~0; 3387#L182-1 assume !false; 3351#L161 assume !(1 == ~q_free~0); 3352#L162-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_read_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3365#L42-3 assume 1 == ~p_dw_pc~0; 3366#L43-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 3394#L53-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3422#is_do_write_p_triggered_returnLabel#2 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 3337#L84-3 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 3338#L84-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3480#L61-3 assume !(1 == ~c_dr_pc~0); 3478#L61-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 3476#L72-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3475#is_do_read_c_triggered_returnLabel#2 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 3474#L92-3 assume !(0 != immediate_notify_threads_~tmp___0~0#1); 3471#L92-5 assume { :end_inline_immediate_notify_threads } true;~q_read_ev~0 := 2; 3469#L182 assume ~p_last_write~0 == ~c_last_read~0; 3467#L183 assume ~p_num_write~0 == ~c_num_read~0; 3466#L182-1 assume !false; 3465#L161 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 3463#do_read_c_returnLabel#1 assume { :end_inline_do_read_c } true; 3459#L272 assume !false; 3456#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3451#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3446#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3442#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 3436#L252 assume 0 != eval_~tmp___1~0#1; 3432#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 3430#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 3428#L106 assume !(0 == ~p_dw_pc~0); 3399#L109 assume 1 == ~p_dw_pc~0; 3400#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3431#L42 assume !(1 == ~p_dw_pc~0); 3418#L42-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3454#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3449#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 3444#L84 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 3439#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3434#L61 assume !(1 == ~c_dr_pc~0); 3346#L61-2 [2022-12-13 19:16:26,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,684 INFO L85 PathProgramCache]: Analyzing trace with hash 562308425, now seen corresponding path program 3 times [2022-12-13 19:16:26,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,684 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511906715] [2022-12-13 19:16:26,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,691 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:26,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,700 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:16:26,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,701 INFO L85 PathProgramCache]: Analyzing trace with hash 1823123391, now seen corresponding path program 1 times [2022-12-13 19:16:26,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,701 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080035954] [2022-12-13 19:16:26,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:26,733 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-13 19:16:26,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:26,734 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1080035954] [2022-12-13 19:16:26,734 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1080035954] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:26,734 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:26,734 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:16:26,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62396578] [2022-12-13 19:16:26,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:26,734 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:26,735 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:26,735 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:16:26,735 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:16:26,735 INFO L87 Difference]: Start difference. First operand 203 states and 244 transitions. cyclomatic complexity: 42 Second operand has 3 states, 3 states have (on average 16.0) internal successors, (48), 3 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:26,753 INFO L93 Difference]: Finished difference Result 204 states and 240 transitions. [2022-12-13 19:16:26,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 204 states and 240 transitions. [2022-12-13 19:16:26,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 170 [2022-12-13 19:16:26,756 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 204 states to 204 states and 240 transitions. [2022-12-13 19:16:26,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 204 [2022-12-13 19:16:26,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 204 [2022-12-13 19:16:26,756 INFO L73 IsDeterministic]: Start isDeterministic. Operand 204 states and 240 transitions. [2022-12-13 19:16:26,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:26,757 INFO L218 hiAutomatonCegarLoop]: Abstraction has 204 states and 240 transitions. [2022-12-13 19:16:26,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states and 240 transitions. [2022-12-13 19:16:26,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 197. [2022-12-13 19:16:26,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 197 states, 197 states have (on average 1.1827411167512691) internal successors, (233), 196 states have internal predecessors, (233), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 233 transitions. [2022-12-13 19:16:26,760 INFO L240 hiAutomatonCegarLoop]: Abstraction has 197 states and 233 transitions. [2022-12-13 19:16:26,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:16:26,762 INFO L428 stractBuchiCegarLoop]: Abstraction has 197 states and 233 transitions. [2022-12-13 19:16:26,762 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 19:16:26,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 197 states and 233 transitions. [2022-12-13 19:16:26,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 170 [2022-12-13 19:16:26,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:26,763 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:26,763 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,763 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,764 INFO L748 eck$LassoCheckResult]: Stem: 3798#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3809#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 3804#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3753#L206-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3754#L211-1 assume { :end_inline_init_threads } true; 3810#L323-2 assume !false; 3886#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 3882#L272 assume !false; 3881#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3879#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3876#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3874#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 3873#L252 assume 0 != eval_~tmp___1~0#1; 3872#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 3845#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 3821#L106 assume 0 == ~p_dw_pc~0; 3822#L117-1 assume !false; 3878#L118 assume !(0 == ~q_free~0); 3829#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3830#L42 assume !(1 == ~p_dw_pc~0); 3835#L42-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3842#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3858#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 3823#L84 assume !(0 != immediate_notify_threads_~tmp~0#1); 3824#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3758#L61 assume !(1 == ~c_dr_pc~0); 3759#L61-2 [2022-12-13 19:16:26,764 INFO L750 eck$LassoCheckResult]: Loop: 3759#L61-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3818#L72 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3800#is_do_read_c_triggered_returnLabel#1 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 3801#L92 assume !(0 != immediate_notify_threads_~tmp___0~0#1); 3816#L92-2 assume { :end_inline_immediate_notify_threads } true;~q_write_ev~0 := 2; 3791#L117-1 assume !false; 3782#L118 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 3783#do_write_p_returnLabel#1 assume { :end_inline_do_write_p } true; 3797#L257 assume 0 == ~c_dr_st~0;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 3755#L276 assume 0 != eval_~tmp___0~1#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 3756#L149 assume 0 == ~c_dr_pc~0; 3785#L182-1 assume !false; 3762#L161 assume !(1 == ~q_free~0); 3763#L162-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_read_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3817#L42-3 assume 1 == ~p_dw_pc~0; 3807#L43-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 3806#L53-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3837#is_do_write_p_triggered_returnLabel#2 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 3748#L84-3 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 3749#L84-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3812#L61-3 assume !(1 == ~c_dr_pc~0); 3833#L61-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 3898#L72-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3899#is_do_read_c_triggered_returnLabel#2 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 3811#L92-3 assume !(0 != immediate_notify_threads_~tmp___0~0#1); 3795#L92-5 assume { :end_inline_immediate_notify_threads } true;~q_read_ev~0 := 2; 3796#L182 assume ~p_last_write~0 == ~c_last_read~0; 3789#L183 assume ~p_num_write~0 == ~c_num_read~0; 3790#L182-1 assume !false; 3861#L161 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 3859#do_read_c_returnLabel#1 assume { :end_inline_do_read_c } true; 3857#L272 assume !false; 3856#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3854#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3853#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3852#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 3851#L252 assume 0 != eval_~tmp___1~0#1; 3850#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 3848#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 3847#L106 assume !(0 == ~p_dw_pc~0); 3813#L109 assume 1 == ~p_dw_pc~0; 3814#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3849#L42 assume 1 == ~p_dw_pc~0; 3831#L43 assume !(1 == ~q_read_ev~0); 3832#L42-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3802#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3793#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 3794#L84 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 3787#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3788#L61 assume !(1 == ~c_dr_pc~0); 3759#L61-2 [2022-12-13 19:16:26,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,764 INFO L85 PathProgramCache]: Analyzing trace with hash 562308425, now seen corresponding path program 4 times [2022-12-13 19:16:26,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,765 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914039900] [2022-12-13 19:16:26,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,772 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:26,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,780 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:16:26,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,780 INFO L85 PathProgramCache]: Analyzing trace with hash 2053233644, now seen corresponding path program 1 times [2022-12-13 19:16:26,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,781 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487833801] [2022-12-13 19:16:26,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:26,819 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-13 19:16:26,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:26,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487833801] [2022-12-13 19:16:26,820 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487833801] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:26,820 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:26,820 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:16:26,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934298661] [2022-12-13 19:16:26,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:26,820 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:26,820 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:26,821 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:16:26,821 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:16:26,821 INFO L87 Difference]: Start difference. First operand 197 states and 233 transitions. cyclomatic complexity: 37 Second operand has 5 states, 5 states have (on average 9.8) internal successors, (49), 5 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:26,850 INFO L93 Difference]: Finished difference Result 249 states and 292 transitions. [2022-12-13 19:16:26,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 249 states and 292 transitions. [2022-12-13 19:16:26,851 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 222 [2022-12-13 19:16:26,852 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 249 states to 249 states and 292 transitions. [2022-12-13 19:16:26,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 249 [2022-12-13 19:16:26,853 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 249 [2022-12-13 19:16:26,853 INFO L73 IsDeterministic]: Start isDeterministic. Operand 249 states and 292 transitions. [2022-12-13 19:16:26,853 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:26,853 INFO L218 hiAutomatonCegarLoop]: Abstraction has 249 states and 292 transitions. [2022-12-13 19:16:26,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states and 292 transitions. [2022-12-13 19:16:26,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 203. [2022-12-13 19:16:26,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 203 states, 203 states have (on average 1.167487684729064) internal successors, (237), 202 states have internal predecessors, (237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 237 transitions. [2022-12-13 19:16:26,857 INFO L240 hiAutomatonCegarLoop]: Abstraction has 203 states and 237 transitions. [2022-12-13 19:16:26,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 19:16:26,858 INFO L428 stractBuchiCegarLoop]: Abstraction has 203 states and 237 transitions. [2022-12-13 19:16:26,858 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 19:16:26,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 203 states and 237 transitions. [2022-12-13 19:16:26,859 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 176 [2022-12-13 19:16:26,860 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:26,860 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:26,860 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,860 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,860 INFO L748 eck$LassoCheckResult]: Stem: 4252#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 4253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4268#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 4262#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 4212#L206-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 4213#L211-1 assume { :end_inline_init_threads } true; 4269#L323-2 assume !false; 4323#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 4320#L272 assume !false; 4317#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4313#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4310#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4308#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 4305#L252 assume 0 != eval_~tmp___1~0#1; 4302#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 4296#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 4277#L106 assume 0 == ~p_dw_pc~0; 4278#L117-1 assume !false; 4354#L118 assume !(0 == ~q_free~0); 4284#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4285#L42 assume !(1 == ~p_dw_pc~0); 4289#L42-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 4294#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4246#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 4247#L84 assume !(0 != immediate_notify_threads_~tmp~0#1); 4241#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4217#L61 assume !(1 == ~c_dr_pc~0); 4218#L61-2 [2022-12-13 19:16:26,861 INFO L750 eck$LassoCheckResult]: Loop: 4218#L61-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 4276#L72 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4256#is_do_read_c_triggered_returnLabel#1 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 4257#L92 assume !(0 != immediate_notify_threads_~tmp___0~0#1); 4273#L92-2 assume { :end_inline_immediate_notify_threads } true;~q_write_ev~0 := 2; 4242#L117-1 assume !false; 4237#L118 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 4238#do_write_p_returnLabel#1 assume { :end_inline_do_write_p } true; 4319#L257 assume 0 == ~c_dr_st~0;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 4315#L276 assume 0 != eval_~tmp___0~1#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 4312#L149 assume 0 == ~c_dr_pc~0; 4255#L182-1 assume !false; 4356#L161 assume !(1 == ~q_free~0); 4355#L162-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_read_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4235#L42-3 assume 1 == ~p_dw_pc~0; 4236#L43-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 4265#L53-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4351#is_do_write_p_triggered_returnLabel#2 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 4349#L84-3 assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0; 4346#L84-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4341#L61-3 assume !(1 == ~c_dr_pc~0); 4339#L61-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 4338#L72-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4337#is_do_read_c_triggered_returnLabel#2 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 4335#L92-3 assume !(0 != immediate_notify_threads_~tmp___0~0#1); 4333#L92-5 assume { :end_inline_immediate_notify_threads } true;~q_read_ev~0 := 2; 4330#L182 assume ~p_last_write~0 == ~c_last_read~0; 4328#L183 assume ~p_num_write~0 == ~c_num_read~0; 4326#L182-1 assume !false; 4324#L161 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 4321#do_read_c_returnLabel#1 assume { :end_inline_do_read_c } true; 4318#L272 assume !false; 4314#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4311#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4309#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4306#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 4303#L252 assume 0 != eval_~tmp___1~0#1; 4300#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 4298#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 4297#L106 assume !(0 == ~p_dw_pc~0); 4271#L109 assume 1 == ~p_dw_pc~0; 4272#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4299#L42 assume 1 == ~p_dw_pc~0; 4286#L43 assume !(1 == ~q_read_ev~0); 4287#L42-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 4258#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4259#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 4307#L84 assume !(0 != immediate_notify_threads_~tmp~0#1); 4304#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4301#L61 assume !(1 == ~c_dr_pc~0); 4218#L61-2 [2022-12-13 19:16:26,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,861 INFO L85 PathProgramCache]: Analyzing trace with hash 562308425, now seen corresponding path program 5 times [2022-12-13 19:16:26,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,861 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061642119] [2022-12-13 19:16:26,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,868 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:26,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,875 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:16:26,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,875 INFO L85 PathProgramCache]: Analyzing trace with hash 2053235566, now seen corresponding path program 1 times [2022-12-13 19:16:26,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,876 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800995005] [2022-12-13 19:16:26,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:26,899 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-13 19:16:26,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:26,899 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800995005] [2022-12-13 19:16:26,900 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800995005] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:26,900 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:26,900 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:16:26,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988982018] [2022-12-13 19:16:26,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:26,900 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:26,900 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:26,901 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:16:26,901 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:16:26,901 INFO L87 Difference]: Start difference. First operand 203 states and 237 transitions. cyclomatic complexity: 35 Second operand has 3 states, 2 states have (on average 24.5) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:26,915 INFO L93 Difference]: Finished difference Result 221 states and 250 transitions. [2022-12-13 19:16:26,915 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 221 states and 250 transitions. [2022-12-13 19:16:26,916 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 150 [2022-12-13 19:16:26,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 221 states to 221 states and 250 transitions. [2022-12-13 19:16:26,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 221 [2022-12-13 19:16:26,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 221 [2022-12-13 19:16:26,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 221 states and 250 transitions. [2022-12-13 19:16:26,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:26,918 INFO L218 hiAutomatonCegarLoop]: Abstraction has 221 states and 250 transitions. [2022-12-13 19:16:26,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states and 250 transitions. [2022-12-13 19:16:26,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 177. [2022-12-13 19:16:26,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 177 states, 177 states have (on average 1.1299435028248588) internal successors, (200), 176 states have internal predecessors, (200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 200 transitions. [2022-12-13 19:16:26,922 INFO L240 hiAutomatonCegarLoop]: Abstraction has 177 states and 200 transitions. [2022-12-13 19:16:26,922 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:16:26,922 INFO L428 stractBuchiCegarLoop]: Abstraction has 177 states and 200 transitions. [2022-12-13 19:16:26,923 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 19:16:26,923 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 177 states and 200 transitions. [2022-12-13 19:16:26,923 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 124 [2022-12-13 19:16:26,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:26,924 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:26,924 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,924 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,924 INFO L748 eck$LassoCheckResult]: Stem: 4685#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 4686#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4699#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 4692#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 4638#L206-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 4639#L211-1 assume { :end_inline_init_threads } true; 4700#L323-2 assume !false; 4755#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 4754#L272 assume !false; 4753#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4752#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4749#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4746#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 4744#L252 assume 0 != eval_~tmp___1~0#1; 4741#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 4734#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 4710#L106 assume 0 == ~p_dw_pc~0; 4711#L117-1 assume !false; 4761#L118 assume !(0 == ~q_free~0); 4718#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4719#L42 assume !(1 == ~p_dw_pc~0); 4724#L42-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 4690#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4681#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 4682#L84 assume !(0 != immediate_notify_threads_~tmp~0#1); 4743#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4647#L61 assume !(1 == ~c_dr_pc~0); 4648#L61-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 4707#L72 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4769#is_do_read_c_triggered_returnLabel#1 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 4705#L92 assume !(0 != immediate_notify_threads_~tmp___0~0#1); 4706#L92-2 assume { :end_inline_immediate_notify_threads } true;~q_write_ev~0 := 2; 4679#L117-1 assume !false; 4669#L118 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 4670#do_write_p_returnLabel#1 assume { :end_inline_do_write_p } true; 4687#L257 [2022-12-13 19:16:26,925 INFO L750 eck$LassoCheckResult]: Loop: 4687#L257 assume !(0 == ~c_dr_st~0); 4646#L272 assume !false; 4801#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4800#L224 assume !(0 == ~p_dw_st~0); 4798#L228 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4796#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4797#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 4716#L252 assume 0 != eval_~tmp___1~0#1; 4691#L252-1 assume !(0 == ~p_dw_st~0); 4687#L257 [2022-12-13 19:16:26,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,925 INFO L85 PathProgramCache]: Analyzing trace with hash -567716911, now seen corresponding path program 1 times [2022-12-13 19:16:26,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901949535] [2022-12-13 19:16:26,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,932 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:26,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,940 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:16:26,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,940 INFO L85 PathProgramCache]: Analyzing trace with hash 718963476, now seen corresponding path program 1 times [2022-12-13 19:16:26,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,941 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452451700] [2022-12-13 19:16:26,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:16:26,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:16:26,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:16:26,949 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452451700] [2022-12-13 19:16:26,949 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [452451700] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:16:26,949 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:16:26,949 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:16:26,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [274634327] [2022-12-13 19:16:26,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:16:26,950 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:16:26,950 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:16:26,950 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:16:26,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:16:26,950 INFO L87 Difference]: Start difference. First operand 177 states and 200 transitions. cyclomatic complexity: 25 Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 2 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:16:26,964 INFO L93 Difference]: Finished difference Result 203 states and 224 transitions. [2022-12-13 19:16:26,964 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 203 states and 224 transitions. [2022-12-13 19:16:26,965 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 117 [2022-12-13 19:16:26,966 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 203 states to 203 states and 224 transitions. [2022-12-13 19:16:26,967 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 203 [2022-12-13 19:16:26,967 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 203 [2022-12-13 19:16:26,967 INFO L73 IsDeterministic]: Start isDeterministic. Operand 203 states and 224 transitions. [2022-12-13 19:16:26,967 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:16:26,967 INFO L218 hiAutomatonCegarLoop]: Abstraction has 203 states and 224 transitions. [2022-12-13 19:16:26,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203 states and 224 transitions. [2022-12-13 19:16:26,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203 to 173. [2022-12-13 19:16:26,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 173 states, 173 states have (on average 1.1098265895953756) internal successors, (192), 172 states have internal predecessors, (192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:16:26,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 192 transitions. [2022-12-13 19:16:26,971 INFO L240 hiAutomatonCegarLoop]: Abstraction has 173 states and 192 transitions. [2022-12-13 19:16:26,971 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:16:26,972 INFO L428 stractBuchiCegarLoop]: Abstraction has 173 states and 192 transitions. [2022-12-13 19:16:26,972 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 19:16:26,972 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 173 states and 192 transitions. [2022-12-13 19:16:26,973 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 92 [2022-12-13 19:16:26,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:16:26,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:16:26,973 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,973 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:16:26,974 INFO L748 eck$LassoCheckResult]: Stem: 5068#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 5069#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 5081#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true; 5074#L206 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5024#L206-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 5025#L211-1 assume { :end_inline_init_threads } true; 5082#L323-2 assume !false; 5146#L324 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1; 5144#L272 assume !false; 5142#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5139#L224 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5135#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5131#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 5127#L252 assume 0 != eval_~tmp___1~0#1; 5123#L252-1 assume 0 == ~p_dw_st~0;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 5109#L261 assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 5089#L106 assume 0 == ~p_dw_pc~0; 5090#L117-1 assume !false; 5163#L118 assume !(0 == ~q_free~0); 5161#L119 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5101#L42 assume !(1 == ~p_dw_pc~0); 5102#L42-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 5073#L53 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5063#is_do_write_p_triggered_returnLabel#1 immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1; 5064#L84 assume !(0 != immediate_notify_threads_~tmp~0#1); 5059#L84-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5033#L61 assume !(1 == ~c_dr_pc~0); 5034#L61-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 5088#L72 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5158#is_do_read_c_triggered_returnLabel#1 immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1; 5156#L92 assume !(0 != immediate_notify_threads_~tmp___0~0#1); 5154#L92-2 assume { :end_inline_immediate_notify_threads } true;~q_write_ev~0 := 2; 5152#L117-1 assume !false; 5150#L118 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 5148#do_write_p_returnLabel#1 assume { :end_inline_do_write_p } true; 5147#L257 [2022-12-13 19:16:26,974 INFO L750 eck$LassoCheckResult]: Loop: 5147#L257 assume 0 == ~c_dr_st~0;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 5030#L276 assume !(0 != eval_~tmp___0~1#1); 5032#L272 assume !false; 5160#L248 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5159#L224 assume !(0 == ~p_dw_st~0); 5157#L228 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5155#L236 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5153#exists_runnable_thread_returnLabel#1 eval_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1; 5151#L252 assume 0 != eval_~tmp___1~0#1; 5149#L252-1 assume !(0 == ~p_dw_st~0); 5147#L257 [2022-12-13 19:16:26,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,974 INFO L85 PathProgramCache]: Analyzing trace with hash -567716911, now seen corresponding path program 2 times [2022-12-13 19:16:26,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798385730] [2022-12-13 19:16:26,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,981 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:26,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,989 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:16:26,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,990 INFO L85 PathProgramCache]: Analyzing trace with hash -934954508, now seen corresponding path program 1 times [2022-12-13 19:16:26,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,990 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [93395467] [2022-12-13 19:16:26,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:26,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,993 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:26,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:26,996 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:16:26,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:16:26,996 INFO L85 PathProgramCache]: Analyzing trace with hash -420181564, now seen corresponding path program 1 times [2022-12-13 19:16:26,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:16:26,997 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997392254] [2022-12-13 19:16:26,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:16:26,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:16:27,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:27,005 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:27,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:27,014 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:16:27,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:27,685 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:16:27,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:16:27,753 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 07:16:27 BoogieIcfgContainer [2022-12-13 19:16:27,753 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 19:16:27,753 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 19:16:27,753 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 19:16:27,754 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 19:16:27,754 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:16:25" (3/4) ... [2022-12-13 19:16:27,756 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 19:16:27,795 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 19:16:27,795 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 19:16:27,795 INFO L158 Benchmark]: Toolchain (without parser) took 3005.52ms. Allocated memory was 138.4MB in the beginning and 167.8MB in the end (delta: 29.4MB). Free memory was 103.5MB in the beginning and 79.9MB in the end (delta: 23.6MB). Peak memory consumption was 55.2MB. Max. memory is 16.1GB. [2022-12-13 19:16:27,796 INFO L158 Benchmark]: CDTParser took 0.13ms. Allocated memory is still 138.4MB. Free memory is still 81.0MB. There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 19:16:27,796 INFO L158 Benchmark]: CACSL2BoogieTranslator took 172.59ms. Allocated memory is still 138.4MB. Free memory was 102.9MB in the beginning and 91.0MB in the end (delta: 11.9MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-12-13 19:16:27,796 INFO L158 Benchmark]: Boogie Procedure Inliner took 25.69ms. Allocated memory is still 138.4MB. Free memory was 91.0MB in the beginning and 88.9MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-12-13 19:16:27,797 INFO L158 Benchmark]: Boogie Preprocessor took 16.58ms. Allocated memory is still 138.4MB. Free memory was 88.9MB in the beginning and 87.4MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-12-13 19:16:27,797 INFO L158 Benchmark]: RCFGBuilder took 302.26ms. Allocated memory is still 138.4MB. Free memory was 87.4MB in the beginning and 72.1MB in the end (delta: 15.2MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2022-12-13 19:16:27,797 INFO L158 Benchmark]: BuchiAutomizer took 2443.12ms. Allocated memory was 138.4MB in the beginning and 167.8MB in the end (delta: 29.4MB). Free memory was 71.5MB in the beginning and 84.1MB in the end (delta: -12.5MB). Peak memory consumption was 19.6MB. Max. memory is 16.1GB. [2022-12-13 19:16:27,797 INFO L158 Benchmark]: Witness Printer took 41.66ms. Allocated memory is still 167.8MB. Free memory was 84.1MB in the beginning and 79.9MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 19:16:27,799 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13ms. Allocated memory is still 138.4MB. Free memory is still 81.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 172.59ms. Allocated memory is still 138.4MB. Free memory was 102.9MB in the beginning and 91.0MB in the end (delta: 11.9MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 25.69ms. Allocated memory is still 138.4MB. Free memory was 91.0MB in the beginning and 88.9MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 16.58ms. Allocated memory is still 138.4MB. Free memory was 88.9MB in the beginning and 87.4MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 302.26ms. Allocated memory is still 138.4MB. Free memory was 87.4MB in the beginning and 72.1MB in the end (delta: 15.2MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 2443.12ms. Allocated memory was 138.4MB in the beginning and 167.8MB in the end (delta: 29.4MB). Free memory was 71.5MB in the beginning and 84.1MB in the end (delta: -12.5MB). Peak memory consumption was 19.6MB. Max. memory is 16.1GB. * Witness Printer took 41.66ms. Allocated memory is still 167.8MB. Free memory was 84.1MB in the beginning and 79.9MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 14 terminating modules (14 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.14 modules have a trivial ranking function, the largest among these consists of 7 locations. The remainder module has 173 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.3s and 15 iterations. TraceHistogramMax:2. Analysis of lassos took 1.6s. Construction of modules took 0.2s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 14. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 14 MinimizatonAttempts, 585 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1878 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1878 mSDsluCounter, 3578 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1901 mSDsCounter, 76 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 276 IncrementalHoareTripleChecker+Invalid, 352 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 76 mSolverCounterUnsat, 1677 mSDtfsCounter, 276 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI10 SFLT0 conc0 concLT0 SILN0 SILU0 SILI4 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 272]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int q_buf_0 ; [L25] int q_free ; [L26] int q_read_ev ; [L27] int q_write_ev ; [L28] int p_num_write ; [L29] int p_last_write ; [L30] int p_dw_st ; [L31] int p_dw_pc ; [L32] int p_dw_i ; [L33] int c_num_read ; [L34] int c_last_read ; [L35] int c_dr_st ; [L36] int c_dr_pc ; [L37] int c_dr_i ; [L144] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=0, q_read_ev=0, q_write_ev=0] [L360] int __retres1 ; [L364] CALL init_model() [L346] q_free = 1 [L347] q_write_ev = 2 [L348] q_read_ev = q_write_ev [L349] p_num_write = 0 [L350] p_dw_pc = 0 [L351] p_dw_i = 1 [L352] c_num_read = 0 [L353] c_dr_pc = 0 [L354] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L364] RET init_model() [L365] CALL start_simulation() [L314] int kernel_st ; [L315] int tmp ; [L319] kernel_st = 0 [L320] CALL init_threads() [L206] COND TRUE (int )p_dw_i == 1 [L207] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L211] COND TRUE (int )c_dr_i == 1 [L212] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L320] RET init_threads() [L323] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L326] kernel_st = 1 [L327] CALL eval() [L241] int tmp ; [L242] int tmp___0 ; [L243] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L247] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L250] CALL, EXPR exists_runnable_thread() [L221] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L224] COND TRUE (int )p_dw_st == 0 [L225] __retres1 = 1 VAL [__retres1=1, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L237] return (__retres1); VAL [\result=1, __retres1=1, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L250] RET, EXPR exists_runnable_thread() [L250] tmp___1 = exists_runnable_thread() [L252] COND TRUE \read(tmp___1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2, tmp___1=1] [L257] COND TRUE (int )p_dw_st == 0 [L259] tmp = __VERIFIER_nondet_int() [L261] COND TRUE \read(tmp) [L263] p_dw_st = 1 [L264] CALL do_write_p() [L106] COND TRUE (int )p_dw_pc == 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L117] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L119] COND FALSE !((int )q_free == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L129] q_buf_0 = __VERIFIER_nondet_int() [L130] p_last_write = q_buf_0 [L131] p_num_write += 1 [L132] q_free = 0 [L133] q_write_ev = 1 [L134] CALL immediate_notify_threads() [L77] int tmp ; [L78] int tmp___0 ; [L82] CALL, EXPR is_do_write_p_triggered() [L39] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L42] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L52] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L54] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L82] RET, EXPR is_do_write_p_triggered() [L82] tmp = is_do_write_p_triggered() [L84] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1, tmp=0] [L90] CALL, EXPR is_do_read_c_triggered() [L58] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L61] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L71] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L73] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L90] RET, EXPR is_do_read_c_triggered() [L90] tmp___0 = is_do_read_c_triggered() [L92] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1, tmp=0, tmp___0=0] [L134] RET immediate_notify_threads() [L135] q_write_ev = 2 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=2] [L117] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=2] [L119] COND TRUE (int )q_free == 0 [L120] p_dw_st = 2 [L121] p_dw_pc = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=1, p_dw_st=2, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=2] [L264] RET do_write_p() Loop: [L272] COND TRUE (int )c_dr_st == 0 [L274] tmp___0 = __VERIFIER_nondet_int() [L276] COND FALSE !(\read(tmp___0)) [L247] COND TRUE 1 [L250] CALL, EXPR exists_runnable_thread() [L221] int __retres1 ; [L224] COND FALSE !((int )p_dw_st == 0) [L228] COND TRUE (int )c_dr_st == 0 [L229] __retres1 = 1 [L237] return (__retres1); [L250] RET, EXPR exists_runnable_thread() [L250] tmp___1 = exists_runnable_thread() [L252] COND TRUE \read(tmp___1) [L257] COND FALSE !((int )p_dw_st == 0) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 272]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int q_buf_0 ; [L25] int q_free ; [L26] int q_read_ev ; [L27] int q_write_ev ; [L28] int p_num_write ; [L29] int p_last_write ; [L30] int p_dw_st ; [L31] int p_dw_pc ; [L32] int p_dw_i ; [L33] int c_num_read ; [L34] int c_last_read ; [L35] int c_dr_st ; [L36] int c_dr_pc ; [L37] int c_dr_i ; [L144] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=0, q_read_ev=0, q_write_ev=0] [L360] int __retres1 ; [L364] CALL init_model() [L346] q_free = 1 [L347] q_write_ev = 2 [L348] q_read_ev = q_write_ev [L349] p_num_write = 0 [L350] p_dw_pc = 0 [L351] p_dw_i = 1 [L352] c_num_read = 0 [L353] c_dr_pc = 0 [L354] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L364] RET init_model() [L365] CALL start_simulation() [L314] int kernel_st ; [L315] int tmp ; [L319] kernel_st = 0 [L320] CALL init_threads() [L206] COND TRUE (int )p_dw_i == 1 [L207] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L211] COND TRUE (int )c_dr_i == 1 [L212] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L320] RET init_threads() [L323] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L326] kernel_st = 1 [L327] CALL eval() [L241] int tmp ; [L242] int tmp___0 ; [L243] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L247] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L250] CALL, EXPR exists_runnable_thread() [L221] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L224] COND TRUE (int )p_dw_st == 0 [L225] __retres1 = 1 VAL [__retres1=1, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L237] return (__retres1); VAL [\result=1, __retres1=1, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L250] RET, EXPR exists_runnable_thread() [L250] tmp___1 = exists_runnable_thread() [L252] COND TRUE \read(tmp___1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2, tmp___1=1] [L257] COND TRUE (int )p_dw_st == 0 [L259] tmp = __VERIFIER_nondet_int() [L261] COND TRUE \read(tmp) [L263] p_dw_st = 1 [L264] CALL do_write_p() [L106] COND TRUE (int )p_dw_pc == 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L117] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L119] COND FALSE !((int )q_free == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=0, p_num_write=0, q_buf_0=0, q_free=1, q_read_ev=2, q_write_ev=2] [L129] q_buf_0 = __VERIFIER_nondet_int() [L130] p_last_write = q_buf_0 [L131] p_num_write += 1 [L132] q_free = 0 [L133] q_write_ev = 1 [L134] CALL immediate_notify_threads() [L77] int tmp ; [L78] int tmp___0 ; [L82] CALL, EXPR is_do_write_p_triggered() [L39] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L42] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L52] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L54] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L82] RET, EXPR is_do_write_p_triggered() [L82] tmp = is_do_write_p_triggered() [L84] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1, tmp=0] [L90] CALL, EXPR is_do_read_c_triggered() [L58] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L61] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L71] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L73] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1] [L90] RET, EXPR is_do_read_c_triggered() [L90] tmp___0 = is_do_read_c_triggered() [L92] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=1, tmp=0, tmp___0=0] [L134] RET immediate_notify_threads() [L135] q_write_ev = 2 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=2] [L117] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=2] [L119] COND TRUE (int )q_free == 0 [L120] p_dw_st = 2 [L121] p_dw_pc = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=1, p_dw_st=2, p_last_write=5, p_num_write=1, q_buf_0=5, q_free=0, q_read_ev=2, q_write_ev=2] [L264] RET do_write_p() Loop: [L272] COND TRUE (int )c_dr_st == 0 [L274] tmp___0 = __VERIFIER_nondet_int() [L276] COND FALSE !(\read(tmp___0)) [L247] COND TRUE 1 [L250] CALL, EXPR exists_runnable_thread() [L221] int __retres1 ; [L224] COND FALSE !((int )p_dw_st == 0) [L228] COND TRUE (int )c_dr_st == 0 [L229] __retres1 = 1 [L237] return (__retres1); [L250] RET, EXPR exists_runnable_thread() [L250] tmp___1 = exists_runnable_thread() [L252] COND TRUE \read(tmp___1) [L257] COND FALSE !((int )p_dw_st == 0) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 19:16:27,852 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f9eaa7ee-65fc-4ea6-a420-6209c243c60b/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)