./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 20:43:25,316 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 20:43:25,317 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 20:43:25,335 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 20:43:25,335 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 20:43:25,336 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 20:43:25,337 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 20:43:25,339 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 20:43:25,341 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 20:43:25,341 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 20:43:25,342 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 20:43:25,344 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 20:43:25,344 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 20:43:25,345 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 20:43:25,346 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 20:43:25,347 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 20:43:25,348 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 20:43:25,349 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 20:43:25,350 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 20:43:25,352 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 20:43:25,353 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 20:43:25,355 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 20:43:25,356 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 20:43:25,357 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 20:43:25,360 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 20:43:25,360 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 20:43:25,361 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 20:43:25,362 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 20:43:25,362 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 20:43:25,363 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 20:43:25,363 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 20:43:25,364 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 20:43:25,365 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 20:43:25,365 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 20:43:25,366 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 20:43:25,367 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 20:43:25,367 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 20:43:25,367 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 20:43:25,368 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 20:43:25,368 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 20:43:25,369 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 20:43:25,370 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 20:43:25,391 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 20:43:25,391 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 20:43:25,391 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 20:43:25,391 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 20:43:25,393 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 20:43:25,393 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 20:43:25,393 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 20:43:25,393 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 20:43:25,393 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 20:43:25,393 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 20:43:25,394 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 20:43:25,394 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 20:43:25,394 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 20:43:25,394 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 20:43:25,394 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 20:43:25,394 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 20:43:25,394 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 20:43:25,395 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 20:43:25,395 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 20:43:25,395 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 20:43:25,395 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 20:43:25,395 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 20:43:25,395 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 20:43:25,396 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 20:43:25,396 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 20:43:25,396 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 20:43:25,396 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 20:43:25,396 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 20:43:25,396 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 20:43:25,397 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 20:43:25,397 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 20:43:25,398 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 20:43:25,398 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f [2022-12-13 20:43:25,584 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 20:43:25,600 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 20:43:25,603 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 20:43:25,604 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 20:43:25,604 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 20:43:25,606 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2022-12-13 20:43:28,158 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 20:43:28,328 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 20:43:28,329 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2022-12-13 20:43:28,336 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/data/49a00fd8e/1ea9033fcfbe4d3b958c42167aef9b17/FLAGbe69100d3 [2022-12-13 20:43:28,735 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/data/49a00fd8e/1ea9033fcfbe4d3b958c42167aef9b17 [2022-12-13 20:43:28,737 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 20:43:28,738 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 20:43:28,739 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 20:43:28,739 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 20:43:28,742 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 20:43:28,742 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 08:43:28" (1/1) ... [2022-12-13 20:43:28,743 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@10ab950f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28, skipping insertion in model container [2022-12-13 20:43:28,743 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 08:43:28" (1/1) ... [2022-12-13 20:43:28,748 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 20:43:28,765 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 20:43:28,853 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c[643,656] [2022-12-13 20:43:28,880 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 20:43:28,889 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 20:43:28,897 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c[643,656] [2022-12-13 20:43:28,911 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 20:43:28,921 INFO L208 MainTranslator]: Completed translation [2022-12-13 20:43:28,921 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28 WrapperNode [2022-12-13 20:43:28,921 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 20:43:28,922 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 20:43:28,922 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 20:43:28,922 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 20:43:28,927 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28" (1/1) ... [2022-12-13 20:43:28,932 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28" (1/1) ... [2022-12-13 20:43:28,948 INFO L138 Inliner]: procedures = 29, calls = 31, calls flagged for inlining = 26, calls inlined = 27, statements flattened = 303 [2022-12-13 20:43:28,948 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 20:43:28,949 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 20:43:28,949 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 20:43:28,949 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 20:43:28,957 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28" (1/1) ... [2022-12-13 20:43:28,957 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28" (1/1) ... [2022-12-13 20:43:28,958 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28" (1/1) ... [2022-12-13 20:43:28,958 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28" (1/1) ... [2022-12-13 20:43:28,961 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28" (1/1) ... [2022-12-13 20:43:28,965 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28" (1/1) ... [2022-12-13 20:43:28,966 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28" (1/1) ... [2022-12-13 20:43:28,967 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28" (1/1) ... [2022-12-13 20:43:28,969 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 20:43:28,969 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 20:43:28,969 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 20:43:28,969 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 20:43:28,970 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28" (1/1) ... [2022-12-13 20:43:28,974 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 20:43:28,983 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 20:43:28,993 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 20:43:28,995 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 20:43:29,029 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 20:43:29,029 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 20:43:29,029 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 20:43:29,029 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 20:43:29,086 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 20:43:29,087 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 20:43:29,340 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 20:43:29,347 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 20:43:29,347 INFO L300 CfgBuilder]: Removed 4 assume(true) statements. [2022-12-13 20:43:29,349 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 08:43:29 BoogieIcfgContainer [2022-12-13 20:43:29,349 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 20:43:29,350 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 20:43:29,350 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 20:43:29,353 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 20:43:29,354 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:43:29,354 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 08:43:28" (1/3) ... [2022-12-13 20:43:29,355 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@25c8b096 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 08:43:29, skipping insertion in model container [2022-12-13 20:43:29,355 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:43:29,355 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:43:28" (2/3) ... [2022-12-13 20:43:29,355 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@25c8b096 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 08:43:29, skipping insertion in model container [2022-12-13 20:43:29,355 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:43:29,355 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 08:43:29" (3/3) ... [2022-12-13 20:43:29,356 INFO L332 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-1.c [2022-12-13 20:43:29,405 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 20:43:29,405 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 20:43:29,405 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 20:43:29,405 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 20:43:29,405 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 20:43:29,405 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 20:43:29,405 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 20:43:29,405 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 20:43:29,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:29,424 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2022-12-13 20:43:29,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:43:29,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:43:29,430 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:29,430 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:29,430 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 20:43:29,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:29,434 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2022-12-13 20:43:29,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:43:29,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:43:29,436 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:29,436 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:29,443 INFO L748 eck$LassoCheckResult]: Stem: 19#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 31#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 99#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62#L222true assume !(1 == ~q_req_up~0); 9#L222-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 78#L237true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 32#L237-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 38#L242-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85#L275true assume !(0 == ~q_read_ev~0); 91#L275-2true assume !(0 == ~q_write_ev~0); 23#L280-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 104#L65true assume !(1 == ~p_dw_pc~0); 30#L65-2true is_do_write_p_triggered_~__retres1~0#1 := 0; 54#L76true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 72#is_do_write_p_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 35#L315true assume !(0 != activate_threads_~tmp~1#1); 60#L315-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 94#L84true assume 1 == ~c_dr_pc~0; 25#L85true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 66#L95true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 21#is_do_read_c_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4#L323true assume !(0 != activate_threads_~tmp___0~1#1); 45#L323-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95#L293true assume !(1 == ~q_read_ev~0); 2#L293-2true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 36#L298-1true assume { :end_inline_reset_delta_events } true; 11#L419-2true [2022-12-13 20:43:29,444 INFO L750 eck$LassoCheckResult]: Loop: 11#L419-2true assume !false; 27#L420true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 100#L364true assume false; 63#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81#L222-3true assume !(1 == ~q_req_up~0); 33#L222-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77#L275-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 39#L275-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 52#L280-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 59#L65-3true assume !(1 == ~p_dw_pc~0); 17#L65-5true is_do_write_p_triggered_~__retres1~0#1 := 0; 92#L76-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 53#is_do_write_p_triggered_returnLabel#2true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 40#L315-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 82#L315-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 57#L84-3true assume 1 == ~c_dr_pc~0; 42#L85-1true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 76#L95-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 29#is_do_read_c_triggered_returnLabel#2true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 102#L323-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 75#L323-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89#L293-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 5#L293-5true assume !(1 == ~q_write_ev~0); 51#L298-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24#L255-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 73#exists_runnable_thread_returnLabel#2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 13#L394true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 7#L401true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 101#stop_simulation_returnLabel#1true start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 28#L436true assume !(0 != start_simulation_~tmp~4#1); 11#L419-2true [2022-12-13 20:43:29,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:29,448 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2022-12-13 20:43:29,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:29,455 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809172721] [2022-12-13 20:43:29,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:29,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:29,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:29,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:29,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:29,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [809172721] [2022-12-13 20:43:29,614 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [809172721] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:29,614 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:29,615 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:43:29,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1587747901] [2022-12-13 20:43:29,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:29,621 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:43:29,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:29,622 INFO L85 PathProgramCache]: Analyzing trace with hash 774851143, now seen corresponding path program 1 times [2022-12-13 20:43:29,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:29,623 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885937458] [2022-12-13 20:43:29,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:29,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:29,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:29,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:29,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:29,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885937458] [2022-12-13 20:43:29,648 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885937458] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:29,648 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:29,648 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:43:29,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [188714392] [2022-12-13 20:43:29,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:29,650 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:43:29,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:43:29,679 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:43:29,680 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:43:29,681 INFO L87 Difference]: Start difference. First operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:29,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:43:29,700 INFO L93 Difference]: Finished difference Result 101 states and 144 transitions. [2022-12-13 20:43:29,701 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 144 transitions. [2022-12-13 20:43:29,703 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2022-12-13 20:43:29,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 95 states and 138 transitions. [2022-12-13 20:43:29,707 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2022-12-13 20:43:29,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2022-12-13 20:43:29,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 138 transitions. [2022-12-13 20:43:29,708 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:43:29,708 INFO L218 hiAutomatonCegarLoop]: Abstraction has 95 states and 138 transitions. [2022-12-13 20:43:29,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 138 transitions. [2022-12-13 20:43:29,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2022-12-13 20:43:29,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.4526315789473685) internal successors, (138), 94 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:29,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 138 transitions. [2022-12-13 20:43:29,730 INFO L240 hiAutomatonCegarLoop]: Abstraction has 95 states and 138 transitions. [2022-12-13 20:43:29,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:43:29,733 INFO L428 stractBuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2022-12-13 20:43:29,734 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 20:43:29,734 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 138 transitions. [2022-12-13 20:43:29,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2022-12-13 20:43:29,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:43:29,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:43:29,736 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:29,742 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:29,742 INFO L748 eck$LassoCheckResult]: Stem: 270#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 271#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 295#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 248#L222 assume !(1 == ~q_req_up~0); 237#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 238#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 278#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 299#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 297#L275 assume !(0 == ~q_read_ev~0); 298#L275-2 assume !(0 == ~q_write_ev~0); 285#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 286#L65 assume !(1 == ~p_dw_pc~0); 281#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 280#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 265#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 266#L315 assume !(0 != activate_threads_~tmp~1#1); 243#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 244#L84 assume 1 == ~c_dr_pc~0; 290#L85 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 257#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 258#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 220#L323 assume !(0 != activate_threads_~tmp___0~1#1); 221#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 306#L293 assume !(1 == ~q_read_ev~0); 213#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 214#L298-1 assume { :end_inline_reset_delta_events } true; 239#L419-2 [2022-12-13 20:43:29,742 INFO L750 eck$LassoCheckResult]: Loop: 239#L419-2 assume !false; 240#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 254#L364 assume !false; 284#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 250#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 216#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 235#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 236#L344 assume !(0 != eval_~tmp___1~0#1); 251#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 252#L222-3 assume !(1 == ~q_req_up~0); 283#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 276#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 277#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 304#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 226#L65-3 assume !(1 == ~p_dw_pc~0); 227#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 261#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 303#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 305#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 293#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 217#L84-3 assume 1 == ~c_dr_pc~0; 218#L85-1 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 274#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 275#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 292#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 272#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 273#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 224#L293-5 assume !(1 == ~q_write_ev~0); 225#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 287#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 288#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 267#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 245#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 231#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 232#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 291#L436 assume !(0 != start_simulation_~tmp~4#1); 239#L419-2 [2022-12-13 20:43:29,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:29,743 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2022-12-13 20:43:29,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:29,744 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254870152] [2022-12-13 20:43:29,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:29,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:29,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:29,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:29,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:29,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254870152] [2022-12-13 20:43:29,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254870152] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:29,845 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:29,845 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-13 20:43:29,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1834004015] [2022-12-13 20:43:29,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:29,846 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:43:29,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:29,847 INFO L85 PathProgramCache]: Analyzing trace with hash -1517218729, now seen corresponding path program 1 times [2022-12-13 20:43:29,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:29,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2068519406] [2022-12-13 20:43:29,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:29,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:29,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:29,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:29,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:29,884 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2068519406] [2022-12-13 20:43:29,885 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2068519406] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:29,885 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:29,885 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:43:29,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300078682] [2022-12-13 20:43:29,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:29,885 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:43:29,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:43:29,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 20:43:29,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 20:43:29,886 INFO L87 Difference]: Start difference. First operand 95 states and 138 transitions. cyclomatic complexity: 44 Second operand has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:29,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:43:29,983 INFO L93 Difference]: Finished difference Result 312 states and 446 transitions. [2022-12-13 20:43:29,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 312 states and 446 transitions. [2022-12-13 20:43:29,987 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 283 [2022-12-13 20:43:29,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 312 states to 312 states and 446 transitions. [2022-12-13 20:43:29,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 312 [2022-12-13 20:43:29,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 312 [2022-12-13 20:43:29,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 312 states and 446 transitions. [2022-12-13 20:43:29,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:43:29,992 INFO L218 hiAutomatonCegarLoop]: Abstraction has 312 states and 446 transitions. [2022-12-13 20:43:29,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states and 446 transitions. [2022-12-13 20:43:30,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 298. [2022-12-13 20:43:30,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 298 states, 298 states have (on average 1.4429530201342282) internal successors, (430), 297 states have internal predecessors, (430), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:30,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 430 transitions. [2022-12-13 20:43:30,009 INFO L240 hiAutomatonCegarLoop]: Abstraction has 298 states and 430 transitions. [2022-12-13 20:43:30,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 20:43:30,010 INFO L428 stractBuchiCegarLoop]: Abstraction has 298 states and 430 transitions. [2022-12-13 20:43:30,010 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 20:43:30,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 298 states and 430 transitions. [2022-12-13 20:43:30,012 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 270 [2022-12-13 20:43:30,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:43:30,013 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:43:30,014 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,014 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,014 INFO L748 eck$LassoCheckResult]: Stem: 690#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 691#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 716#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 665#L222 assume !(1 == ~q_req_up~0); 656#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 657#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 698#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 722#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 718#L275 assume !(0 == ~q_read_ev~0); 719#L275-2 assume !(0 == ~q_write_ev~0); 706#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 707#L65 assume !(1 == ~p_dw_pc~0); 701#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 700#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 684#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 685#L315 assume !(0 != activate_threads_~tmp~1#1); 662#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 663#L84 assume !(1 == ~c_dr_pc~0); 679#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 674#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 675#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 639#L323 assume !(0 != activate_threads_~tmp___0~1#1); 640#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 732#L293 assume !(1 == ~q_read_ev~0); 633#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 634#L298-1 assume { :end_inline_reset_delta_events } true; 728#L419-2 [2022-12-13 20:43:30,014 INFO L750 eck$LassoCheckResult]: Loop: 728#L419-2 assume !false; 815#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 670#L364 assume !false; 814#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 813#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 811#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 810#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 686#L344 assume !(0 != eval_~tmp___1~0#1); 688#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 844#L222-3 assume !(1 == ~q_req_up~0); 843#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 842#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 841#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 840#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 839#L65-3 assume !(1 == ~p_dw_pc~0); 837#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 836#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 835#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 834#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 833#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 832#L84-3 assume !(1 == ~c_dr_pc~0); 831#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 830#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 829#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 828#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 827#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 826#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 825#L293-5 assume !(1 == ~q_write_ev~0); 824#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 822#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 821#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 820#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 819#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 818#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 817#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 816#L436 assume !(0 != start_simulation_~tmp~4#1); 728#L419-2 [2022-12-13 20:43:30,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,015 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2022-12-13 20:43:30,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,015 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1924235158] [2022-12-13 20:43:30,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:30,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:30,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:30,068 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1924235158] [2022-12-13 20:43:30,068 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1924235158] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:30,068 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:30,068 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-13 20:43:30,068 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1986867398] [2022-12-13 20:43:30,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:30,069 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:43:30,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,069 INFO L85 PathProgramCache]: Analyzing trace with hash -340614410, now seen corresponding path program 1 times [2022-12-13 20:43:30,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,070 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [72106117] [2022-12-13 20:43:30,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:30,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:30,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:30,100 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [72106117] [2022-12-13 20:43:30,101 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [72106117] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:30,101 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:30,101 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:43:30,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [588536859] [2022-12-13 20:43:30,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:30,101 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:43:30,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:43:30,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:43:30,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:43:30,102 INFO L87 Difference]: Start difference. First operand 298 states and 430 transitions. cyclomatic complexity: 134 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:30,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:43:30,181 INFO L93 Difference]: Finished difference Result 683 states and 957 transitions. [2022-12-13 20:43:30,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 683 states and 957 transitions. [2022-12-13 20:43:30,186 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2022-12-13 20:43:30,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 683 states to 683 states and 957 transitions. [2022-12-13 20:43:30,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 683 [2022-12-13 20:43:30,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 683 [2022-12-13 20:43:30,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 683 states and 957 transitions. [2022-12-13 20:43:30,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:43:30,195 INFO L218 hiAutomatonCegarLoop]: Abstraction has 683 states and 957 transitions. [2022-12-13 20:43:30,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 683 states and 957 transitions. [2022-12-13 20:43:30,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 683 to 683. [2022-12-13 20:43:30,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 683 states, 683 states have (on average 1.4011713030746706) internal successors, (957), 682 states have internal predecessors, (957), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:30,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 683 states to 683 states and 957 transitions. [2022-12-13 20:43:30,219 INFO L240 hiAutomatonCegarLoop]: Abstraction has 683 states and 957 transitions. [2022-12-13 20:43:30,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:43:30,220 INFO L428 stractBuchiCegarLoop]: Abstraction has 683 states and 957 transitions. [2022-12-13 20:43:30,220 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 20:43:30,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 683 states and 957 transitions. [2022-12-13 20:43:30,224 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2022-12-13 20:43:30,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:43:30,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:43:30,225 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,225 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,225 INFO L748 eck$LassoCheckResult]: Stem: 1682#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1683#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1711#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1657#L222 assume !(1 == ~q_req_up~0); 1648#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1649#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1692#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1718#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1713#L275 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1714#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1728#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1761#L65 assume !(1 == ~p_dw_pc~0); 1759#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 1758#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1757#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1756#L315 assume !(0 != activate_threads_~tmp~1#1); 1755#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1754#L84 assume !(1 == ~c_dr_pc~0); 1753#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1752#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1751#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1750#L323 assume !(0 != activate_threads_~tmp___0~1#1); 1749#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1748#L293 assume !(1 == ~q_read_ev~0); 1746#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1747#L298-1 assume { :end_inline_reset_delta_events } true; 2025#L419-2 [2022-12-13 20:43:30,225 INFO L750 eck$LassoCheckResult]: Loop: 2025#L419-2 assume !false; 2024#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1710#L364 assume !false; 2023#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2022#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2020#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2019#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2017#L344 assume !(0 != eval_~tmp___1~0#1); 2018#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2081#L222-3 assume !(1 == ~q_req_up~0); 2079#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2077#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 2074#L275-5 assume !(0 == ~q_write_ev~0); 2072#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2070#L65-3 assume !(1 == ~p_dw_pc~0); 2067#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 2064#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2062#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2060#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 2057#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2055#L84-3 assume !(1 == ~c_dr_pc~0); 2053#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 2051#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2049#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2047#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2045#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2043#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2035#L293-5 assume !(1 == ~q_write_ev~0); 2034#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2032#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2031#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2030#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2029#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2028#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2027#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2026#L436 assume !(0 != start_simulation_~tmp~4#1); 2025#L419-2 [2022-12-13 20:43:30,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,226 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2022-12-13 20:43:30,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,227 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815866924] [2022-12-13 20:43:30,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:30,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:30,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:30,262 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815866924] [2022-12-13 20:43:30,262 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815866924] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:30,262 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:30,262 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:43:30,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2032889909] [2022-12-13 20:43:30,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:30,263 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:43:30,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,264 INFO L85 PathProgramCache]: Analyzing trace with hash -474627916, now seen corresponding path program 1 times [2022-12-13 20:43:30,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,264 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359699580] [2022-12-13 20:43:30,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:30,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:30,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:30,304 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359699580] [2022-12-13 20:43:30,304 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359699580] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:30,304 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:30,304 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:43:30,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [691526418] [2022-12-13 20:43:30,304 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:30,305 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:43:30,305 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:43:30,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:43:30,305 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:43:30,306 INFO L87 Difference]: Start difference. First operand 683 states and 957 transitions. cyclomatic complexity: 278 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:30,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:43:30,329 INFO L93 Difference]: Finished difference Result 952 states and 1311 transitions. [2022-12-13 20:43:30,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 952 states and 1311 transitions. [2022-12-13 20:43:30,336 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 906 [2022-12-13 20:43:30,340 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 952 states to 952 states and 1311 transitions. [2022-12-13 20:43:30,341 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 952 [2022-12-13 20:43:30,342 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 952 [2022-12-13 20:43:30,342 INFO L73 IsDeterministic]: Start isDeterministic. Operand 952 states and 1311 transitions. [2022-12-13 20:43:30,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:43:30,343 INFO L218 hiAutomatonCegarLoop]: Abstraction has 952 states and 1311 transitions. [2022-12-13 20:43:30,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 952 states and 1311 transitions. [2022-12-13 20:43:30,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 952 to 680. [2022-12-13 20:43:30,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 680 states, 680 states have (on average 1.3794117647058823) internal successors, (938), 679 states have internal predecessors, (938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:30,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 938 transitions. [2022-12-13 20:43:30,370 INFO L240 hiAutomatonCegarLoop]: Abstraction has 680 states and 938 transitions. [2022-12-13 20:43:30,371 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:43:30,371 INFO L428 stractBuchiCegarLoop]: Abstraction has 680 states and 938 transitions. [2022-12-13 20:43:30,371 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 20:43:30,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 680 states and 938 transitions. [2022-12-13 20:43:30,375 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 636 [2022-12-13 20:43:30,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:43:30,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:43:30,376 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,376 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,376 INFO L748 eck$LassoCheckResult]: Stem: 3324#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3325#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3355#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3301#L222 assume !(1 == ~q_req_up~0); 3290#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3291#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3337#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3363#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3360#L275 assume !(0 == ~q_read_ev~0); 3361#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3372#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3392#L65 assume !(1 == ~p_dw_pc~0); 3339#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3390#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3391#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3369#L315 assume !(0 != activate_threads_~tmp~1#1); 3370#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3378#L84 assume !(1 == ~c_dr_pc~0); 3379#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3309#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3310#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3275#L323 assume !(0 != activate_threads_~tmp___0~1#1); 3276#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3380#L293 assume !(1 == ~q_read_ev~0); 3381#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 3270#L298-1 assume { :end_inline_reset_delta_events } true; 3371#L419-2 [2022-12-13 20:43:30,376 INFO L750 eck$LassoCheckResult]: Loop: 3371#L419-2 assume !false; 3431#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3358#L364 assume !false; 3430#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3429#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3427#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3425#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3422#L344 assume !(0 != eval_~tmp___1~0#1); 3423#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3465#L222-3 assume !(1 == ~q_req_up~0); 3463#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3461#L275-3 assume !(0 == ~q_read_ev~0); 3458#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3457#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3455#L65-3 assume !(1 == ~p_dw_pc~0); 3454#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 3453#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3452#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3451#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 3450#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3449#L84-3 assume !(1 == ~c_dr_pc~0); 3448#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 3447#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3446#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3445#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 3444#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3443#L293-3 assume !(1 == ~q_read_ev~0); 3442#L293-5 assume !(1 == ~q_write_ev~0); 3440#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3438#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3437#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3436#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3435#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3434#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3433#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3432#L436 assume !(0 != start_simulation_~tmp~4#1); 3371#L419-2 [2022-12-13 20:43:30,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,377 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2022-12-13 20:43:30,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,377 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622662821] [2022-12-13 20:43:30,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:30,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:30,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:30,410 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [622662821] [2022-12-13 20:43:30,411 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [622662821] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:30,411 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:30,411 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-13 20:43:30,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2022974255] [2022-12-13 20:43:30,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:30,411 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:43:30,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,412 INFO L85 PathProgramCache]: Analyzing trace with hash -593092810, now seen corresponding path program 1 times [2022-12-13 20:43:30,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127753737] [2022-12-13 20:43:30,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:30,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:30,434 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:30,434 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2127753737] [2022-12-13 20:43:30,435 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2127753737] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:30,435 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:30,435 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:43:30,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1546221021] [2022-12-13 20:43:30,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:30,435 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:43:30,436 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:43:30,436 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:43:30,436 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:43:30,436 INFO L87 Difference]: Start difference. First operand 680 states and 938 transitions. cyclomatic complexity: 260 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:30,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:43:30,478 INFO L93 Difference]: Finished difference Result 830 states and 1136 transitions. [2022-12-13 20:43:30,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1136 transitions. [2022-12-13 20:43:30,483 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 802 [2022-12-13 20:43:30,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1136 transitions. [2022-12-13 20:43:30,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-12-13 20:43:30,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-12-13 20:43:30,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1136 transitions. [2022-12-13 20:43:30,489 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:43:30,489 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1136 transitions. [2022-12-13 20:43:30,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1136 transitions. [2022-12-13 20:43:30,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 608. [2022-12-13 20:43:30,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 608 states, 608 states have (on average 1.3717105263157894) internal successors, (834), 607 states have internal predecessors, (834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:30,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 608 states to 608 states and 834 transitions. [2022-12-13 20:43:30,502 INFO L240 hiAutomatonCegarLoop]: Abstraction has 608 states and 834 transitions. [2022-12-13 20:43:30,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-12-13 20:43:30,503 INFO L428 stractBuchiCegarLoop]: Abstraction has 608 states and 834 transitions. [2022-12-13 20:43:30,504 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 20:43:30,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 608 states and 834 transitions. [2022-12-13 20:43:30,507 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 580 [2022-12-13 20:43:30,507 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:43:30,507 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:43:30,507 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,507 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,508 INFO L748 eck$LassoCheckResult]: Stem: 4847#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 4848#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4872#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4822#L222 assume !(1 == ~q_req_up~0); 4813#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4814#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 4855#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 4877#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4874#L275 assume !(0 == ~q_read_ev~0); 4875#L275-2 assume !(0 == ~q_write_ev~0); 4861#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4862#L65 assume !(1 == ~p_dw_pc~0); 4859#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 4868#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4842#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4843#L315 assume !(0 != activate_threads_~tmp~1#1); 4819#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4820#L84 assume !(1 == ~c_dr_pc~0); 4837#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 4831#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4832#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4795#L323 assume !(0 != activate_threads_~tmp___0~1#1); 4796#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4888#L293 assume !(1 == ~q_read_ev~0); 4789#L293-2 assume !(1 == ~q_write_ev~0); 4790#L298-1 assume { :end_inline_reset_delta_events } true; 4883#L419-2 [2022-12-13 20:43:30,508 INFO L750 eck$LassoCheckResult]: Loop: 4883#L419-2 assume !false; 5166#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 4825#L364 assume !false; 5154#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5148#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5143#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5139#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5134#L344 assume !(0 != eval_~tmp___1~0#1); 5135#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5232#L222-3 assume !(1 == ~q_req_up~0); 5231#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5230#L275-3 assume !(0 == ~q_read_ev~0); 5229#L275-5 assume !(0 == ~q_write_ev~0); 5228#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5226#L65-3 assume !(1 == ~p_dw_pc~0); 5225#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 5224#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5223#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5222#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 5221#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5220#L84-3 assume !(1 == ~c_dr_pc~0); 5219#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 5218#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5217#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5216#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5215#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5214#L293-3 assume !(1 == ~q_read_ev~0); 5213#L293-5 assume !(1 == ~q_write_ev~0); 5212#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5210#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5209#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5208#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5188#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5183#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5179#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5174#L436 assume !(0 != start_simulation_~tmp~4#1); 4883#L419-2 [2022-12-13 20:43:30,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,508 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2022-12-13 20:43:30,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,509 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [871095533] [2022-12-13 20:43:30,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:30,516 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:43:30,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:30,542 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:43:30,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,542 INFO L85 PathProgramCache]: Analyzing trace with hash -727106316, now seen corresponding path program 1 times [2022-12-13 20:43:30,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,543 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803528522] [2022-12-13 20:43:30,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:30,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:30,578 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:30,578 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1803528522] [2022-12-13 20:43:30,579 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1803528522] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:30,579 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:30,579 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:43:30,579 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [303911173] [2022-12-13 20:43:30,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:30,579 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:43:30,580 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:43:30,580 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 20:43:30,580 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 20:43:30,580 INFO L87 Difference]: Start difference. First operand 608 states and 834 transitions. cyclomatic complexity: 228 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:30,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:43:30,631 INFO L93 Difference]: Finished difference Result 919 states and 1251 transitions. [2022-12-13 20:43:30,632 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 919 states and 1251 transitions. [2022-12-13 20:43:30,637 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 890 [2022-12-13 20:43:30,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 919 states to 919 states and 1251 transitions. [2022-12-13 20:43:30,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 919 [2022-12-13 20:43:30,642 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 919 [2022-12-13 20:43:30,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 919 states and 1251 transitions. [2022-12-13 20:43:30,644 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:43:30,644 INFO L218 hiAutomatonCegarLoop]: Abstraction has 919 states and 1251 transitions. [2022-12-13 20:43:30,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states and 1251 transitions. [2022-12-13 20:43:30,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 635. [2022-12-13 20:43:30,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 635 states, 635 states have (on average 1.3559055118110237) internal successors, (861), 634 states have internal predecessors, (861), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:30,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 635 states to 635 states and 861 transitions. [2022-12-13 20:43:30,657 INFO L240 hiAutomatonCegarLoop]: Abstraction has 635 states and 861 transitions. [2022-12-13 20:43:30,658 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 20:43:30,658 INFO L428 stractBuchiCegarLoop]: Abstraction has 635 states and 861 transitions. [2022-12-13 20:43:30,658 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 20:43:30,658 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 635 states and 861 transitions. [2022-12-13 20:43:30,661 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 607 [2022-12-13 20:43:30,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:43:30,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:43:30,662 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,662 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,662 INFO L748 eck$LassoCheckResult]: Stem: 6388#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 6389#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6416#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6366#L222 assume !(1 == ~q_req_up~0); 6357#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6358#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 6396#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6422#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6419#L275 assume !(0 == ~q_read_ev~0); 6420#L275-2 assume !(0 == ~q_write_ev~0); 6402#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6403#L65 assume !(1 == ~p_dw_pc~0); 6398#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 6412#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6384#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6385#L315 assume !(0 != activate_threads_~tmp~1#1); 6363#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6364#L84 assume !(1 == ~c_dr_pc~0); 6380#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 6375#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6376#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6339#L323 assume !(0 != activate_threads_~tmp___0~1#1); 6340#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6437#L293 assume !(1 == ~q_read_ev~0); 6332#L293-2 assume !(1 == ~q_write_ev~0); 6333#L298-1 assume { :end_inline_reset_delta_events } true; 6429#L419-2 [2022-12-13 20:43:30,662 INFO L750 eck$LassoCheckResult]: Loop: 6429#L419-2 assume !false; 6851#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6632#L364 assume !false; 6649#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6648#L255 assume !(0 == ~p_dw_st~0); 6647#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6646#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6644#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6641#L344 assume !(0 != eval_~tmp___1~0#1); 6642#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6888#L222-3 assume !(1 == ~q_req_up~0); 6887#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6886#L275-3 assume !(0 == ~q_read_ev~0); 6885#L275-5 assume !(0 == ~q_write_ev~0); 6884#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6882#L65-3 assume !(1 == ~p_dw_pc~0); 6881#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 6880#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6879#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6878#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 6877#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6876#L84-3 assume !(1 == ~c_dr_pc~0); 6875#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 6874#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6873#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6872#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6871#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6870#L293-3 assume !(1 == ~q_read_ev~0); 6869#L293-5 assume !(1 == ~q_write_ev~0); 6868#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6866#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6864#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6862#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6860#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6858#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6856#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6854#L436 assume !(0 != start_simulation_~tmp~4#1); 6429#L419-2 [2022-12-13 20:43:30,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,663 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2022-12-13 20:43:30,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463933938] [2022-12-13 20:43:30,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:30,670 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:43:30,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:30,678 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:43:30,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,679 INFO L85 PathProgramCache]: Analyzing trace with hash -366252558, now seen corresponding path program 1 times [2022-12-13 20:43:30,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,679 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455332834] [2022-12-13 20:43:30,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:30,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:30,739 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:30,739 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455332834] [2022-12-13 20:43:30,739 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [455332834] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:30,739 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:30,739 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:43:30,740 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [527113346] [2022-12-13 20:43:30,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:30,740 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:43:30,740 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:43:30,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 20:43:30,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 20:43:30,741 INFO L87 Difference]: Start difference. First operand 635 states and 861 transitions. cyclomatic complexity: 228 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:30,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:43:30,797 INFO L93 Difference]: Finished difference Result 1521 states and 2071 transitions. [2022-12-13 20:43:30,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1521 states and 2071 transitions. [2022-12-13 20:43:30,807 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1493 [2022-12-13 20:43:30,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1521 states to 1521 states and 2071 transitions. [2022-12-13 20:43:30,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1521 [2022-12-13 20:43:30,817 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1521 [2022-12-13 20:43:30,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1521 states and 2071 transitions. [2022-12-13 20:43:30,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:43:30,819 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1521 states and 2071 transitions. [2022-12-13 20:43:30,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1521 states and 2071 transitions. [2022-12-13 20:43:30,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1521 to 653. [2022-12-13 20:43:30,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 653 states, 653 states have (on average 1.333843797856049) internal successors, (871), 652 states have internal predecessors, (871), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:30,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 653 states to 653 states and 871 transitions. [2022-12-13 20:43:30,840 INFO L240 hiAutomatonCegarLoop]: Abstraction has 653 states and 871 transitions. [2022-12-13 20:43:30,840 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 20:43:30,841 INFO L428 stractBuchiCegarLoop]: Abstraction has 653 states and 871 transitions. [2022-12-13 20:43:30,841 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 20:43:30,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 653 states and 871 transitions. [2022-12-13 20:43:30,844 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 625 [2022-12-13 20:43:30,845 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:43:30,845 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:43:30,845 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,845 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,846 INFO L748 eck$LassoCheckResult]: Stem: 8557#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 8558#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8585#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8535#L222 assume !(1 == ~q_req_up~0); 8524#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8525#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 8568#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8592#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8589#L275 assume !(0 == ~q_read_ev~0); 8590#L275-2 assume !(0 == ~q_write_ev~0); 8573#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8574#L65 assume !(1 == ~p_dw_pc~0); 8572#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 8583#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8555#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8556#L315 assume !(0 != activate_threads_~tmp~1#1); 8532#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8533#L84 assume !(1 == ~c_dr_pc~0); 8551#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 8544#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8545#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8508#L323 assume !(0 != activate_threads_~tmp___0~1#1); 8509#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8604#L293 assume !(1 == ~q_read_ev~0); 8501#L293-2 assume !(1 == ~q_write_ev~0); 8502#L298-1 assume { :end_inline_reset_delta_events } true; 8599#L419-2 [2022-12-13 20:43:30,846 INFO L750 eck$LassoCheckResult]: Loop: 8599#L419-2 assume !false; 8905#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8887#L364 assume !false; 8904#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8903#L255 assume !(0 == ~p_dw_st~0); 8901#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 8902#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8897#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8898#L344 assume !(0 != eval_~tmp___1~0#1); 8935#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8934#L222-3 assume !(1 == ~q_req_up~0); 8933#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8932#L275-3 assume !(0 == ~q_read_ev~0); 8931#L275-5 assume !(0 == ~q_write_ev~0); 8930#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8928#L65-3 assume !(1 == ~p_dw_pc~0); 8927#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 8926#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8925#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8924#L315-3 assume !(0 != activate_threads_~tmp~1#1); 8923#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8922#L84-3 assume !(1 == ~c_dr_pc~0); 8921#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 8920#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8919#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8918#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 8917#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8916#L293-3 assume !(1 == ~q_read_ev~0); 8915#L293-5 assume !(1 == ~q_write_ev~0); 8914#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8912#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8911#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8910#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 8909#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8908#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8907#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8906#L436 assume !(0 != start_simulation_~tmp~4#1); 8599#L419-2 [2022-12-13 20:43:30,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,847 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2022-12-13 20:43:30,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1383405831] [2022-12-13 20:43:30,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:30,855 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:43:30,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:30,864 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:43:30,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,865 INFO L85 PathProgramCache]: Analyzing trace with hash 1934570032, now seen corresponding path program 1 times [2022-12-13 20:43:30,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,865 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [608069280] [2022-12-13 20:43:30,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:30,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:30,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:30,889 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [608069280] [2022-12-13 20:43:30,890 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [608069280] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:30,890 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:30,890 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:43:30,890 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [878267849] [2022-12-13 20:43:30,890 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:30,891 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:43:30,891 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:43:30,891 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:43:30,891 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:43:30,891 INFO L87 Difference]: Start difference. First operand 653 states and 871 transitions. cyclomatic complexity: 220 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:30,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:43:30,914 INFO L93 Difference]: Finished difference Result 936 states and 1217 transitions. [2022-12-13 20:43:30,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1217 transitions. [2022-12-13 20:43:30,920 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 879 [2022-12-13 20:43:30,924 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1217 transitions. [2022-12-13 20:43:30,925 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2022-12-13 20:43:30,926 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2022-12-13 20:43:30,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1217 transitions. [2022-12-13 20:43:30,927 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:43:30,928 INFO L218 hiAutomatonCegarLoop]: Abstraction has 936 states and 1217 transitions. [2022-12-13 20:43:30,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1217 transitions. [2022-12-13 20:43:30,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2022-12-13 20:43:30,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 936 states, 936 states have (on average 1.3002136752136753) internal successors, (1217), 935 states have internal predecessors, (1217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:30,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1217 transitions. [2022-12-13 20:43:30,950 INFO L240 hiAutomatonCegarLoop]: Abstraction has 936 states and 1217 transitions. [2022-12-13 20:43:30,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:43:30,951 INFO L428 stractBuchiCegarLoop]: Abstraction has 936 states and 1217 transitions. [2022-12-13 20:43:30,951 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 20:43:30,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1217 transitions. [2022-12-13 20:43:30,955 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 879 [2022-12-13 20:43:30,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:43:30,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:43:30,956 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,956 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:30,957 INFO L748 eck$LassoCheckResult]: Stem: 10154#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 10155#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 10186#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10130#L222 assume !(1 == ~q_req_up~0); 10119#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10120#L237 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 10168#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 10202#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10203#L275 assume !(0 == ~q_read_ev~0); 10204#L275-2 assume !(0 == ~q_write_ev~0); 10205#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10232#L65 assume !(1 == ~p_dw_pc~0); 10171#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 10230#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10231#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10197#L315 assume !(0 != activate_threads_~tmp~1#1); 10198#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10210#L84 assume !(1 == ~c_dr_pc~0); 10211#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 10139#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10140#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10103#L323 assume !(0 != activate_threads_~tmp___0~1#1); 10104#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10213#L293 assume !(1 == ~q_read_ev~0); 10214#L293-2 assume !(1 == ~q_write_ev~0); 10199#L298-1 assume { :end_inline_reset_delta_events } true; 10200#L419-2 [2022-12-13 20:43:30,957 INFO L750 eck$LassoCheckResult]: Loop: 10200#L419-2 assume !false; 10344#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10311#L364 assume !false; 10343#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10342#L255 assume !(0 == ~p_dw_st~0); 10327#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 10341#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10334#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10335#L344 assume !(0 != eval_~tmp___1~0#1); 10374#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10373#L222-3 assume !(1 == ~q_req_up~0); 10372#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10371#L275-3 assume !(0 == ~q_read_ev~0); 10370#L275-5 assume !(0 == ~q_write_ev~0); 10369#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10367#L65-3 assume !(1 == ~p_dw_pc~0); 10366#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 10365#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10364#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10363#L315-3 assume !(0 != activate_threads_~tmp~1#1); 10362#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10361#L84-3 assume !(1 == ~c_dr_pc~0); 10360#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 10359#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10358#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10357#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 10356#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10355#L293-3 assume !(1 == ~q_read_ev~0); 10354#L293-5 assume !(1 == ~q_write_ev~0); 10353#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10352#L255-1 assume !(0 == ~p_dw_st~0); 10351#L259-1 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10350#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10349#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10348#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 10347#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10346#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10345#L436 assume !(0 != start_simulation_~tmp~4#1); 10200#L419-2 [2022-12-13 20:43:30,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,957 INFO L85 PathProgramCache]: Analyzing trace with hash -1194945487, now seen corresponding path program 1 times [2022-12-13 20:43:30,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285348583] [2022-12-13 20:43:30,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:30,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:30,977 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:30,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285348583] [2022-12-13 20:43:30,977 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285348583] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:30,978 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:30,978 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:43:30,978 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [842798954] [2022-12-13 20:43:30,978 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:30,978 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:43:30,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:30,978 INFO L85 PathProgramCache]: Analyzing trace with hash -282414912, now seen corresponding path program 1 times [2022-12-13 20:43:30,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:30,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788188070] [2022-12-13 20:43:30,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:30,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:30,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:31,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:31,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:31,032 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788188070] [2022-12-13 20:43:31,032 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [788188070] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:31,032 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:31,033 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:43:31,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1328244115] [2022-12-13 20:43:31,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:31,033 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:43:31,033 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:43:31,033 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:43:31,034 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:43:31,034 INFO L87 Difference]: Start difference. First operand 936 states and 1217 transitions. cyclomatic complexity: 284 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:31,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:43:31,041 INFO L93 Difference]: Finished difference Result 915 states and 1193 transitions. [2022-12-13 20:43:31,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 915 states and 1193 transitions. [2022-12-13 20:43:31,045 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 879 [2022-12-13 20:43:31,049 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 915 states to 915 states and 1193 transitions. [2022-12-13 20:43:31,049 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 915 [2022-12-13 20:43:31,050 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 915 [2022-12-13 20:43:31,050 INFO L73 IsDeterministic]: Start isDeterministic. Operand 915 states and 1193 transitions. [2022-12-13 20:43:31,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:43:31,052 INFO L218 hiAutomatonCegarLoop]: Abstraction has 915 states and 1193 transitions. [2022-12-13 20:43:31,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 915 states and 1193 transitions. [2022-12-13 20:43:31,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 915 to 915. [2022-12-13 20:43:31,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 915 states, 915 states have (on average 1.303825136612022) internal successors, (1193), 914 states have internal predecessors, (1193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:31,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 915 states to 915 states and 1193 transitions. [2022-12-13 20:43:31,067 INFO L240 hiAutomatonCegarLoop]: Abstraction has 915 states and 1193 transitions. [2022-12-13 20:43:31,068 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:43:31,068 INFO L428 stractBuchiCegarLoop]: Abstraction has 915 states and 1193 transitions. [2022-12-13 20:43:31,068 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 20:43:31,069 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 915 states and 1193 transitions. [2022-12-13 20:43:31,072 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 879 [2022-12-13 20:43:31,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:43:31,072 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:43:31,072 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:31,072 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:31,072 INFO L748 eck$LassoCheckResult]: Stem: 12012#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 12013#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 12041#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11990#L222 assume !(1 == ~q_req_up~0); 11979#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11980#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 12023#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 12047#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12045#L275 assume !(0 == ~q_read_ev~0); 12046#L275-2 assume !(0 == ~q_write_ev~0); 12028#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 12029#L65 assume !(1 == ~p_dw_pc~0); 12025#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 12039#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 12009#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 12010#L315 assume !(0 != activate_threads_~tmp~1#1); 11987#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 11988#L84 assume !(1 == ~c_dr_pc~0); 12005#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 11999#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 12000#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11963#L323 assume !(0 != activate_threads_~tmp___0~1#1); 11964#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12057#L293 assume !(1 == ~q_read_ev~0); 11956#L293-2 assume !(1 == ~q_write_ev~0); 11957#L298-1 assume { :end_inline_reset_delta_events } true; 11983#L419-2 assume !false; 11984#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 12035#L364 [2022-12-13 20:43:31,072 INFO L750 eck$LassoCheckResult]: Loop: 12035#L364 assume !false; 12030#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12031#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 12101#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12829#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 12097#L344 assume 0 != eval_~tmp___1~0#1; 12096#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 12006#L353 assume !(0 != eval_~tmp~2#1); 12008#L349 assume !(0 == ~c_dr_st~0); 12035#L364 [2022-12-13 20:43:31,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:31,073 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 1 times [2022-12-13 20:43:31,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:31,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1053211445] [2022-12-13 20:43:31,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:31,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:31,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:31,077 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:43:31,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:31,082 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:43:31,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:31,082 INFO L85 PathProgramCache]: Analyzing trace with hash -479000201, now seen corresponding path program 1 times [2022-12-13 20:43:31,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:31,082 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1561189497] [2022-12-13 20:43:31,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:31,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:31,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:31,085 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:43:31,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:31,087 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:43:31,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:31,087 INFO L85 PathProgramCache]: Analyzing trace with hash 519639655, now seen corresponding path program 1 times [2022-12-13 20:43:31,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:31,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942309887] [2022-12-13 20:43:31,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:31,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:31,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:43:31,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:43:31,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:43:31,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1942309887] [2022-12-13 20:43:31,105 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1942309887] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:43:31,105 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:43:31,105 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:43:31,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1555668045] [2022-12-13 20:43:31,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:43:31,146 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:43:31,146 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:43:31,146 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:43:31,146 INFO L87 Difference]: Start difference. First operand 915 states and 1193 transitions. cyclomatic complexity: 281 Second operand has 3 states, 2 states have (on average 18.5) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:31,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:43:31,167 INFO L93 Difference]: Finished difference Result 1272 states and 1634 transitions. [2022-12-13 20:43:31,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1272 states and 1634 transitions. [2022-12-13 20:43:31,171 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1236 [2022-12-13 20:43:31,173 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1272 states to 1272 states and 1634 transitions. [2022-12-13 20:43:31,174 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1272 [2022-12-13 20:43:31,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1272 [2022-12-13 20:43:31,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1272 states and 1634 transitions. [2022-12-13 20:43:31,175 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:43:31,175 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1272 states and 1634 transitions. [2022-12-13 20:43:31,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1272 states and 1634 transitions. [2022-12-13 20:43:31,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1272 to 1272. [2022-12-13 20:43:31,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1272 states, 1272 states have (on average 1.2845911949685536) internal successors, (1634), 1271 states have internal predecessors, (1634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:43:31,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1272 states to 1272 states and 1634 transitions. [2022-12-13 20:43:31,189 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1272 states and 1634 transitions. [2022-12-13 20:43:31,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:43:31,189 INFO L428 stractBuchiCegarLoop]: Abstraction has 1272 states and 1634 transitions. [2022-12-13 20:43:31,189 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 20:43:31,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1272 states and 1634 transitions. [2022-12-13 20:43:31,192 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1236 [2022-12-13 20:43:31,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:43:31,192 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:43:31,193 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:31,193 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:43:31,193 INFO L748 eck$LassoCheckResult]: Stem: 14208#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 14209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 14237#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14184#L222 assume !(1 == ~q_req_up~0); 14173#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14174#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 14219#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 14244#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14242#L275 assume !(0 == ~q_read_ev~0); 14243#L275-2 assume !(0 == ~q_write_ev~0); 14224#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 14225#L65 assume !(1 == ~p_dw_pc~0); 14221#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 14234#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 14205#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 14206#L315 assume !(0 != activate_threads_~tmp~1#1); 14181#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 14182#L84 assume !(1 == ~c_dr_pc~0); 14199#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 14192#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 14193#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 14157#L323 assume !(0 != activate_threads_~tmp___0~1#1); 14158#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14257#L293 assume !(1 == ~q_read_ev~0); 14151#L293-2 assume !(1 == ~q_write_ev~0); 14152#L298-1 assume { :end_inline_reset_delta_events } true; 14250#L419-2 assume !false; 15017#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 15013#L364 [2022-12-13 20:43:31,193 INFO L750 eck$LassoCheckResult]: Loop: 15013#L364 assume !false; 15011#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 15009#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 15007#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 15005#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 15002#L344 assume 0 != eval_~tmp___1~0#1; 15000#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 14996#L353 assume !(0 != eval_~tmp~2#1); 14997#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 15016#L368 assume !(0 != eval_~tmp___0~2#1); 15013#L364 [2022-12-13 20:43:31,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:31,193 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 2 times [2022-12-13 20:43:31,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:31,193 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623194813] [2022-12-13 20:43:31,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:31,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:31,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:31,197 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:43:31,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:31,213 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:43:31,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:31,214 INFO L85 PathProgramCache]: Analyzing trace with hash -1964106000, now seen corresponding path program 1 times [2022-12-13 20:43:31,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:31,214 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012574738] [2022-12-13 20:43:31,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:31,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:31,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:31,216 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:43:31,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:31,218 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:43:31,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:43:31,219 INFO L85 PathProgramCache]: Analyzing trace with hash -1071041536, now seen corresponding path program 1 times [2022-12-13 20:43:31,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:43:31,219 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245433903] [2022-12-13 20:43:31,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:43:31,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:43:31,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:31,223 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:43:31,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:31,229 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:43:31,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:31,771 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:43:31,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:43:31,830 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 08:43:31 BoogieIcfgContainer [2022-12-13 20:43:31,830 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 20:43:31,830 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 20:43:31,830 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 20:43:31,830 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 20:43:31,831 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 08:43:29" (3/4) ... [2022-12-13 20:43:31,832 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 20:43:31,870 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 20:43:31,870 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 20:43:31,870 INFO L158 Benchmark]: Toolchain (without parser) took 3132.30ms. Allocated memory was 148.9MB in the beginning and 184.5MB in the end (delta: 35.7MB). Free memory was 115.2MB in the beginning and 76.2MB in the end (delta: 39.0MB). Peak memory consumption was 76.4MB. Max. memory is 16.1GB. [2022-12-13 20:43:31,870 INFO L158 Benchmark]: CDTParser took 0.21ms. Allocated memory is still 148.9MB. Free memory is still 124.8MB. There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 20:43:31,871 INFO L158 Benchmark]: CACSL2BoogieTranslator took 182.62ms. Allocated memory is still 148.9MB. Free memory was 115.2MB in the beginning and 102.5MB in the end (delta: 12.7MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-12-13 20:43:31,871 INFO L158 Benchmark]: Boogie Procedure Inliner took 26.39ms. Allocated memory is still 148.9MB. Free memory was 102.5MB in the beginning and 100.2MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-12-13 20:43:31,871 INFO L158 Benchmark]: Boogie Preprocessor took 19.99ms. Allocated memory is still 148.9MB. Free memory was 100.2MB in the beginning and 98.4MB in the end (delta: 1.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-12-13 20:43:31,871 INFO L158 Benchmark]: RCFGBuilder took 380.13ms. Allocated memory is still 148.9MB. Free memory was 98.4MB in the beginning and 80.6MB in the end (delta: 17.8MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2022-12-13 20:43:31,871 INFO L158 Benchmark]: BuchiAutomizer took 2479.71ms. Allocated memory was 148.9MB in the beginning and 184.5MB in the end (delta: 35.7MB). Free memory was 80.6MB in the beginning and 80.4MB in the end (delta: 208.1kB). Peak memory consumption was 38.7MB. Max. memory is 16.1GB. [2022-12-13 20:43:31,872 INFO L158 Benchmark]: Witness Printer took 39.79ms. Allocated memory is still 184.5MB. Free memory was 80.4MB in the beginning and 76.2MB in the end (delta: 4.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-12-13 20:43:31,873 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21ms. Allocated memory is still 148.9MB. Free memory is still 124.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 182.62ms. Allocated memory is still 148.9MB. Free memory was 115.2MB in the beginning and 102.5MB in the end (delta: 12.7MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 26.39ms. Allocated memory is still 148.9MB. Free memory was 102.5MB in the beginning and 100.2MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 19.99ms. Allocated memory is still 148.9MB. Free memory was 100.2MB in the beginning and 98.4MB in the end (delta: 1.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 380.13ms. Allocated memory is still 148.9MB. Free memory was 98.4MB in the beginning and 80.6MB in the end (delta: 17.8MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 2479.71ms. Allocated memory was 148.9MB in the beginning and 184.5MB in the end (delta: 35.7MB). Free memory was 80.6MB in the beginning and 80.4MB in the end (delta: 208.1kB). Peak memory consumption was 38.7MB. Max. memory is 16.1GB. * Witness Printer took 39.79ms. Allocated memory is still 184.5MB. Free memory was 80.4MB in the beginning and 76.2MB in the end (delta: 4.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (10 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.10 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1272 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.4s and 11 iterations. TraceHistogramMax:1. Analysis of lassos took 1.5s. Construction of modules took 0.1s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 10. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 10 MinimizatonAttempts, 1660 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1998 SdHoareTripleChecker+Valid, 0.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1998 mSDsluCounter, 3046 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1683 mSDsCounter, 71 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 229 IncrementalHoareTripleChecker+Invalid, 300 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 71 mSolverCounterUnsat, 1363 mSDtfsCounter, 229 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 339]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0, tmp___0=0] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 339]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0, tmp___0=0] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 20:43:31,903 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eba2e52b-ae89-4f7e-b0fe-804588d58f01/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)