./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 16:07:26,676 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 16:07:26,678 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 16:07:26,696 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 16:07:26,696 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 16:07:26,697 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 16:07:26,698 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 16:07:26,700 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 16:07:26,701 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 16:07:26,702 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 16:07:26,703 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 16:07:26,704 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 16:07:26,704 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 16:07:26,705 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 16:07:26,706 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 16:07:26,707 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 16:07:26,708 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 16:07:26,709 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 16:07:26,710 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 16:07:26,712 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 16:07:26,713 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 16:07:26,715 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 16:07:26,716 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 16:07:26,716 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 16:07:26,720 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 16:07:26,720 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 16:07:26,720 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 16:07:26,721 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 16:07:26,721 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 16:07:26,722 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 16:07:26,722 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 16:07:26,723 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 16:07:26,724 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 16:07:26,725 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 16:07:26,725 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 16:07:26,726 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 16:07:26,726 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 16:07:26,727 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 16:07:26,727 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 16:07:26,727 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 16:07:26,728 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 16:07:26,729 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 16:07:26,750 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 16:07:26,750 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 16:07:26,750 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 16:07:26,750 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 16:07:26,751 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 16:07:26,751 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 16:07:26,752 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 16:07:26,752 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 16:07:26,752 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 16:07:26,752 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 16:07:26,752 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 16:07:26,752 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 16:07:26,753 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 16:07:26,753 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 16:07:26,753 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 16:07:26,753 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 16:07:26,753 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 16:07:26,753 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 16:07:26,754 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 16:07:26,754 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 16:07:26,754 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 16:07:26,754 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 16:07:26,754 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 16:07:26,754 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 16:07:26,754 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 16:07:26,755 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 16:07:26,755 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 16:07:26,755 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 16:07:26,755 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 16:07:26,755 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 16:07:26,755 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 16:07:26,756 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 16:07:26,756 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 [2022-12-13 16:07:26,943 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 16:07:26,963 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 16:07:26,965 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 16:07:26,967 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 16:07:26,967 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 16:07:26,968 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2022-12-13 16:07:29,477 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 16:07:29,636 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 16:07:29,636 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2022-12-13 16:07:29,642 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/data/ddff31359/2ae4236962694b8bb163470ca2a88786/FLAGd115daff7 [2022-12-13 16:07:30,045 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/data/ddff31359/2ae4236962694b8bb163470ca2a88786 [2022-12-13 16:07:30,050 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 16:07:30,052 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 16:07:30,054 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 16:07:30,054 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 16:07:30,058 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 16:07:30,059 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 04:07:30" (1/1) ... [2022-12-13 16:07:30,060 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@30be7d82 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30, skipping insertion in model container [2022-12-13 16:07:30,060 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 04:07:30" (1/1) ... [2022-12-13 16:07:30,067 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 16:07:30,094 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 16:07:30,215 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/sv-benchmarks/c/systemc/token_ring.03.cil-1.c[671,684] [2022-12-13 16:07:30,270 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 16:07:30,279 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 16:07:30,287 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/sv-benchmarks/c/systemc/token_ring.03.cil-1.c[671,684] [2022-12-13 16:07:30,307 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 16:07:30,318 INFO L208 MainTranslator]: Completed translation [2022-12-13 16:07:30,318 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30 WrapperNode [2022-12-13 16:07:30,318 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 16:07:30,319 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 16:07:30,319 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 16:07:30,319 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 16:07:30,324 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30" (1/1) ... [2022-12-13 16:07:30,330 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30" (1/1) ... [2022-12-13 16:07:30,354 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 63, statements flattened = 825 [2022-12-13 16:07:30,354 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 16:07:30,354 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 16:07:30,355 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 16:07:30,355 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 16:07:30,363 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30" (1/1) ... [2022-12-13 16:07:30,363 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30" (1/1) ... [2022-12-13 16:07:30,366 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30" (1/1) ... [2022-12-13 16:07:30,366 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30" (1/1) ... [2022-12-13 16:07:30,372 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30" (1/1) ... [2022-12-13 16:07:30,379 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30" (1/1) ... [2022-12-13 16:07:30,380 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30" (1/1) ... [2022-12-13 16:07:30,382 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30" (1/1) ... [2022-12-13 16:07:30,385 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 16:07:30,386 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 16:07:30,386 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 16:07:30,386 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 16:07:30,386 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30" (1/1) ... [2022-12-13 16:07:30,391 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 16:07:30,400 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 16:07:30,411 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 16:07:30,413 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 16:07:30,445 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 16:07:30,445 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 16:07:30,445 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 16:07:30,446 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 16:07:30,513 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 16:07:30,514 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 16:07:31,033 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 16:07:31,043 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 16:07:31,043 INFO L300 CfgBuilder]: Removed 6 assume(true) statements. [2022-12-13 16:07:31,046 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 04:07:31 BoogieIcfgContainer [2022-12-13 16:07:31,046 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 16:07:31,047 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 16:07:31,047 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 16:07:31,051 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 16:07:31,052 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:07:31,052 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 04:07:30" (1/3) ... [2022-12-13 16:07:31,053 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4df081ef and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 04:07:31, skipping insertion in model container [2022-12-13 16:07:31,053 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:07:31,053 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:07:30" (2/3) ... [2022-12-13 16:07:31,053 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4df081ef and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 04:07:31, skipping insertion in model container [2022-12-13 16:07:31,054 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:07:31,054 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 04:07:31" (3/3) ... [2022-12-13 16:07:31,055 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-1.c [2022-12-13 16:07:31,115 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 16:07:31,115 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 16:07:31,115 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 16:07:31,116 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 16:07:31,116 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 16:07:31,116 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 16:07:31,116 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 16:07:31,116 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 16:07:31,122 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 331 states, 330 states have (on average 1.5393939393939393) internal successors, (508), 330 states have internal predecessors, (508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:31,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2022-12-13 16:07:31,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:31,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:31,167 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:31,167 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:31,167 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 16:07:31,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 331 states, 330 states have (on average 1.5393939393939393) internal successors, (508), 330 states have internal predecessors, (508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:31,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2022-12-13 16:07:31,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:31,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:31,187 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:31,187 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:31,195 INFO L748 eck$LassoCheckResult]: Stem: 209#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 220#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 325#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 217#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 284#L304true assume !(1 == ~m_i~0);~m_st~0 := 2; 124#L304-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 26#L309-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 238#L314-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 139#L319-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32#L441true assume !(0 == ~M_E~0); 122#L441-2true assume !(0 == ~T1_E~0); 254#L446-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 95#L451-1true assume !(0 == ~T3_E~0); 275#L456-1true assume !(0 == ~E_M~0); 231#L461-1true assume !(0 == ~E_1~0); 250#L466-1true assume !(0 == ~E_2~0); 297#L471-1true assume !(0 == ~E_3~0); 49#L476-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87#L220true assume 1 == ~m_pc~0; 264#L221true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 104#L231true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67#L543true assume !(0 != activate_threads_~tmp~1#1); 323#L543-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 205#L239true assume !(1 == ~t1_pc~0); 227#L239-2true is_transmit1_triggered_~__retres1~1#1 := 0; 271#L250true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 210#L551true assume !(0 != activate_threads_~tmp___0~0#1); 327#L551-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 211#L258true assume 1 == ~t2_pc~0; 248#L259true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86#L269true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 329#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 225#L559true assume !(0 != activate_threads_~tmp___1~0#1); 131#L559-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173#L277true assume !(1 == ~t3_pc~0); 324#L277-2true is_transmit3_triggered_~__retres1~3#1 := 0; 38#L288true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64#L567true assume !(0 != activate_threads_~tmp___2~0#1); 92#L567-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 305#L489true assume !(1 == ~M_E~0); 228#L489-2true assume !(1 == ~T1_E~0); 151#L494-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 59#L499-1true assume !(1 == ~T3_E~0); 125#L504-1true assume !(1 == ~E_M~0); 263#L509-1true assume !(1 == ~E_1~0); 51#L514-1true assume !(1 == ~E_2~0); 181#L519-1true assume !(1 == ~E_3~0); 56#L524-1true assume { :end_inline_reset_delta_events } true; 37#L690-2true [2022-12-13 16:07:31,197 INFO L750 eck$LassoCheckResult]: Loop: 37#L690-2true assume !false; 52#L691true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23#L416true assume false; 113#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 154#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 197#L441-3true assume 0 == ~M_E~0;~M_E~0 := 1; 8#L441-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 256#L446-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 193#L451-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 35#L456-3true assume 0 == ~E_M~0;~E_M~0 := 1; 72#L461-3true assume 0 == ~E_1~0;~E_1~0 := 1; 156#L466-3true assume 0 == ~E_2~0;~E_2~0 := 1; 259#L471-3true assume !(0 == ~E_3~0); 65#L476-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105#L220-15true assume !(1 == ~m_pc~0); 162#L220-17true is_master_triggered_~__retres1~0#1 := 0; 208#L231-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106#is_master_triggered_returnLabel#6true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 222#L543-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 132#L543-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123#L239-15true assume 1 == ~t1_pc~0; 268#L240-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 282#L250-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90#is_transmit1_triggered_returnLabel#6true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 27#L551-15true assume !(0 != activate_threads_~tmp___0~0#1); 315#L551-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 314#L258-15true assume 1 == ~t2_pc~0; 155#L259-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 279#L269-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 280#is_transmit2_triggered_returnLabel#6true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 332#L559-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 233#L559-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 301#L277-15true assume !(1 == ~t3_pc~0); 13#L277-17true is_transmit3_triggered_~__retres1~3#1 := 0; 326#L288-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 243#is_transmit3_triggered_returnLabel#6true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 270#L567-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33#L567-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28#L489-3true assume 1 == ~M_E~0;~M_E~0 := 2; 176#L489-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 223#L494-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 299#L499-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 107#L504-3true assume 1 == ~E_M~0;~E_M~0 := 2; 17#L509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 298#L514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 167#L519-3true assume !(1 == ~E_3~0); 42#L524-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 53#L332-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 57#L354-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 283#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 152#L709true assume !(0 == start_simulation_~tmp~3#1); 7#L709-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 116#L332-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 55#L354-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 47#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 54#L664true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 157#L671true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 178#stop_simulation_returnLabel#1true start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 85#L722true assume !(0 != start_simulation_~tmp___0~1#1); 37#L690-2true [2022-12-13 16:07:31,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:31,203 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2022-12-13 16:07:31,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:31,212 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704051439] [2022-12-13 16:07:31,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:31,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:31,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:31,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:31,360 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:31,360 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [704051439] [2022-12-13 16:07:31,361 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [704051439] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:31,361 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:31,361 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:07:31,362 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805655522] [2022-12-13 16:07:31,363 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:31,366 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:07:31,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:31,367 INFO L85 PathProgramCache]: Analyzing trace with hash 266127093, now seen corresponding path program 1 times [2022-12-13 16:07:31,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:31,367 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150402366] [2022-12-13 16:07:31,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:31,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:31,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:31,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:31,390 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:31,390 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [150402366] [2022-12-13 16:07:31,390 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [150402366] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:31,390 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:31,391 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:07:31,391 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777702074] [2022-12-13 16:07:31,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:31,392 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:07:31,392 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:31,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:07:31,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:07:31,417 INFO L87 Difference]: Start difference. First operand has 331 states, 330 states have (on average 1.5393939393939393) internal successors, (508), 330 states have internal predecessors, (508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:31,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:31,447 INFO L93 Difference]: Finished difference Result 329 states and 491 transitions. [2022-12-13 16:07:31,448 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 329 states and 491 transitions. [2022-12-13 16:07:31,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2022-12-13 16:07:31,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 329 states to 323 states and 485 transitions. [2022-12-13 16:07:31,455 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 323 [2022-12-13 16:07:31,456 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 323 [2022-12-13 16:07:31,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 323 states and 485 transitions. [2022-12-13 16:07:31,458 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:31,458 INFO L218 hiAutomatonCegarLoop]: Abstraction has 323 states and 485 transitions. [2022-12-13 16:07:31,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states and 485 transitions. [2022-12-13 16:07:31,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 323. [2022-12-13 16:07:31,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 323 states have (on average 1.501547987616099) internal successors, (485), 322 states have internal predecessors, (485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:31,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 485 transitions. [2022-12-13 16:07:31,487 INFO L240 hiAutomatonCegarLoop]: Abstraction has 323 states and 485 transitions. [2022-12-13 16:07:31,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:07:31,492 INFO L428 stractBuchiCegarLoop]: Abstraction has 323 states and 485 transitions. [2022-12-13 16:07:31,492 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 16:07:31,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 485 transitions. [2022-12-13 16:07:31,493 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2022-12-13 16:07:31,493 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:31,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:31,495 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:31,495 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:31,495 INFO L748 eck$LassoCheckResult]: Stem: 942#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 943#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 955#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 953#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 954#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 873#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 724#L309-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 725#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 892#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 734#L441 assume !(0 == ~M_E~0); 735#L441-2 assume !(0 == ~T1_E~0); 869#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 836#L451-1 assume !(0 == ~T3_E~0); 837#L456-1 assume !(0 == ~E_M~0); 959#L461-1 assume !(0 == ~E_1~0); 960#L466-1 assume !(0 == ~E_2~0); 970#L471-1 assume !(0 == ~E_3~0); 769#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 770#L220 assume 1 == ~m_pc~0; 827#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 801#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 850#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 796#L543 assume !(0 != activate_threads_~tmp~1#1); 797#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 941#L239 assume !(1 == ~t1_pc~0); 939#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 940#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 765#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 766#L551 assume !(0 != activate_threads_~tmp___0~0#1); 944#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 945#L258 assume 1 == ~t2_pc~0; 946#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 824#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 825#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 957#L559 assume !(0 != activate_threads_~tmp___1~0#1); 880#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 881#L277 assume !(1 == ~t3_pc~0); 920#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 745#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 700#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 701#L567 assume !(0 != activate_threads_~tmp___2~0#1); 792#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 831#L489 assume !(1 == ~M_E~0); 958#L489-2 assume !(1 == ~T1_E~0); 903#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 783#L499-1 assume !(1 == ~T3_E~0); 784#L504-1 assume !(1 == ~E_M~0); 874#L509-1 assume !(1 == ~E_1~0); 771#L514-1 assume !(1 == ~E_2~0); 772#L519-1 assume !(1 == ~E_3~0); 777#L524-1 assume { :end_inline_reset_delta_events } true; 743#L690-2 [2022-12-13 16:07:31,495 INFO L750 eck$LassoCheckResult]: Loop: 743#L690-2 assume !false; 744#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 672#L416 assume !false; 716#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 806#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 752#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 702#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 703#L369 assume !(0 != eval_~tmp~0#1); 860#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 861#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 905#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 683#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 684#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 930#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 739#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 740#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 805#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 907#L471-3 assume !(0 == ~E_3~0); 794#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 795#L220-15 assume 1 == ~m_pc~0; 689#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 690#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 851#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 852#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 882#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 870#L239-15 assume !(1 == ~t1_pc~0); 871#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 973#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 826#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 722#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 723#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 991#L258-15 assume !(1 == ~t2_pc~0); 832#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 833#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 980#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 982#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 961#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 962#L277-15 assume 1 == ~t3_pc~0; 804#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 696#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 966#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 967#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 736#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 726#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 727#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 923#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 956#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 849#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 704#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 705#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 914#L519-3 assume !(1 == ~E_3~0); 753#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 754#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 773#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 778#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 902#L709 assume !(0 == start_simulation_~tmp~3#1); 679#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 680#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 776#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 758#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 759#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 775#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 906#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 823#L722 assume !(0 != start_simulation_~tmp___0~1#1); 743#L690-2 [2022-12-13 16:07:31,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:31,496 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2022-12-13 16:07:31,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:31,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [27014760] [2022-12-13 16:07:31,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:31,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:31,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:31,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:31,537 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:31,537 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [27014760] [2022-12-13 16:07:31,537 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [27014760] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:31,537 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:31,537 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:07:31,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [127506054] [2022-12-13 16:07:31,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:31,537 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:07:31,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:31,538 INFO L85 PathProgramCache]: Analyzing trace with hash 1906336898, now seen corresponding path program 1 times [2022-12-13 16:07:31,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:31,538 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1100711435] [2022-12-13 16:07:31,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:31,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:31,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:31,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:31,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:31,591 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1100711435] [2022-12-13 16:07:31,591 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1100711435] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:31,592 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:31,592 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:07:31,592 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [602145738] [2022-12-13 16:07:31,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:31,592 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:07:31,593 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:31,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:07:31,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:07:31,593 INFO L87 Difference]: Start difference. First operand 323 states and 485 transitions. cyclomatic complexity: 163 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:31,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:31,607 INFO L93 Difference]: Finished difference Result 323 states and 484 transitions. [2022-12-13 16:07:31,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 484 transitions. [2022-12-13 16:07:31,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2022-12-13 16:07:31,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 323 states and 484 transitions. [2022-12-13 16:07:31,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 323 [2022-12-13 16:07:31,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 323 [2022-12-13 16:07:31,611 INFO L73 IsDeterministic]: Start isDeterministic. Operand 323 states and 484 transitions. [2022-12-13 16:07:31,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:31,611 INFO L218 hiAutomatonCegarLoop]: Abstraction has 323 states and 484 transitions. [2022-12-13 16:07:31,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states and 484 transitions. [2022-12-13 16:07:31,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 323. [2022-12-13 16:07:31,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 323 states have (on average 1.498452012383901) internal successors, (484), 322 states have internal predecessors, (484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:31,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 484 transitions. [2022-12-13 16:07:31,618 INFO L240 hiAutomatonCegarLoop]: Abstraction has 323 states and 484 transitions. [2022-12-13 16:07:31,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:07:31,620 INFO L428 stractBuchiCegarLoop]: Abstraction has 323 states and 484 transitions. [2022-12-13 16:07:31,620 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 16:07:31,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 484 transitions. [2022-12-13 16:07:31,622 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2022-12-13 16:07:31,622 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:31,622 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:31,625 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:31,625 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:31,625 INFO L748 eck$LassoCheckResult]: Stem: 1595#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1596#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1608#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1606#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1607#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 1527#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1377#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1378#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1545#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1387#L441 assume !(0 == ~M_E~0); 1388#L441-2 assume !(0 == ~T1_E~0); 1522#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1489#L451-1 assume !(0 == ~T3_E~0); 1490#L456-1 assume !(0 == ~E_M~0); 1612#L461-1 assume !(0 == ~E_1~0); 1613#L466-1 assume !(0 == ~E_2~0); 1623#L471-1 assume !(0 == ~E_3~0); 1422#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1423#L220 assume 1 == ~m_pc~0; 1482#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1454#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1505#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1451#L543 assume !(0 != activate_threads_~tmp~1#1); 1452#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1594#L239 assume !(1 == ~t1_pc~0); 1592#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1593#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1418#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1419#L551 assume !(0 != activate_threads_~tmp___0~0#1); 1597#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1598#L258 assume 1 == ~t2_pc~0; 1599#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1477#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1478#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1610#L559 assume !(0 != activate_threads_~tmp___1~0#1); 1533#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1534#L277 assume !(1 == ~t3_pc~0); 1572#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1398#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1353#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1354#L567 assume !(0 != activate_threads_~tmp___2~0#1); 1445#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1484#L489 assume !(1 == ~M_E~0); 1611#L489-2 assume !(1 == ~T1_E~0); 1555#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1434#L499-1 assume !(1 == ~T3_E~0); 1435#L504-1 assume !(1 == ~E_M~0); 1526#L509-1 assume !(1 == ~E_1~0); 1424#L514-1 assume !(1 == ~E_2~0); 1425#L519-1 assume !(1 == ~E_3~0); 1430#L524-1 assume { :end_inline_reset_delta_events } true; 1396#L690-2 [2022-12-13 16:07:31,625 INFO L750 eck$LassoCheckResult]: Loop: 1396#L690-2 assume !false; 1397#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1325#L416 assume !false; 1369#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1459#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1405#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1355#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1356#L369 assume !(0 != eval_~tmp~0#1); 1512#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1513#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1557#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1336#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1337#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1583#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1392#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1393#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1458#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1559#L471-3 assume !(0 == ~E_3~0); 1447#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1448#L220-15 assume !(1 == ~m_pc~0); 1344#L220-17 is_master_triggered_~__retres1~0#1 := 0; 1343#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1502#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1503#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1535#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1523#L239-15 assume !(1 == ~t1_pc~0); 1524#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1626#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1481#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1375#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 1376#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1644#L258-15 assume 1 == ~t2_pc~0; 1558#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1486#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1634#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1635#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1614#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1615#L277-15 assume 1 == ~t3_pc~0; 1457#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1349#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1619#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1620#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1389#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1379#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1380#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1576#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1609#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1504#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1357#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1358#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1567#L519-3 assume !(1 == ~E_3~0); 1406#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1407#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1426#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1431#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1556#L709 assume !(0 == start_simulation_~tmp~3#1); 1334#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1335#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1429#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1416#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1417#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1428#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1560#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1476#L722 assume !(0 != start_simulation_~tmp___0~1#1); 1396#L690-2 [2022-12-13 16:07:31,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:31,626 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2022-12-13 16:07:31,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:31,627 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412879898] [2022-12-13 16:07:31,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:31,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:31,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:31,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:31,656 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:31,656 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412879898] [2022-12-13 16:07:31,657 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [412879898] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:31,657 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:31,657 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:07:31,657 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515013463] [2022-12-13 16:07:31,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:31,658 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:07:31,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:31,658 INFO L85 PathProgramCache]: Analyzing trace with hash -1685550334, now seen corresponding path program 1 times [2022-12-13 16:07:31,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:31,659 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725059063] [2022-12-13 16:07:31,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:31,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:31,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:31,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:31,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:31,713 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [725059063] [2022-12-13 16:07:31,713 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [725059063] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:31,714 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:31,714 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:07:31,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [784554002] [2022-12-13 16:07:31,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:31,714 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:07:31,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:31,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:07:31,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:07:31,715 INFO L87 Difference]: Start difference. First operand 323 states and 484 transitions. cyclomatic complexity: 162 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:31,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:31,727 INFO L93 Difference]: Finished difference Result 323 states and 483 transitions. [2022-12-13 16:07:31,727 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 483 transitions. [2022-12-13 16:07:31,730 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2022-12-13 16:07:31,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 323 states and 483 transitions. [2022-12-13 16:07:31,734 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 323 [2022-12-13 16:07:31,735 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 323 [2022-12-13 16:07:31,735 INFO L73 IsDeterministic]: Start isDeterministic. Operand 323 states and 483 transitions. [2022-12-13 16:07:31,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:31,737 INFO L218 hiAutomatonCegarLoop]: Abstraction has 323 states and 483 transitions. [2022-12-13 16:07:31,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states and 483 transitions. [2022-12-13 16:07:31,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 323. [2022-12-13 16:07:31,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 323 states have (on average 1.4953560371517027) internal successors, (483), 322 states have internal predecessors, (483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:31,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 483 transitions. [2022-12-13 16:07:31,752 INFO L240 hiAutomatonCegarLoop]: Abstraction has 323 states and 483 transitions. [2022-12-13 16:07:31,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:07:31,753 INFO L428 stractBuchiCegarLoop]: Abstraction has 323 states and 483 transitions. [2022-12-13 16:07:31,753 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 16:07:31,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 483 transitions. [2022-12-13 16:07:31,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2022-12-13 16:07:31,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:31,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:31,757 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:31,757 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:31,758 INFO L748 eck$LassoCheckResult]: Stem: 2248#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2249#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2261#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2259#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2260#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 2179#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2028#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2029#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2198#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2040#L441 assume !(0 == ~M_E~0); 2041#L441-2 assume !(0 == ~T1_E~0); 2175#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2140#L451-1 assume !(0 == ~T3_E~0); 2141#L456-1 assume !(0 == ~E_M~0); 2265#L461-1 assume !(0 == ~E_1~0); 2266#L466-1 assume !(0 == ~E_2~0); 2276#L471-1 assume !(0 == ~E_3~0); 2073#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2074#L220 assume 1 == ~m_pc~0; 2132#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2107#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2155#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2102#L543 assume !(0 != activate_threads_~tmp~1#1); 2103#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2247#L239 assume !(1 == ~t1_pc~0); 2245#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2246#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2071#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2072#L551 assume !(0 != activate_threads_~tmp___0~0#1); 2250#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2251#L258 assume 1 == ~t2_pc~0; 2252#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2130#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2131#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2263#L559 assume !(0 != activate_threads_~tmp___1~0#1); 2186#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2187#L277 assume !(1 == ~t3_pc~0); 2225#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2051#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2006#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2007#L567 assume !(0 != activate_threads_~tmp___2~0#1); 2098#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2137#L489 assume !(1 == ~M_E~0); 2264#L489-2 assume !(1 == ~T1_E~0); 2208#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2087#L499-1 assume !(1 == ~T3_E~0); 2088#L504-1 assume !(1 == ~E_M~0); 2180#L509-1 assume !(1 == ~E_1~0); 2077#L514-1 assume !(1 == ~E_2~0); 2078#L519-1 assume !(1 == ~E_3~0); 2083#L524-1 assume { :end_inline_reset_delta_events } true; 2049#L690-2 [2022-12-13 16:07:31,758 INFO L750 eck$LassoCheckResult]: Loop: 2049#L690-2 assume !false; 2050#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1978#L416 assume !false; 2022#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2112#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2058#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2008#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2009#L369 assume !(0 != eval_~tmp~0#1); 2165#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2166#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2210#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1989#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1990#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2236#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2045#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2046#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2111#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2212#L471-3 assume !(0 == ~E_3~0); 2100#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2101#L220-15 assume 1 == ~m_pc~0; 1995#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1996#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2156#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2157#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2188#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2176#L239-15 assume !(1 == ~t1_pc~0); 2177#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 2279#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2135#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2030#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 2031#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2297#L258-15 assume 1 == ~t2_pc~0; 2211#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2139#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2287#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2288#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2267#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2268#L277-15 assume !(1 == ~t3_pc~0); 2001#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2002#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2272#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2273#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2042#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2032#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2033#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2229#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2262#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2158#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2010#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2011#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2220#L519-3 assume !(1 == ~E_3~0); 2059#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2060#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2079#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2084#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2209#L709 assume !(0 == start_simulation_~tmp~3#1); 1987#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1988#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2082#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2069#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2070#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2081#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2213#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2129#L722 assume !(0 != start_simulation_~tmp___0~1#1); 2049#L690-2 [2022-12-13 16:07:31,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:31,759 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2022-12-13 16:07:31,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:31,759 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149386708] [2022-12-13 16:07:31,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:31,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:31,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:31,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:31,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:31,837 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1149386708] [2022-12-13 16:07:31,837 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1149386708] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:31,837 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:31,837 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:07:31,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [427947271] [2022-12-13 16:07:31,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:31,838 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:07:31,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:31,839 INFO L85 PathProgramCache]: Analyzing trace with hash 1810377026, now seen corresponding path program 1 times [2022-12-13 16:07:31,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:31,839 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322150830] [2022-12-13 16:07:31,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:31,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:31,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:31,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:31,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:31,907 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [322150830] [2022-12-13 16:07:31,907 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [322150830] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:31,907 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:31,907 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:07:31,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1701618604] [2022-12-13 16:07:31,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:31,908 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:07:31,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:31,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 16:07:31,909 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 16:07:31,909 INFO L87 Difference]: Start difference. First operand 323 states and 483 transitions. cyclomatic complexity: 161 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:31,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:31,975 INFO L93 Difference]: Finished difference Result 561 states and 834 transitions. [2022-12-13 16:07:31,975 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 561 states and 834 transitions. [2022-12-13 16:07:31,978 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 498 [2022-12-13 16:07:31,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 561 states to 561 states and 834 transitions. [2022-12-13 16:07:31,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 561 [2022-12-13 16:07:31,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 561 [2022-12-13 16:07:31,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 561 states and 834 transitions. [2022-12-13 16:07:31,980 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:31,981 INFO L218 hiAutomatonCegarLoop]: Abstraction has 561 states and 834 transitions. [2022-12-13 16:07:31,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 561 states and 834 transitions. [2022-12-13 16:07:31,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 561 to 561. [2022-12-13 16:07:31,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 561 states, 561 states have (on average 1.4866310160427807) internal successors, (834), 560 states have internal predecessors, (834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:31,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 561 states to 561 states and 834 transitions. [2022-12-13 16:07:31,990 INFO L240 hiAutomatonCegarLoop]: Abstraction has 561 states and 834 transitions. [2022-12-13 16:07:31,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:07:31,991 INFO L428 stractBuchiCegarLoop]: Abstraction has 561 states and 834 transitions. [2022-12-13 16:07:31,991 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 16:07:31,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 561 states and 834 transitions. [2022-12-13 16:07:31,993 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 498 [2022-12-13 16:07:31,993 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:31,993 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:31,993 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:31,993 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:31,994 INFO L748 eck$LassoCheckResult]: Stem: 3172#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3173#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3187#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3185#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3186#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 3081#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2924#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2925#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3102#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2936#L441 assume !(0 == ~M_E~0); 2937#L441-2 assume !(0 == ~T1_E~0); 3077#L446-1 assume !(0 == ~T2_E~0); 3038#L451-1 assume !(0 == ~T3_E~0); 3039#L456-1 assume !(0 == ~E_M~0); 3194#L461-1 assume !(0 == ~E_1~0); 3195#L466-1 assume !(0 == ~E_2~0); 3210#L471-1 assume !(0 == ~E_3~0); 2969#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2970#L220 assume 1 == ~m_pc~0; 3030#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3004#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3054#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2999#L543 assume !(0 != activate_threads_~tmp~1#1); 3000#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3170#L239 assume !(1 == ~t1_pc~0); 3168#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3169#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2967#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2968#L551 assume !(0 != activate_threads_~tmp___0~0#1); 3174#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3175#L258 assume 1 == ~t2_pc~0; 3176#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3028#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3029#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3190#L559 assume !(0 != activate_threads_~tmp___1~0#1); 3090#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3091#L277 assume !(1 == ~t3_pc~0); 3133#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2947#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2902#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2903#L567 assume !(0 != activate_threads_~tmp___2~0#1); 2995#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3035#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 3238#L489-2 assume !(1 == ~T1_E~0); 3275#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3113#L499-1 assume !(1 == ~T3_E~0); 3270#L504-1 assume !(1 == ~E_M~0); 3268#L509-1 assume !(1 == ~E_1~0); 3266#L514-1 assume !(1 == ~E_2~0); 3264#L519-1 assume !(1 == ~E_3~0); 3262#L524-1 assume { :end_inline_reset_delta_events } true; 3261#L690-2 [2022-12-13 16:07:31,994 INFO L750 eck$LassoCheckResult]: Loop: 3261#L690-2 assume !false; 2975#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2874#L416 assume !false; 2918#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3010#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3202#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3203#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3180#L369 assume !(0 != eval_~tmp~0#1); 3182#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3115#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3116#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2885#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2886#L446-3 assume !(0 == ~T2_E~0); 3157#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2941#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2942#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3394#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3392#L471-3 assume !(0 == ~E_3~0); 2997#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2998#L220-15 assume 1 == ~m_pc~0; 2891#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2892#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3055#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3056#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3092#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3078#L239-15 assume !(1 == ~t1_pc~0); 3079#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3214#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3226#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3359#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 3357#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3327#L258-15 assume 1 == ~t2_pc~0; 3325#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3324#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3323#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3321#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3319#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3318#L277-15 assume !(1 == ~t3_pc~0); 2897#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2898#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3244#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3313#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2938#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2928#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2929#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3188#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3189#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3057#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2906#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2907#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3127#L519-3 assume !(1 == ~E_3~0); 2955#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2956#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2976#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2981#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3227#L709 assume !(0 == start_simulation_~tmp~3#1); 3145#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3068#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2979#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2965#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2966#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2978#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3119#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3143#L722 assume !(0 != start_simulation_~tmp___0~1#1); 3261#L690-2 [2022-12-13 16:07:31,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:31,994 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2022-12-13 16:07:31,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:31,994 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581686641] [2022-12-13 16:07:31,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:31,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:32,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:32,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:32,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:32,023 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1581686641] [2022-12-13 16:07:32,023 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1581686641] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:32,023 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:32,023 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:07:32,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075084580] [2022-12-13 16:07:32,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:32,024 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:07:32,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:32,024 INFO L85 PathProgramCache]: Analyzing trace with hash -946250240, now seen corresponding path program 1 times [2022-12-13 16:07:32,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:32,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1674461421] [2022-12-13 16:07:32,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:32,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:32,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:32,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:32,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:32,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1674461421] [2022-12-13 16:07:32,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1674461421] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:32,075 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:32,075 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:07:32,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [769752818] [2022-12-13 16:07:32,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:32,075 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:07:32,076 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:32,076 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:07:32,076 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:07:32,076 INFO L87 Difference]: Start difference. First operand 561 states and 834 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:32,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:32,117 INFO L93 Difference]: Finished difference Result 1031 states and 1507 transitions. [2022-12-13 16:07:32,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1031 states and 1507 transitions. [2022-12-13 16:07:32,123 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 967 [2022-12-13 16:07:32,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1031 states to 1031 states and 1507 transitions. [2022-12-13 16:07:32,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1031 [2022-12-13 16:07:32,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1031 [2022-12-13 16:07:32,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1031 states and 1507 transitions. [2022-12-13 16:07:32,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:32,131 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1031 states and 1507 transitions. [2022-12-13 16:07:32,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1031 states and 1507 transitions. [2022-12-13 16:07:32,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1031 to 977. [2022-12-13 16:07:32,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 977 states, 977 states have (on average 1.4667349027635619) internal successors, (1433), 976 states have internal predecessors, (1433), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:32,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 977 states to 977 states and 1433 transitions. [2022-12-13 16:07:32,153 INFO L240 hiAutomatonCegarLoop]: Abstraction has 977 states and 1433 transitions. [2022-12-13 16:07:32,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:07:32,155 INFO L428 stractBuchiCegarLoop]: Abstraction has 977 states and 1433 transitions. [2022-12-13 16:07:32,155 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 16:07:32,155 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 977 states and 1433 transitions. [2022-12-13 16:07:32,158 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 913 [2022-12-13 16:07:32,158 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:32,158 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:32,159 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:32,159 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:32,159 INFO L748 eck$LassoCheckResult]: Stem: 4789#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4806#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4802#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 4695#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4528#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4529#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4717#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4539#L441 assume !(0 == ~M_E~0); 4540#L441-2 assume !(0 == ~T1_E~0); 4690#L446-1 assume !(0 == ~T2_E~0); 4648#L451-1 assume !(0 == ~T3_E~0); 4649#L456-1 assume !(0 == ~E_M~0); 4814#L461-1 assume !(0 == ~E_1~0); 4815#L466-1 assume !(0 == ~E_2~0); 4832#L471-1 assume !(0 == ~E_3~0); 4575#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4576#L220 assume !(1 == ~m_pc~0); 4609#L220-2 is_master_triggered_~__retres1~0#1 := 0; 4610#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4669#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4605#L543 assume !(0 != activate_threads_~tmp~1#1); 4606#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4786#L239 assume !(1 == ~t1_pc~0); 4784#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4785#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4571#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4572#L551 assume !(0 != activate_threads_~tmp___0~0#1); 4791#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4792#L258 assume 1 == ~t2_pc~0; 4793#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4636#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4637#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4812#L559 assume !(0 != activate_threads_~tmp___1~0#1); 4704#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4705#L277 assume !(1 == ~t3_pc~0); 4753#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4551#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4503#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4504#L567 assume !(0 != activate_threads_~tmp___2~0#1); 4601#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4643#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 4887#L489-2 assume !(1 == ~T1_E~0); 5171#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4730#L499-1 assume !(1 == ~T3_E~0); 5170#L504-1 assume !(1 == ~E_M~0); 5169#L509-1 assume !(1 == ~E_1~0); 5168#L514-1 assume !(1 == ~E_2~0); 5167#L519-1 assume !(1 == ~E_3~0); 5158#L524-1 assume { :end_inline_reset_delta_events } true; 4549#L690-2 [2022-12-13 16:07:32,159 INFO L750 eck$LassoCheckResult]: Loop: 4549#L690-2 assume !false; 4550#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4475#L416 assume !false; 4522#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4615#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4558#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4505#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4506#L369 assume !(0 != eval_~tmp~0#1); 4678#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4679#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4733#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5099#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5097#L446-3 assume !(0 == ~T2_E~0); 5094#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5092#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5090#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5088#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5086#L471-3 assume !(0 == ~E_3~0); 5084#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5081#L220-15 assume !(1 == ~m_pc~0); 5079#L220-17 is_master_triggered_~__retres1~0#1 := 0; 5077#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5075#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5073#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5070#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5068#L239-15 assume 1 == ~t1_pc~0; 5065#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5063#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5061#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5059#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 5056#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5055#L258-15 assume 1 == ~t2_pc~0; 5051#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5028#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5025#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5024#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5015#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5010#L277-15 assume !(1 == ~t3_pc~0); 5004#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 4999#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4993#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4989#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4983#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4977#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4969#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4962#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4957#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4947#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4948#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5225#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5223#L519-3 assume !(1 == ~E_3~0); 4927#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4928#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4913#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4914#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4728#L709 assume !(0 == start_simulation_~tmp~3#1); 4482#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4483#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5201#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5200#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5198#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4736#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4737#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5159#L722 assume !(0 != start_simulation_~tmp___0~1#1); 4549#L690-2 [2022-12-13 16:07:32,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:32,159 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2022-12-13 16:07:32,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:32,160 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1522325006] [2022-12-13 16:07:32,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:32,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:32,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:32,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:32,191 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:32,191 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1522325006] [2022-12-13 16:07:32,191 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1522325006] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:32,191 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:32,192 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:07:32,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [377495193] [2022-12-13 16:07:32,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:32,192 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:07:32,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:32,193 INFO L85 PathProgramCache]: Analyzing trace with hash -862799552, now seen corresponding path program 1 times [2022-12-13 16:07:32,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:32,193 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315850199] [2022-12-13 16:07:32,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:32,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:32,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:32,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:32,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:32,235 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1315850199] [2022-12-13 16:07:32,235 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1315850199] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:32,235 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:32,235 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:07:32,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498612160] [2022-12-13 16:07:32,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:32,236 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:07:32,236 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:32,236 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 16:07:32,236 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 16:07:32,237 INFO L87 Difference]: Start difference. First operand 977 states and 1433 transitions. cyclomatic complexity: 460 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:32,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:32,338 INFO L93 Difference]: Finished difference Result 2207 states and 3186 transitions. [2022-12-13 16:07:32,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2207 states and 3186 transitions. [2022-12-13 16:07:32,352 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2074 [2022-12-13 16:07:32,363 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2207 states to 2207 states and 3186 transitions. [2022-12-13 16:07:32,363 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2207 [2022-12-13 16:07:32,365 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2207 [2022-12-13 16:07:32,365 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2207 states and 3186 transitions. [2022-12-13 16:07:32,368 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:32,368 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2207 states and 3186 transitions. [2022-12-13 16:07:32,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2207 states and 3186 transitions. [2022-12-13 16:07:32,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2207 to 1745. [2022-12-13 16:07:32,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1745 states, 1745 states have (on average 1.4573065902578797) internal successors, (2543), 1744 states have internal predecessors, (2543), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:32,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1745 states to 1745 states and 2543 transitions. [2022-12-13 16:07:32,414 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1745 states and 2543 transitions. [2022-12-13 16:07:32,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:07:32,415 INFO L428 stractBuchiCegarLoop]: Abstraction has 1745 states and 2543 transitions. [2022-12-13 16:07:32,415 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 16:07:32,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1745 states and 2543 transitions. [2022-12-13 16:07:32,423 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1680 [2022-12-13 16:07:32,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:32,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:32,425 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:32,425 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:32,425 INFO L748 eck$LassoCheckResult]: Stem: 7980#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 7981#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7992#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7990#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7991#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 7885#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7721#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7722#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7907#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7734#L441 assume !(0 == ~M_E~0); 7735#L441-2 assume !(0 == ~T1_E~0); 7881#L446-1 assume !(0 == ~T2_E~0); 7842#L451-1 assume !(0 == ~T3_E~0); 7843#L456-1 assume !(0 == ~E_M~0); 7998#L461-1 assume !(0 == ~E_1~0); 7999#L466-1 assume !(0 == ~E_2~0); 8012#L471-1 assume !(0 == ~E_3~0); 7768#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7769#L220 assume !(1 == ~m_pc~0); 7803#L220-2 is_master_triggered_~__retres1~0#1 := 0; 7804#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7858#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7799#L543 assume !(0 != activate_threads_~tmp~1#1); 7800#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7979#L239 assume !(1 == ~t1_pc~0); 7977#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7978#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7766#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7767#L551 assume !(0 != activate_threads_~tmp___0~0#1); 7982#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7983#L258 assume !(1 == ~t2_pc~0); 7984#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7831#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7832#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7995#L559 assume !(0 != activate_threads_~tmp___1~0#1); 7894#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7895#L277 assume !(1 == ~t3_pc~0); 7944#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7746#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7699#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7700#L567 assume !(0 != activate_threads_~tmp___2~0#1); 7795#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7839#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 7996#L489-2 assume !(1 == ~T1_E~0); 7997#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7784#L499-1 assume !(1 == ~T3_E~0); 7785#L504-1 assume !(1 == ~E_M~0); 8016#L509-1 assume !(1 == ~E_1~0); 8017#L514-1 assume !(1 == ~E_2~0); 7957#L519-1 assume !(1 == ~E_3~0); 7958#L524-1 assume { :end_inline_reset_delta_events } true; 9342#L690-2 [2022-12-13 16:07:32,425 INFO L750 eck$LassoCheckResult]: Loop: 9342#L690-2 assume !false; 9336#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7714#L416 assume !false; 7715#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9331#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9328#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9327#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9291#L369 assume !(0 != eval_~tmp~0#1); 9292#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9376#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9374#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9375#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9412#L446-3 assume !(0 == ~T2_E~0); 9411#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9410#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9409#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9408#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9407#L471-3 assume !(0 == ~E_3~0); 9406#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9405#L220-15 assume !(1 == ~m_pc~0); 9404#L220-17 is_master_triggered_~__retres1~0#1 := 0; 9403#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9402#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9401#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9400#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9399#L239-15 assume 1 == ~t1_pc~0; 9397#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9396#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9395#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9394#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 9393#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9392#L258-15 assume !(1 == ~t2_pc~0); 8340#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 9391#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9390#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9389#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9388#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9387#L277-15 assume !(1 == ~t3_pc~0); 9385#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 9384#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8008#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8009#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8021#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7725#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7726#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7993#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7994#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7862#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7703#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7704#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7938#L519-3 assume !(1 == ~E_3~0); 7754#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 7755#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9356#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8030#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 8031#L709 assume !(0 == start_simulation_~tmp~3#1); 7956#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9353#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 7778#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 7779#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 9346#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9345#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7952#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7953#L722 assume !(0 != start_simulation_~tmp___0~1#1); 9342#L690-2 [2022-12-13 16:07:32,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:32,426 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2022-12-13 16:07:32,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:32,426 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1832496659] [2022-12-13 16:07:32,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:32,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:32,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:32,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:32,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:32,467 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1832496659] [2022-12-13 16:07:32,467 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1832496659] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:32,467 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:32,467 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:07:32,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561270997] [2022-12-13 16:07:32,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:32,468 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:07:32,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:32,468 INFO L85 PathProgramCache]: Analyzing trace with hash 1855609985, now seen corresponding path program 1 times [2022-12-13 16:07:32,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:32,469 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460154893] [2022-12-13 16:07:32,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:32,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:32,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:32,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:32,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:32,511 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1460154893] [2022-12-13 16:07:32,511 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1460154893] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:32,511 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:32,511 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:07:32,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1117264458] [2022-12-13 16:07:32,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:32,512 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:07:32,512 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:32,512 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:07:32,513 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:07:32,513 INFO L87 Difference]: Start difference. First operand 1745 states and 2543 transitions. cyclomatic complexity: 802 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:32,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:32,544 INFO L93 Difference]: Finished difference Result 2543 states and 3704 transitions. [2022-12-13 16:07:32,544 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2543 states and 3704 transitions. [2022-12-13 16:07:32,554 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2478 [2022-12-13 16:07:32,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2543 states to 2543 states and 3704 transitions. [2022-12-13 16:07:32,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2543 [2022-12-13 16:07:32,569 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2543 [2022-12-13 16:07:32,569 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2543 states and 3704 transitions. [2022-12-13 16:07:32,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:32,571 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2543 states and 3704 transitions. [2022-12-13 16:07:32,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2543 states and 3704 transitions. [2022-12-13 16:07:32,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2543 to 1769. [2022-12-13 16:07:32,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1769 states, 1769 states have (on average 1.4601469756924816) internal successors, (2583), 1768 states have internal predecessors, (2583), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:32,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1769 states to 1769 states and 2583 transitions. [2022-12-13 16:07:32,595 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1769 states and 2583 transitions. [2022-12-13 16:07:32,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:07:32,596 INFO L428 stractBuchiCegarLoop]: Abstraction has 1769 states and 2583 transitions. [2022-12-13 16:07:32,596 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 16:07:32,596 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1769 states and 2583 transitions. [2022-12-13 16:07:32,605 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1712 [2022-12-13 16:07:32,605 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:32,605 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:32,606 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:32,606 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:32,606 INFO L748 eck$LassoCheckResult]: Stem: 12253#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 12254#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12266#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12264#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12265#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 12171#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12017#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12018#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12192#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12030#L441 assume !(0 == ~M_E~0); 12031#L441-2 assume !(0 == ~T1_E~0); 12167#L446-1 assume !(0 == ~T2_E~0); 12130#L451-1 assume !(0 == ~T3_E~0); 12131#L456-1 assume !(0 == ~E_M~0); 12270#L461-1 assume !(0 == ~E_1~0); 12271#L466-1 assume !(0 == ~E_2~0); 12285#L471-1 assume !(0 == ~E_3~0); 12063#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12064#L220 assume !(1 == ~m_pc~0); 12096#L220-2 is_master_triggered_~__retres1~0#1 := 0; 12097#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12145#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12092#L543 assume !(0 != activate_threads_~tmp~1#1); 12093#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12252#L239 assume !(1 == ~t1_pc~0); 12250#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12251#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12061#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12062#L551 assume !(0 != activate_threads_~tmp___0~0#1); 12255#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12256#L258 assume !(1 == ~t2_pc~0); 12257#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12121#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12122#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12268#L559 assume !(0 != activate_threads_~tmp___1~0#1); 12178#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12179#L277 assume !(1 == ~t3_pc~0); 12226#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12041#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11996#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11997#L567 assume !(0 != activate_threads_~tmp___2~0#1); 12088#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12127#L489 assume !(1 == ~M_E~0); 12269#L489-2 assume !(1 == ~T1_E~0); 12204#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12077#L499-1 assume !(1 == ~T3_E~0); 12078#L504-1 assume !(1 == ~E_M~0); 12172#L509-1 assume !(1 == ~E_1~0); 12067#L514-1 assume !(1 == ~E_2~0); 12068#L519-1 assume !(1 == ~E_3~0); 12073#L524-1 assume { :end_inline_reset_delta_events } true; 12039#L690-2 [2022-12-13 16:07:32,606 INFO L750 eck$LassoCheckResult]: Loop: 12039#L690-2 assume !false; 12040#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11968#L416 assume !false; 12011#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12102#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12048#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11998#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11999#L369 assume !(0 != eval_~tmp~0#1); 12261#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13731#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12244#L441-3 assume !(0 == ~M_E~0); 11979#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11980#L446-3 assume !(0 == ~T2_E~0); 12240#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12035#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12036#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12101#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12212#L471-3 assume !(0 == ~E_3~0); 12090#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12091#L220-15 assume !(1 == ~m_pc~0); 12146#L220-17 is_master_triggered_~__retres1~0#1 := 0; 12218#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12147#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12148#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12180#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12168#L239-15 assume !(1 == ~t1_pc~0); 12169#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 12291#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12125#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12019#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 12020#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12316#L258-15 assume !(1 == ~t2_pc~0); 12128#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 12129#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12300#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12301#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12272#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12273#L277-15 assume 1 == ~t3_pc~0; 12100#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11992#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12281#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12282#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12032#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12021#L489-3 assume !(1 == ~M_E~0); 12022#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12231#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12267#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12149#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12000#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12001#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12221#L519-3 assume !(1 == ~E_3~0); 12049#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12050#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12069#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12074#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 12205#L709 assume !(0 == start_simulation_~tmp~3#1); 11977#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11978#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12072#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12059#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 12060#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 12071#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12213#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 12120#L722 assume !(0 != start_simulation_~tmp___0~1#1); 12039#L690-2 [2022-12-13 16:07:32,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:32,607 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2022-12-13 16:07:32,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:32,607 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447416389] [2022-12-13 16:07:32,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:32,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:32,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:32,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:32,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:32,636 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447416389] [2022-12-13 16:07:32,636 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [447416389] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:32,636 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:32,636 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:07:32,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844616102] [2022-12-13 16:07:32,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:32,637 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:07:32,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:32,637 INFO L85 PathProgramCache]: Analyzing trace with hash -425047231, now seen corresponding path program 1 times [2022-12-13 16:07:32,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:32,637 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1254519776] [2022-12-13 16:07:32,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:32,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:32,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:32,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:32,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:32,664 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1254519776] [2022-12-13 16:07:32,664 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1254519776] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:32,664 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:32,664 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:07:32,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [494962379] [2022-12-13 16:07:32,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:32,665 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:07:32,665 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:32,665 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 16:07:32,666 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 16:07:32,666 INFO L87 Difference]: Start difference. First operand 1769 states and 2583 transitions. cyclomatic complexity: 816 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:32,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:32,712 INFO L93 Difference]: Finished difference Result 2537 states and 3672 transitions. [2022-12-13 16:07:32,712 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2537 states and 3672 transitions. [2022-12-13 16:07:32,722 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2478 [2022-12-13 16:07:32,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2537 states to 2537 states and 3672 transitions. [2022-12-13 16:07:32,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2537 [2022-12-13 16:07:32,747 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2537 [2022-12-13 16:07:32,747 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2537 states and 3672 transitions. [2022-12-13 16:07:32,752 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:32,752 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2537 states and 3672 transitions. [2022-12-13 16:07:32,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2537 states and 3672 transitions. [2022-12-13 16:07:32,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2537 to 1769. [2022-12-13 16:07:32,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1769 states, 1769 states have (on average 1.4505370265686828) internal successors, (2566), 1768 states have internal predecessors, (2566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:32,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1769 states to 1769 states and 2566 transitions. [2022-12-13 16:07:32,785 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1769 states and 2566 transitions. [2022-12-13 16:07:32,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:07:32,786 INFO L428 stractBuchiCegarLoop]: Abstraction has 1769 states and 2566 transitions. [2022-12-13 16:07:32,786 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 16:07:32,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1769 states and 2566 transitions. [2022-12-13 16:07:32,798 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1712 [2022-12-13 16:07:32,798 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:32,798 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:32,799 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:32,799 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:32,800 INFO L748 eck$LassoCheckResult]: Stem: 16579#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 16580#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16592#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16590#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16591#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 16494#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16333#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16334#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16515#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16346#L441 assume !(0 == ~M_E~0); 16347#L441-2 assume !(0 == ~T1_E~0); 16490#L446-1 assume !(0 == ~T2_E~0); 16450#L451-1 assume !(0 == ~T3_E~0); 16451#L456-1 assume !(0 == ~E_M~0); 16596#L461-1 assume !(0 == ~E_1~0); 16597#L466-1 assume !(0 == ~E_2~0); 16612#L471-1 assume !(0 == ~E_3~0); 16379#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16380#L220 assume !(1 == ~m_pc~0); 16413#L220-2 is_master_triggered_~__retres1~0#1 := 0; 16414#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16465#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16409#L543 assume !(0 != activate_threads_~tmp~1#1); 16410#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16578#L239 assume !(1 == ~t1_pc~0); 16576#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16577#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16377#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16378#L551 assume !(0 != activate_threads_~tmp___0~0#1); 16581#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16582#L258 assume !(1 == ~t2_pc~0); 16583#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16439#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16440#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16594#L559 assume !(0 != activate_threads_~tmp___1~0#1); 16501#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16502#L277 assume !(1 == ~t3_pc~0); 16553#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16357#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16312#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16313#L567 assume !(0 != activate_threads_~tmp___2~0#1); 16405#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16447#L489 assume !(1 == ~M_E~0); 16595#L489-2 assume !(1 == ~T1_E~0); 16528#L494-1 assume !(1 == ~T2_E~0); 16394#L499-1 assume !(1 == ~T3_E~0); 16395#L504-1 assume !(1 == ~E_M~0); 16495#L509-1 assume !(1 == ~E_1~0); 16383#L514-1 assume !(1 == ~E_2~0); 16384#L519-1 assume !(1 == ~E_3~0); 16389#L524-1 assume { :end_inline_reset_delta_events } true; 16390#L690-2 [2022-12-13 16:07:32,800 INFO L750 eck$LassoCheckResult]: Loop: 16390#L690-2 assume !false; 17878#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17873#L416 assume !false; 17871#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17847#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17843#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17841#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 17840#L369 assume !(0 != eval_~tmp~0#1); 16478#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16479#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16533#L441-3 assume !(0 == ~M_E~0); 16295#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16296#L446-3 assume !(0 == ~T2_E~0); 16567#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16351#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16352#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16418#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16618#L471-3 assume !(0 == ~E_3~0); 16407#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16408#L220-15 assume !(1 == ~m_pc~0); 16466#L220-17 is_master_triggered_~__retres1~0#1 := 0; 18049#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18048#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18047#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18046#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18045#L239-15 assume 1 == ~t1_pc~0; 18043#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18042#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18025#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18023#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 16650#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16651#L258-15 assume !(1 == ~t2_pc~0); 17954#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 18017#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18015#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18012#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18009#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18005#L277-15 assume !(1 == ~t3_pc~0); 18000#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 17997#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17992#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16624#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16348#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16337#L489-3 assume !(1 == ~M_E~0); 16338#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17634#L494-3 assume !(1 == ~T2_E~0); 16753#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16746#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16739#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16729#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16721#L519-3 assume !(1 == ~E_3~0); 16717#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16705#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16696#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16692#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 16687#L709 assume !(0 == start_simulation_~tmp~3#1); 16688#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17894#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17890#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17888#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 17886#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 17885#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17884#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 17881#L722 assume !(0 != start_simulation_~tmp___0~1#1); 16390#L690-2 [2022-12-13 16:07:32,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:32,800 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2022-12-13 16:07:32,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:32,800 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [316658607] [2022-12-13 16:07:32,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:32,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:32,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:32,808 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:32,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:32,830 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:32,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:32,831 INFO L85 PathProgramCache]: Analyzing trace with hash 1465387075, now seen corresponding path program 1 times [2022-12-13 16:07:32,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:32,831 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [465754228] [2022-12-13 16:07:32,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:32,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:32,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:32,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:32,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:32,862 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [465754228] [2022-12-13 16:07:32,862 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [465754228] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:32,862 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:32,862 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:07:32,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243564285] [2022-12-13 16:07:32,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:32,863 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:07:32,863 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:32,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 16:07:32,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 16:07:32,864 INFO L87 Difference]: Start difference. First operand 1769 states and 2566 transitions. cyclomatic complexity: 799 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:32,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:32,937 INFO L93 Difference]: Finished difference Result 3093 states and 4410 transitions. [2022-12-13 16:07:32,937 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3093 states and 4410 transitions. [2022-12-13 16:07:32,954 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3032 [2022-12-13 16:07:32,967 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3093 states to 3093 states and 4410 transitions. [2022-12-13 16:07:32,967 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3093 [2022-12-13 16:07:32,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3093 [2022-12-13 16:07:32,970 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3093 states and 4410 transitions. [2022-12-13 16:07:32,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:32,974 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3093 states and 4410 transitions. [2022-12-13 16:07:32,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3093 states and 4410 transitions. [2022-12-13 16:07:33,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3093 to 1793. [2022-12-13 16:07:33,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1793 states, 1793 states have (on average 1.4445064138315673) internal successors, (2590), 1792 states have internal predecessors, (2590), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:33,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1793 states to 1793 states and 2590 transitions. [2022-12-13 16:07:33,012 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1793 states and 2590 transitions. [2022-12-13 16:07:33,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 16:07:33,013 INFO L428 stractBuchiCegarLoop]: Abstraction has 1793 states and 2590 transitions. [2022-12-13 16:07:33,013 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 16:07:33,013 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1793 states and 2590 transitions. [2022-12-13 16:07:33,020 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1736 [2022-12-13 16:07:33,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:33,020 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:33,021 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:33,021 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:33,021 INFO L748 eck$LassoCheckResult]: Stem: 21463#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 21464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 21475#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21473#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21474#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 21379#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21211#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21212#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21400#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21224#L441 assume !(0 == ~M_E~0); 21225#L441-2 assume !(0 == ~T1_E~0); 21375#L446-1 assume !(0 == ~T2_E~0); 21333#L451-1 assume !(0 == ~T3_E~0); 21334#L456-1 assume !(0 == ~E_M~0); 21481#L461-1 assume !(0 == ~E_1~0); 21482#L466-1 assume !(0 == ~E_2~0); 21498#L471-1 assume !(0 == ~E_3~0); 21259#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21260#L220 assume !(1 == ~m_pc~0); 21293#L220-2 is_master_triggered_~__retres1~0#1 := 0; 21294#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21348#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21289#L543 assume !(0 != activate_threads_~tmp~1#1); 21290#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21462#L239 assume !(1 == ~t1_pc~0); 21460#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21461#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21257#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21258#L551 assume !(0 != activate_threads_~tmp___0~0#1); 21465#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21466#L258 assume !(1 == ~t2_pc~0); 21467#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21322#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21323#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21478#L559 assume !(0 != activate_threads_~tmp___1~0#1); 21386#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21387#L277 assume !(1 == ~t3_pc~0); 21436#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21236#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21190#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21191#L567 assume !(0 != activate_threads_~tmp___2~0#1); 21285#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21330#L489 assume !(1 == ~M_E~0); 21479#L489-2 assume !(1 == ~T1_E~0); 21412#L494-1 assume !(1 == ~T2_E~0); 21274#L499-1 assume !(1 == ~T3_E~0); 21275#L504-1 assume !(1 == ~E_M~0); 21380#L509-1 assume !(1 == ~E_1~0); 21263#L514-1 assume !(1 == ~E_2~0); 21264#L519-1 assume !(1 == ~E_3~0); 21270#L524-1 assume { :end_inline_reset_delta_events } true; 21234#L690-2 [2022-12-13 16:07:33,021 INFO L750 eck$LassoCheckResult]: Loop: 21234#L690-2 assume !false; 21235#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21162#L416 assume !false; 21205#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 22736#L332 assume !(0 == ~m_st~0); 22737#L336 assume !(0 == ~t1_st~0); 22734#L340 assume !(0 == ~t2_st~0); 22735#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 22711#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22708#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22709#L369 assume !(0 != eval_~tmp~0#1); 21363#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21364#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21415#L441-3 assume !(0 == ~M_E~0); 21454#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21501#L446-3 assume !(0 == ~T2_E~0); 21502#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21230#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21231#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21419#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21420#L471-3 assume !(0 == ~E_3~0); 21287#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21288#L220-15 assume !(1 == ~m_pc~0); 21349#L220-17 is_master_triggered_~__retres1~0#1 := 0; 22664#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22665#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22658#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22659#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22651#L239-15 assume !(1 == ~t1_pc~0); 22652#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 21522#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21523#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22899#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 21546#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21547#L258-15 assume !(1 == ~t2_pc~0); 21685#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 21518#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21519#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21520#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22897#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22896#L277-15 assume !(1 == ~t3_pc~0); 21185#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 21186#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22895#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21509#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21510#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21215#L489-3 assume !(1 == ~M_E~0); 21216#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21440#L494-3 assume !(1 == ~T2_E~0); 21534#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21535#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21194#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21195#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21429#L519-3 assume !(1 == ~E_3~0); 21430#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21265#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21266#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21271#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 21413#L709 assume !(0 == start_simulation_~tmp~3#1); 21171#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21172#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 22911#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22910#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 22909#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 22908#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22907#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 21321#L722 assume !(0 != start_simulation_~tmp___0~1#1); 21234#L690-2 [2022-12-13 16:07:33,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:33,021 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2022-12-13 16:07:33,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:33,022 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1451793857] [2022-12-13 16:07:33,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:33,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:33,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:33,030 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:33,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:33,040 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:33,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:33,040 INFO L85 PathProgramCache]: Analyzing trace with hash -2116089398, now seen corresponding path program 1 times [2022-12-13 16:07:33,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:33,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2054659346] [2022-12-13 16:07:33,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:33,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:33,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:33,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:33,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:33,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2054659346] [2022-12-13 16:07:33,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2054659346] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:33,075 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:33,075 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:07:33,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1187244935] [2022-12-13 16:07:33,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:33,075 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:07:33,076 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:33,076 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 16:07:33,076 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 16:07:33,076 INFO L87 Difference]: Start difference. First operand 1793 states and 2590 transitions. cyclomatic complexity: 799 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:33,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:33,190 INFO L93 Difference]: Finished difference Result 5813 states and 8306 transitions. [2022-12-13 16:07:33,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5813 states and 8306 transitions. [2022-12-13 16:07:33,229 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5744 [2022-12-13 16:07:33,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5813 states to 5813 states and 8306 transitions. [2022-12-13 16:07:33,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5813 [2022-12-13 16:07:33,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5813 [2022-12-13 16:07:33,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5813 states and 8306 transitions. [2022-12-13 16:07:33,264 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:33,264 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5813 states and 8306 transitions. [2022-12-13 16:07:33,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5813 states and 8306 transitions. [2022-12-13 16:07:33,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5813 to 1817. [2022-12-13 16:07:33,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1817 states, 1817 states have (on average 1.4386351128233352) internal successors, (2614), 1816 states have internal predecessors, (2614), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:33,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1817 states to 1817 states and 2614 transitions. [2022-12-13 16:07:33,303 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1817 states and 2614 transitions. [2022-12-13 16:07:33,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 16:07:33,304 INFO L428 stractBuchiCegarLoop]: Abstraction has 1817 states and 2614 transitions. [2022-12-13 16:07:33,304 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 16:07:33,304 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1817 states and 2614 transitions. [2022-12-13 16:07:33,308 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1760 [2022-12-13 16:07:33,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:33,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:33,309 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:33,309 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:33,309 INFO L748 eck$LassoCheckResult]: Stem: 29083#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 29084#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 29096#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29094#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29095#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 28996#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28836#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28837#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29018#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28846#L441 assume !(0 == ~M_E~0); 28847#L441-2 assume !(0 == ~T1_E~0); 28992#L446-1 assume !(0 == ~T2_E~0); 28955#L451-1 assume !(0 == ~T3_E~0); 28956#L456-1 assume !(0 == ~E_M~0); 29101#L461-1 assume !(0 == ~E_1~0); 29102#L466-1 assume !(0 == ~E_2~0); 29118#L471-1 assume !(0 == ~E_3~0); 28882#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28883#L220 assume !(1 == ~m_pc~0); 28915#L220-2 is_master_triggered_~__retres1~0#1 := 0; 28916#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28973#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28913#L543 assume !(0 != activate_threads_~tmp~1#1); 28914#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29082#L239 assume !(1 == ~t1_pc~0); 29080#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29081#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28878#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28879#L551 assume !(0 != activate_threads_~tmp___0~0#1); 29085#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29086#L258 assume !(1 == ~t2_pc~0); 29087#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28942#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28943#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29099#L559 assume !(0 != activate_threads_~tmp___1~0#1); 29005#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29006#L277 assume !(1 == ~t3_pc~0); 29060#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28857#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28815#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28816#L567 assume !(0 != activate_threads_~tmp___2~0#1); 28907#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28950#L489 assume !(1 == ~M_E~0); 29100#L489-2 assume !(1 == ~T1_E~0); 29034#L494-1 assume !(1 == ~T2_E~0); 28898#L499-1 assume !(1 == ~T3_E~0); 28899#L504-1 assume !(1 == ~E_M~0); 28997#L509-1 assume !(1 == ~E_1~0); 28885#L514-1 assume !(1 == ~E_2~0); 28886#L519-1 assume !(1 == ~E_3~0); 28891#L524-1 assume { :end_inline_reset_delta_events } true; 28892#L690-2 [2022-12-13 16:07:33,309 INFO L750 eck$LassoCheckResult]: Loop: 28892#L690-2 assume !false; 30232#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30226#L416 assume !false; 30123#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30121#L332 assume !(0 == ~m_st~0); 30118#L336 assume !(0 == ~t1_st~0); 30115#L340 assume !(0 == ~t2_st~0); 30111#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 30108#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30103#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30099#L369 assume !(0 != eval_~tmp~0#1); 30096#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29036#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29037#L441-3 assume !(0 == ~M_E~0); 28796#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28797#L446-3 assume !(0 == ~T2_E~0); 29071#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28853#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28854#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29042#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29043#L471-3 assume !(0 == ~E_3~0); 28909#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28910#L220-15 assume !(1 == ~m_pc~0); 28970#L220-17 is_master_triggered_~__retres1~0#1 := 0; 29050#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28971#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28972#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29097#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30418#L239-15 assume !(1 == ~t1_pc~0); 29124#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 29125#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30417#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30416#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 30415#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30414#L258-15 assume !(1 == ~t2_pc~0); 29160#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 30413#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30412#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29157#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29103#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29104#L277-15 assume !(1 == ~t3_pc~0); 30409#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 29156#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29114#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 29115#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28850#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28838#L489-3 assume !(1 == ~M_E~0); 28839#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29062#L494-3 assume !(1 == ~T2_E~0); 29098#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28968#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28969#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30400#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30399#L519-3 assume !(1 == ~E_3~0); 30398#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30396#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 30389#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30385#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 30381#L709 assume !(0 == start_simulation_~tmp~3#1); 30246#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30244#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 30241#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30239#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 30237#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30235#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30234#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 30233#L722 assume !(0 != start_simulation_~tmp___0~1#1); 28892#L690-2 [2022-12-13 16:07:33,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:33,309 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2022-12-13 16:07:33,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:33,310 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [556439830] [2022-12-13 16:07:33,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:33,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:33,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:33,315 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:33,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:33,323 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:33,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:33,323 INFO L85 PathProgramCache]: Analyzing trace with hash -2116148980, now seen corresponding path program 1 times [2022-12-13 16:07:33,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:33,324 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134817800] [2022-12-13 16:07:33,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:33,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:33,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:33,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:33,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:33,382 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [134817800] [2022-12-13 16:07:33,382 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [134817800] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:33,382 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:33,382 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:07:33,382 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [694131636] [2022-12-13 16:07:33,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:33,383 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:07:33,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:33,383 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 16:07:33,383 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 16:07:33,383 INFO L87 Difference]: Start difference. First operand 1817 states and 2614 transitions. cyclomatic complexity: 799 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:33,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:33,531 INFO L93 Difference]: Finished difference Result 3575 states and 5111 transitions. [2022-12-13 16:07:33,531 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3575 states and 5111 transitions. [2022-12-13 16:07:33,543 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3518 [2022-12-13 16:07:33,553 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3575 states to 3575 states and 5111 transitions. [2022-12-13 16:07:33,553 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3575 [2022-12-13 16:07:33,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3575 [2022-12-13 16:07:33,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3575 states and 5111 transitions. [2022-12-13 16:07:33,559 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:33,559 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3575 states and 5111 transitions. [2022-12-13 16:07:33,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3575 states and 5111 transitions. [2022-12-13 16:07:33,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3575 to 1877. [2022-12-13 16:07:33,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1877 states, 1877 states have (on average 1.4155567394778903) internal successors, (2657), 1876 states have internal predecessors, (2657), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:33,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1877 states to 1877 states and 2657 transitions. [2022-12-13 16:07:33,592 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1877 states and 2657 transitions. [2022-12-13 16:07:33,592 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 16:07:33,593 INFO L428 stractBuchiCegarLoop]: Abstraction has 1877 states and 2657 transitions. [2022-12-13 16:07:33,593 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 16:07:33,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1877 states and 2657 transitions. [2022-12-13 16:07:33,596 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1820 [2022-12-13 16:07:33,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:33,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:33,597 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:33,597 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:33,597 INFO L748 eck$LassoCheckResult]: Stem: 34508#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 34509#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 34526#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34520#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34521#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 34410#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34242#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34243#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34432#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34252#L441 assume !(0 == ~M_E~0); 34253#L441-2 assume !(0 == ~T1_E~0); 34406#L446-1 assume !(0 == ~T2_E~0); 34363#L451-1 assume !(0 == ~T3_E~0); 34364#L456-1 assume !(0 == ~E_M~0); 34534#L461-1 assume !(0 == ~E_1~0); 34535#L466-1 assume !(0 == ~E_2~0); 34551#L471-1 assume !(0 == ~E_3~0); 34289#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34290#L220 assume !(1 == ~m_pc~0); 34321#L220-2 is_master_triggered_~__retres1~0#1 := 0; 34322#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34383#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34319#L543 assume !(0 != activate_threads_~tmp~1#1); 34320#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34505#L239 assume !(1 == ~t1_pc~0); 34503#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34504#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34285#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34286#L551 assume !(0 != activate_threads_~tmp___0~0#1); 34510#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34511#L258 assume !(1 == ~t2_pc~0); 34512#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34351#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34352#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34531#L559 assume !(0 != activate_threads_~tmp___1~0#1); 34419#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34420#L277 assume !(1 == ~t3_pc~0); 34473#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34263#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34220#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34221#L567 assume !(0 != activate_threads_~tmp___2~0#1); 34313#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34360#L489 assume !(1 == ~M_E~0); 34533#L489-2 assume !(1 == ~T1_E~0); 34446#L494-1 assume !(1 == ~T2_E~0); 34302#L499-1 assume !(1 == ~T3_E~0); 34303#L504-1 assume !(1 == ~E_M~0); 34411#L509-1 assume !(1 == ~E_1~0); 34291#L514-1 assume !(1 == ~E_2~0); 34292#L519-1 assume !(1 == ~E_3~0); 34297#L524-1 assume { :end_inline_reset_delta_events } true; 34298#L690-2 [2022-12-13 16:07:33,597 INFO L750 eck$LassoCheckResult]: Loop: 34298#L690-2 assume !false; 35363#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35359#L416 assume !false; 35358#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 35356#L332 assume !(0 == ~m_st~0); 35357#L336 assume !(0 == ~t1_st~0); 35353#L340 assume !(0 == ~t2_st~0); 35354#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 35355#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 35349#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 35350#L369 assume !(0 != eval_~tmp~0#1); 35567#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35566#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35565#L441-3 assume !(0 == ~M_E~0); 35564#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35563#L446-3 assume !(0 == ~T2_E~0); 35562#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35561#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35560#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35559#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35558#L471-3 assume !(0 == ~E_3~0); 34314#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34315#L220-15 assume !(1 == ~m_pc~0); 34379#L220-17 is_master_triggered_~__retres1~0#1 := 0; 35335#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35333#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 35331#L543-15 assume !(0 != activate_threads_~tmp~1#1); 35329#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35327#L239-15 assume 1 == ~t1_pc~0; 35324#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35321#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35319#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 35317#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 35315#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35313#L258-15 assume !(1 == ~t2_pc~0); 34722#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 35311#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35309#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 35307#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35305#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35303#L277-15 assume !(1 == ~t3_pc~0); 35300#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 35297#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35295#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 35292#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35289#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35286#L489-3 assume !(1 == ~M_E~0); 35283#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35280#L494-3 assume !(1 == ~T2_E~0); 35276#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35273#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35270#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35267#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35264#L519-3 assume !(1 == ~E_3~0); 35177#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 35178#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 35115#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 35116#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 34444#L709 assume !(0 == start_simulation_~tmp~3#1); 34445#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 35385#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 35380#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 35377#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 35374#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35371#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35369#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 35366#L722 assume !(0 != start_simulation_~tmp___0~1#1); 34298#L690-2 [2022-12-13 16:07:33,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:33,598 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 4 times [2022-12-13 16:07:33,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:33,598 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006681014] [2022-12-13 16:07:33,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:33,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:33,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:33,603 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:33,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:33,611 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:33,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:33,612 INFO L85 PathProgramCache]: Analyzing trace with hash -735573875, now seen corresponding path program 1 times [2022-12-13 16:07:33,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:33,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714356880] [2022-12-13 16:07:33,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:33,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:33,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:33,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:33,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:33,632 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1714356880] [2022-12-13 16:07:33,632 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1714356880] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:33,632 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:33,632 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:07:33,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1797777376] [2022-12-13 16:07:33,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:33,633 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:07:33,633 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:33,633 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:07:33,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:07:33,633 INFO L87 Difference]: Start difference. First operand 1877 states and 2657 transitions. cyclomatic complexity: 782 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:33,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:33,671 INFO L93 Difference]: Finished difference Result 2868 states and 3998 transitions. [2022-12-13 16:07:33,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2868 states and 3998 transitions. [2022-12-13 16:07:33,678 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2811 [2022-12-13 16:07:33,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2868 states to 2868 states and 3998 transitions. [2022-12-13 16:07:33,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2868 [2022-12-13 16:07:33,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2868 [2022-12-13 16:07:33,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2868 states and 3998 transitions. [2022-12-13 16:07:33,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:33,688 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2868 states and 3998 transitions. [2022-12-13 16:07:33,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2868 states and 3998 transitions. [2022-12-13 16:07:33,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2868 to 2778. [2022-12-13 16:07:33,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2778 states, 2778 states have (on average 1.3952483801295896) internal successors, (3876), 2777 states have internal predecessors, (3876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:33,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2778 states to 2778 states and 3876 transitions. [2022-12-13 16:07:33,743 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2778 states and 3876 transitions. [2022-12-13 16:07:33,744 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:07:33,744 INFO L428 stractBuchiCegarLoop]: Abstraction has 2778 states and 3876 transitions. [2022-12-13 16:07:33,744 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 16:07:33,744 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2778 states and 3876 transitions. [2022-12-13 16:07:33,749 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2721 [2022-12-13 16:07:33,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:33,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:33,750 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:33,750 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:33,750 INFO L748 eck$LassoCheckResult]: Stem: 39252#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 39253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 39268#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39263#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39264#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 39159#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38992#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38993#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39180#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39002#L441 assume !(0 == ~M_E~0); 39003#L441-2 assume !(0 == ~T1_E~0); 39155#L446-1 assume !(0 == ~T2_E~0); 39114#L451-1 assume !(0 == ~T3_E~0); 39115#L456-1 assume !(0 == ~E_M~0); 39278#L461-1 assume !(0 == ~E_1~0); 39279#L466-1 assume !(0 == ~E_2~0); 39294#L471-1 assume !(0 == ~E_3~0); 39038#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39039#L220 assume !(1 == ~m_pc~0); 39072#L220-2 is_master_triggered_~__retres1~0#1 := 0; 39073#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39134#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 39070#L543 assume !(0 != activate_threads_~tmp~1#1); 39071#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39249#L239 assume !(1 == ~t1_pc~0); 39246#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39247#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39034#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 39035#L551 assume !(0 != activate_threads_~tmp___0~0#1); 39254#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39255#L258 assume !(1 == ~t2_pc~0); 39256#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39101#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39102#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39274#L559 assume !(0 != activate_threads_~tmp___1~0#1); 39167#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39168#L277 assume !(1 == ~t3_pc~0); 39218#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39013#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38971#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38972#L567 assume !(0 != activate_threads_~tmp___2~0#1); 39064#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39109#L489 assume !(1 == ~M_E~0); 39275#L489-2 assume !(1 == ~T1_E~0); 39197#L494-1 assume !(1 == ~T2_E~0); 39055#L499-1 assume !(1 == ~T3_E~0); 39056#L504-1 assume !(1 == ~E_M~0); 39160#L509-1 assume !(1 == ~E_1~0); 39041#L514-1 assume !(1 == ~E_2~0); 39042#L519-1 assume !(1 == ~E_3~0); 39047#L524-1 assume { :end_inline_reset_delta_events } true; 39048#L690-2 assume !false; 39973#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39969#L416 [2022-12-13 16:07:33,750 INFO L750 eck$LassoCheckResult]: Loop: 39969#L416 assume !false; 39936#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 39937#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 40039#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 40038#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40036#L369 assume 0 != eval_~tmp~0#1; 40028#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 40026#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 40020#L374 assume !(0 == ~t1_st~0); 40017#L388 assume !(0 == ~t2_st~0); 39972#L402 assume !(0 == ~t3_st~0); 39969#L416 [2022-12-13 16:07:33,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:33,751 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2022-12-13 16:07:33,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:33,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [944118656] [2022-12-13 16:07:33,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:33,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:33,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:33,756 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:33,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:33,764 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:33,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:33,764 INFO L85 PathProgramCache]: Analyzing trace with hash 258292880, now seen corresponding path program 1 times [2022-12-13 16:07:33,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:33,765 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [679992374] [2022-12-13 16:07:33,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:33,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:33,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:33,767 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:33,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:33,769 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:33,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:33,769 INFO L85 PathProgramCache]: Analyzing trace with hash 1139971210, now seen corresponding path program 1 times [2022-12-13 16:07:33,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:33,770 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920196212] [2022-12-13 16:07:33,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:33,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:33,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:33,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:33,799 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:33,799 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [920196212] [2022-12-13 16:07:33,800 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [920196212] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:33,800 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:33,800 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:07:33,800 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [14116322] [2022-12-13 16:07:33,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:33,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:33,862 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:07:33,862 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:07:33,862 INFO L87 Difference]: Start difference. First operand 2778 states and 3876 transitions. cyclomatic complexity: 1101 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:33,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:33,914 INFO L93 Difference]: Finished difference Result 4956 states and 6841 transitions. [2022-12-13 16:07:33,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4956 states and 6841 transitions. [2022-12-13 16:07:33,931 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4848 [2022-12-13 16:07:33,940 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4956 states to 4956 states and 6841 transitions. [2022-12-13 16:07:33,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4956 [2022-12-13 16:07:33,943 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4956 [2022-12-13 16:07:33,943 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4956 states and 6841 transitions. [2022-12-13 16:07:33,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:33,946 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4956 states and 6841 transitions. [2022-12-13 16:07:33,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4956 states and 6841 transitions. [2022-12-13 16:07:33,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4956 to 4711. [2022-12-13 16:07:34,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4711 states, 4711 states have (on average 1.3852685204839736) internal successors, (6526), 4710 states have internal predecessors, (6526), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:34,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4711 states to 4711 states and 6526 transitions. [2022-12-13 16:07:34,016 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4711 states and 6526 transitions. [2022-12-13 16:07:34,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:07:34,017 INFO L428 stractBuchiCegarLoop]: Abstraction has 4711 states and 6526 transitions. [2022-12-13 16:07:34,017 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 16:07:34,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4711 states and 6526 transitions. [2022-12-13 16:07:34,032 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4603 [2022-12-13 16:07:34,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:34,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:34,033 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:34,033 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:34,033 INFO L748 eck$LassoCheckResult]: Stem: 47009#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 47010#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 47023#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47021#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47022#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 46904#L304-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 46905#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47038#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47039#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46746#L441 assume !(0 == ~M_E~0); 46747#L441-2 assume !(0 == ~T1_E~0); 47052#L446-1 assume !(0 == ~T2_E~0); 47053#L451-1 assume !(0 == ~T3_E~0); 47076#L456-1 assume !(0 == ~E_M~0); 47077#L461-1 assume !(0 == ~E_1~0); 47047#L466-1 assume !(0 == ~E_2~0); 47048#L471-1 assume !(0 == ~E_3~0); 46781#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46782#L220 assume !(1 == ~m_pc~0); 46816#L220-2 is_master_triggered_~__retres1~0#1 := 0; 46817#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46989#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 46990#L543 assume !(0 != activate_threads_~tmp~1#1); 47109#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47110#L239 assume !(1 == ~t1_pc~0); 47004#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47005#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46779#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46780#L551 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47012#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47013#L258 assume !(1 == ~t2_pc~0); 47014#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46845#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46846#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 47026#L559 assume !(0 != activate_threads_~tmp___1~0#1); 47027#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46969#L277 assume !(1 == ~t3_pc~0); 46970#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46757#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46758#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46807#L567 assume !(0 != activate_threads_~tmp___2~0#1); 46808#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47098#L489 assume !(1 == ~M_E~0); 47099#L489-2 assume !(1 == ~T1_E~0); 46944#L494-1 assume !(1 == ~T2_E~0); 46945#L499-1 assume !(1 == ~T3_E~0); 46906#L504-1 assume !(1 == ~E_M~0); 46907#L509-1 assume !(1 == ~E_1~0); 46785#L514-1 assume !(1 == ~E_2~0); 46786#L519-1 assume !(1 == ~E_3~0); 46790#L524-1 assume { :end_inline_reset_delta_events } true; 46791#L690-2 assume !false; 48171#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48165#L416 [2022-12-13 16:07:34,033 INFO L750 eck$LassoCheckResult]: Loop: 48165#L416 assume !false; 48163#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 48161#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 48158#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 48159#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 48151#L369 assume 0 != eval_~tmp~0#1; 48152#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 48195#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 48191#L374 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 48100#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 48176#L388 assume !(0 == ~t2_st~0); 48170#L402 assume !(0 == ~t3_st~0); 48165#L416 [2022-12-13 16:07:34,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:34,033 INFO L85 PathProgramCache]: Analyzing trace with hash -934376957, now seen corresponding path program 1 times [2022-12-13 16:07:34,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:34,034 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26144670] [2022-12-13 16:07:34,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:34,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:34,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:34,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:34,054 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:34,054 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [26144670] [2022-12-13 16:07:34,055 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [26144670] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:34,055 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:34,055 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:07:34,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1309518795] [2022-12-13 16:07:34,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:34,055 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:07:34,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:34,056 INFO L85 PathProgramCache]: Analyzing trace with hash -586893878, now seen corresponding path program 1 times [2022-12-13 16:07:34,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:34,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713582461] [2022-12-13 16:07:34,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:34,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:34,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:34,059 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:34,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:34,062 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:34,130 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:34,130 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:07:34,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:07:34,130 INFO L87 Difference]: Start difference. First operand 4711 states and 6526 transitions. cyclomatic complexity: 1818 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:34,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:34,153 INFO L93 Difference]: Finished difference Result 4662 states and 6457 transitions. [2022-12-13 16:07:34,153 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4662 states and 6457 transitions. [2022-12-13 16:07:34,171 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4603 [2022-12-13 16:07:34,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4662 states to 4662 states and 6457 transitions. [2022-12-13 16:07:34,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4662 [2022-12-13 16:07:34,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4662 [2022-12-13 16:07:34,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4662 states and 6457 transitions. [2022-12-13 16:07:34,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:34,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4662 states and 6457 transitions. [2022-12-13 16:07:34,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4662 states and 6457 transitions. [2022-12-13 16:07:34,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4662 to 4662. [2022-12-13 16:07:34,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4662 states, 4662 states have (on average 1.385027885027885) internal successors, (6457), 4661 states have internal predecessors, (6457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:34,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4662 states to 4662 states and 6457 transitions. [2022-12-13 16:07:34,274 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4662 states and 6457 transitions. [2022-12-13 16:07:34,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:07:34,275 INFO L428 stractBuchiCegarLoop]: Abstraction has 4662 states and 6457 transitions. [2022-12-13 16:07:34,275 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 16:07:34,275 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4662 states and 6457 transitions. [2022-12-13 16:07:34,288 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4603 [2022-12-13 16:07:34,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:34,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:34,289 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:34,289 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:34,289 INFO L748 eck$LassoCheckResult]: Stem: 56383#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 56384#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 56400#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56397#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56398#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 56284#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56112#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56113#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56306#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56125#L441 assume !(0 == ~M_E~0); 56126#L441-2 assume !(0 == ~T1_E~0); 56280#L446-1 assume !(0 == ~T2_E~0); 56236#L451-1 assume !(0 == ~T3_E~0); 56237#L456-1 assume !(0 == ~E_M~0); 56413#L461-1 assume !(0 == ~E_1~0); 56414#L466-1 assume !(0 == ~E_2~0); 56431#L471-1 assume !(0 == ~E_3~0); 56160#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56161#L220 assume !(1 == ~m_pc~0); 56194#L220-2 is_master_triggered_~__retres1~0#1 := 0; 56195#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56254#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 56190#L543 assume !(0 != activate_threads_~tmp~1#1); 56191#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56378#L239 assume !(1 == ~t1_pc~0); 56376#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56377#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56158#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56159#L551 assume !(0 != activate_threads_~tmp___0~0#1); 56385#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56386#L258 assume !(1 == ~t2_pc~0); 56387#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56224#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56225#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56407#L559 assume !(0 != activate_threads_~tmp___1~0#1); 56292#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56293#L277 assume !(1 == ~t3_pc~0); 56346#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 56136#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56090#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 56091#L567 assume !(0 != activate_threads_~tmp___2~0#1); 56186#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56233#L489 assume !(1 == ~M_E~0); 56409#L489-2 assume !(1 == ~T1_E~0); 56322#L494-1 assume !(1 == ~T2_E~0); 56175#L499-1 assume !(1 == ~T3_E~0); 56176#L504-1 assume !(1 == ~E_M~0); 56285#L509-1 assume !(1 == ~E_1~0); 56164#L514-1 assume !(1 == ~E_2~0); 56165#L519-1 assume !(1 == ~E_3~0); 56169#L524-1 assume { :end_inline_reset_delta_events } true; 56170#L690-2 assume !false; 57768#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57760#L416 [2022-12-13 16:07:34,290 INFO L750 eck$LassoCheckResult]: Loop: 57760#L416 assume !false; 57753#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 57746#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 57741#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 57735#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 57730#L369 assume 0 != eval_~tmp~0#1; 57722#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 57713#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 57709#L374 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 57681#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 57704#L388 assume !(0 == ~t2_st~0); 57767#L402 assume !(0 == ~t3_st~0); 57760#L416 [2022-12-13 16:07:34,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:34,290 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 2 times [2022-12-13 16:07:34,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:34,290 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2132905223] [2022-12-13 16:07:34,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:34,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:34,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:34,298 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:34,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:34,309 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:34,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:34,309 INFO L85 PathProgramCache]: Analyzing trace with hash -586893878, now seen corresponding path program 2 times [2022-12-13 16:07:34,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:34,309 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436502541] [2022-12-13 16:07:34,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:34,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:34,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:34,313 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:34,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:34,316 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:34,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:34,317 INFO L85 PathProgramCache]: Analyzing trace with hash 975330576, now seen corresponding path program 1 times [2022-12-13 16:07:34,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:34,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178060396] [2022-12-13 16:07:34,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:34,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:34,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:34,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:34,351 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:34,351 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [178060396] [2022-12-13 16:07:34,351 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [178060396] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:34,351 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:34,351 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:07:34,351 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [270688872] [2022-12-13 16:07:34,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:34,413 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:34,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:07:34,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:07:34,414 INFO L87 Difference]: Start difference. First operand 4662 states and 6457 transitions. cyclomatic complexity: 1798 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:34,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:34,497 INFO L93 Difference]: Finished difference Result 8403 states and 11556 transitions. [2022-12-13 16:07:34,497 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8403 states and 11556 transitions. [2022-12-13 16:07:34,528 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8340 [2022-12-13 16:07:34,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8403 states to 8403 states and 11556 transitions. [2022-12-13 16:07:34,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8403 [2022-12-13 16:07:34,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8403 [2022-12-13 16:07:34,547 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8403 states and 11556 transitions. [2022-12-13 16:07:34,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:34,552 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8403 states and 11556 transitions. [2022-12-13 16:07:34,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8403 states and 11556 transitions. [2022-12-13 16:07:34,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8403 to 8249. [2022-12-13 16:07:34,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8249 states, 8249 states have (on average 1.3771366226209238) internal successors, (11360), 8248 states have internal predecessors, (11360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:34,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8249 states to 8249 states and 11360 transitions. [2022-12-13 16:07:34,663 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8249 states and 11360 transitions. [2022-12-13 16:07:34,663 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:07:34,664 INFO L428 stractBuchiCegarLoop]: Abstraction has 8249 states and 11360 transitions. [2022-12-13 16:07:34,664 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 16:07:34,664 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8249 states and 11360 transitions. [2022-12-13 16:07:34,687 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8186 [2022-12-13 16:07:34,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:34,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:34,688 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:34,688 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:34,688 INFO L748 eck$LassoCheckResult]: Stem: 69441#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 69442#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 69457#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69451#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69452#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 69351#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69187#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69188#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69373#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69197#L441 assume !(0 == ~M_E~0); 69198#L441-2 assume !(0 == ~T1_E~0); 69347#L446-1 assume !(0 == ~T2_E~0); 69306#L451-1 assume !(0 == ~T3_E~0); 69307#L456-1 assume !(0 == ~E_M~0); 69462#L461-1 assume !(0 == ~E_1~0); 69463#L466-1 assume !(0 == ~E_2~0); 69479#L471-1 assume !(0 == ~E_3~0); 69233#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69234#L220 assume !(1 == ~m_pc~0); 69266#L220-2 is_master_triggered_~__retres1~0#1 := 0; 69267#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69327#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 69264#L543 assume !(0 != activate_threads_~tmp~1#1); 69265#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69440#L239 assume !(1 == ~t1_pc~0); 69438#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 69439#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69229#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 69230#L551 assume !(0 != activate_threads_~tmp___0~0#1); 69443#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69444#L258 assume !(1 == ~t2_pc~0); 69445#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69297#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69298#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 69459#L559 assume !(0 != activate_threads_~tmp___1~0#1); 69360#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69361#L277 assume !(1 == ~t3_pc~0); 69413#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69208#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69165#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 69166#L567 assume !(0 != activate_threads_~tmp___2~0#1); 69257#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69303#L489 assume !(1 == ~M_E~0); 69460#L489-2 assume !(1 == ~T1_E~0); 69389#L494-1 assume !(1 == ~T2_E~0); 69248#L499-1 assume !(1 == ~T3_E~0); 69249#L504-1 assume !(1 == ~E_M~0); 69352#L509-1 assume !(1 == ~E_1~0); 69235#L514-1 assume !(1 == ~E_2~0); 69236#L519-1 assume !(1 == ~E_3~0); 69240#L524-1 assume { :end_inline_reset_delta_events } true; 69241#L690-2 assume !false; 71815#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 71811#L416 [2022-12-13 16:07:34,688 INFO L750 eck$LassoCheckResult]: Loop: 71811#L416 assume !false; 71806#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 71807#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 71799#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 71797#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 71794#L369 assume 0 != eval_~tmp~0#1; 71795#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 71788#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 71786#L374 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 71781#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 71782#L388 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 71220#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 71814#L402 assume !(0 == ~t3_st~0); 71811#L416 [2022-12-13 16:07:34,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:34,688 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 3 times [2022-12-13 16:07:34,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:34,689 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209162865] [2022-12-13 16:07:34,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:34,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:34,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:34,697 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:34,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:34,707 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:34,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:34,708 INFO L85 PathProgramCache]: Analyzing trace with hash -1013970345, now seen corresponding path program 1 times [2022-12-13 16:07:34,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:34,708 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20079728] [2022-12-13 16:07:34,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:34,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:34,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:34,711 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:34,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:34,713 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:34,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:34,714 INFO L85 PathProgramCache]: Analyzing trace with hash 170347473, now seen corresponding path program 1 times [2022-12-13 16:07:34,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:34,714 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344892976] [2022-12-13 16:07:34,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:34,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:34,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:07:34,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:07:34,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:07:34,743 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344892976] [2022-12-13 16:07:34,743 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [344892976] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:07:34,744 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:07:34,744 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:07:34,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1711351881] [2022-12-13 16:07:34,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:07:34,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:07:34,824 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:07:34,824 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:07:34,825 INFO L87 Difference]: Start difference. First operand 8249 states and 11360 transitions. cyclomatic complexity: 3114 Second operand has 3 states, 2 states have (on average 33.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:34,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:07:34,928 INFO L93 Difference]: Finished difference Result 13791 states and 18894 transitions. [2022-12-13 16:07:34,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13791 states and 18894 transitions. [2022-12-13 16:07:34,966 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 13720 [2022-12-13 16:07:34,993 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13791 states to 13791 states and 18894 transitions. [2022-12-13 16:07:34,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13791 [2022-12-13 16:07:35,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13791 [2022-12-13 16:07:35,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13791 states and 18894 transitions. [2022-12-13 16:07:35,007 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:07:35,007 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13791 states and 18894 transitions. [2022-12-13 16:07:35,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13791 states and 18894 transitions. [2022-12-13 16:07:35,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13791 to 13567. [2022-12-13 16:07:35,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13567 states, 13567 states have (on average 1.3761332645389548) internal successors, (18670), 13566 states have internal predecessors, (18670), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:07:35,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13567 states to 13567 states and 18670 transitions. [2022-12-13 16:07:35,192 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13567 states and 18670 transitions. [2022-12-13 16:07:35,192 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:07:35,192 INFO L428 stractBuchiCegarLoop]: Abstraction has 13567 states and 18670 transitions. [2022-12-13 16:07:35,193 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 16:07:35,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13567 states and 18670 transitions. [2022-12-13 16:07:35,213 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 13496 [2022-12-13 16:07:35,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:07:35,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:07:35,214 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:35,214 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:07:35,214 INFO L748 eck$LassoCheckResult]: Stem: 91500#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 91501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 91514#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 91511#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91512#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 91397#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 91233#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 91234#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 91420#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 91246#L441 assume !(0 == ~M_E~0); 91247#L441-2 assume !(0 == ~T1_E~0); 91393#L446-1 assume !(0 == ~T2_E~0); 91352#L451-1 assume !(0 == ~T3_E~0); 91353#L456-1 assume !(0 == ~E_M~0); 91519#L461-1 assume !(0 == ~E_1~0); 91520#L466-1 assume !(0 == ~E_2~0); 91536#L471-1 assume !(0 == ~E_3~0); 91279#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91280#L220 assume !(1 == ~m_pc~0); 91314#L220-2 is_master_triggered_~__retres1~0#1 := 0; 91315#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91367#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 91310#L543 assume !(0 != activate_threads_~tmp~1#1); 91311#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91497#L239 assume !(1 == ~t1_pc~0); 91495#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 91496#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91277#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 91278#L551 assume !(0 != activate_threads_~tmp___0~0#1); 91502#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 91503#L258 assume !(1 == ~t2_pc~0); 91504#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 91342#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91343#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 91517#L559 assume !(0 != activate_threads_~tmp___1~0#1); 91405#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91406#L277 assume !(1 == ~t3_pc~0); 91463#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 91257#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91211#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 91212#L567 assume !(0 != activate_threads_~tmp___2~0#1); 91306#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91349#L489 assume !(1 == ~M_E~0); 91518#L489-2 assume !(1 == ~T1_E~0); 91437#L494-1 assume !(1 == ~T2_E~0); 91295#L499-1 assume !(1 == ~T3_E~0); 91296#L504-1 assume !(1 == ~E_M~0); 91398#L509-1 assume !(1 == ~E_1~0); 91283#L514-1 assume !(1 == ~E_2~0); 91284#L519-1 assume !(1 == ~E_3~0); 91289#L524-1 assume { :end_inline_reset_delta_events } true; 91290#L690-2 assume !false; 94984#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 94978#L416 [2022-12-13 16:07:35,214 INFO L750 eck$LassoCheckResult]: Loop: 94978#L416 assume !false; 94975#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 94970#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 94965#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 94961#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 94957#L369 assume 0 != eval_~tmp~0#1; 94953#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 94948#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 94817#L374 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 94809#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 94808#L388 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 94802#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 94807#L402 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 94301#L419 assume !(0 != eval_~tmp_ndt_4~0#1); 94978#L416 [2022-12-13 16:07:35,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:35,215 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 4 times [2022-12-13 16:07:35,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:35,215 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816235551] [2022-12-13 16:07:35,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:35,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:35,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:35,220 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:35,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:35,227 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:35,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:35,227 INFO L85 PathProgramCache]: Analyzing trace with hash -1368312829, now seen corresponding path program 1 times [2022-12-13 16:07:35,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:35,227 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81430338] [2022-12-13 16:07:35,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:35,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:35,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:35,230 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:35,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:35,232 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:35,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:07:35,233 INFO L85 PathProgramCache]: Analyzing trace with hash 985801161, now seen corresponding path program 1 times [2022-12-13 16:07:35,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:07:35,233 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [693087929] [2022-12-13 16:07:35,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:07:35,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:07:35,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:35,240 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:35,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:35,248 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:07:36,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:36,151 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:07:36,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:07:36,266 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 04:07:36 BoogieIcfgContainer [2022-12-13 16:07:36,266 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 16:07:36,266 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 16:07:36,267 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 16:07:36,267 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 16:07:36,267 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 04:07:31" (3/4) ... [2022-12-13 16:07:36,270 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 16:07:36,334 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 16:07:36,334 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 16:07:36,335 INFO L158 Benchmark]: Toolchain (without parser) took 6282.66ms. Allocated memory was 125.8MB in the beginning and 587.2MB in the end (delta: 461.4MB). Free memory was 92.9MB in the beginning and 308.1MB in the end (delta: -215.2MB). Peak memory consumption was 249.4MB. Max. memory is 16.1GB. [2022-12-13 16:07:36,335 INFO L158 Benchmark]: CDTParser took 0.13ms. Allocated memory is still 125.8MB. Free memory is still 96.2MB. There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 16:07:36,335 INFO L158 Benchmark]: CACSL2BoogieTranslator took 264.32ms. Allocated memory is still 125.8MB. Free memory was 92.5MB in the beginning and 78.2MB in the end (delta: 14.3MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-12-13 16:07:36,335 INFO L158 Benchmark]: Boogie Procedure Inliner took 35.41ms. Allocated memory is still 125.8MB. Free memory was 78.2MB in the beginning and 74.6MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 16:07:36,336 INFO L158 Benchmark]: Boogie Preprocessor took 30.78ms. Allocated memory is still 125.8MB. Free memory was 74.6MB in the beginning and 71.2MB in the end (delta: 3.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 16:07:36,336 INFO L158 Benchmark]: RCFGBuilder took 660.32ms. Allocated memory was 125.8MB in the beginning and 151.0MB in the end (delta: 25.2MB). Free memory was 71.2MB in the beginning and 113.6MB in the end (delta: -42.4MB). Peak memory consumption was 38.1MB. Max. memory is 16.1GB. [2022-12-13 16:07:36,337 INFO L158 Benchmark]: BuchiAutomizer took 5219.10ms. Allocated memory was 151.0MB in the beginning and 587.2MB in the end (delta: 436.2MB). Free memory was 113.6MB in the beginning and 314.4MB in the end (delta: -200.8MB). Peak memory consumption was 236.5MB. Max. memory is 16.1GB. [2022-12-13 16:07:36,337 INFO L158 Benchmark]: Witness Printer took 67.55ms. Allocated memory is still 587.2MB. Free memory was 314.4MB in the beginning and 308.1MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-12-13 16:07:36,339 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13ms. Allocated memory is still 125.8MB. Free memory is still 96.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 264.32ms. Allocated memory is still 125.8MB. Free memory was 92.5MB in the beginning and 78.2MB in the end (delta: 14.3MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 35.41ms. Allocated memory is still 125.8MB. Free memory was 78.2MB in the beginning and 74.6MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 30.78ms. Allocated memory is still 125.8MB. Free memory was 74.6MB in the beginning and 71.2MB in the end (delta: 3.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 660.32ms. Allocated memory was 125.8MB in the beginning and 151.0MB in the end (delta: 25.2MB). Free memory was 71.2MB in the beginning and 113.6MB in the end (delta: -42.4MB). Peak memory consumption was 38.1MB. Max. memory is 16.1GB. * BuchiAutomizer took 5219.10ms. Allocated memory was 151.0MB in the beginning and 587.2MB in the end (delta: 436.2MB). Free memory was 113.6MB in the beginning and 314.4MB in the end (delta: -200.8MB). Peak memory consumption was 236.5MB. Max. memory is 16.1GB. * Witness Printer took 67.55ms. Allocated memory is still 587.2MB. Free memory was 314.4MB in the beginning and 308.1MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 16 terminating modules (16 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.16 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 13567 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.0s and 17 iterations. TraceHistogramMax:1. Analysis of lassos took 2.5s. Construction of modules took 0.3s. Büchi inclusion checks took 1.9s. Highest rank in rank-based complementation 0. Minimization of det autom 16. Minimization of nondet autom 0. Automata minimization 0.8s AutomataMinimizationTime, 16 MinimizatonAttempts, 9765 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 0.4s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 10705 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 10705 mSDsluCounter, 17945 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 9528 mSDsCounter, 164 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 406 IncrementalHoareTripleChecker+Invalid, 570 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 164 mSolverCounterUnsat, 8417 mSDtfsCounter, 406 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc3 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 364]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L690] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L364] COND TRUE 1 [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE !(\read(tmp_ndt_1)) [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE !(\read(tmp_ndt_2)) [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE !(\read(tmp_ndt_3)) [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 364]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L690] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L364] COND TRUE 1 [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE !(\read(tmp_ndt_1)) [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE !(\read(tmp_ndt_2)) [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE !(\read(tmp_ndt_3)) [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 16:07:36,420 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ffd3c30a-ab1c-4135-becd-59f82402647e/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)