./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 16:15:53,477 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 16:15:53,479 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 16:15:53,490 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 16:15:53,490 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 16:15:53,491 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 16:15:53,492 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 16:15:53,493 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 16:15:53,494 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 16:15:53,494 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 16:15:53,495 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 16:15:53,496 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 16:15:53,496 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 16:15:53,496 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 16:15:53,497 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 16:15:53,498 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 16:15:53,498 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 16:15:53,499 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 16:15:53,500 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 16:15:53,501 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 16:15:53,502 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 16:15:53,503 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 16:15:53,503 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 16:15:53,504 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 16:15:53,506 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 16:15:53,506 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 16:15:53,506 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 16:15:53,507 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 16:15:53,507 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 16:15:53,507 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 16:15:53,508 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 16:15:53,508 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 16:15:53,509 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 16:15:53,509 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 16:15:53,510 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 16:15:53,510 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 16:15:53,510 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 16:15:53,510 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 16:15:53,510 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 16:15:53,511 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 16:15:53,511 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 16:15:53,512 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 16:15:53,526 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 16:15:53,526 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 16:15:53,526 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 16:15:53,527 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 16:15:53,527 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 16:15:53,527 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 16:15:53,527 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 16:15:53,528 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 16:15:53,528 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 16:15:53,528 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 16:15:53,528 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 16:15:53,528 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 16:15:53,528 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 16:15:53,528 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 16:15:53,528 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 16:15:53,528 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 16:15:53,528 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 16:15:53,529 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 16:15:53,529 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 16:15:53,529 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 16:15:53,529 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 16:15:53,529 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 16:15:53,529 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 16:15:53,529 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 16:15:53,529 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 16:15:53,529 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 16:15:53,529 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 16:15:53,529 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 16:15:53,530 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 16:15:53,530 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 16:15:53,530 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 16:15:53,530 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 16:15:53,531 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 [2022-12-13 16:15:53,694 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 16:15:53,712 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 16:15:53,715 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 16:15:53,716 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 16:15:53,716 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 16:15:53,717 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2022-12-13 16:15:56,363 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 16:15:56,516 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 16:15:56,516 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2022-12-13 16:15:56,523 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/data/05a4f8cc0/30502d8e5b6d452391805fbba7310b2b/FLAGbd7567db4 [2022-12-13 16:15:56,533 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/data/05a4f8cc0/30502d8e5b6d452391805fbba7310b2b [2022-12-13 16:15:56,535 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 16:15:56,536 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 16:15:56,537 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 16:15:56,537 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 16:15:56,540 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 16:15:56,540 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 04:15:56" (1/1) ... [2022-12-13 16:15:56,541 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@f2fe632 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56, skipping insertion in model container [2022-12-13 16:15:56,541 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 04:15:56" (1/1) ... [2022-12-13 16:15:56,546 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 16:15:56,570 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 16:15:56,664 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/sv-benchmarks/c/systemc/token_ring.05.cil-2.c[671,684] [2022-12-13 16:15:56,710 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 16:15:56,720 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 16:15:56,729 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/sv-benchmarks/c/systemc/token_ring.05.cil-2.c[671,684] [2022-12-13 16:15:56,755 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 16:15:56,766 INFO L208 MainTranslator]: Completed translation [2022-12-13 16:15:56,767 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56 WrapperNode [2022-12-13 16:15:56,767 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 16:15:56,767 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 16:15:56,768 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 16:15:56,768 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 16:15:56,773 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56" (1/1) ... [2022-12-13 16:15:56,779 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56" (1/1) ... [2022-12-13 16:15:56,809 INFO L138 Inliner]: procedures = 38, calls = 47, calls flagged for inlining = 42, calls inlined = 95, statements flattened = 1353 [2022-12-13 16:15:56,809 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 16:15:56,809 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 16:15:56,809 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 16:15:56,809 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 16:15:56,816 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56" (1/1) ... [2022-12-13 16:15:56,817 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56" (1/1) ... [2022-12-13 16:15:56,820 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56" (1/1) ... [2022-12-13 16:15:56,821 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56" (1/1) ... [2022-12-13 16:15:56,830 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56" (1/1) ... [2022-12-13 16:15:56,839 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56" (1/1) ... [2022-12-13 16:15:56,841 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56" (1/1) ... [2022-12-13 16:15:56,843 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56" (1/1) ... [2022-12-13 16:15:56,847 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 16:15:56,848 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 16:15:56,848 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 16:15:56,848 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 16:15:56,848 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56" (1/1) ... [2022-12-13 16:15:56,853 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 16:15:56,861 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 16:15:56,873 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 16:15:56,875 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 16:15:56,899 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 16:15:56,899 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 16:15:56,899 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 16:15:56,899 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 16:15:56,972 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 16:15:56,974 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 16:15:57,707 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 16:15:57,719 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 16:15:57,719 INFO L300 CfgBuilder]: Removed 8 assume(true) statements. [2022-12-13 16:15:57,722 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 04:15:57 BoogieIcfgContainer [2022-12-13 16:15:57,722 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 16:15:57,723 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 16:15:57,723 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 16:15:57,727 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 16:15:57,728 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:15:57,728 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 04:15:56" (1/3) ... [2022-12-13 16:15:57,729 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e9986ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 04:15:57, skipping insertion in model container [2022-12-13 16:15:57,729 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:15:57,729 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:15:56" (2/3) ... [2022-12-13 16:15:57,730 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e9986ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 04:15:57, skipping insertion in model container [2022-12-13 16:15:57,730 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:15:57,730 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 04:15:57" (3/3) ... [2022-12-13 16:15:57,732 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-2.c [2022-12-13 16:15:57,791 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 16:15:57,791 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 16:15:57,791 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 16:15:57,791 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 16:15:57,791 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 16:15:57,791 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 16:15:57,791 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 16:15:57,792 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 16:15:57,798 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 559 states, 558 states have (on average 1.5304659498207884) internal successors, (854), 558 states have internal predecessors, (854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:57,825 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2022-12-13 16:15:57,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:15:57,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:15:57,832 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:57,832 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:57,832 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 16:15:57,833 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 559 states, 558 states have (on average 1.5304659498207884) internal successors, (854), 558 states have internal predecessors, (854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:57,841 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2022-12-13 16:15:57,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:15:57,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:15:57,843 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:57,843 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:57,849 INFO L748 eck$LassoCheckResult]: Stem: 190#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 465#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 275#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 462#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 261#L426true assume !(1 == ~m_i~0);~m_st~0 := 2; 322#L426-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 151#L431-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 317#L436-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 136#L441-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 498#L446-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 358#L451-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 206#L611true assume 0 == ~M_E~0;~M_E~0 := 1; 378#L611-2true assume !(0 == ~T1_E~0); 375#L616-1true assume !(0 == ~T2_E~0); 383#L621-1true assume !(0 == ~T3_E~0); 63#L626-1true assume !(0 == ~T4_E~0); 348#L631-1true assume !(0 == ~T5_E~0); 175#L636-1true assume !(0 == ~E_M~0); 89#L641-1true assume !(0 == ~E_1~0); 186#L646-1true assume 0 == ~E_2~0;~E_2~0 := 1; 489#L651-1true assume !(0 == ~E_3~0); 438#L656-1true assume !(0 == ~E_4~0); 356#L661-1true assume !(0 == ~E_5~0); 400#L666-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 522#L304true assume !(1 == ~m_pc~0); 101#L304-2true is_master_triggered_~__retres1~0#1 := 0; 50#L315true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26#L755true assume !(0 != activate_threads_~tmp~1#1); 545#L755-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6#L323true assume 1 == ~t1_pc~0; 304#L324true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34#L334true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 490#L763true assume !(0 != activate_threads_~tmp___0~0#1); 501#L763-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36#L342true assume 1 == ~t2_pc~0; 516#L343true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 107#L353true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 276#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 524#L771true assume !(0 != activate_threads_~tmp___1~0#1); 349#L771-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 234#L361true assume !(1 == ~t3_pc~0); 252#L361-2true is_transmit3_triggered_~__retres1~3#1 := 0; 456#L372true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 429#L779true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44#L779-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 233#L380true assume 1 == ~t4_pc~0; 75#L381true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 368#L391true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 266#L787true assume !(0 != activate_threads_~tmp___3~0#1); 514#L787-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76#L399true assume !(1 == ~t5_pc~0); 157#L399-2true is_transmit5_triggered_~__retres1~5#1 := 0; 380#L410true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 162#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 152#L795true assume !(0 != activate_threads_~tmp___4~0#1); 451#L795-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 525#L679true assume !(1 == ~M_E~0); 204#L679-2true assume !(1 == ~T1_E~0); 115#L684-1true assume !(1 == ~T2_E~0); 240#L689-1true assume !(1 == ~T3_E~0); 536#L694-1true assume !(1 == ~T4_E~0); 239#L699-1true assume !(1 == ~T5_E~0); 357#L704-1true assume !(1 == ~E_M~0); 220#L709-1true assume 1 == ~E_1~0;~E_1~0 := 2; 178#L714-1true assume !(1 == ~E_2~0); 338#L719-1true assume !(1 == ~E_3~0); 475#L724-1true assume !(1 == ~E_4~0); 57#L729-1true assume !(1 == ~E_5~0); 458#L734-1true assume { :end_inline_reset_delta_events } true; 327#L940-2true [2022-12-13 16:15:57,850 INFO L750 eck$LassoCheckResult]: Loop: 327#L940-2true assume !false; 394#L941true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 113#L586true assume !true; 93#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 405#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 298#L611-3true assume 0 == ~M_E~0;~M_E~0 := 1; 58#L611-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 313#L616-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 55#L621-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 29#L626-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 555#L631-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 30#L636-3true assume !(0 == ~E_M~0); 64#L641-3true assume 0 == ~E_1~0;~E_1~0 := 1; 236#L646-3true assume 0 == ~E_2~0;~E_2~0 := 1; 70#L651-3true assume 0 == ~E_3~0;~E_3~0 := 1; 214#L656-3true assume 0 == ~E_4~0;~E_4~0 := 1; 491#L661-3true assume 0 == ~E_5~0;~E_5~0 := 1; 503#L666-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 155#L304-21true assume !(1 == ~m_pc~0); 72#L304-23true is_master_triggered_~__retres1~0#1 := 0; 263#L315-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111#is_master_triggered_returnLabel#8true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 195#L755-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 216#L755-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 486#L323-21true assume !(1 == ~t1_pc~0); 366#L323-23true is_transmit1_triggered_~__retres1~1#1 := 0; 401#L334-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 80#is_transmit1_triggered_returnLabel#8true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 395#L763-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 417#L763-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 552#L342-21true assume 1 == ~t2_pc~0; 24#L343-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 257#L353-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 203#is_transmit2_triggered_returnLabel#8true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 351#L771-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77#L771-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 471#L361-21true assume 1 == ~t3_pc~0; 502#L362-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 474#L372-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 476#is_transmit3_triggered_returnLabel#8true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 176#L779-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28#L779-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 510#L380-21true assume !(1 == ~t4_pc~0); 61#L380-23true is_transmit4_triggered_~__retres1~4#1 := 0; 96#L391-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 447#is_transmit4_triggered_returnLabel#8true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 337#L787-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 267#L787-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 142#L399-21true assume !(1 == ~t5_pc~0); 66#L399-23true is_transmit5_triggered_~__retres1~5#1 := 0; 281#L410-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 251#is_transmit5_triggered_returnLabel#8true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 496#L795-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 444#L795-23true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25#L679-3true assume 1 == ~M_E~0;~M_E~0 := 2; 183#L679-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 226#L684-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 2#L689-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 166#L694-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 20#L699-3true assume !(1 == ~T5_E~0); 302#L704-3true assume 1 == ~E_M~0;~E_M~0 := 2; 392#L709-3true assume 1 == ~E_1~0;~E_1~0 := 2; 286#L714-3true assume 1 == ~E_2~0;~E_2~0 := 2; 160#L719-3true assume 1 == ~E_3~0;~E_3~0 := 2; 19#L724-3true assume 1 == ~E_4~0;~E_4~0 := 2; 272#L729-3true assume 1 == ~E_5~0;~E_5~0 := 2; 320#L734-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 33#L464-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 215#L496-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 246#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 249#L959true assume !(0 == start_simulation_~tmp~3#1); 509#L959-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 180#L464-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 377#L496-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 41#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 367#L914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 126#L921true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 416#stop_simulation_returnLabel#1true start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 303#L972true assume !(0 != start_simulation_~tmp___0~1#1); 327#L940-2true [2022-12-13 16:15:57,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:57,855 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2022-12-13 16:15:57,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:57,862 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487537608] [2022-12-13 16:15:57,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:57,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:57,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,014 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,014 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487537608] [2022-12-13 16:15:58,015 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487537608] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,015 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,015 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:58,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1118864160] [2022-12-13 16:15:58,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,021 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:15:58,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,022 INFO L85 PathProgramCache]: Analyzing trace with hash -1670652393, now seen corresponding path program 1 times [2022-12-13 16:15:58,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,023 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054375394] [2022-12-13 16:15:58,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,079 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054375394] [2022-12-13 16:15:58,079 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1054375394] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,079 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,079 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:15:58,079 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1434254358] [2022-12-13 16:15:58,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,081 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:15:58,082 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:15:58,109 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:15:58,110 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:15:58,113 INFO L87 Difference]: Start difference. First operand has 559 states, 558 states have (on average 1.5304659498207884) internal successors, (854), 558 states have internal predecessors, (854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:15:58,154 INFO L93 Difference]: Finished difference Result 557 states and 833 transitions. [2022-12-13 16:15:58,154 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 833 transitions. [2022-12-13 16:15:58,158 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-12-13 16:15:58,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 551 states and 827 transitions. [2022-12-13 16:15:58,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2022-12-13 16:15:58,165 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2022-12-13 16:15:58,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 827 transitions. [2022-12-13 16:15:58,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:15:58,168 INFO L218 hiAutomatonCegarLoop]: Abstraction has 551 states and 827 transitions. [2022-12-13 16:15:58,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 827 transitions. [2022-12-13 16:15:58,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2022-12-13 16:15:58,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.5009074410163339) internal successors, (827), 550 states have internal predecessors, (827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 827 transitions. [2022-12-13 16:15:58,212 INFO L240 hiAutomatonCegarLoop]: Abstraction has 551 states and 827 transitions. [2022-12-13 16:15:58,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:15:58,217 INFO L428 stractBuchiCegarLoop]: Abstraction has 551 states and 827 transitions. [2022-12-13 16:15:58,217 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 16:15:58,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 827 transitions. [2022-12-13 16:15:58,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-12-13 16:15:58,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:15:58,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:15:58,223 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,223 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,224 INFO L748 eck$LassoCheckResult]: Stem: 1460#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1461#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1559#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1560#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1545#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1546#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1403#L431-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1404#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1381#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1382#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1610#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1484#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 1485#L611-2 assume !(0 == ~T1_E~0); 1622#L616-1 assume !(0 == ~T2_E~0); 1623#L621-1 assume !(0 == ~T3_E~0); 1249#L626-1 assume !(0 == ~T4_E~0); 1250#L631-1 assume !(0 == ~T5_E~0); 1441#L636-1 assume !(0 == ~E_M~0); 1302#L641-1 assume !(0 == ~E_1~0); 1303#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1458#L651-1 assume !(0 == ~E_3~0); 1652#L656-1 assume !(0 == ~E_4~0); 1608#L661-1 assume !(0 == ~E_5~0); 1609#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1635#L304 assume !(1 == ~m_pc~0); 1325#L304-2 is_master_triggered_~__retres1~0#1 := 0; 1224#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1225#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1177#L755 assume !(0 != activate_threads_~tmp~1#1); 1178#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1135#L323 assume 1 == ~t1_pc~0; 1136#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1196#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1197#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1212#L763 assume !(0 != activate_threads_~tmp___0~0#1); 1671#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1199#L342 assume 1 == ~t2_pc~0; 1200#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1331#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1332#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1561#L771 assume !(0 != activate_threads_~tmp___1~0#1); 1605#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1516#L361 assume !(1 == ~t3_pc~0); 1517#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1541#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1151#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1152#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1217#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1218#L380 assume 1 == ~t4_pc~0; 1271#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1272#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1297#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1298#L787 assume !(0 != activate_threads_~tmp___3~0#1); 1548#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1274#L399 assume !(1 == ~t5_pc~0); 1275#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1413#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1418#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1405#L795 assume !(0 != activate_threads_~tmp___4~0#1); 1406#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1660#L679 assume !(1 == ~M_E~0); 1482#L679-2 assume !(1 == ~T1_E~0); 1346#L684-1 assume !(1 == ~T2_E~0); 1347#L689-1 assume !(1 == ~T3_E~0); 1524#L694-1 assume !(1 == ~T4_E~0); 1522#L699-1 assume !(1 == ~T5_E~0); 1523#L704-1 assume !(1 == ~E_M~0); 1506#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1448#L714-1 assume !(1 == ~E_2~0); 1449#L719-1 assume !(1 == ~E_3~0); 1601#L724-1 assume !(1 == ~E_4~0); 1235#L729-1 assume !(1 == ~E_5~0); 1236#L734-1 assume { :end_inline_reset_delta_events } true; 1578#L940-2 [2022-12-13 16:15:58,224 INFO L750 eck$LassoCheckResult]: Loop: 1578#L940-2 assume !false; 1591#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1342#L586 assume !false; 1343#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1657#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1519#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1520#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1515#L511 assume !(0 != eval_~tmp~0#1); 1310#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1311#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1572#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1237#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1238#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1233#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1184#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1185#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1186#L636-3 assume !(0 == ~E_M~0); 1187#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1251#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1261#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1262#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1500#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1672#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1410#L304-21 assume !(1 == ~m_pc~0); 1264#L304-23 is_master_triggered_~__retres1~0#1 := 0; 1265#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1338#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1339#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1469#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1502#L323-21 assume 1 == ~t1_pc~0; 1148#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1150#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1284#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1285#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1633#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1645#L342-21 assume 1 == ~t2_pc~0; 1172#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1173#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1480#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1481#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1277#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1278#L361-21 assume 1 == ~t3_pc~0; 1665#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1662#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1666#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1444#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1182#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1183#L380-21 assume 1 == ~t4_pc~0; 1651#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1244#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1317#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1600#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1549#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1391#L399-21 assume 1 == ~t5_pc~0; 1367#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1248#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1539#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1540#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1656#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1175#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1176#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1454#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1125#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1126#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1164#L699-3 assume !(1 == ~T5_E~0); 1165#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1576#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1567#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1415#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1162#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1163#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1555#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1193#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1194#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1501#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1534#L959 assume !(0 == start_simulation_~tmp~3#1); 1538#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1445#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1446#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1208#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1209#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1365#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1366#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1577#L972 assume !(0 != start_simulation_~tmp___0~1#1); 1578#L940-2 [2022-12-13 16:15:58,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,226 INFO L85 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2022-12-13 16:15:58,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,226 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [516812803] [2022-12-13 16:15:58,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,286 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [516812803] [2022-12-13 16:15:58,286 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [516812803] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,286 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,286 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:58,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1658787664] [2022-12-13 16:15:58,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,287 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:15:58,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,287 INFO L85 PathProgramCache]: Analyzing trace with hash -2017445525, now seen corresponding path program 1 times [2022-12-13 16:15:58,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,287 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556133322] [2022-12-13 16:15:58,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1556133322] [2022-12-13 16:15:58,346 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1556133322] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,346 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,346 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:58,346 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988134654] [2022-12-13 16:15:58,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,347 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:15:58,347 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:15:58,347 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:15:58,347 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:15:58,348 INFO L87 Difference]: Start difference. First operand 551 states and 827 transitions. cyclomatic complexity: 277 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:15:58,369 INFO L93 Difference]: Finished difference Result 551 states and 826 transitions. [2022-12-13 16:15:58,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 826 transitions. [2022-12-13 16:15:58,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-12-13 16:15:58,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 826 transitions. [2022-12-13 16:15:58,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2022-12-13 16:15:58,375 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2022-12-13 16:15:58,375 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 826 transitions. [2022-12-13 16:15:58,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:15:58,376 INFO L218 hiAutomatonCegarLoop]: Abstraction has 551 states and 826 transitions. [2022-12-13 16:15:58,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 826 transitions. [2022-12-13 16:15:58,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2022-12-13 16:15:58,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4990925589836661) internal successors, (826), 550 states have internal predecessors, (826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 826 transitions. [2022-12-13 16:15:58,385 INFO L240 hiAutomatonCegarLoop]: Abstraction has 551 states and 826 transitions. [2022-12-13 16:15:58,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:15:58,386 INFO L428 stractBuchiCegarLoop]: Abstraction has 551 states and 826 transitions. [2022-12-13 16:15:58,386 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 16:15:58,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 826 transitions. [2022-12-13 16:15:58,390 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-12-13 16:15:58,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:15:58,391 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:15:58,393 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,394 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,394 INFO L748 eck$LassoCheckResult]: Stem: 2569#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2570#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2668#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2669#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2654#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 2655#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2512#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2513#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2490#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2491#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2719#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2593#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 2594#L611-2 assume !(0 == ~T1_E~0); 2731#L616-1 assume !(0 == ~T2_E~0); 2732#L621-1 assume !(0 == ~T3_E~0); 2358#L626-1 assume !(0 == ~T4_E~0); 2359#L631-1 assume !(0 == ~T5_E~0); 2553#L636-1 assume !(0 == ~E_M~0); 2411#L641-1 assume !(0 == ~E_1~0); 2412#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2567#L651-1 assume !(0 == ~E_3~0); 2761#L656-1 assume !(0 == ~E_4~0); 2717#L661-1 assume !(0 == ~E_5~0); 2718#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2744#L304 assume !(1 == ~m_pc~0); 2435#L304-2 is_master_triggered_~__retres1~0#1 := 0; 2333#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2334#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2288#L755 assume !(0 != activate_threads_~tmp~1#1); 2289#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2244#L323 assume 1 == ~t1_pc~0; 2245#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2305#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2306#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2321#L763 assume !(0 != activate_threads_~tmp___0~0#1); 2780#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2312#L342 assume 1 == ~t2_pc~0; 2313#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2440#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2441#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2670#L771 assume !(0 != activate_threads_~tmp___1~0#1); 2714#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2625#L361 assume !(1 == ~t3_pc~0); 2626#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2650#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2260#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2261#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2326#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2327#L380 assume 1 == ~t4_pc~0; 2380#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2381#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2406#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2407#L787 assume !(0 != activate_threads_~tmp___3~0#1); 2657#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2383#L399 assume !(1 == ~t5_pc~0); 2384#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2522#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2527#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2514#L795 assume !(0 != activate_threads_~tmp___4~0#1); 2515#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2769#L679 assume !(1 == ~M_E~0); 2591#L679-2 assume !(1 == ~T1_E~0); 2455#L684-1 assume !(1 == ~T2_E~0); 2456#L689-1 assume !(1 == ~T3_E~0); 2633#L694-1 assume !(1 == ~T4_E~0); 2631#L699-1 assume !(1 == ~T5_E~0); 2632#L704-1 assume !(1 == ~E_M~0); 2615#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2557#L714-1 assume !(1 == ~E_2~0); 2558#L719-1 assume !(1 == ~E_3~0); 2710#L724-1 assume !(1 == ~E_4~0); 2344#L729-1 assume !(1 == ~E_5~0); 2345#L734-1 assume { :end_inline_reset_delta_events } true; 2687#L940-2 [2022-12-13 16:15:58,394 INFO L750 eck$LassoCheckResult]: Loop: 2687#L940-2 assume !false; 2700#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2453#L586 assume !false; 2454#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2766#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2628#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2629#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2624#L511 assume !(0 != eval_~tmp~0#1); 2419#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2420#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2681#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2346#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2347#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2343#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2293#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2294#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2295#L636-3 assume !(0 == ~E_M~0); 2296#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2360#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2370#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2371#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2609#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2781#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2519#L304-21 assume !(1 == ~m_pc~0); 2373#L304-23 is_master_triggered_~__retres1~0#1 := 0; 2374#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2447#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2448#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2578#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2611#L323-21 assume 1 == ~t1_pc~0; 2257#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2259#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2393#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2394#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2742#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2754#L342-21 assume 1 == ~t2_pc~0; 2281#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2282#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2589#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2590#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2386#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2387#L361-21 assume !(1 == ~t3_pc~0); 2770#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 2771#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2775#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2552#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2286#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2287#L380-21 assume 1 == ~t4_pc~0; 2760#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2351#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2424#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2707#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2658#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2500#L399-21 assume !(1 == ~t5_pc~0); 2356#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 2357#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2648#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2649#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2765#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2284#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2285#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2563#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2234#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2235#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2273#L699-3 assume !(1 == ~T5_E~0); 2274#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2685#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2676#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2524#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2271#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2272#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2664#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2302#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2303#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2610#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2643#L959 assume !(0 == start_simulation_~tmp~3#1); 2647#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2554#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2555#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2317#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2318#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2474#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2475#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2686#L972 assume !(0 != start_simulation_~tmp___0~1#1); 2687#L940-2 [2022-12-13 16:15:58,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,395 INFO L85 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2022-12-13 16:15:58,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,396 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729498871] [2022-12-13 16:15:58,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,429 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [729498871] [2022-12-13 16:15:58,429 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [729498871] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,429 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,429 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:58,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2019756613] [2022-12-13 16:15:58,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,430 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:15:58,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,430 INFO L85 PathProgramCache]: Analyzing trace with hash -1890386195, now seen corresponding path program 1 times [2022-12-13 16:15:58,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,430 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425861748] [2022-12-13 16:15:58,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,467 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425861748] [2022-12-13 16:15:58,468 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425861748] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,468 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,468 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:58,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1325605258] [2022-12-13 16:15:58,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,468 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:15:58,468 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:15:58,468 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:15:58,469 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:15:58,469 INFO L87 Difference]: Start difference. First operand 551 states and 826 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:15:58,483 INFO L93 Difference]: Finished difference Result 551 states and 825 transitions. [2022-12-13 16:15:58,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 825 transitions. [2022-12-13 16:15:58,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-12-13 16:15:58,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 825 transitions. [2022-12-13 16:15:58,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2022-12-13 16:15:58,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2022-12-13 16:15:58,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 825 transitions. [2022-12-13 16:15:58,488 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:15:58,488 INFO L218 hiAutomatonCegarLoop]: Abstraction has 551 states and 825 transitions. [2022-12-13 16:15:58,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 825 transitions. [2022-12-13 16:15:58,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2022-12-13 16:15:58,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4972776769509981) internal successors, (825), 550 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 825 transitions. [2022-12-13 16:15:58,495 INFO L240 hiAutomatonCegarLoop]: Abstraction has 551 states and 825 transitions. [2022-12-13 16:15:58,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:15:58,496 INFO L428 stractBuchiCegarLoop]: Abstraction has 551 states and 825 transitions. [2022-12-13 16:15:58,496 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 16:15:58,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 825 transitions. [2022-12-13 16:15:58,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-12-13 16:15:58,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:15:58,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:15:58,499 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,499 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,499 INFO L748 eck$LassoCheckResult]: Stem: 3678#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3679#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3777#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3778#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3763#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 3764#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3621#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3622#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3599#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3600#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3828#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3702#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 3703#L611-2 assume !(0 == ~T1_E~0); 3841#L616-1 assume !(0 == ~T2_E~0); 3842#L621-1 assume !(0 == ~T3_E~0); 3467#L626-1 assume !(0 == ~T4_E~0); 3468#L631-1 assume !(0 == ~T5_E~0); 3662#L636-1 assume !(0 == ~E_M~0); 3520#L641-1 assume !(0 == ~E_1~0); 3521#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3676#L651-1 assume !(0 == ~E_3~0); 3870#L656-1 assume !(0 == ~E_4~0); 3826#L661-1 assume !(0 == ~E_5~0); 3827#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3853#L304 assume !(1 == ~m_pc~0); 3546#L304-2 is_master_triggered_~__retres1~0#1 := 0; 3442#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3443#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3397#L755 assume !(0 != activate_threads_~tmp~1#1); 3398#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3353#L323 assume 1 == ~t1_pc~0; 3354#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3414#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3415#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3430#L763 assume !(0 != activate_threads_~tmp___0~0#1); 3889#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3421#L342 assume 1 == ~t2_pc~0; 3422#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3549#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3550#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3779#L771 assume !(0 != activate_threads_~tmp___1~0#1); 3823#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3734#L361 assume !(1 == ~t3_pc~0); 3735#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3759#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3369#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3370#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3435#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3436#L380 assume 1 == ~t4_pc~0; 3489#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3490#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3516#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3517#L787 assume !(0 != activate_threads_~tmp___3~0#1); 3766#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3492#L399 assume !(1 == ~t5_pc~0); 3493#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3632#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3636#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3623#L795 assume !(0 != activate_threads_~tmp___4~0#1); 3624#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3878#L679 assume !(1 == ~M_E~0); 3700#L679-2 assume !(1 == ~T1_E~0); 3564#L684-1 assume !(1 == ~T2_E~0); 3565#L689-1 assume !(1 == ~T3_E~0); 3742#L694-1 assume !(1 == ~T4_E~0); 3740#L699-1 assume !(1 == ~T5_E~0); 3741#L704-1 assume !(1 == ~E_M~0); 3724#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3666#L714-1 assume !(1 == ~E_2~0); 3667#L719-1 assume !(1 == ~E_3~0); 3819#L724-1 assume !(1 == ~E_4~0); 3453#L729-1 assume !(1 == ~E_5~0); 3454#L734-1 assume { :end_inline_reset_delta_events } true; 3796#L940-2 [2022-12-13 16:15:58,500 INFO L750 eck$LassoCheckResult]: Loop: 3796#L940-2 assume !false; 3809#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3562#L586 assume !false; 3563#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3875#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3737#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3738#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3733#L511 assume !(0 != eval_~tmp~0#1); 3528#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3529#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3790#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3455#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3456#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3452#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3402#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3403#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3404#L636-3 assume !(0 == ~E_M~0); 3405#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3469#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3479#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3480#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3718#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3890#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3628#L304-21 assume !(1 == ~m_pc~0); 3482#L304-23 is_master_triggered_~__retres1~0#1 := 0; 3483#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3556#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3557#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3687#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3720#L323-21 assume 1 == ~t1_pc~0; 3366#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3368#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3502#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3503#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3851#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3863#L342-21 assume !(1 == ~t2_pc~0); 3392#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 3391#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3696#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3697#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3495#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3496#L361-21 assume !(1 == ~t3_pc~0); 3879#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 3880#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3884#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3661#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3395#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3396#L380-21 assume !(1 == ~t4_pc~0); 3459#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 3460#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3533#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3816#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3767#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3609#L399-21 assume 1 == ~t5_pc~0; 3585#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3466#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3757#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3758#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3874#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3393#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3394#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3672#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3343#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3344#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3382#L699-3 assume !(1 == ~T5_E~0); 3383#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3794#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3785#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3633#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3380#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3381#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3775#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3411#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3412#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3719#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3752#L959 assume !(0 == start_simulation_~tmp~3#1); 3756#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3663#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3664#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3426#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 3427#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3583#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3584#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3795#L972 assume !(0 != start_simulation_~tmp___0~1#1); 3796#L940-2 [2022-12-13 16:15:58,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,500 INFO L85 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2022-12-13 16:15:58,500 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,500 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458137648] [2022-12-13 16:15:58,500 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,500 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,526 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,526 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1458137648] [2022-12-13 16:15:58,526 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1458137648] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,526 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,526 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:58,526 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1277386114] [2022-12-13 16:15:58,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,527 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:15:58,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,527 INFO L85 PathProgramCache]: Analyzing trace with hash -1820419218, now seen corresponding path program 1 times [2022-12-13 16:15:58,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1377089113] [2022-12-13 16:15:58,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,568 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,568 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1377089113] [2022-12-13 16:15:58,568 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1377089113] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,568 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,568 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:58,568 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1789148086] [2022-12-13 16:15:58,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,569 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:15:58,569 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:15:58,569 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:15:58,569 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:15:58,569 INFO L87 Difference]: Start difference. First operand 551 states and 825 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:15:58,582 INFO L93 Difference]: Finished difference Result 551 states and 824 transitions. [2022-12-13 16:15:58,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 824 transitions. [2022-12-13 16:15:58,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-12-13 16:15:58,586 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 824 transitions. [2022-12-13 16:15:58,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2022-12-13 16:15:58,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2022-12-13 16:15:58,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 824 transitions. [2022-12-13 16:15:58,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:15:58,587 INFO L218 hiAutomatonCegarLoop]: Abstraction has 551 states and 824 transitions. [2022-12-13 16:15:58,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 824 transitions. [2022-12-13 16:15:58,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2022-12-13 16:15:58,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4954627949183303) internal successors, (824), 550 states have internal predecessors, (824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 824 transitions. [2022-12-13 16:15:58,593 INFO L240 hiAutomatonCegarLoop]: Abstraction has 551 states and 824 transitions. [2022-12-13 16:15:58,593 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:15:58,594 INFO L428 stractBuchiCegarLoop]: Abstraction has 551 states and 824 transitions. [2022-12-13 16:15:58,594 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 16:15:58,594 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 824 transitions. [2022-12-13 16:15:58,595 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-12-13 16:15:58,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:15:58,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:15:58,596 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,596 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,597 INFO L748 eck$LassoCheckResult]: Stem: 4787#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4788#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4886#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4887#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4872#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 4873#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4730#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4731#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4708#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4709#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4937#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4811#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 4812#L611-2 assume !(0 == ~T1_E~0); 4950#L616-1 assume !(0 == ~T2_E~0); 4951#L621-1 assume !(0 == ~T3_E~0); 4576#L626-1 assume !(0 == ~T4_E~0); 4577#L631-1 assume !(0 == ~T5_E~0); 4771#L636-1 assume !(0 == ~E_M~0); 4629#L641-1 assume !(0 == ~E_1~0); 4630#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4785#L651-1 assume !(0 == ~E_3~0); 4979#L656-1 assume !(0 == ~E_4~0); 4935#L661-1 assume !(0 == ~E_5~0); 4936#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4962#L304 assume !(1 == ~m_pc~0); 4655#L304-2 is_master_triggered_~__retres1~0#1 := 0; 4551#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4552#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4506#L755 assume !(0 != activate_threads_~tmp~1#1); 4507#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4464#L323 assume 1 == ~t1_pc~0; 4465#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4523#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4524#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4539#L763 assume !(0 != activate_threads_~tmp___0~0#1); 4998#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4530#L342 assume 1 == ~t2_pc~0; 4531#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4658#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4659#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4888#L771 assume !(0 != activate_threads_~tmp___1~0#1); 4932#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4843#L361 assume !(1 == ~t3_pc~0); 4844#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4868#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4478#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4479#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4544#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4545#L380 assume 1 == ~t4_pc~0; 4598#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4599#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4625#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4626#L787 assume !(0 != activate_threads_~tmp___3~0#1); 4875#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4601#L399 assume !(1 == ~t5_pc~0); 4602#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4741#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4745#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4732#L795 assume !(0 != activate_threads_~tmp___4~0#1); 4733#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4987#L679 assume !(1 == ~M_E~0); 4810#L679-2 assume !(1 == ~T1_E~0); 4673#L684-1 assume !(1 == ~T2_E~0); 4674#L689-1 assume !(1 == ~T3_E~0); 4851#L694-1 assume !(1 == ~T4_E~0); 4849#L699-1 assume !(1 == ~T5_E~0); 4850#L704-1 assume !(1 == ~E_M~0); 4833#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4776#L714-1 assume !(1 == ~E_2~0); 4777#L719-1 assume !(1 == ~E_3~0); 4928#L724-1 assume !(1 == ~E_4~0); 4562#L729-1 assume !(1 == ~E_5~0); 4563#L734-1 assume { :end_inline_reset_delta_events } true; 4905#L940-2 [2022-12-13 16:15:58,597 INFO L750 eck$LassoCheckResult]: Loop: 4905#L940-2 assume !false; 4918#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4671#L586 assume !false; 4672#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4984#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4846#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4847#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4842#L511 assume !(0 != eval_~tmp~0#1); 4637#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4638#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4899#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4564#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4565#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4561#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4511#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4512#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4513#L636-3 assume !(0 == ~E_M~0); 4514#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4578#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4588#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4589#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4827#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4999#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4737#L304-21 assume 1 == ~m_pc~0; 4738#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4592#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4665#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4666#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4796#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4829#L323-21 assume 1 == ~t1_pc~0; 4475#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4477#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4611#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4612#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4960#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4972#L342-21 assume 1 == ~t2_pc~0; 4499#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4500#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4807#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4808#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4604#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4605#L361-21 assume 1 == ~t3_pc~0; 4992#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4989#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4993#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4770#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4504#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4505#L380-21 assume 1 == ~t4_pc~0; 4978#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4571#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4642#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4926#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4876#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4718#L399-21 assume 1 == ~t5_pc~0; 4694#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4575#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4866#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4867#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4983#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4502#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4503#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4781#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4452#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4453#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4491#L699-3 assume !(1 == ~T5_E~0); 4492#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4903#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4894#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4742#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4489#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4490#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4884#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4520#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4521#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4828#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4861#L959 assume !(0 == start_simulation_~tmp~3#1); 4865#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4773#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4774#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4537#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 4538#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4692#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4693#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4904#L972 assume !(0 != start_simulation_~tmp___0~1#1); 4905#L940-2 [2022-12-13 16:15:58,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,597 INFO L85 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2022-12-13 16:15:58,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,598 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538325091] [2022-12-13 16:15:58,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,619 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1538325091] [2022-12-13 16:15:58,620 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1538325091] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,620 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,620 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:58,620 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201312535] [2022-12-13 16:15:58,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,621 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:15:58,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,621 INFO L85 PathProgramCache]: Analyzing trace with hash 1248989610, now seen corresponding path program 1 times [2022-12-13 16:15:58,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,621 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242109820] [2022-12-13 16:15:58,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,653 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242109820] [2022-12-13 16:15:58,653 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [242109820] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,653 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,654 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:58,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2021267520] [2022-12-13 16:15:58,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,654 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:15:58,654 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:15:58,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:15:58,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:15:58,655 INFO L87 Difference]: Start difference. First operand 551 states and 824 transitions. cyclomatic complexity: 274 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:15:58,665 INFO L93 Difference]: Finished difference Result 551 states and 823 transitions. [2022-12-13 16:15:58,665 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 823 transitions. [2022-12-13 16:15:58,667 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-12-13 16:15:58,669 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 823 transitions. [2022-12-13 16:15:58,669 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2022-12-13 16:15:58,669 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2022-12-13 16:15:58,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 823 transitions. [2022-12-13 16:15:58,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:15:58,670 INFO L218 hiAutomatonCegarLoop]: Abstraction has 551 states and 823 transitions. [2022-12-13 16:15:58,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 823 transitions. [2022-12-13 16:15:58,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2022-12-13 16:15:58,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4936479128856623) internal successors, (823), 550 states have internal predecessors, (823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 823 transitions. [2022-12-13 16:15:58,676 INFO L240 hiAutomatonCegarLoop]: Abstraction has 551 states and 823 transitions. [2022-12-13 16:15:58,676 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:15:58,677 INFO L428 stractBuchiCegarLoop]: Abstraction has 551 states and 823 transitions. [2022-12-13 16:15:58,677 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 16:15:58,677 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 823 transitions. [2022-12-13 16:15:58,678 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-12-13 16:15:58,678 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:15:58,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:15:58,679 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,679 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,680 INFO L748 eck$LassoCheckResult]: Stem: 5896#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5897#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5995#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5996#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5981#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 5982#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5839#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5840#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5817#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5818#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6046#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5920#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 5921#L611-2 assume !(0 == ~T1_E~0); 6059#L616-1 assume !(0 == ~T2_E~0); 6060#L621-1 assume !(0 == ~T3_E~0); 5689#L626-1 assume !(0 == ~T4_E~0); 5690#L631-1 assume !(0 == ~T5_E~0); 5880#L636-1 assume !(0 == ~E_M~0); 5741#L641-1 assume !(0 == ~E_1~0); 5742#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5894#L651-1 assume !(0 == ~E_3~0); 6088#L656-1 assume !(0 == ~E_4~0); 6044#L661-1 assume !(0 == ~E_5~0); 6045#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6071#L304 assume !(1 == ~m_pc~0); 5765#L304-2 is_master_triggered_~__retres1~0#1 := 0; 5660#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5661#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5618#L755 assume !(0 != activate_threads_~tmp~1#1); 5619#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5573#L323 assume 1 == ~t1_pc~0; 5574#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5632#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5633#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5648#L763 assume !(0 != activate_threads_~tmp___0~0#1); 6107#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5641#L342 assume 1 == ~t2_pc~0; 5642#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5767#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5768#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5997#L771 assume !(0 != activate_threads_~tmp___1~0#1); 6041#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5952#L361 assume !(1 == ~t3_pc~0); 5953#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5977#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5587#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5588#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5653#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5654#L380 assume 1 == ~t4_pc~0; 5707#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5708#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5736#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5737#L787 assume !(0 != activate_threads_~tmp___3~0#1); 5984#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5710#L399 assume !(1 == ~t5_pc~0); 5711#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5850#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5854#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5841#L795 assume !(0 != activate_threads_~tmp___4~0#1); 5842#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6096#L679 assume !(1 == ~M_E~0); 5919#L679-2 assume !(1 == ~T1_E~0); 5782#L684-1 assume !(1 == ~T2_E~0); 5783#L689-1 assume !(1 == ~T3_E~0); 5960#L694-1 assume !(1 == ~T4_E~0); 5958#L699-1 assume !(1 == ~T5_E~0); 5959#L704-1 assume !(1 == ~E_M~0); 5942#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5885#L714-1 assume !(1 == ~E_2~0); 5886#L719-1 assume !(1 == ~E_3~0); 6037#L724-1 assume !(1 == ~E_4~0); 5671#L729-1 assume !(1 == ~E_5~0); 5672#L734-1 assume { :end_inline_reset_delta_events } true; 6015#L940-2 [2022-12-13 16:15:58,680 INFO L750 eck$LassoCheckResult]: Loop: 6015#L940-2 assume !false; 6027#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5780#L586 assume !false; 5781#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6093#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5955#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5956#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5951#L511 assume !(0 != eval_~tmp~0#1); 5746#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5747#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6008#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5673#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5674#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5669#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5620#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5621#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5622#L636-3 assume !(0 == ~E_M~0); 5623#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5683#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5697#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5698#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5936#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6108#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5846#L304-21 assume !(1 == ~m_pc~0); 5700#L304-23 is_master_triggered_~__retres1~0#1 := 0; 5701#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5774#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5775#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5905#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5938#L323-21 assume 1 == ~t1_pc~0; 5584#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5586#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5720#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5721#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6069#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6081#L342-21 assume 1 == ~t2_pc~0; 5608#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5609#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5916#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5917#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5713#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5714#L361-21 assume !(1 == ~t3_pc~0); 6097#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 6098#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6102#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5879#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5616#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5617#L380-21 assume 1 == ~t4_pc~0; 6087#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5680#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5751#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6035#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5985#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5827#L399-21 assume !(1 == ~t5_pc~0); 5687#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 5688#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5975#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5976#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6092#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5611#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5612#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5890#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5561#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5562#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5600#L699-3 assume !(1 == ~T5_E~0); 5601#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6013#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6003#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5851#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5598#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5599#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5993#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5629#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5630#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5937#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5970#L959 assume !(0 == start_simulation_~tmp~3#1); 5974#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5882#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5883#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5646#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 5647#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5801#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5802#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6014#L972 assume !(0 != start_simulation_~tmp___0~1#1); 6015#L940-2 [2022-12-13 16:15:58,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,680 INFO L85 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2022-12-13 16:15:58,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,680 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759849372] [2022-12-13 16:15:58,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1759849372] [2022-12-13 16:15:58,715 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1759849372] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,716 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,716 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:15:58,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1947663760] [2022-12-13 16:15:58,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,716 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:15:58,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,717 INFO L85 PathProgramCache]: Analyzing trace with hash -1890386195, now seen corresponding path program 2 times [2022-12-13 16:15:58,717 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,717 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322163689] [2022-12-13 16:15:58,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,745 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,745 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1322163689] [2022-12-13 16:15:58,745 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1322163689] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,745 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,746 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:58,746 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1448323184] [2022-12-13 16:15:58,746 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,746 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:15:58,746 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:15:58,747 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:15:58,747 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:15:58,747 INFO L87 Difference]: Start difference. First operand 551 states and 823 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:15:58,779 INFO L93 Difference]: Finished difference Result 979 states and 1457 transitions. [2022-12-13 16:15:58,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 979 states and 1457 transitions. [2022-12-13 16:15:58,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 900 [2022-12-13 16:15:58,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 979 states to 979 states and 1457 transitions. [2022-12-13 16:15:58,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 979 [2022-12-13 16:15:58,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 979 [2022-12-13 16:15:58,786 INFO L73 IsDeterministic]: Start isDeterministic. Operand 979 states and 1457 transitions. [2022-12-13 16:15:58,787 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:15:58,787 INFO L218 hiAutomatonCegarLoop]: Abstraction has 979 states and 1457 transitions. [2022-12-13 16:15:58,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 979 states and 1457 transitions. [2022-12-13 16:15:58,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 979 to 979. [2022-12-13 16:15:58,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 979 states, 979 states have (on average 1.4882533197139938) internal successors, (1457), 978 states have internal predecessors, (1457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 979 states to 979 states and 1457 transitions. [2022-12-13 16:15:58,800 INFO L240 hiAutomatonCegarLoop]: Abstraction has 979 states and 1457 transitions. [2022-12-13 16:15:58,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:15:58,801 INFO L428 stractBuchiCegarLoop]: Abstraction has 979 states and 1457 transitions. [2022-12-13 16:15:58,801 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 16:15:58,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 979 states and 1457 transitions. [2022-12-13 16:15:58,805 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 900 [2022-12-13 16:15:58,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:15:58,806 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:15:58,807 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,807 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,807 INFO L748 eck$LassoCheckResult]: Stem: 7441#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7442#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7540#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7541#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7526#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 7527#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7381#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7382#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7356#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7357#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7600#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7465#L611 assume !(0 == ~M_E~0); 7466#L611-2 assume !(0 == ~T1_E~0); 7613#L616-1 assume !(0 == ~T2_E~0); 7614#L621-1 assume !(0 == ~T3_E~0); 7226#L626-1 assume !(0 == ~T4_E~0); 7227#L631-1 assume !(0 == ~T5_E~0); 7422#L636-1 assume !(0 == ~E_M~0); 7278#L641-1 assume !(0 == ~E_1~0); 7279#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7437#L651-1 assume !(0 == ~E_3~0); 7646#L656-1 assume !(0 == ~E_4~0); 7598#L661-1 assume !(0 == ~E_5~0); 7599#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7627#L304 assume !(1 == ~m_pc~0); 7299#L304-2 is_master_triggered_~__retres1~0#1 := 0; 7197#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7198#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7150#L755 assume !(0 != activate_threads_~tmp~1#1); 7151#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7106#L323 assume 1 == ~t1_pc~0; 7107#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7169#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7170#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7185#L763 assume !(0 != activate_threads_~tmp___0~0#1); 7670#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7172#L342 assume 1 == ~t2_pc~0; 7173#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7305#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7306#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7542#L771 assume !(0 != activate_threads_~tmp___1~0#1); 7594#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7497#L361 assume !(1 == ~t3_pc~0); 7498#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7522#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7124#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7125#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7188#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7189#L380 assume 1 == ~t4_pc~0; 7244#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7245#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7270#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7271#L787 assume !(0 != activate_threads_~tmp___3~0#1); 7529#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7247#L399 assume !(1 == ~t5_pc~0); 7248#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7391#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7396#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7383#L795 assume !(0 != activate_threads_~tmp___4~0#1); 7384#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7655#L679 assume !(1 == ~M_E~0); 7463#L679-2 assume !(1 == ~T1_E~0); 7320#L684-1 assume !(1 == ~T2_E~0); 7321#L689-1 assume !(1 == ~T3_E~0); 7505#L694-1 assume !(1 == ~T4_E~0); 7503#L699-1 assume !(1 == ~T5_E~0); 7504#L704-1 assume !(1 == ~E_M~0); 7487#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7423#L714-1 assume !(1 == ~E_2~0); 7424#L719-1 assume !(1 == ~E_3~0); 7588#L724-1 assume !(1 == ~E_4~0); 7208#L729-1 assume !(1 == ~E_5~0); 7209#L734-1 assume { :end_inline_reset_delta_events } true; 7658#L940-2 [2022-12-13 16:15:58,807 INFO L750 eck$LassoCheckResult]: Loop: 7658#L940-2 assume !false; 7624#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7316#L586 assume !false; 7317#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7651#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7500#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7501#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7496#L511 assume !(0 != eval_~tmp~0#1); 7283#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7284#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7557#L611-3 assume !(0 == ~M_E~0); 7210#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7211#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7206#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7157#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7158#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7159#L636-3 assume !(0 == ~E_M~0); 7160#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7220#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7234#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7235#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7481#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7671#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7388#L304-21 assume !(1 == ~m_pc~0); 7237#L304-23 is_master_triggered_~__retres1~0#1 := 0; 7238#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7312#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7313#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7450#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7483#L323-21 assume 1 == ~t1_pc~0; 7121#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7123#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7257#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7258#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7625#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7639#L342-21 assume 1 == ~t2_pc~0; 7145#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7146#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7461#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7462#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7692#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7691#L361-21 assume !(1 == ~t3_pc~0); 7689#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 7662#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7663#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7688#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7687#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7686#L380-21 assume !(1 == ~t4_pc~0); 7216#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 7217#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7685#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7586#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7587#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7684#L399-21 assume !(1 == ~t5_pc~0); 7224#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 7225#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7520#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7521#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7650#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7148#L679-3 assume !(1 == ~M_E~0); 7149#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8076#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8075#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8074#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8073#L699-3 assume !(1 == ~T5_E~0); 8072#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8071#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8070#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8069#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8067#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8065#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8063#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 8055#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 8049#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 8048#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 8047#L959 assume !(0 == start_simulation_~tmp~3#1); 8045#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7754#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7748#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7746#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7744#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7743#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7742#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7741#L972 assume !(0 != start_simulation_~tmp___0~1#1); 7658#L940-2 [2022-12-13 16:15:58,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,808 INFO L85 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2022-12-13 16:15:58,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,808 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131809341] [2022-12-13 16:15:58,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,856 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131809341] [2022-12-13 16:15:58,857 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [131809341] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,857 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,857 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:15:58,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2033018015] [2022-12-13 16:15:58,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,857 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:15:58,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,858 INFO L85 PathProgramCache]: Analyzing trace with hash 262645230, now seen corresponding path program 1 times [2022-12-13 16:15:58,858 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,858 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1519058493] [2022-12-13 16:15:58,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,893 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1519058493] [2022-12-13 16:15:58,893 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1519058493] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,893 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,893 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:58,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2071056051] [2022-12-13 16:15:58,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,894 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:15:58,894 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:15:58,894 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:15:58,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:15:58,895 INFO L87 Difference]: Start difference. First operand 979 states and 1457 transitions. cyclomatic complexity: 479 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:15:58,925 INFO L93 Difference]: Finished difference Result 979 states and 1435 transitions. [2022-12-13 16:15:58,926 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 979 states and 1435 transitions. [2022-12-13 16:15:58,929 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 900 [2022-12-13 16:15:58,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 979 states to 979 states and 1435 transitions. [2022-12-13 16:15:58,932 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 979 [2022-12-13 16:15:58,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 979 [2022-12-13 16:15:58,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 979 states and 1435 transitions. [2022-12-13 16:15:58,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:15:58,934 INFO L218 hiAutomatonCegarLoop]: Abstraction has 979 states and 1435 transitions. [2022-12-13 16:15:58,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 979 states and 1435 transitions. [2022-12-13 16:15:58,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 979 to 979. [2022-12-13 16:15:58,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 979 states, 979 states have (on average 1.4657814096016344) internal successors, (1435), 978 states have internal predecessors, (1435), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:58,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 979 states to 979 states and 1435 transitions. [2022-12-13 16:15:58,947 INFO L240 hiAutomatonCegarLoop]: Abstraction has 979 states and 1435 transitions. [2022-12-13 16:15:58,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:15:58,948 INFO L428 stractBuchiCegarLoop]: Abstraction has 979 states and 1435 transitions. [2022-12-13 16:15:58,948 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 16:15:58,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 979 states and 1435 transitions. [2022-12-13 16:15:58,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 900 [2022-12-13 16:15:58,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:15:58,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:15:58,952 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,952 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:58,952 INFO L748 eck$LassoCheckResult]: Stem: 9405#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9406#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9509#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9510#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9495#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 9496#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9343#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9344#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9319#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9320#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9575#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9429#L611 assume !(0 == ~M_E~0); 9430#L611-2 assume !(0 == ~T1_E~0); 9588#L616-1 assume !(0 == ~T2_E~0); 9589#L621-1 assume !(0 == ~T3_E~0); 9190#L626-1 assume !(0 == ~T4_E~0); 9191#L631-1 assume !(0 == ~T5_E~0); 9385#L636-1 assume !(0 == ~E_M~0); 9242#L641-1 assume !(0 == ~E_1~0); 9243#L646-1 assume !(0 == ~E_2~0); 9400#L651-1 assume !(0 == ~E_3~0); 9627#L656-1 assume !(0 == ~E_4~0); 9573#L661-1 assume !(0 == ~E_5~0); 9574#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9604#L304 assume !(1 == ~m_pc~0); 9267#L304-2 is_master_triggered_~__retres1~0#1 := 0; 9161#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9162#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9119#L755 assume !(0 != activate_threads_~tmp~1#1); 9120#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9075#L323 assume 1 == ~t1_pc~0; 9076#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9133#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9134#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9149#L763 assume !(0 != activate_threads_~tmp___0~0#1); 9648#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9142#L342 assume !(1 == ~t2_pc~0); 9144#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9269#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9270#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9511#L771 assume !(0 != activate_threads_~tmp___1~0#1); 9569#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9463#L361 assume !(1 == ~t3_pc~0); 9464#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9490#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9089#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9090#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9154#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9155#L380 assume 1 == ~t4_pc~0; 9208#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9209#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9237#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9238#L787 assume !(0 != activate_threads_~tmp___3~0#1); 9498#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9211#L399 assume !(1 == ~t5_pc~0); 9212#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9354#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9358#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9345#L795 assume !(0 != activate_threads_~tmp___4~0#1); 9346#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9636#L679 assume !(1 == ~M_E~0); 9428#L679-2 assume !(1 == ~T1_E~0); 9284#L684-1 assume !(1 == ~T2_E~0); 9285#L689-1 assume !(1 == ~T3_E~0); 9472#L694-1 assume !(1 == ~T4_E~0); 9470#L699-1 assume !(1 == ~T5_E~0); 9471#L704-1 assume !(1 == ~E_M~0); 9453#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9390#L714-1 assume !(1 == ~E_2~0); 9391#L719-1 assume !(1 == ~E_3~0); 9563#L724-1 assume !(1 == ~E_4~0); 9172#L729-1 assume !(1 == ~E_5~0); 9173#L734-1 assume { :end_inline_reset_delta_events } true; 9551#L940-2 [2022-12-13 16:15:58,952 INFO L750 eck$LassoCheckResult]: Loop: 9551#L940-2 assume !false; 9552#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9282#L586 assume !false; 9283#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9632#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9701#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9526#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9462#L511 assume !(0 != eval_~tmp~0#1); 9247#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9248#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9527#L611-3 assume !(0 == ~M_E~0); 9528#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9700#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9170#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9121#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9122#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9123#L636-3 assume !(0 == ~E_M~0); 9124#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9184#L646-3 assume !(0 == ~E_2~0); 9695#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9445#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9446#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9649#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9350#L304-21 assume !(1 == ~m_pc~0); 9201#L304-23 is_master_triggered_~__retres1~0#1 := 0; 9202#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9276#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9277#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9414#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9449#L323-21 assume 1 == ~t1_pc~0; 9086#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9088#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9682#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9681#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9680#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9679#L342-21 assume !(1 == ~t2_pc~0); 9677#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 9676#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9675#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9570#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9214#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9215#L361-21 assume !(1 == ~t3_pc~0); 9637#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 9638#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9670#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9669#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9668#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9667#L380-21 assume 1 == ~t4_pc~0; 9625#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9181#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9666#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9560#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9561#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9665#L399-21 assume !(1 == ~t5_pc~0); 9188#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 9189#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9488#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9489#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9631#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9112#L679-3 assume !(1 == ~M_E~0); 9113#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9787#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9786#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9785#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9784#L699-3 assume !(1 == ~T5_E~0); 9783#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9782#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9781#L714-3 assume !(1 == ~E_2~0); 9780#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9779#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9778#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9547#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9548#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9447#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9448#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9482#L959 assume !(0 == start_simulation_~tmp~3#1); 9760#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9758#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9753#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9752#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 9751#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9750#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9749#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 9748#L972 assume !(0 != start_simulation_~tmp___0~1#1); 9551#L940-2 [2022-12-13 16:15:58,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,952 INFO L85 PathProgramCache]: Analyzing trace with hash -820631741, now seen corresponding path program 1 times [2022-12-13 16:15:58,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,953 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145224521] [2022-12-13 16:15:58,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:58,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:58,987 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:58,987 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1145224521] [2022-12-13 16:15:58,987 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1145224521] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:58,987 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:58,987 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:58,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [714611316] [2022-12-13 16:15:58,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:58,987 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:15:58,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:58,988 INFO L85 PathProgramCache]: Analyzing trace with hash -1714726738, now seen corresponding path program 1 times [2022-12-13 16:15:58,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:58,988 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413445981] [2022-12-13 16:15:58,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:58,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:58,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:59,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:59,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:59,012 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413445981] [2022-12-13 16:15:59,012 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [413445981] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:59,012 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:59,012 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:59,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1789271670] [2022-12-13 16:15:59,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:59,013 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:15:59,013 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:15:59,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 16:15:59,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 16:15:59,013 INFO L87 Difference]: Start difference. First operand 979 states and 1435 transitions. cyclomatic complexity: 457 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:59,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:15:59,145 INFO L93 Difference]: Finished difference Result 2612 states and 3762 transitions. [2022-12-13 16:15:59,145 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2612 states and 3762 transitions. [2022-12-13 16:15:59,155 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2437 [2022-12-13 16:15:59,162 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2612 states to 2612 states and 3762 transitions. [2022-12-13 16:15:59,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2612 [2022-12-13 16:15:59,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2612 [2022-12-13 16:15:59,164 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2612 states and 3762 transitions. [2022-12-13 16:15:59,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:15:59,167 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2612 states and 3762 transitions. [2022-12-13 16:15:59,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2612 states and 3762 transitions. [2022-12-13 16:15:59,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2612 to 2452. [2022-12-13 16:15:59,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2452 states, 2452 states have (on average 1.4469820554649266) internal successors, (3548), 2451 states have internal predecessors, (3548), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:59,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2452 states to 2452 states and 3548 transitions. [2022-12-13 16:15:59,212 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2452 states and 3548 transitions. [2022-12-13 16:15:59,212 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:15:59,213 INFO L428 stractBuchiCegarLoop]: Abstraction has 2452 states and 3548 transitions. [2022-12-13 16:15:59,213 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 16:15:59,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2452 states and 3548 transitions. [2022-12-13 16:15:59,221 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2365 [2022-12-13 16:15:59,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:15:59,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:15:59,222 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:59,222 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:59,222 INFO L748 eck$LassoCheckResult]: Stem: 13018#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 13019#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 13131#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13132#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13117#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 13118#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12953#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12954#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12928#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12929#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13207#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13044#L611 assume !(0 == ~M_E~0); 13045#L611-2 assume !(0 == ~T1_E~0); 13224#L616-1 assume !(0 == ~T2_E~0); 13225#L621-1 assume !(0 == ~T3_E~0); 12791#L626-1 assume !(0 == ~T4_E~0); 12792#L631-1 assume !(0 == ~T5_E~0); 12998#L636-1 assume !(0 == ~E_M~0); 12844#L641-1 assume !(0 == ~E_1~0); 12845#L646-1 assume !(0 == ~E_2~0); 13013#L651-1 assume !(0 == ~E_3~0); 13276#L656-1 assume !(0 == ~E_4~0); 13205#L661-1 assume !(0 == ~E_5~0); 13206#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13243#L304 assume !(1 == ~m_pc~0); 12869#L304-2 is_master_triggered_~__retres1~0#1 := 0; 12764#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12765#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12716#L755 assume !(0 != activate_threads_~tmp~1#1); 12717#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12672#L323 assume !(1 == ~t1_pc~0); 12673#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12733#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12734#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12748#L763 assume !(0 != activate_threads_~tmp___0~0#1); 13320#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12740#L342 assume !(1 == ~t2_pc~0); 12742#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12875#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12876#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13133#L771 assume !(0 != activate_threads_~tmp___1~0#1); 13198#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13080#L361 assume !(1 == ~t3_pc~0); 13081#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13110#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12689#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12690#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12753#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12754#L380 assume 1 == ~t4_pc~0; 12814#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12815#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12840#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12841#L787 assume !(0 != activate_threads_~tmp___3~0#1); 13120#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12817#L399 assume !(1 == ~t5_pc~0); 12818#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12963#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12970#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12955#L795 assume !(0 != activate_threads_~tmp___4~0#1); 12956#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13290#L679 assume !(1 == ~M_E~0); 13042#L679-2 assume !(1 == ~T1_E~0); 12891#L684-1 assume !(1 == ~T2_E~0); 12892#L689-1 assume !(1 == ~T3_E~0); 13089#L694-1 assume !(1 == ~T4_E~0); 13087#L699-1 assume !(1 == ~T5_E~0); 13088#L704-1 assume !(1 == ~E_M~0); 13067#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12999#L714-1 assume !(1 == ~E_2~0); 13000#L719-1 assume !(1 == ~E_3~0); 13191#L724-1 assume !(1 == ~E_4~0); 12777#L729-1 assume !(1 == ~E_5~0); 12778#L734-1 assume { :end_inline_reset_delta_events } true; 13179#L940-2 [2022-12-13 16:15:59,222 INFO L750 eck$LassoCheckResult]: Loop: 13179#L940-2 assume !false; 13180#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12889#L586 assume !false; 12890#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13352#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13084#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13085#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13078#L511 assume !(0 != eval_~tmp~0#1); 12852#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12853#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13152#L611-3 assume !(0 == ~M_E~0); 12779#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12780#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12775#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12776#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13369#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13370#L636-3 assume !(0 == ~E_M~0); 12793#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12794#L646-3 assume !(0 == ~E_2~0); 15041#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15040#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15039#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15038#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15037#L304-21 assume !(1 == ~m_pc~0); 15036#L304-23 is_master_triggered_~__retres1~0#1 := 0; 15035#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15034#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13026#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13027#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13317#L323-21 assume !(1 == ~t1_pc~0); 13214#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 13215#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13244#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15030#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15029#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15028#L342-21 assume !(1 == ~t2_pc~0); 13322#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 13113#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13036#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13037#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13202#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15023#L361-21 assume 1 == ~t3_pc~0; 13329#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13294#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13305#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13306#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15017#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15016#L380-21 assume 1 == ~t4_pc~0; 13269#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12784#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13287#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13187#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13188#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15011#L399-21 assume !(1 == ~t5_pc~0); 15009#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 15006#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15005#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13324#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13325#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12712#L679-3 assume !(1 == ~M_E~0); 12713#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13068#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13069#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12979#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12980#L699-3 assume !(1 == ~T5_E~0); 15002#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14999#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14998#L714-3 assume !(1 == ~E_2~0); 14756#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14757#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14752#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14753#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14748#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14598#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 14599#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 13106#L959 assume !(0 == start_simulation_~tmp~3#1); 13107#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13333#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14846#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 14845#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 14844#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14843#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14842#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 14841#L972 assume !(0 != start_simulation_~tmp___0~1#1); 13179#L940-2 [2022-12-13 16:15:59,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:59,223 INFO L85 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2022-12-13 16:15:59,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:59,223 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1792983866] [2022-12-13 16:15:59,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:59,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:59,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:59,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:59,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:59,261 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1792983866] [2022-12-13 16:15:59,261 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1792983866] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:59,261 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:59,261 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:15:59,261 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1076021833] [2022-12-13 16:15:59,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:59,262 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:15:59,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:59,262 INFO L85 PathProgramCache]: Analyzing trace with hash -426418386, now seen corresponding path program 1 times [2022-12-13 16:15:59,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:59,262 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065645138] [2022-12-13 16:15:59,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:59,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:59,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:59,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:59,296 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:59,296 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065645138] [2022-12-13 16:15:59,297 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2065645138] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:59,297 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:59,297 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:59,297 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1522357267] [2022-12-13 16:15:59,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:59,297 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:15:59,297 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:15:59,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 16:15:59,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 16:15:59,298 INFO L87 Difference]: Start difference. First operand 2452 states and 3548 transitions. cyclomatic complexity: 1098 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:59,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:15:59,467 INFO L93 Difference]: Finished difference Result 6124 states and 8898 transitions. [2022-12-13 16:15:59,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6124 states and 8898 transitions. [2022-12-13 16:15:59,490 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5960 [2022-12-13 16:15:59,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6124 states to 6124 states and 8898 transitions. [2022-12-13 16:15:59,518 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6124 [2022-12-13 16:15:59,526 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6124 [2022-12-13 16:15:59,526 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6124 states and 8898 transitions. [2022-12-13 16:15:59,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:15:59,536 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6124 states and 8898 transitions. [2022-12-13 16:15:59,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6124 states and 8898 transitions. [2022-12-13 16:15:59,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6124 to 2572. [2022-12-13 16:15:59,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2572 states, 2572 states have (on average 1.4261275272161742) internal successors, (3668), 2571 states have internal predecessors, (3668), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:59,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2572 states to 2572 states and 3668 transitions. [2022-12-13 16:15:59,635 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2572 states and 3668 transitions. [2022-12-13 16:15:59,635 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 16:15:59,636 INFO L428 stractBuchiCegarLoop]: Abstraction has 2572 states and 3668 transitions. [2022-12-13 16:15:59,636 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 16:15:59,636 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2572 states and 3668 transitions. [2022-12-13 16:15:59,644 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2482 [2022-12-13 16:15:59,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:15:59,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:15:59,645 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:59,646 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:59,646 INFO L748 eck$LassoCheckResult]: Stem: 21602#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 21603#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 21727#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21728#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21709#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 21710#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21537#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21538#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21514#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21515#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21808#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21632#L611 assume !(0 == ~M_E~0); 21633#L611-2 assume !(0 == ~T1_E~0); 21824#L616-1 assume !(0 == ~T2_E~0); 21825#L621-1 assume !(0 == ~T3_E~0); 21381#L626-1 assume !(0 == ~T4_E~0); 21382#L631-1 assume !(0 == ~T5_E~0); 21583#L636-1 assume !(0 == ~E_M~0); 21434#L641-1 assume !(0 == ~E_1~0); 21435#L646-1 assume !(0 == ~E_2~0); 21600#L651-1 assume !(0 == ~E_3~0); 21879#L656-1 assume !(0 == ~E_4~0); 21806#L661-1 assume !(0 == ~E_5~0); 21807#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21845#L304 assume !(1 == ~m_pc~0); 21459#L304-2 is_master_triggered_~__retres1~0#1 := 0; 21352#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21353#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21308#L755 assume !(0 != activate_threads_~tmp~1#1); 21309#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21265#L323 assume !(1 == ~t1_pc~0); 21266#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21322#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21323#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21339#L763 assume !(0 != activate_threads_~tmp___0~0#1); 21927#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21332#L342 assume !(1 == ~t2_pc~0); 21334#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21461#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21462#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21729#L771 assume !(0 != activate_threads_~tmp___1~0#1); 21798#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21670#L361 assume !(1 == ~t3_pc~0); 21671#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21699#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21897#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21877#L779 assume !(0 != activate_threads_~tmp___2~0#1); 21344#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21345#L380 assume 1 == ~t4_pc~0; 21400#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21401#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21429#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21430#L787 assume !(0 != activate_threads_~tmp___3~0#1); 21716#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21403#L399 assume !(1 == ~t5_pc~0); 21404#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21549#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21555#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21539#L795 assume !(0 != activate_threads_~tmp___4~0#1); 21540#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21890#L679 assume !(1 == ~M_E~0); 21631#L679-2 assume !(1 == ~T1_E~0); 21477#L684-1 assume !(1 == ~T2_E~0); 21478#L689-1 assume !(1 == ~T3_E~0); 21678#L694-1 assume !(1 == ~T4_E~0); 21676#L699-1 assume !(1 == ~T5_E~0); 21677#L704-1 assume !(1 == ~E_M~0); 21657#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21590#L714-1 assume !(1 == ~E_2~0); 21591#L719-1 assume !(1 == ~E_3~0); 21789#L724-1 assume !(1 == ~E_4~0); 21363#L729-1 assume !(1 == ~E_5~0); 21364#L734-1 assume { :end_inline_reset_delta_events } true; 21898#L940-2 [2022-12-13 16:15:59,646 INFO L750 eck$LassoCheckResult]: Loop: 21898#L940-2 assume !false; 22406#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22397#L586 assume !false; 22391#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22379#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22370#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 22368#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22365#L511 assume !(0 != eval_~tmp~0#1); 22362#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22360#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22358#L611-3 assume !(0 == ~M_E~0); 22356#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22354#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22352#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22350#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22348#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22346#L636-3 assume !(0 == ~E_M~0); 22344#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22342#L646-3 assume !(0 == ~E_2~0); 22340#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22338#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22336#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22334#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22333#L304-21 assume !(1 == ~m_pc~0); 22332#L304-23 is_master_triggered_~__retres1~0#1 := 0; 22331#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22330#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22329#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22328#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22327#L323-21 assume !(1 == ~t1_pc~0); 22326#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 22325#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22324#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22323#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22322#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22321#L342-21 assume !(1 == ~t2_pc~0); 22319#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 22318#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22317#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22316#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22315#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22314#L361-21 assume 1 == ~t3_pc~0; 22312#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22310#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22308#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22306#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22276#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22274#L380-21 assume !(1 == ~t4_pc~0); 22272#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 22268#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22266#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22264#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22262#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22260#L399-21 assume !(1 == ~t5_pc~0); 22257#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 22254#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22252#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22250#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22248#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22246#L679-3 assume !(1 == ~M_E~0); 22245#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22578#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22577#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22576#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22575#L699-3 assume !(1 == ~T5_E~0); 22574#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22573#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22572#L714-3 assume !(1 == ~E_2~0); 22571#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22570#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22569#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22568#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22506#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22501#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 22497#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 21985#L959 assume !(0 == start_simulation_~tmp~3#1); 21986#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22437#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22430#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 22428#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 22426#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22424#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22422#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 22420#L972 assume !(0 != start_simulation_~tmp___0~1#1); 21898#L940-2 [2022-12-13 16:15:59,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:59,647 INFO L85 PathProgramCache]: Analyzing trace with hash -1293840698, now seen corresponding path program 1 times [2022-12-13 16:15:59,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:59,647 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [994528888] [2022-12-13 16:15:59,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:59,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:59,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:59,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:59,686 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:59,686 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [994528888] [2022-12-13 16:15:59,686 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [994528888] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:59,686 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:59,686 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:15:59,686 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1053636605] [2022-12-13 16:15:59,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:59,687 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:15:59,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:59,687 INFO L85 PathProgramCache]: Analyzing trace with hash 698841583, now seen corresponding path program 1 times [2022-12-13 16:15:59,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:59,687 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564630998] [2022-12-13 16:15:59,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:59,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:59,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:59,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:59,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:59,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [564630998] [2022-12-13 16:15:59,714 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [564630998] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:59,714 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:59,714 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:59,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164609210] [2022-12-13 16:15:59,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:59,715 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:15:59,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:15:59,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:15:59,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:15:59,715 INFO L87 Difference]: Start difference. First operand 2572 states and 3668 transitions. cyclomatic complexity: 1098 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:59,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:15:59,775 INFO L93 Difference]: Finished difference Result 4748 states and 6742 transitions. [2022-12-13 16:15:59,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4748 states and 6742 transitions. [2022-12-13 16:15:59,791 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4637 [2022-12-13 16:15:59,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4748 states to 4748 states and 6742 transitions. [2022-12-13 16:15:59,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4748 [2022-12-13 16:15:59,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4748 [2022-12-13 16:15:59,821 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4748 states and 6742 transitions. [2022-12-13 16:15:59,825 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:15:59,826 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4748 states and 6742 transitions. [2022-12-13 16:15:59,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4748 states and 6742 transitions. [2022-12-13 16:15:59,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4748 to 4736. [2022-12-13 16:15:59,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4736 states, 4736 states have (on average 1.4210304054054055) internal successors, (6730), 4735 states have internal predecessors, (6730), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:15:59,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4736 states to 4736 states and 6730 transitions. [2022-12-13 16:15:59,897 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4736 states and 6730 transitions. [2022-12-13 16:15:59,897 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:15:59,897 INFO L428 stractBuchiCegarLoop]: Abstraction has 4736 states and 6730 transitions. [2022-12-13 16:15:59,898 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 16:15:59,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4736 states and 6730 transitions. [2022-12-13 16:15:59,908 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4625 [2022-12-13 16:15:59,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:15:59,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:15:59,909 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:59,909 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:15:59,910 INFO L748 eck$LassoCheckResult]: Stem: 28932#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 28933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 29045#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29046#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29032#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 29033#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28865#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28866#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28841#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28842#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29120#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28957#L611 assume !(0 == ~M_E~0); 28958#L611-2 assume !(0 == ~T1_E~0); 29137#L616-1 assume !(0 == ~T2_E~0); 29138#L621-1 assume !(0 == ~T3_E~0); 28710#L626-1 assume !(0 == ~T4_E~0); 28711#L631-1 assume !(0 == ~T5_E~0); 28909#L636-1 assume !(0 == ~E_M~0); 28760#L641-1 assume !(0 == ~E_1~0); 28761#L646-1 assume !(0 == ~E_2~0); 28927#L651-1 assume !(0 == ~E_3~0); 29193#L656-1 assume !(0 == ~E_4~0); 29118#L661-1 assume !(0 == ~E_5~0); 29119#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29156#L304 assume !(1 == ~m_pc~0); 28786#L304-2 is_master_triggered_~__retres1~0#1 := 0; 28680#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28681#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28635#L755 assume !(0 != activate_threads_~tmp~1#1); 28636#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28592#L323 assume !(1 == ~t1_pc~0); 28593#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28649#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28650#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28665#L763 assume !(0 != activate_threads_~tmp___0~0#1); 29229#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28659#L342 assume !(1 == ~t2_pc~0); 28661#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28788#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28789#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29047#L771 assume !(0 != activate_threads_~tmp___1~0#1); 29115#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28995#L361 assume !(1 == ~t3_pc~0); 28996#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29023#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28605#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28606#L779 assume !(0 != activate_threads_~tmp___2~0#1); 28670#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28671#L380 assume !(1 == ~t4_pc~0); 28993#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29129#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28755#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28756#L787 assume !(0 != activate_threads_~tmp___3~0#1); 29034#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28729#L399 assume !(1 == ~t5_pc~0); 28730#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28876#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28881#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28867#L795 assume !(0 != activate_threads_~tmp___4~0#1); 28868#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29203#L679 assume !(1 == ~M_E~0); 28956#L679-2 assume !(1 == ~T1_E~0); 28804#L684-1 assume !(1 == ~T2_E~0); 28805#L689-1 assume !(1 == ~T3_E~0); 29003#L694-1 assume !(1 == ~T4_E~0); 29001#L699-1 assume !(1 == ~T5_E~0); 29002#L704-1 assume !(1 == ~E_M~0); 28982#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 28916#L714-1 assume !(1 == ~E_2~0); 28917#L719-1 assume !(1 == ~E_3~0); 29106#L724-1 assume !(1 == ~E_4~0); 28692#L729-1 assume !(1 == ~E_5~0); 28693#L734-1 assume { :end_inline_reset_delta_events } true; 29207#L940-2 [2022-12-13 16:15:59,910 INFO L750 eck$LassoCheckResult]: Loop: 29207#L940-2 assume !false; 30412#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30404#L586 assume !false; 30402#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 30397#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30388#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30386#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30383#L511 assume !(0 != eval_~tmp~0#1); 30380#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30378#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30376#L611-3 assume !(0 == ~M_E~0); 30374#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30372#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30370#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30368#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30366#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30364#L636-3 assume !(0 == ~E_M~0); 30362#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30360#L646-3 assume !(0 == ~E_2~0); 30358#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30356#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30354#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30352#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30350#L304-21 assume !(1 == ~m_pc~0); 30348#L304-23 is_master_triggered_~__retres1~0#1 := 0; 30346#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30344#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30342#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30340#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30338#L323-21 assume !(1 == ~t1_pc~0); 30336#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 30334#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30332#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30330#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30328#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30326#L342-21 assume !(1 == ~t2_pc~0); 30322#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 30320#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30318#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30316#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30314#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30312#L361-21 assume 1 == ~t3_pc~0; 30309#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30305#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30301#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30297#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30294#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30292#L380-21 assume !(1 == ~t4_pc~0); 30290#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 30288#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30286#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30284#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30282#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30280#L399-21 assume !(1 == ~t5_pc~0); 30277#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 30274#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30272#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30270#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30268#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30266#L679-3 assume !(1 == ~M_E~0); 30262#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30263#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30255#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30256#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30248#L699-3 assume !(1 == ~T5_E~0); 30249#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30240#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30241#L714-3 assume !(1 == ~E_2~0); 30236#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30237#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30232#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30233#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 30228#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30223#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30222#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 30220#L959 assume !(0 == start_simulation_~tmp~3#1); 30221#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 30448#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30442#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30440#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 30438#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30437#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30433#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 30431#L972 assume !(0 != start_simulation_~tmp___0~1#1); 29207#L940-2 [2022-12-13 16:15:59,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:59,910 INFO L85 PathProgramCache]: Analyzing trace with hash 943522567, now seen corresponding path program 1 times [2022-12-13 16:15:59,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:59,910 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074936901] [2022-12-13 16:15:59,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:59,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:59,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:59,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:59,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:59,949 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1074936901] [2022-12-13 16:15:59,949 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1074936901] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:59,949 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:59,949 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:59,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2081161823] [2022-12-13 16:15:59,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:59,950 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:15:59,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:15:59,950 INFO L85 PathProgramCache]: Analyzing trace with hash 698841583, now seen corresponding path program 2 times [2022-12-13 16:15:59,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:15:59,950 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099442197] [2022-12-13 16:15:59,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:15:59,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:15:59,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:15:59,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:15:59,981 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:15:59,981 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099442197] [2022-12-13 16:15:59,981 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2099442197] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:15:59,981 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:15:59,981 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:15:59,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351440368] [2022-12-13 16:15:59,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:15:59,982 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:15:59,982 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:15:59,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 16:15:59,982 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 16:15:59,982 INFO L87 Difference]: Start difference. First operand 4736 states and 6730 transitions. cyclomatic complexity: 1998 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:00,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:16:00,090 INFO L93 Difference]: Finished difference Result 7546 states and 10646 transitions. [2022-12-13 16:16:00,090 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7546 states and 10646 transitions. [2022-12-13 16:16:00,110 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7321 [2022-12-13 16:16:00,133 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7546 states to 7546 states and 10646 transitions. [2022-12-13 16:16:00,133 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7546 [2022-12-13 16:16:00,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7546 [2022-12-13 16:16:00,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7546 states and 10646 transitions. [2022-12-13 16:16:00,142 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:16:00,142 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7546 states and 10646 transitions. [2022-12-13 16:16:00,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7546 states and 10646 transitions. [2022-12-13 16:16:00,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7546 to 5465. [2022-12-13 16:16:00,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5465 states, 5465 states have (on average 1.413540713632205) internal successors, (7725), 5464 states have internal predecessors, (7725), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:00,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5465 states to 5465 states and 7725 transitions. [2022-12-13 16:16:00,214 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5465 states and 7725 transitions. [2022-12-13 16:16:00,214 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:16:00,215 INFO L428 stractBuchiCegarLoop]: Abstraction has 5465 states and 7725 transitions. [2022-12-13 16:16:00,215 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 16:16:00,215 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5465 states and 7725 transitions. [2022-12-13 16:16:00,226 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5299 [2022-12-13 16:16:00,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:16:00,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:16:00,243 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:00,243 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:00,243 INFO L748 eck$LassoCheckResult]: Stem: 41214#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 41215#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 41329#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41330#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41312#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 41313#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41152#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41153#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41130#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41131#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41394#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41241#L611 assume !(0 == ~M_E~0); 41242#L611-2 assume !(0 == ~T1_E~0); 41412#L616-1 assume !(0 == ~T2_E~0); 41413#L621-1 assume !(0 == ~T3_E~0); 40993#L626-1 assume !(0 == ~T4_E~0); 40994#L631-1 assume !(0 == ~T5_E~0); 41194#L636-1 assume !(0 == ~E_M~0); 41046#L641-1 assume 0 == ~E_1~0;~E_1~0 := 1; 41047#L646-1 assume !(0 == ~E_2~0); 41493#L651-1 assume !(0 == ~E_3~0); 41494#L656-1 assume !(0 == ~E_4~0); 41392#L661-1 assume !(0 == ~E_5~0); 41393#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41511#L304 assume !(1 == ~m_pc~0); 41512#L304-2 is_master_triggered_~__retres1~0#1 := 0; 40970#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40971#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 41581#L755 assume !(0 != activate_threads_~tmp~1#1); 41528#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41529#L323 assume !(1 == ~t1_pc~0); 41266#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41267#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40956#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40957#L763 assume !(0 != activate_threads_~tmp___0~0#1); 41500#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41501#L342 assume !(1 == ~t2_pc~0); 41391#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41078#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41079#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41515#L771 assume !(0 != activate_threads_~tmp___1~0#1); 41385#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41278#L361 assume !(1 == ~t3_pc~0); 41279#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41306#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40896#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40897#L779 assume !(0 != activate_threads_~tmp___2~0#1); 41456#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41562#L380 assume !(1 == ~t4_pc~0); 41520#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41404#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41041#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41042#L787 assume !(0 != activate_threads_~tmp___3~0#1); 41559#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41019#L399 assume !(1 == ~t5_pc~0); 41020#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41558#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41170#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41171#L795 assume !(0 != activate_threads_~tmp___4~0#1); 41557#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41516#L679 assume !(1 == ~M_E~0); 41239#L679-2 assume !(1 == ~T1_E~0); 41093#L684-1 assume !(1 == ~T2_E~0); 41094#L689-1 assume !(1 == ~T3_E~0); 41287#L694-1 assume !(1 == ~T4_E~0); 41553#L699-1 assume !(1 == ~T5_E~0); 41552#L704-1 assume !(1 == ~E_M~0); 41551#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 41198#L714-1 assume !(1 == ~E_2~0); 41199#L719-1 assume !(1 == ~E_3~0); 41381#L724-1 assume !(1 == ~E_4~0); 40981#L729-1 assume !(1 == ~E_5~0); 40982#L734-1 assume { :end_inline_reset_delta_events } true; 41478#L940-2 [2022-12-13 16:16:00,243 INFO L750 eck$LassoCheckResult]: Loop: 41478#L940-2 assume !false; 42332#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42329#L586 assume !false; 42328#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 42324#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 42321#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 42320#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 42254#L511 assume !(0 != eval_~tmp~0#1); 42253#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42252#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42251#L611-3 assume !(0 == ~M_E~0); 42250#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42249#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42248#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42247#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42246#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 42245#L636-3 assume !(0 == ~E_M~0); 41928#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41925#L646-3 assume !(0 == ~E_2~0); 41923#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41921#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41919#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41917#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41915#L304-21 assume !(1 == ~m_pc~0); 41913#L304-23 is_master_triggered_~__retres1~0#1 := 0; 41911#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41909#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 41907#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41905#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41903#L323-21 assume !(1 == ~t1_pc~0); 41901#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 41899#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41897#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41895#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41893#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41891#L342-21 assume !(1 == ~t2_pc~0); 41887#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 41885#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41883#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41881#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41879#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41877#L361-21 assume 1 == ~t3_pc~0; 41874#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41870#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41866#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41862#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41859#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41857#L380-21 assume !(1 == ~t4_pc~0); 41855#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 41853#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41851#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41849#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41847#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41845#L399-21 assume !(1 == ~t5_pc~0); 41842#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 41839#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41837#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41835#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41833#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41831#L679-3 assume !(1 == ~M_E~0); 41827#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41828#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41823#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41824#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41819#L699-3 assume !(1 == ~T5_E~0); 41820#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41815#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41813#L714-3 assume !(1 == ~E_2~0); 41809#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41807#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41805#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41803#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 41750#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 41738#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 41735#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 41732#L959 assume !(0 == start_simulation_~tmp~3#1); 41733#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 42470#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 42464#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 42462#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 42460#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42458#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42455#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 42453#L972 assume !(0 != start_simulation_~tmp___0~1#1); 41478#L940-2 [2022-12-13 16:16:00,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:00,243 INFO L85 PathProgramCache]: Analyzing trace with hash -443262843, now seen corresponding path program 1 times [2022-12-13 16:16:00,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:00,244 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648262257] [2022-12-13 16:16:00,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:00,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:00,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:00,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:00,278 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:00,278 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1648262257] [2022-12-13 16:16:00,278 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1648262257] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:00,278 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:00,278 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:16:00,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [387294870] [2022-12-13 16:16:00,279 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:00,279 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:16:00,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:00,279 INFO L85 PathProgramCache]: Analyzing trace with hash 698841583, now seen corresponding path program 3 times [2022-12-13 16:16:00,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:00,279 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523520063] [2022-12-13 16:16:00,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:00,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:00,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:00,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:00,315 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:00,315 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523520063] [2022-12-13 16:16:00,315 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [523520063] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:00,315 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:00,315 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:16:00,316 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901550325] [2022-12-13 16:16:00,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:00,316 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:16:00,316 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:16:00,316 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 16:16:00,316 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 16:16:00,316 INFO L87 Difference]: Start difference. First operand 5465 states and 7725 transitions. cyclomatic complexity: 2264 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:00,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:16:00,397 INFO L93 Difference]: Finished difference Result 6670 states and 9389 transitions. [2022-12-13 16:16:00,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6670 states and 9389 transitions. [2022-12-13 16:16:00,424 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6505 [2022-12-13 16:16:00,445 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6670 states to 6670 states and 9389 transitions. [2022-12-13 16:16:00,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6670 [2022-12-13 16:16:00,452 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6670 [2022-12-13 16:16:00,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6670 states and 9389 transitions. [2022-12-13 16:16:00,458 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:16:00,458 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6670 states and 9389 transitions. [2022-12-13 16:16:00,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6670 states and 9389 transitions. [2022-12-13 16:16:00,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6670 to 4736. [2022-12-13 16:16:00,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4736 states, 4736 states have (on average 1.4079391891891893) internal successors, (6668), 4735 states have internal predecessors, (6668), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:00,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4736 states to 4736 states and 6668 transitions. [2022-12-13 16:16:00,536 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4736 states and 6668 transitions. [2022-12-13 16:16:00,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:16:00,536 INFO L428 stractBuchiCegarLoop]: Abstraction has 4736 states and 6668 transitions. [2022-12-13 16:16:00,536 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 16:16:00,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4736 states and 6668 transitions. [2022-12-13 16:16:00,547 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4625 [2022-12-13 16:16:00,547 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:16:00,547 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:16:00,548 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:00,548 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:00,548 INFO L748 eck$LassoCheckResult]: Stem: 53355#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 53356#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 53461#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53462#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53445#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 53446#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53296#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53297#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53275#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53276#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53526#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53379#L611 assume !(0 == ~M_E~0); 53380#L611-2 assume !(0 == ~T1_E~0); 53543#L616-1 assume !(0 == ~T2_E~0); 53544#L621-1 assume !(0 == ~T3_E~0); 53144#L626-1 assume !(0 == ~T4_E~0); 53145#L631-1 assume !(0 == ~T5_E~0); 53338#L636-1 assume !(0 == ~E_M~0); 53192#L641-1 assume !(0 == ~E_1~0); 53193#L646-1 assume !(0 == ~E_2~0); 53353#L651-1 assume !(0 == ~E_3~0); 53586#L656-1 assume !(0 == ~E_4~0); 53524#L661-1 assume !(0 == ~E_5~0); 53525#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53558#L304 assume !(1 == ~m_pc~0); 53218#L304-2 is_master_triggered_~__retres1~0#1 := 0; 53115#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53116#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53071#L755 assume !(0 != activate_threads_~tmp~1#1); 53072#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53029#L323 assume !(1 == ~t1_pc~0); 53030#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53085#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53086#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53102#L763 assume !(0 != activate_threads_~tmp___0~0#1); 53616#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53095#L342 assume !(1 == ~t2_pc~0); 53097#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 53220#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53221#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 53463#L771 assume !(0 != activate_threads_~tmp___1~0#1); 53520#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53412#L361 assume !(1 == ~t3_pc~0); 53413#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53438#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53041#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 53042#L779 assume !(0 != activate_threads_~tmp___2~0#1); 53107#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53108#L380 assume !(1 == ~t4_pc~0); 53411#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 53535#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53187#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53188#L787 assume !(0 != activate_threads_~tmp___3~0#1); 53449#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53162#L399 assume !(1 == ~t5_pc~0); 53163#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 53307#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53312#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53298#L795 assume !(0 != activate_threads_~tmp___4~0#1); 53299#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53595#L679 assume !(1 == ~M_E~0); 53378#L679-2 assume !(1 == ~T1_E~0); 53236#L684-1 assume !(1 == ~T2_E~0); 53237#L689-1 assume !(1 == ~T3_E~0); 53420#L694-1 assume !(1 == ~T4_E~0); 53418#L699-1 assume !(1 == ~T5_E~0); 53419#L704-1 assume !(1 == ~E_M~0); 53401#L709-1 assume !(1 == ~E_1~0); 53343#L714-1 assume !(1 == ~E_2~0); 53344#L719-1 assume !(1 == ~E_3~0); 53515#L724-1 assume !(1 == ~E_4~0); 53126#L729-1 assume !(1 == ~E_5~0); 53127#L734-1 assume { :end_inline_reset_delta_events } true; 53600#L940-2 [2022-12-13 16:16:00,548 INFO L750 eck$LassoCheckResult]: Loop: 53600#L940-2 assume !false; 54913#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54909#L586 assume !false; 54845#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54779#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54770#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54768#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 54765#L511 assume !(0 != eval_~tmp~0#1); 54766#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55318#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55316#L611-3 assume !(0 == ~M_E~0); 55313#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55311#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55309#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55307#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55305#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55303#L636-3 assume !(0 == ~E_M~0); 55301#L641-3 assume !(0 == ~E_1~0); 55299#L646-3 assume !(0 == ~E_2~0); 55297#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55295#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55293#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55291#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55290#L304-21 assume !(1 == ~m_pc~0); 55287#L304-23 is_master_triggered_~__retres1~0#1 := 0; 55285#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55283#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55281#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55279#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55277#L323-21 assume !(1 == ~t1_pc~0); 55273#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 55271#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55269#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55267#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55264#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55262#L342-21 assume !(1 == ~t2_pc~0); 55259#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 55257#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55255#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55253#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55251#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55246#L361-21 assume !(1 == ~t3_pc~0); 55243#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 55241#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55239#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 55237#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 55234#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55233#L380-21 assume !(1 == ~t4_pc~0); 55229#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 55227#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55225#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55224#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55218#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55216#L399-21 assume !(1 == ~t5_pc~0); 55213#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 55212#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55211#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55210#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55209#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55120#L679-3 assume !(1 == ~M_E~0); 55115#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55113#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55111#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55109#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55107#L699-3 assume !(1 == ~T5_E~0); 55105#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 55101#L709-3 assume !(1 == ~E_1~0); 55099#L714-3 assume !(1 == ~E_2~0); 55097#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55095#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55092#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55090#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 55085#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 55079#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 55077#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 55075#L959 assume !(0 == start_simulation_~tmp~3#1); 55072#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 55066#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 55060#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 55058#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 55057#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55053#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55051#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 55033#L972 assume !(0 != start_simulation_~tmp___0~1#1); 53600#L940-2 [2022-12-13 16:16:00,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:00,549 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2022-12-13 16:16:00,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:00,549 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1906821004] [2022-12-13 16:16:00,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:00,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:00,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:00,555 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:00,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:00,583 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:00,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:00,584 INFO L85 PathProgramCache]: Analyzing trace with hash 1836673586, now seen corresponding path program 1 times [2022-12-13 16:16:00,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:00,584 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816018128] [2022-12-13 16:16:00,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:00,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:00,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:00,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:00,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:00,607 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816018128] [2022-12-13 16:16:00,607 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [816018128] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:00,607 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:00,608 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:16:00,608 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1319715204] [2022-12-13 16:16:00,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:00,608 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:16:00,608 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:16:00,608 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:16:00,609 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:16:00,609 INFO L87 Difference]: Start difference. First operand 4736 states and 6668 transitions. cyclomatic complexity: 1936 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:00,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:16:00,647 INFO L93 Difference]: Finished difference Result 5469 states and 7686 transitions. [2022-12-13 16:16:00,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5469 states and 7686 transitions. [2022-12-13 16:16:00,694 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5303 [2022-12-13 16:16:00,713 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5469 states to 5469 states and 7686 transitions. [2022-12-13 16:16:00,713 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5469 [2022-12-13 16:16:00,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5469 [2022-12-13 16:16:00,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5469 states and 7686 transitions. [2022-12-13 16:16:00,723 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:16:00,723 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5469 states and 7686 transitions. [2022-12-13 16:16:00,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5469 states and 7686 transitions. [2022-12-13 16:16:00,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5469 to 5469. [2022-12-13 16:16:00,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5469 states, 5469 states have (on average 1.4053757542512342) internal successors, (7686), 5468 states have internal predecessors, (7686), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:00,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5469 states to 5469 states and 7686 transitions. [2022-12-13 16:16:00,816 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5469 states and 7686 transitions. [2022-12-13 16:16:00,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:16:00,817 INFO L428 stractBuchiCegarLoop]: Abstraction has 5469 states and 7686 transitions. [2022-12-13 16:16:00,817 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 16:16:00,817 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5469 states and 7686 transitions. [2022-12-13 16:16:00,832 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5303 [2022-12-13 16:16:00,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:16:00,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:16:00,833 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:00,833 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:00,833 INFO L748 eck$LassoCheckResult]: Stem: 63576#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 63577#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 63687#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63688#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63671#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 63672#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63508#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63509#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63487#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63488#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63751#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63601#L611 assume !(0 == ~M_E~0); 63602#L611-2 assume !(0 == ~T1_E~0); 63768#L616-1 assume !(0 == ~T2_E~0); 63769#L621-1 assume !(0 == ~T3_E~0); 63350#L626-1 assume !(0 == ~T4_E~0); 63351#L631-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 63743#L636-1 assume !(0 == ~E_M~0); 63403#L641-1 assume !(0 == ~E_1~0); 63404#L646-1 assume !(0 == ~E_2~0); 63860#L651-1 assume !(0 == ~E_3~0); 63861#L656-1 assume !(0 == ~E_4~0); 63749#L661-1 assume !(0 == ~E_5~0); 63750#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63942#L304 assume !(1 == ~m_pc~0); 63427#L304-2 is_master_triggered_~__retres1~0#1 := 0; 63428#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63515#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 63277#L755 assume !(0 != activate_threads_~tmp~1#1); 63278#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63940#L323 assume !(1 == ~t1_pc~0); 63625#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63626#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63312#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 63313#L763 assume !(0 != activate_threads_~tmp___0~0#1); 63869#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63870#L342 assume !(1 == ~t2_pc~0); 63747#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63748#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63689#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 63690#L771 assume !(0 != activate_threads_~tmp___1~0#1); 63744#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63637#L361 assume !(1 == ~t3_pc~0); 63638#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63923#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63921#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63919#L779 assume !(0 != activate_threads_~tmp___2~0#1); 63316#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63317#L380 assume !(1 == ~t4_pc~0); 63636#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63759#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63396#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63397#L787 assume !(0 != activate_threads_~tmp___3~0#1); 63913#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63374#L399 assume !(1 == ~t5_pc~0); 63375#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 63519#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63525#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63510#L795 assume !(0 != activate_threads_~tmp___4~0#1); 63511#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63836#L679 assume !(1 == ~M_E~0); 63903#L679-2 assume !(1 == ~T1_E~0); 63902#L684-1 assume !(1 == ~T2_E~0); 63645#L689-1 assume !(1 == ~T3_E~0); 63646#L694-1 assume !(1 == ~T4_E~0); 63643#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63644#L704-1 assume !(1 == ~E_M~0); 63624#L709-1 assume !(1 == ~E_1~0); 63556#L714-1 assume !(1 == ~E_2~0); 63557#L719-1 assume !(1 == ~E_3~0); 63739#L724-1 assume !(1 == ~E_4~0); 63338#L729-1 assume !(1 == ~E_5~0); 63339#L734-1 assume { :end_inline_reset_delta_events } true; 63842#L940-2 [2022-12-13 16:16:00,833 INFO L750 eck$LassoCheckResult]: Loop: 63842#L940-2 assume !false; 64906#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64901#L586 assume !false; 64898#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 64899#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 68177#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 68176#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 68174#L511 assume !(0 != eval_~tmp~0#1); 68175#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68491#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68490#L611-3 assume !(0 == ~M_E~0); 68489#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 68487#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 68485#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68483#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 63895#L631-3 assume !(0 == ~T5_E~0); 63286#L636-3 assume !(0 == ~E_M~0); 63287#L641-3 assume !(0 == ~E_1~0); 63352#L646-3 assume !(0 == ~E_2~0); 63364#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 63365#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 63617#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 63866#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63516#L304-21 assume !(1 == ~m_pc~0); 63517#L304-23 is_master_triggered_~__retres1~0#1 := 0; 68680#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68678#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68676#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68674#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68672#L323-21 assume !(1 == ~t1_pc~0); 68670#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 68668#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68666#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68664#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68662#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68660#L342-21 assume !(1 == ~t2_pc~0); 68657#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 68655#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68653#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68650#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 68648#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68643#L361-21 assume !(1 == ~t3_pc~0); 68641#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 68639#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68638#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68634#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 68631#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68629#L380-21 assume !(1 == ~t4_pc~0); 68627#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 68624#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68622#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68620#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 68618#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68616#L399-21 assume !(1 == ~t5_pc~0); 68613#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 68611#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68609#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68607#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 68604#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68602#L679-3 assume !(1 == ~M_E~0); 66913#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68368#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68367#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68366#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68016#L699-3 assume !(1 == ~T5_E~0); 68015#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 64992#L709-3 assume !(1 == ~E_1~0); 64987#L714-3 assume !(1 == ~E_2~0); 64982#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64980#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64977#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64975#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 64965#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 64959#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 64957#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 64954#L959 assume !(0 == start_simulation_~tmp~3#1); 64948#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 64943#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 64937#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 64935#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 64933#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64931#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64929#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 64926#L972 assume !(0 != start_simulation_~tmp___0~1#1); 63842#L940-2 [2022-12-13 16:16:00,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:00,834 INFO L85 PathProgramCache]: Analyzing trace with hash 549210245, now seen corresponding path program 1 times [2022-12-13 16:16:00,834 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:00,834 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111622859] [2022-12-13 16:16:00,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:00,834 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:00,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:00,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:00,867 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:00,867 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111622859] [2022-12-13 16:16:00,867 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1111622859] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:00,867 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:00,867 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:16:00,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769573692] [2022-12-13 16:16:00,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:00,868 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:16:00,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:00,868 INFO L85 PathProgramCache]: Analyzing trace with hash 1344047412, now seen corresponding path program 1 times [2022-12-13 16:16:00,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:00,868 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175721285] [2022-12-13 16:16:00,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:00,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:00,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:00,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:00,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:00,927 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175721285] [2022-12-13 16:16:00,927 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1175721285] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:00,927 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:00,927 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:16:00,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1698242323] [2022-12-13 16:16:00,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:00,928 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:16:00,928 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:16:00,928 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 16:16:00,928 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 16:16:00,929 INFO L87 Difference]: Start difference. First operand 5469 states and 7686 transitions. cyclomatic complexity: 2221 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:01,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:16:01,009 INFO L93 Difference]: Finished difference Result 6863 states and 9627 transitions. [2022-12-13 16:16:01,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6863 states and 9627 transitions. [2022-12-13 16:16:01,036 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6729 [2022-12-13 16:16:01,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6863 states to 6863 states and 9627 transitions. [2022-12-13 16:16:01,058 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6863 [2022-12-13 16:16:01,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6863 [2022-12-13 16:16:01,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6863 states and 9627 transitions. [2022-12-13 16:16:01,066 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:16:01,066 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6863 states and 9627 transitions. [2022-12-13 16:16:01,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6863 states and 9627 transitions. [2022-12-13 16:16:01,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6863 to 4736. [2022-12-13 16:16:01,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4736 states, 4736 states have (on average 1.4051942567567568) internal successors, (6655), 4735 states have internal predecessors, (6655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:01,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4736 states to 4736 states and 6655 transitions. [2022-12-13 16:16:01,143 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4736 states and 6655 transitions. [2022-12-13 16:16:01,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:16:01,144 INFO L428 stractBuchiCegarLoop]: Abstraction has 4736 states and 6655 transitions. [2022-12-13 16:16:01,145 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 16:16:01,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4736 states and 6655 transitions. [2022-12-13 16:16:01,152 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4625 [2022-12-13 16:16:01,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:16:01,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:16:01,153 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:01,153 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:01,153 INFO L748 eck$LassoCheckResult]: Stem: 75913#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 75914#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 76023#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76009#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 76010#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75851#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75852#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75829#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75830#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76088#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75937#L611 assume !(0 == ~M_E~0); 75938#L611-2 assume !(0 == ~T1_E~0); 76108#L616-1 assume !(0 == ~T2_E~0); 76109#L621-1 assume !(0 == ~T3_E~0); 75693#L626-1 assume !(0 == ~T4_E~0); 75694#L631-1 assume !(0 == ~T5_E~0); 75889#L636-1 assume !(0 == ~E_M~0); 75744#L641-1 assume !(0 == ~E_1~0); 75745#L646-1 assume !(0 == ~E_2~0); 75910#L651-1 assume !(0 == ~E_3~0); 76150#L656-1 assume !(0 == ~E_4~0); 76086#L661-1 assume !(0 == ~E_5~0); 76087#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76123#L304 assume !(1 == ~m_pc~0); 75767#L304-2 is_master_triggered_~__retres1~0#1 := 0; 75670#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75671#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75621#L755 assume !(0 != activate_threads_~tmp~1#1); 75622#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75580#L323 assume !(1 == ~t1_pc~0); 75581#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75640#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75641#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75657#L763 assume !(0 != activate_threads_~tmp___0~0#1); 76186#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75644#L342 assume !(1 == ~t2_pc~0); 75646#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 75774#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75775#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 76025#L771 assume !(0 != activate_threads_~tmp___1~0#1); 76081#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75973#L361 assume !(1 == ~t3_pc~0); 75974#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76002#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75596#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 75597#L779 assume !(0 != activate_threads_~tmp___2~0#1); 75660#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75661#L380 assume !(1 == ~t4_pc~0); 75972#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76098#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75739#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75740#L787 assume !(0 != activate_threads_~tmp___3~0#1); 76011#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75717#L399 assume !(1 == ~t5_pc~0); 75718#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 75861#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75866#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75853#L795 assume !(0 != activate_threads_~tmp___4~0#1); 75854#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76161#L679 assume !(1 == ~M_E~0); 75935#L679-2 assume !(1 == ~T1_E~0); 75789#L684-1 assume !(1 == ~T2_E~0); 75790#L689-1 assume !(1 == ~T3_E~0); 75982#L694-1 assume !(1 == ~T4_E~0); 75980#L699-1 assume !(1 == ~T5_E~0); 75981#L704-1 assume !(1 == ~E_M~0); 75962#L709-1 assume !(1 == ~E_1~0); 75894#L714-1 assume !(1 == ~E_2~0); 75895#L719-1 assume !(1 == ~E_3~0); 76074#L724-1 assume !(1 == ~E_4~0); 75681#L729-1 assume !(1 == ~E_5~0); 75682#L734-1 assume { :end_inline_reset_delta_events } true; 76167#L940-2 [2022-12-13 16:16:01,153 INFO L750 eck$LassoCheckResult]: Loop: 76167#L940-2 assume !false; 79424#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 79420#L586 assume !false; 79418#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 79401#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 79397#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 79395#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 79392#L511 assume !(0 != eval_~tmp~0#1); 79390#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 79388#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79385#L611-3 assume !(0 == ~M_E~0); 79383#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 79381#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 79379#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 79377#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 79376#L631-3 assume !(0 == ~T5_E~0); 79372#L636-3 assume !(0 == ~E_M~0); 79370#L641-3 assume !(0 == ~E_1~0); 79368#L646-3 assume !(0 == ~E_2~0); 79366#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 79362#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 79360#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79358#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79357#L304-21 assume !(1 == ~m_pc~0); 79356#L304-23 is_master_triggered_~__retres1~0#1 := 0; 79355#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79354#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 79353#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 79351#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79350#L323-21 assume !(1 == ~t1_pc~0); 79349#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 79348#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79346#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 79345#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 79344#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79343#L342-21 assume !(1 == ~t2_pc~0); 79341#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 79339#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79337#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 79335#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 79333#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79327#L361-21 assume 1 == ~t3_pc~0; 79328#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 79329#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79347#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 79318#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 79314#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79312#L380-21 assume !(1 == ~t4_pc~0); 79310#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 79308#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79305#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 79303#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 79301#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79298#L399-21 assume 1 == ~t5_pc~0; 79296#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 79293#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79291#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 79289#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 79287#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79284#L679-3 assume !(1 == ~M_E~0); 78545#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 79281#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 79279#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 79277#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 79276#L699-3 assume !(1 == ~T5_E~0); 79272#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 79271#L709-3 assume !(1 == ~E_1~0); 79269#L714-3 assume !(1 == ~E_2~0); 79267#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 79266#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 79265#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 79264#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 79262#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 79257#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 79256#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 75997#L959 assume !(0 == start_simulation_~tmp~3#1); 75998#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 79494#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 79488#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 79486#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 79484#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 79483#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 79480#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 79478#L972 assume !(0 != start_simulation_~tmp___0~1#1); 76167#L940-2 [2022-12-13 16:16:01,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:01,154 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2022-12-13 16:16:01,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:01,154 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234727655] [2022-12-13 16:16:01,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:01,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:01,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:01,161 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:01,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:01,178 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:01,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:01,179 INFO L85 PathProgramCache]: Analyzing trace with hash -1232612048, now seen corresponding path program 1 times [2022-12-13 16:16:01,179 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:01,179 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [994410679] [2022-12-13 16:16:01,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:01,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:01,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:01,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:01,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:01,219 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [994410679] [2022-12-13 16:16:01,219 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [994410679] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:01,219 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:01,219 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:16:01,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285575789] [2022-12-13 16:16:01,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:01,220 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:16:01,220 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:16:01,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 16:16:01,220 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 16:16:01,220 INFO L87 Difference]: Start difference. First operand 4736 states and 6655 transitions. cyclomatic complexity: 1923 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:01,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:16:01,310 INFO L93 Difference]: Finished difference Result 8463 states and 11736 transitions. [2022-12-13 16:16:01,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8463 states and 11736 transitions. [2022-12-13 16:16:01,347 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8320 [2022-12-13 16:16:01,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8463 states to 8463 states and 11736 transitions. [2022-12-13 16:16:01,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8463 [2022-12-13 16:16:01,377 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8463 [2022-12-13 16:16:01,378 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8463 states and 11736 transitions. [2022-12-13 16:16:01,383 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:16:01,383 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8463 states and 11736 transitions. [2022-12-13 16:16:01,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8463 states and 11736 transitions. [2022-12-13 16:16:01,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8463 to 4772. [2022-12-13 16:16:01,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4772 states, 4772 states have (on average 1.4021374685666388) internal successors, (6691), 4771 states have internal predecessors, (6691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:01,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4772 states to 4772 states and 6691 transitions. [2022-12-13 16:16:01,475 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4772 states and 6691 transitions. [2022-12-13 16:16:01,475 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 16:16:01,476 INFO L428 stractBuchiCegarLoop]: Abstraction has 4772 states and 6691 transitions. [2022-12-13 16:16:01,476 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 16:16:01,476 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4772 states and 6691 transitions. [2022-12-13 16:16:01,486 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4661 [2022-12-13 16:16:01,486 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:16:01,486 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:16:01,487 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:01,488 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:01,488 INFO L748 eck$LassoCheckResult]: Stem: 89126#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 89127#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 89242#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 89243#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89225#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 89226#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89064#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 89065#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89042#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 89043#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 89315#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89151#L611 assume !(0 == ~M_E~0); 89152#L611-2 assume !(0 == ~T1_E~0); 89332#L616-1 assume !(0 == ~T2_E~0); 89333#L621-1 assume !(0 == ~T3_E~0); 88915#L626-1 assume !(0 == ~T4_E~0); 88916#L631-1 assume !(0 == ~T5_E~0); 89107#L636-1 assume !(0 == ~E_M~0); 88964#L641-1 assume !(0 == ~E_1~0); 88965#L646-1 assume !(0 == ~E_2~0); 89123#L651-1 assume !(0 == ~E_3~0); 89377#L656-1 assume !(0 == ~E_4~0); 89313#L661-1 assume !(0 == ~E_5~0); 89314#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89348#L304 assume !(1 == ~m_pc~0); 88989#L304-2 is_master_triggered_~__retres1~0#1 := 0; 88884#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88885#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 88841#L755 assume !(0 != activate_threads_~tmp~1#1); 88842#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88799#L323 assume !(1 == ~t1_pc~0); 88800#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88854#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88855#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88870#L763 assume !(0 != activate_threads_~tmp___0~0#1); 89409#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88864#L342 assume !(1 == ~t2_pc~0); 88866#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 88991#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88992#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 89244#L771 assume !(0 != activate_threads_~tmp___1~0#1); 89309#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89188#L361 assume !(1 == ~t3_pc~0); 89189#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 89216#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88811#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88812#L779 assume !(0 != activate_threads_~tmp___2~0#1); 88875#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88876#L380 assume !(1 == ~t4_pc~0); 89185#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 89324#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88960#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88961#L787 assume !(0 != activate_threads_~tmp___3~0#1); 89228#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88933#L399 assume !(1 == ~t5_pc~0); 88934#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 89075#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89079#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 89066#L795 assume !(0 != activate_threads_~tmp___4~0#1); 89067#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89388#L679 assume !(1 == ~M_E~0); 89150#L679-2 assume !(1 == ~T1_E~0); 89006#L684-1 assume !(1 == ~T2_E~0); 89007#L689-1 assume !(1 == ~T3_E~0); 89198#L694-1 assume !(1 == ~T4_E~0); 89196#L699-1 assume !(1 == ~T5_E~0); 89197#L704-1 assume !(1 == ~E_M~0); 89174#L709-1 assume !(1 == ~E_1~0); 89112#L714-1 assume !(1 == ~E_2~0); 89113#L719-1 assume !(1 == ~E_3~0); 89305#L724-1 assume !(1 == ~E_4~0); 88896#L729-1 assume !(1 == ~E_5~0); 88897#L734-1 assume { :end_inline_reset_delta_events } true; 89391#L940-2 [2022-12-13 16:16:01,488 INFO L750 eck$LassoCheckResult]: Loop: 89391#L940-2 assume !false; 93460#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 89004#L586 assume !false; 89005#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 89384#L464 assume !(0 == ~m_st~0); 89357#L468 assume !(0 == ~t1_st~0); 89358#L472 assume !(0 == ~t2_st~0); 89296#L476 assume !(0 == ~t3_st~0); 89298#L480 assume !(0 == ~t4_st~0); 89304#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 89193#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 89194#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 91432#L511 assume !(0 != eval_~tmp~0#1); 88969#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 88970#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 89264#L611-3 assume !(0 == ~M_E~0); 89265#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 93144#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 88894#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 88895#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 92216#L631-3 assume !(0 == ~T5_E~0); 92217#L636-3 assume !(0 == ~E_M~0); 92210#L641-3 assume !(0 == ~E_1~0); 92211#L646-3 assume !(0 == ~E_2~0); 92204#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 92205#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 89410#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 89411#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89071#L304-21 assume !(1 == ~m_pc~0); 89072#L304-23 is_master_triggered_~__retres1~0#1 := 0; 93381#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93380#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 93379#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 93378#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93377#L323-21 assume !(1 == ~t1_pc~0); 89321#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 89322#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88943#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88944#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 89346#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89363#L342-21 assume !(1 == ~t2_pc~0); 93371#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 89220#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89221#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 93370#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 93369#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 93368#L361-21 assume 1 == ~t3_pc~0; 89414#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 89415#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 93254#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 93255#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88836#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88837#L380-21 assume !(1 == ~t4_pc~0); 88902#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 88903#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88974#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 89385#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 93361#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89052#L399-21 assume 1 == ~t5_pc~0; 89027#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 88909#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 93358#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 93357#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 93356#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93355#L679-3 assume !(1 == ~M_E~0); 93102#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 93354#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 93353#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 93352#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 93351#L699-3 assume !(1 == ~T5_E~0); 93350#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 93349#L709-3 assume !(1 == ~E_1~0); 93348#L714-3 assume !(1 == ~E_2~0); 93347#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 93345#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 93344#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 93343#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 93341#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 93335#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 93333#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 93330#L959 assume !(0 == start_simulation_~tmp~3#1); 93331#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 93480#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 93473#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 93471#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 93469#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 93467#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 93465#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 93463#L972 assume !(0 != start_simulation_~tmp___0~1#1); 89391#L940-2 [2022-12-13 16:16:01,488 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:01,489 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2022-12-13 16:16:01,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:01,489 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531189527] [2022-12-13 16:16:01,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:01,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:01,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:01,497 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:01,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:01,513 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:01,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:01,513 INFO L85 PathProgramCache]: Analyzing trace with hash -1341720261, now seen corresponding path program 1 times [2022-12-13 16:16:01,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:01,513 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524842442] [2022-12-13 16:16:01,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:01,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:01,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:01,596 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:01,596 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:01,596 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524842442] [2022-12-13 16:16:01,596 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [524842442] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:01,596 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:01,596 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:16:01,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1365703432] [2022-12-13 16:16:01,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:01,597 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:16:01,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:16:01,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 16:16:01,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 16:16:01,597 INFO L87 Difference]: Start difference. First operand 4772 states and 6691 transitions. cyclomatic complexity: 1923 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:01,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:16:01,798 INFO L93 Difference]: Finished difference Result 11016 states and 15346 transitions. [2022-12-13 16:16:01,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11016 states and 15346 transitions. [2022-12-13 16:16:01,843 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10889 [2022-12-13 16:16:01,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11016 states to 11016 states and 15346 transitions. [2022-12-13 16:16:01,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11016 [2022-12-13 16:16:01,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11016 [2022-12-13 16:16:01,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11016 states and 15346 transitions. [2022-12-13 16:16:01,911 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:16:01,911 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11016 states and 15346 transitions. [2022-12-13 16:16:01,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11016 states and 15346 transitions. [2022-12-13 16:16:01,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11016 to 4928. [2022-12-13 16:16:01,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4928 states, 4928 states have (on average 1.385146103896104) internal successors, (6826), 4927 states have internal predecessors, (6826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:01,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4928 states to 4928 states and 6826 transitions. [2022-12-13 16:16:01,969 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4928 states and 6826 transitions. [2022-12-13 16:16:01,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 16:16:01,970 INFO L428 stractBuchiCegarLoop]: Abstraction has 4928 states and 6826 transitions. [2022-12-13 16:16:01,970 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 16:16:01,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4928 states and 6826 transitions. [2022-12-13 16:16:01,979 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4817 [2022-12-13 16:16:01,979 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:16:01,979 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:16:01,980 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:01,980 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:01,980 INFO L748 eck$LassoCheckResult]: Stem: 104935#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 104936#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 105049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 105050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105034#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 105035#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 104870#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 104871#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 104848#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 104849#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 105121#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 104962#L611 assume !(0 == ~M_E~0); 104963#L611-2 assume !(0 == ~T1_E~0); 105137#L616-1 assume !(0 == ~T2_E~0); 105138#L621-1 assume !(0 == ~T3_E~0); 104714#L626-1 assume !(0 == ~T4_E~0); 104715#L631-1 assume !(0 == ~T5_E~0); 104915#L636-1 assume !(0 == ~E_M~0); 104766#L641-1 assume !(0 == ~E_1~0); 104767#L646-1 assume !(0 == ~E_2~0); 104930#L651-1 assume !(0 == ~E_3~0); 105183#L656-1 assume !(0 == ~E_4~0); 105119#L661-1 assume !(0 == ~E_5~0); 105120#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105155#L304 assume !(1 == ~m_pc~0); 104792#L304-2 is_master_triggered_~__retres1~0#1 := 0; 104685#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104686#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 104642#L755 assume !(0 != activate_threads_~tmp~1#1); 104643#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104600#L323 assume !(1 == ~t1_pc~0); 104601#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 104656#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104657#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 104671#L763 assume !(0 != activate_threads_~tmp___0~0#1); 105219#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104665#L342 assume !(1 == ~t2_pc~0); 104667#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 104794#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104795#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 105051#L771 assume !(0 != activate_threads_~tmp___1~0#1); 105115#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104997#L361 assume !(1 == ~t3_pc~0); 104998#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 105025#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104612#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 104613#L779 assume !(0 != activate_threads_~tmp___2~0#1); 104676#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 104677#L380 assume !(1 == ~t4_pc~0); 104996#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 105130#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 104761#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 104762#L787 assume !(0 != activate_threads_~tmp___3~0#1); 105038#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 104733#L399 assume !(1 == ~t5_pc~0); 104734#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 104883#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 104888#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 104872#L795 assume !(0 != activate_threads_~tmp___4~0#1); 104873#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105195#L679 assume !(1 == ~M_E~0); 104961#L679-2 assume !(1 == ~T1_E~0); 104809#L684-1 assume !(1 == ~T2_E~0); 104810#L689-1 assume !(1 == ~T3_E~0); 105005#L694-1 assume !(1 == ~T4_E~0); 105003#L699-1 assume !(1 == ~T5_E~0); 105004#L704-1 assume !(1 == ~E_M~0); 104986#L709-1 assume !(1 == ~E_1~0); 104920#L714-1 assume !(1 == ~E_2~0); 104921#L719-1 assume !(1 == ~E_3~0); 105108#L724-1 assume !(1 == ~E_4~0); 104696#L729-1 assume !(1 == ~E_5~0); 104697#L734-1 assume { :end_inline_reset_delta_events } true; 105200#L940-2 [2022-12-13 16:16:01,981 INFO L750 eck$LassoCheckResult]: Loop: 105200#L940-2 assume !false; 106231#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 106229#L586 assume !false; 106228#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 106223#L464 assume !(0 == ~m_st~0); 106224#L468 assume !(0 == ~t1_st~0); 106226#L472 assume !(0 == ~t2_st~0); 106221#L476 assume !(0 == ~t3_st~0); 106222#L480 assume !(0 == ~t4_st~0); 106225#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 106227#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 106213#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 106214#L511 assume !(0 != eval_~tmp~0#1); 106537#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 106533#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 106529#L611-3 assume !(0 == ~M_E~0); 106525#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 106521#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 106517#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 106513#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 106508#L631-3 assume !(0 == ~T5_E~0); 106503#L636-3 assume !(0 == ~E_M~0); 106498#L641-3 assume !(0 == ~E_1~0); 106493#L646-3 assume !(0 == ~E_2~0); 106489#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 106484#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 106480#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 106476#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106472#L304-21 assume !(1 == ~m_pc~0); 106468#L304-23 is_master_triggered_~__retres1~0#1 := 0; 106462#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106458#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 106453#L755-21 assume !(0 != activate_threads_~tmp~1#1); 106450#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 106447#L323-21 assume !(1 == ~t1_pc~0); 106443#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 106439#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 106434#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 106430#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 106426#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106422#L342-21 assume !(1 == ~t2_pc~0); 106417#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 106413#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 106410#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 106406#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 106403#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106396#L361-21 assume !(1 == ~t3_pc~0); 106394#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 106392#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 106390#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 106388#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 106378#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 106373#L380-21 assume !(1 == ~t4_pc~0); 106369#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 106364#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 106359#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 106354#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 106349#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 106347#L399-21 assume 1 == ~t5_pc~0; 106320#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 106316#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106314#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 106312#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 106310#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106308#L679-3 assume !(1 == ~M_E~0); 106306#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 106304#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 106302#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 106300#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 106298#L699-3 assume !(1 == ~T5_E~0); 106296#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 106294#L709-3 assume !(1 == ~E_1~0); 106292#L714-3 assume !(1 == ~E_2~0); 106290#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 106288#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 106286#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 106284#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 105670#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 105666#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 105657#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 105658#L959 assume !(0 == start_simulation_~tmp~3#1); 106257#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 106253#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 106247#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 106245#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 106243#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 106241#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 106237#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 106235#L972 assume !(0 != start_simulation_~tmp___0~1#1); 105200#L940-2 [2022-12-13 16:16:01,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:01,981 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2022-12-13 16:16:01,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:01,981 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130373095] [2022-12-13 16:16:01,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:01,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:01,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:01,990 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:01,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:02,002 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:02,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:02,003 INFO L85 PathProgramCache]: Analyzing trace with hash -27639872, now seen corresponding path program 1 times [2022-12-13 16:16:02,003 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:02,003 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803290389] [2022-12-13 16:16:02,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:02,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:02,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:02,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:02,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:02,030 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803290389] [2022-12-13 16:16:02,030 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [803290389] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:02,030 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:02,030 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:16:02,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1808442284] [2022-12-13 16:16:02,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:02,031 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:16:02,031 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:16:02,031 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:16:02,031 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:16:02,031 INFO L87 Difference]: Start difference. First operand 4928 states and 6826 transitions. cyclomatic complexity: 1902 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:02,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:16:02,089 INFO L93 Difference]: Finished difference Result 8309 states and 11344 transitions. [2022-12-13 16:16:02,090 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8309 states and 11344 transitions. [2022-12-13 16:16:02,110 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8196 [2022-12-13 16:16:02,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8309 states to 8309 states and 11344 transitions. [2022-12-13 16:16:02,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8309 [2022-12-13 16:16:02,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8309 [2022-12-13 16:16:02,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8309 states and 11344 transitions. [2022-12-13 16:16:02,160 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:16:02,160 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8309 states and 11344 transitions. [2022-12-13 16:16:02,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8309 states and 11344 transitions. [2022-12-13 16:16:02,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8309 to 7997. [2022-12-13 16:16:02,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7997 states, 7997 states have (on average 1.3675128173064899) internal successors, (10936), 7996 states have internal predecessors, (10936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:02,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7997 states to 7997 states and 10936 transitions. [2022-12-13 16:16:02,226 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7997 states and 10936 transitions. [2022-12-13 16:16:02,226 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:16:02,226 INFO L428 stractBuchiCegarLoop]: Abstraction has 7997 states and 10936 transitions. [2022-12-13 16:16:02,226 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 16:16:02,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7997 states and 10936 transitions. [2022-12-13 16:16:02,243 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7884 [2022-12-13 16:16:02,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:16:02,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:16:02,244 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:02,244 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:02,244 INFO L748 eck$LassoCheckResult]: Stem: 118171#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 118172#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 118285#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 118286#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 118270#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 118271#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118111#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118112#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118089#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118090#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 118357#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 118198#L611 assume !(0 == ~M_E~0); 118199#L611-2 assume !(0 == ~T1_E~0); 118377#L616-1 assume !(0 == ~T2_E~0); 118378#L621-1 assume !(0 == ~T3_E~0); 117959#L626-1 assume !(0 == ~T4_E~0); 117960#L631-1 assume !(0 == ~T5_E~0); 118154#L636-1 assume !(0 == ~E_M~0); 118007#L641-1 assume !(0 == ~E_1~0); 118008#L646-1 assume !(0 == ~E_2~0); 118169#L651-1 assume !(0 == ~E_3~0); 118427#L656-1 assume !(0 == ~E_4~0); 118355#L661-1 assume !(0 == ~E_5~0); 118356#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118396#L304 assume !(1 == ~m_pc~0); 118034#L304-2 is_master_triggered_~__retres1~0#1 := 0; 117929#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117930#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 117885#L755 assume !(0 != activate_threads_~tmp~1#1); 117886#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117841#L323 assume !(1 == ~t1_pc~0); 117842#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 117898#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117899#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 117914#L763 assume !(0 != activate_threads_~tmp___0~0#1); 118458#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117908#L342 assume !(1 == ~t2_pc~0); 117910#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 118036#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118037#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 118287#L771 assume !(0 != activate_threads_~tmp___1~0#1); 118349#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118232#L361 assume !(1 == ~t3_pc~0); 118233#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 118262#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117855#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 117856#L779 assume !(0 != activate_threads_~tmp___2~0#1); 117920#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117921#L380 assume !(1 == ~t4_pc~0); 118231#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 118369#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118003#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 118004#L787 assume !(0 != activate_threads_~tmp___3~0#1); 118273#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117977#L399 assume !(1 == ~t5_pc~0); 117978#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 118123#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118127#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 118113#L795 assume !(0 != activate_threads_~tmp___4~0#1); 118114#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118437#L679 assume !(1 == ~M_E~0); 118197#L679-2 assume !(1 == ~T1_E~0); 118051#L684-1 assume !(1 == ~T2_E~0); 118052#L689-1 assume !(1 == ~T3_E~0); 118243#L694-1 assume !(1 == ~T4_E~0); 118241#L699-1 assume !(1 == ~T5_E~0); 118242#L704-1 assume !(1 == ~E_M~0); 118222#L709-1 assume !(1 == ~E_1~0); 118156#L714-1 assume !(1 == ~E_2~0); 118157#L719-1 assume !(1 == ~E_3~0); 118345#L724-1 assume !(1 == ~E_4~0); 117940#L729-1 assume !(1 == ~E_5~0); 117941#L734-1 assume { :end_inline_reset_delta_events } true; 118440#L940-2 assume !false; 121106#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 121100#L586 [2022-12-13 16:16:02,244 INFO L750 eck$LassoCheckResult]: Loop: 121100#L586 assume !false; 121098#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 121094#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 121091#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 121088#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 121085#L511 assume 0 != eval_~tmp~0#1; 121080#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 121076#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 121073#L516 assume !(0 == ~t1_st~0); 121018#L530 assume !(0 == ~t2_st~0); 122232#L544 assume !(0 == ~t3_st~0); 121162#L558 assume !(0 == ~t4_st~0); 121104#L572 assume !(0 == ~t5_st~0); 121100#L586 [2022-12-13 16:16:02,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:02,244 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 1 times [2022-12-13 16:16:02,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:02,245 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091760074] [2022-12-13 16:16:02,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:02,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:02,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:02,251 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:02,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:02,264 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:02,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:02,264 INFO L85 PathProgramCache]: Analyzing trace with hash 1854600747, now seen corresponding path program 1 times [2022-12-13 16:16:02,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:02,264 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791028160] [2022-12-13 16:16:02,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:02,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:02,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:02,267 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:02,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:02,269 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:02,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:02,269 INFO L85 PathProgramCache]: Analyzing trace with hash 1112358501, now seen corresponding path program 1 times [2022-12-13 16:16:02,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:02,269 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101116143] [2022-12-13 16:16:02,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:02,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:02,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:02,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:02,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:02,296 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101116143] [2022-12-13 16:16:02,296 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2101116143] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:02,296 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:02,296 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:16:02,296 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830120940] [2022-12-13 16:16:02,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:02,365 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:16:02,366 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:16:02,366 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:16:02,366 INFO L87 Difference]: Start difference. First operand 7997 states and 10936 transitions. cyclomatic complexity: 2945 Second operand has 3 states, 3 states have (on average 29.333333333333332) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:02,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:16:02,467 INFO L93 Difference]: Finished difference Result 15210 states and 20633 transitions. [2022-12-13 16:16:02,467 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15210 states and 20633 transitions. [2022-12-13 16:16:02,505 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14611 [2022-12-13 16:16:02,535 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15210 states to 15210 states and 20633 transitions. [2022-12-13 16:16:02,535 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15210 [2022-12-13 16:16:02,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15210 [2022-12-13 16:16:02,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15210 states and 20633 transitions. [2022-12-13 16:16:02,548 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:16:02,548 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15210 states and 20633 transitions. [2022-12-13 16:16:02,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15210 states and 20633 transitions. [2022-12-13 16:16:02,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15210 to 14934. [2022-12-13 16:16:02,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14934 states, 14934 states have (on average 1.3572385161376723) internal successors, (20269), 14933 states have internal predecessors, (20269), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:02,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14934 states to 14934 states and 20269 transitions. [2022-12-13 16:16:02,709 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14934 states and 20269 transitions. [2022-12-13 16:16:02,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:16:02,710 INFO L428 stractBuchiCegarLoop]: Abstraction has 14934 states and 20269 transitions. [2022-12-13 16:16:02,710 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 16:16:02,710 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14934 states and 20269 transitions. [2022-12-13 16:16:02,749 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14335 [2022-12-13 16:16:02,749 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:16:02,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:16:02,750 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:02,750 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:02,750 INFO L748 eck$LassoCheckResult]: Stem: 141391#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 141392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 141513#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 141514#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 141497#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 141498#L426-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 141555#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 141551#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 141552#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 141716#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 141717#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 141418#L611 assume !(0 == ~M_E~0); 141419#L611-2 assume !(0 == ~T1_E~0); 141609#L616-1 assume !(0 == ~T2_E~0); 141610#L621-1 assume !(0 == ~T3_E~0); 141175#L626-1 assume !(0 == ~T4_E~0); 141176#L631-1 assume !(0 == ~T5_E~0); 141373#L636-1 assume !(0 == ~E_M~0); 141374#L641-1 assume !(0 == ~E_1~0); 141388#L646-1 assume !(0 == ~E_2~0); 141389#L651-1 assume !(0 == ~E_3~0); 141669#L656-1 assume !(0 == ~E_4~0); 141670#L661-1 assume !(0 == ~E_5~0); 141633#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 141634#L304 assume !(1 == ~m_pc~0); 141248#L304-2 is_master_triggered_~__retres1~0#1 := 0; 141249#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 141336#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 141337#L755 assume !(0 != activate_threads_~tmp~1#1); 141753#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 141754#L323 assume !(1 == ~t1_pc~0); 141445#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 141446#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 141129#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 141130#L763 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 141712#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 141123#L342 assume !(1 == ~t2_pc~0); 141125#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 141251#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 141252#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 141735#L771 assume !(0 != activate_threads_~tmp___1~0#1); 141736#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 141460#L361 assume !(1 == ~t3_pc~0); 141461#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 141687#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 141688#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 141665#L779 assume !(0 != activate_threads_~tmp___2~0#1); 141666#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 141456#L380 assume !(1 == ~t4_pc~0); 141457#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 141601#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 141602#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 141500#L787 assume !(0 != activate_threads_~tmp___3~0#1); 141501#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 141192#L399 assume !(1 == ~t5_pc~0); 141193#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 141615#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 141616#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 141329#L795 assume !(0 != activate_threads_~tmp___4~0#1); 141330#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 141737#L679 assume !(1 == ~M_E~0); 141738#L679-2 assume !(1 == ~T1_E~0); 141268#L684-1 assume !(1 == ~T2_E~0); 141269#L689-1 assume !(1 == ~T3_E~0); 141741#L694-1 assume !(1 == ~T4_E~0); 141742#L699-1 assume !(1 == ~T5_E~0); 141588#L704-1 assume !(1 == ~E_M~0); 141589#L709-1 assume !(1 == ~E_1~0); 141378#L714-1 assume !(1 == ~E_2~0); 141379#L719-1 assume !(1 == ~E_3~0); 141701#L724-1 assume !(1 == ~E_4~0); 141702#L729-1 assume !(1 == ~E_5~0); 141690#L734-1 assume { :end_inline_reset_delta_events } true; 141691#L940-2 assume !false; 146844#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 146840#L586 [2022-12-13 16:16:02,750 INFO L750 eck$LassoCheckResult]: Loop: 146840#L586 assume !false; 146839#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 146837#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 146836#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 146835#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 146834#L511 assume 0 != eval_~tmp~0#1; 146832#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 146831#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 146202#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 146203#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 146881#L530 assume !(0 == ~t2_st~0); 146883#L544 assume !(0 == ~t3_st~0); 146851#L558 assume !(0 == ~t4_st~0); 146849#L572 assume !(0 == ~t5_st~0); 146840#L586 [2022-12-13 16:16:02,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:02,751 INFO L85 PathProgramCache]: Analyzing trace with hash 1162562755, now seen corresponding path program 1 times [2022-12-13 16:16:02,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:02,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1601763933] [2022-12-13 16:16:02,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:02,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:02,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:02,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:02,773 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:02,773 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1601763933] [2022-12-13 16:16:02,773 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1601763933] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:02,773 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:02,773 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:16:02,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790913736] [2022-12-13 16:16:02,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:02,773 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:16:02,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:02,774 INFO L85 PathProgramCache]: Analyzing trace with hash 710157811, now seen corresponding path program 1 times [2022-12-13 16:16:02,774 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:02,774 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239057125] [2022-12-13 16:16:02,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:02,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:02,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:02,777 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:02,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:02,781 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:02,861 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:16:02,861 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:16:02,861 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:16:02,861 INFO L87 Difference]: Start difference. First operand 14934 states and 20269 transitions. cyclomatic complexity: 5347 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:02,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:16:02,912 INFO L93 Difference]: Finished difference Result 12393 states and 16854 transitions. [2022-12-13 16:16:02,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12393 states and 16854 transitions. [2022-12-13 16:16:02,960 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12266 [2022-12-13 16:16:02,993 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12393 states to 12393 states and 16854 transitions. [2022-12-13 16:16:02,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12393 [2022-12-13 16:16:03,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12393 [2022-12-13 16:16:03,001 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12393 states and 16854 transitions. [2022-12-13 16:16:03,008 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:16:03,008 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12393 states and 16854 transitions. [2022-12-13 16:16:03,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12393 states and 16854 transitions. [2022-12-13 16:16:03,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12393 to 12393. [2022-12-13 16:16:03,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12393 states, 12393 states have (on average 1.3599612684580005) internal successors, (16854), 12392 states have internal predecessors, (16854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:03,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12393 states to 12393 states and 16854 transitions. [2022-12-13 16:16:03,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12393 states and 16854 transitions. [2022-12-13 16:16:03,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:16:03,203 INFO L428 stractBuchiCegarLoop]: Abstraction has 12393 states and 16854 transitions. [2022-12-13 16:16:03,204 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 16:16:03,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12393 states and 16854 transitions. [2022-12-13 16:16:03,225 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12266 [2022-12-13 16:16:03,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:16:03,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:16:03,225 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:03,226 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:03,226 INFO L748 eck$LassoCheckResult]: Stem: 168724#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 168725#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 168844#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 168845#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 168829#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 168830#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 168658#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 168659#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 168636#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 168637#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 168923#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 168750#L611 assume !(0 == ~M_E~0); 168751#L611-2 assume !(0 == ~T1_E~0); 168941#L616-1 assume !(0 == ~T2_E~0); 168942#L621-1 assume !(0 == ~T3_E~0); 168506#L626-1 assume !(0 == ~T4_E~0); 168507#L631-1 assume !(0 == ~T5_E~0); 168705#L636-1 assume !(0 == ~E_M~0); 168553#L641-1 assume !(0 == ~E_1~0); 168554#L646-1 assume !(0 == ~E_2~0); 168721#L651-1 assume !(0 == ~E_3~0); 168995#L656-1 assume !(0 == ~E_4~0); 168921#L661-1 assume !(0 == ~E_5~0); 168922#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168964#L304 assume !(1 == ~m_pc~0); 168579#L304-2 is_master_triggered_~__retres1~0#1 := 0; 168476#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 168477#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 168433#L755 assume !(0 != activate_threads_~tmp~1#1); 168434#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 168389#L323 assume !(1 == ~t1_pc~0); 168390#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 168446#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 168447#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 168461#L763 assume !(0 != activate_threads_~tmp___0~0#1); 169033#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 168455#L342 assume !(1 == ~t2_pc~0); 168457#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 168581#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 168582#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 168846#L771 assume !(0 != activate_threads_~tmp___1~0#1); 168915#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 168790#L361 assume !(1 == ~t3_pc~0); 168791#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 168819#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 168403#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 168404#L779 assume !(0 != activate_threads_~tmp___2~0#1); 168467#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 168468#L380 assume !(1 == ~t4_pc~0); 168789#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 168933#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 168549#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 168550#L787 assume !(0 != activate_threads_~tmp___3~0#1); 168833#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 168524#L399 assume !(1 == ~t5_pc~0); 168525#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 168670#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 168675#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 168660#L795 assume !(0 != activate_threads_~tmp___4~0#1); 168661#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169008#L679 assume !(1 == ~M_E~0); 168749#L679-2 assume !(1 == ~T1_E~0); 168597#L684-1 assume !(1 == ~T2_E~0); 168598#L689-1 assume !(1 == ~T3_E~0); 168801#L694-1 assume !(1 == ~T4_E~0); 168799#L699-1 assume !(1 == ~T5_E~0); 168800#L704-1 assume !(1 == ~E_M~0); 168777#L709-1 assume !(1 == ~E_1~0); 168707#L714-1 assume !(1 == ~E_2~0); 168708#L719-1 assume !(1 == ~E_3~0); 168906#L724-1 assume !(1 == ~E_4~0); 168488#L729-1 assume !(1 == ~E_5~0); 168489#L734-1 assume { :end_inline_reset_delta_events } true; 169011#L940-2 assume !false; 172785#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 172657#L586 [2022-12-13 16:16:03,226 INFO L750 eck$LassoCheckResult]: Loop: 172657#L586 assume !false; 172658#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 172649#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 172650#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 172642#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 172643#L511 assume 0 != eval_~tmp~0#1; 172635#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 172637#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 172013#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 172014#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 172956#L530 assume !(0 == ~t2_st~0); 172810#L544 assume !(0 == ~t3_st~0); 172795#L558 assume !(0 == ~t4_st~0); 172794#L572 assume !(0 == ~t5_st~0); 172657#L586 [2022-12-13 16:16:03,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:03,226 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 2 times [2022-12-13 16:16:03,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:03,226 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1811126360] [2022-12-13 16:16:03,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:03,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:03,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:03,233 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:03,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:03,245 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:03,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:03,245 INFO L85 PathProgramCache]: Analyzing trace with hash 710157811, now seen corresponding path program 2 times [2022-12-13 16:16:03,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:03,245 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472214932] [2022-12-13 16:16:03,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:03,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:03,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:03,248 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:03,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:03,251 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:03,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:03,251 INFO L85 PathProgramCache]: Analyzing trace with hash -824515335, now seen corresponding path program 1 times [2022-12-13 16:16:03,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:03,252 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1250985368] [2022-12-13 16:16:03,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:03,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:03,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:03,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:03,276 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:03,276 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1250985368] [2022-12-13 16:16:03,276 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1250985368] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:03,277 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:03,277 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:16:03,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [245214858] [2022-12-13 16:16:03,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:03,349 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:16:03,349 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:16:03,349 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:16:03,349 INFO L87 Difference]: Start difference. First operand 12393 states and 16854 transitions. cyclomatic complexity: 4467 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:03,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:16:03,469 INFO L93 Difference]: Finished difference Result 23117 states and 31364 transitions. [2022-12-13 16:16:03,469 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23117 states and 31364 transitions. [2022-12-13 16:16:03,531 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 22944 [2022-12-13 16:16:03,580 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23117 states to 23117 states and 31364 transitions. [2022-12-13 16:16:03,581 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23117 [2022-12-13 16:16:03,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23117 [2022-12-13 16:16:03,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23117 states and 31364 transitions. [2022-12-13 16:16:03,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:16:03,600 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23117 states and 31364 transitions. [2022-12-13 16:16:03,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23117 states and 31364 transitions. [2022-12-13 16:16:03,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23117 to 22127. [2022-12-13 16:16:03,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22127 states, 22127 states have (on average 1.359696298639671) internal successors, (30086), 22126 states have internal predecessors, (30086), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:03,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22127 states to 22127 states and 30086 transitions. [2022-12-13 16:16:03,804 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22127 states and 30086 transitions. [2022-12-13 16:16:03,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:16:03,805 INFO L428 stractBuchiCegarLoop]: Abstraction has 22127 states and 30086 transitions. [2022-12-13 16:16:03,805 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 16:16:03,805 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22127 states and 30086 transitions. [2022-12-13 16:16:03,850 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 21954 [2022-12-13 16:16:03,850 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:16:03,850 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:16:03,851 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:03,851 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:03,851 INFO L748 eck$LassoCheckResult]: Stem: 204238#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 204239#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 204355#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 204356#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 204340#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 204341#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 204173#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 204174#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 204152#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 204153#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 204432#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 204264#L611 assume !(0 == ~M_E~0); 204265#L611-2 assume !(0 == ~T1_E~0); 204451#L616-1 assume !(0 == ~T2_E~0); 204452#L621-1 assume !(0 == ~T3_E~0); 204025#L626-1 assume !(0 == ~T4_E~0); 204026#L631-1 assume !(0 == ~T5_E~0); 204219#L636-1 assume !(0 == ~E_M~0); 204073#L641-1 assume !(0 == ~E_1~0); 204074#L646-1 assume !(0 == ~E_2~0); 204234#L651-1 assume !(0 == ~E_3~0); 204502#L656-1 assume !(0 == ~E_4~0); 204430#L661-1 assume !(0 == ~E_5~0); 204431#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 204474#L304 assume !(1 == ~m_pc~0); 204098#L304-2 is_master_triggered_~__retres1~0#1 := 0; 203994#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 203995#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 203948#L755 assume !(0 != activate_threads_~tmp~1#1); 203949#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 203907#L323 assume !(1 == ~t1_pc~0); 203908#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 203963#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 203964#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 203980#L763 assume !(0 != activate_threads_~tmp___0~0#1); 204547#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 203971#L342 assume !(1 == ~t2_pc~0); 203973#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 204100#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 204101#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 204357#L771 assume !(0 != activate_threads_~tmp___1~0#1); 204425#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 204299#L361 assume !(1 == ~t3_pc~0); 204300#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 204330#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 203921#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 203922#L779 assume !(0 != activate_threads_~tmp___2~0#1); 203986#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 203987#L380 assume !(1 == ~t4_pc~0); 204298#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 204440#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 204069#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 204070#L787 assume !(0 != activate_threads_~tmp___3~0#1); 204343#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 204043#L399 assume !(1 == ~t5_pc~0); 204044#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 204184#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 204190#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 204175#L795 assume !(0 != activate_threads_~tmp___4~0#1); 204176#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 204515#L679 assume !(1 == ~M_E~0); 204263#L679-2 assume !(1 == ~T1_E~0); 204115#L684-1 assume !(1 == ~T2_E~0); 204116#L689-1 assume !(1 == ~T3_E~0); 204311#L694-1 assume !(1 == ~T4_E~0); 204309#L699-1 assume !(1 == ~T5_E~0); 204310#L704-1 assume !(1 == ~E_M~0); 204289#L709-1 assume !(1 == ~E_1~0); 204221#L714-1 assume !(1 == ~E_2~0); 204222#L719-1 assume !(1 == ~E_3~0); 204420#L724-1 assume !(1 == ~E_4~0); 204006#L729-1 assume !(1 == ~E_5~0); 204007#L734-1 assume { :end_inline_reset_delta_events } true; 204520#L940-2 assume !false; 224891#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 224888#L586 [2022-12-13 16:16:03,851 INFO L750 eck$LassoCheckResult]: Loop: 224888#L586 assume !false; 224886#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 224301#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 224302#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 224921#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 224920#L511 assume 0 != eval_~tmp~0#1; 224919#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 219240#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 218066#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 214684#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 214685#L530 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 219570#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 220402#L544 assume !(0 == ~t3_st~0); 223566#L558 assume !(0 == ~t4_st~0); 223564#L572 assume !(0 == ~t5_st~0); 224888#L586 [2022-12-13 16:16:03,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:03,852 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 3 times [2022-12-13 16:16:03,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:03,852 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724067016] [2022-12-13 16:16:03,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:03,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:03,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:03,859 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:03,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:03,870 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:03,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:03,870 INFO L85 PathProgramCache]: Analyzing trace with hash 370932868, now seen corresponding path program 1 times [2022-12-13 16:16:03,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:03,870 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640779897] [2022-12-13 16:16:03,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:03,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:03,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:03,873 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:03,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:03,876 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:03,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:03,877 INFO L85 PathProgramCache]: Analyzing trace with hash 40705598, now seen corresponding path program 1 times [2022-12-13 16:16:03,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:03,877 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [298325672] [2022-12-13 16:16:03,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:03,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:03,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:03,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:03,901 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:03,901 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [298325672] [2022-12-13 16:16:03,901 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [298325672] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:03,901 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:03,901 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:16:03,902 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508406370] [2022-12-13 16:16:03,902 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:03,993 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:16:03,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:16:03,993 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:16:03,993 INFO L87 Difference]: Start difference. First operand 22127 states and 30086 transitions. cyclomatic complexity: 7965 Second operand has 3 states, 3 states have (on average 30.0) internal successors, (90), 3 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:04,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:16:04,103 INFO L93 Difference]: Finished difference Result 40277 states and 54772 transitions. [2022-12-13 16:16:04,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40277 states and 54772 transitions. [2022-12-13 16:16:04,257 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 40012 [2022-12-13 16:16:04,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40277 states to 40277 states and 54772 transitions. [2022-12-13 16:16:04,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40277 [2022-12-13 16:16:04,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40277 [2022-12-13 16:16:04,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40277 states and 54772 transitions. [2022-12-13 16:16:04,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:16:04,357 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40277 states and 54772 transitions. [2022-12-13 16:16:04,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40277 states and 54772 transitions. [2022-12-13 16:16:04,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40277 to 39017. [2022-12-13 16:16:04,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39017 states, 39017 states have (on average 1.3622779813927262) internal successors, (53152), 39016 states have internal predecessors, (53152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:04,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39017 states to 39017 states and 53152 transitions. [2022-12-13 16:16:04,774 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39017 states and 53152 transitions. [2022-12-13 16:16:04,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:16:04,775 INFO L428 stractBuchiCegarLoop]: Abstraction has 39017 states and 53152 transitions. [2022-12-13 16:16:04,775 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 16:16:04,775 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39017 states and 53152 transitions. [2022-12-13 16:16:04,888 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 38752 [2022-12-13 16:16:04,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:16:04,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:16:04,889 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:04,889 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:04,889 INFO L748 eck$LassoCheckResult]: Stem: 266652#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 266653#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 266776#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 266777#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 266757#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 266758#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 266588#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 266589#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 266566#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 266567#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 266872#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 266678#L611 assume !(0 == ~M_E~0); 266679#L611-2 assume !(0 == ~T1_E~0); 266889#L616-1 assume !(0 == ~T2_E~0); 266890#L621-1 assume !(0 == ~T3_E~0); 266432#L626-1 assume !(0 == ~T4_E~0); 266433#L631-1 assume !(0 == ~T5_E~0); 266634#L636-1 assume !(0 == ~E_M~0); 266481#L641-1 assume !(0 == ~E_1~0); 266482#L646-1 assume !(0 == ~E_2~0); 266649#L651-1 assume !(0 == ~E_3~0); 266940#L656-1 assume !(0 == ~E_4~0); 266870#L661-1 assume !(0 == ~E_5~0); 266871#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 266910#L304 assume !(1 == ~m_pc~0); 266507#L304-2 is_master_triggered_~__retres1~0#1 := 0; 266405#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 266406#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 266360#L755 assume !(0 != activate_threads_~tmp~1#1); 266361#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 266317#L323 assume !(1 == ~t1_pc~0); 266318#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 266376#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 266377#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 266391#L763 assume !(0 != activate_threads_~tmp___0~0#1); 266984#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 266383#L342 assume !(1 == ~t2_pc~0); 266385#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 266513#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 266514#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 266778#L771 assume !(0 != activate_threads_~tmp___1~0#1); 266864#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 266716#L361 assume !(1 == ~t3_pc~0); 266717#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 266746#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 266333#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 266334#L779 assume !(0 != activate_threads_~tmp___2~0#1); 266396#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 266397#L380 assume !(1 == ~t4_pc~0); 266715#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 266880#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 266476#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 266477#L787 assume !(0 != activate_threads_~tmp___3~0#1); 266760#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 266454#L399 assume !(1 == ~t5_pc~0); 266455#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 266598#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 266604#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 266590#L795 assume !(0 != activate_threads_~tmp___4~0#1); 266591#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 266954#L679 assume !(1 == ~M_E~0); 266676#L679-2 assume !(1 == ~T1_E~0); 266528#L684-1 assume !(1 == ~T2_E~0); 266529#L689-1 assume !(1 == ~T3_E~0); 266730#L694-1 assume !(1 == ~T4_E~0); 266728#L699-1 assume !(1 == ~T5_E~0); 266729#L704-1 assume !(1 == ~E_M~0); 266705#L709-1 assume !(1 == ~E_1~0); 266635#L714-1 assume !(1 == ~E_2~0); 266636#L719-1 assume !(1 == ~E_3~0); 266853#L724-1 assume !(1 == ~E_4~0); 266417#L729-1 assume !(1 == ~E_5~0); 266418#L734-1 assume { :end_inline_reset_delta_events } true; 266961#L940-2 assume !false; 281990#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 281985#L586 [2022-12-13 16:16:04,889 INFO L750 eck$LassoCheckResult]: Loop: 281985#L586 assume !false; 281981#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 281977#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 281975#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 281973#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 281969#L511 assume 0 != eval_~tmp~0#1; 281966#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 281963#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 281961#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 281959#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 281957#L530 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 281926#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 281955#L544 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 281790#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 282092#L558 assume !(0 == ~t4_st~0); 281988#L572 assume !(0 == ~t5_st~0); 281985#L586 [2022-12-13 16:16:04,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:04,890 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 4 times [2022-12-13 16:16:04,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:04,890 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [755718194] [2022-12-13 16:16:04,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:04,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:04,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:04,899 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:04,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:04,913 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:04,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:04,913 INFO L85 PathProgramCache]: Analyzing trace with hash -1391436902, now seen corresponding path program 1 times [2022-12-13 16:16:04,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:04,914 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123337985] [2022-12-13 16:16:04,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:04,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:04,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:04,917 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:04,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:04,920 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:04,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:04,921 INFO L85 PathProgramCache]: Analyzing trace with hash 1256419616, now seen corresponding path program 1 times [2022-12-13 16:16:04,921 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:04,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582454161] [2022-12-13 16:16:04,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:04,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:04,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:04,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:04,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:04,953 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [582454161] [2022-12-13 16:16:04,953 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [582454161] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:04,954 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:04,954 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:16:04,954 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [44234776] [2022-12-13 16:16:04,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:05,080 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:16:05,080 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:16:05,080 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:16:05,080 INFO L87 Difference]: Start difference. First operand 39017 states and 53152 transitions. cyclomatic complexity: 14141 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:05,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:16:05,233 INFO L93 Difference]: Finished difference Result 45199 states and 61510 transitions. [2022-12-13 16:16:05,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45199 states and 61510 transitions. [2022-12-13 16:16:05,394 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 44978 [2022-12-13 16:16:05,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45199 states to 45199 states and 61510 transitions. [2022-12-13 16:16:05,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45199 [2022-12-13 16:16:05,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45199 [2022-12-13 16:16:05,516 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45199 states and 61510 transitions. [2022-12-13 16:16:05,538 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:16:05,539 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45199 states and 61510 transitions. [2022-12-13 16:16:05,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45199 states and 61510 transitions. [2022-12-13 16:16:05,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45199 to 44407. [2022-12-13 16:16:05,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44407 states, 44407 states have (on average 1.362442858107956) internal successors, (60502), 44406 states have internal predecessors, (60502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:05,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44407 states to 44407 states and 60502 transitions. [2022-12-13 16:16:05,937 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44407 states and 60502 transitions. [2022-12-13 16:16:05,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:16:05,938 INFO L428 stractBuchiCegarLoop]: Abstraction has 44407 states and 60502 transitions. [2022-12-13 16:16:05,938 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 16:16:05,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44407 states and 60502 transitions. [2022-12-13 16:16:06,037 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 44186 [2022-12-13 16:16:06,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:16:06,038 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:16:06,038 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:06,038 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:06,038 INFO L748 eck$LassoCheckResult]: Stem: 350870#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 350871#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 350994#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 350995#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 350977#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 350978#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 350810#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 350811#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 350790#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 350791#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 351083#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 350898#L611 assume !(0 == ~M_E~0); 350899#L611-2 assume !(0 == ~T1_E~0); 351103#L616-1 assume !(0 == ~T2_E~0); 351104#L621-1 assume !(0 == ~T3_E~0); 350661#L626-1 assume !(0 == ~T4_E~0); 350662#L631-1 assume !(0 == ~T5_E~0); 350853#L636-1 assume !(0 == ~E_M~0); 350709#L641-1 assume !(0 == ~E_1~0); 350710#L646-1 assume !(0 == ~E_2~0); 350867#L651-1 assume !(0 == ~E_3~0); 351178#L656-1 assume !(0 == ~E_4~0); 351081#L661-1 assume !(0 == ~E_5~0); 351082#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 351130#L304 assume !(1 == ~m_pc~0); 350735#L304-2 is_master_triggered_~__retres1~0#1 := 0; 350630#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 350631#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 350587#L755 assume !(0 != activate_threads_~tmp~1#1); 350588#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 350545#L323 assume !(1 == ~t1_pc~0); 350546#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 350599#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 350600#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 350616#L763 assume !(0 != activate_threads_~tmp___0~0#1); 351224#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 350609#L342 assume !(1 == ~t2_pc~0); 350611#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 350737#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 350738#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 350996#L771 assume !(0 != activate_threads_~tmp___1~0#1); 351076#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 350934#L361 assume !(1 == ~t3_pc~0); 350935#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 350966#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 350557#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 350558#L779 assume !(0 != activate_threads_~tmp___2~0#1); 350621#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 350622#L380 assume !(1 == ~t4_pc~0); 350933#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 351094#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 350705#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 350706#L787 assume !(0 != activate_threads_~tmp___3~0#1); 350980#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 350678#L399 assume !(1 == ~t5_pc~0); 350679#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 350821#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 350826#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 350812#L795 assume !(0 != activate_threads_~tmp___4~0#1); 350813#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 351188#L679 assume !(1 == ~M_E~0); 350897#L679-2 assume !(1 == ~T1_E~0); 350753#L684-1 assume !(1 == ~T2_E~0); 350754#L689-1 assume !(1 == ~T3_E~0); 350946#L694-1 assume !(1 == ~T4_E~0); 350944#L699-1 assume !(1 == ~T5_E~0); 350945#L704-1 assume !(1 == ~E_M~0); 350923#L709-1 assume !(1 == ~E_1~0); 350857#L714-1 assume !(1 == ~E_2~0); 350858#L719-1 assume !(1 == ~E_3~0); 351066#L724-1 assume !(1 == ~E_4~0); 350642#L729-1 assume !(1 == ~E_5~0); 350643#L734-1 assume { :end_inline_reset_delta_events } true; 351196#L940-2 assume !false; 378822#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 378819#L586 [2022-12-13 16:16:06,039 INFO L750 eck$LassoCheckResult]: Loop: 378819#L586 assume !false; 378758#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 378750#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 378745#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 378736#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 378729#L511 assume 0 != eval_~tmp~0#1; 378722#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 378713#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 378708#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 378703#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 378698#L530 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 378674#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 378694#L544 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 378739#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 378834#L558 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 378931#L575 assume !(0 != eval_~tmp_ndt_5~0#1); 378820#L572 assume !(0 == ~t5_st~0); 378819#L586 [2022-12-13 16:16:06,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:06,039 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 5 times [2022-12-13 16:16:06,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:06,039 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359389018] [2022-12-13 16:16:06,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:06,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:06,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:06,046 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:06,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:06,058 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:06,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:06,058 INFO L85 PathProgramCache]: Analyzing trace with hash -185045283, now seen corresponding path program 1 times [2022-12-13 16:16:06,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:06,058 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544975302] [2022-12-13 16:16:06,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:06,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:06,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:06,061 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:06,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:06,064 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:06,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:06,064 INFO L85 PathProgramCache]: Analyzing trace with hash 294128151, now seen corresponding path program 1 times [2022-12-13 16:16:06,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:06,064 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [988625663] [2022-12-13 16:16:06,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:06,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:06,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:16:06,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:16:06,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:16:06,088 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [988625663] [2022-12-13 16:16:06,088 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [988625663] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:16:06,088 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:16:06,089 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:16:06,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1001761442] [2022-12-13 16:16:06,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:16:06,212 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:16:06,212 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:16:06,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:16:06,212 INFO L87 Difference]: Start difference. First operand 44407 states and 60502 transitions. cyclomatic complexity: 16101 Second operand has 3 states, 2 states have (on average 46.0) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:06,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:16:06,394 INFO L93 Difference]: Finished difference Result 77457 states and 105418 transitions. [2022-12-13 16:16:06,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77457 states and 105418 transitions. [2022-12-13 16:16:06,719 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 77096 [2022-12-13 16:16:06,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77457 states to 77457 states and 105418 transitions. [2022-12-13 16:16:06,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77457 [2022-12-13 16:16:06,855 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77457 [2022-12-13 16:16:06,856 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77457 states and 105418 transitions. [2022-12-13 16:16:06,881 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:16:06,881 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77457 states and 105418 transitions. [2022-12-13 16:16:06,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77457 states and 105418 transitions. [2022-12-13 16:16:07,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77457 to 76721. [2022-12-13 16:16:07,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76721 states, 76721 states have (on average 1.364450411230302) internal successors, (104682), 76720 states have internal predecessors, (104682), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:16:07,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76721 states to 76721 states and 104682 transitions. [2022-12-13 16:16:07,467 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76721 states and 104682 transitions. [2022-12-13 16:16:07,467 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:16:07,468 INFO L428 stractBuchiCegarLoop]: Abstraction has 76721 states and 104682 transitions. [2022-12-13 16:16:07,468 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 16:16:07,468 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76721 states and 104682 transitions. [2022-12-13 16:16:07,681 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 76360 [2022-12-13 16:16:07,681 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:16:07,681 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:16:07,682 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:07,682 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:16:07,682 INFO L748 eck$LassoCheckResult]: Stem: 472750#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 472751#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 472872#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 472873#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 472855#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 472856#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 472683#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 472684#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 472663#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 472664#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 472955#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 472777#L611 assume !(0 == ~M_E~0); 472778#L611-2 assume !(0 == ~T1_E~0); 472971#L616-1 assume !(0 == ~T2_E~0); 472972#L621-1 assume !(0 == ~T3_E~0); 472526#L626-1 assume !(0 == ~T4_E~0); 472527#L631-1 assume !(0 == ~T5_E~0); 472726#L636-1 assume !(0 == ~E_M~0); 472579#L641-1 assume !(0 == ~E_1~0); 472580#L646-1 assume !(0 == ~E_2~0); 472746#L651-1 assume !(0 == ~E_3~0); 473042#L656-1 assume !(0 == ~E_4~0); 472953#L661-1 assume !(0 == ~E_5~0); 472954#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 473002#L304 assume !(1 == ~m_pc~0); 472602#L304-2 is_master_triggered_~__retres1~0#1 := 0; 472502#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 472503#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 472454#L755 assume !(0 != activate_threads_~tmp~1#1); 472455#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 472413#L323 assume !(1 == ~t1_pc~0); 472414#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 472472#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 472473#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 472488#L763 assume !(0 != activate_threads_~tmp___0~0#1); 473090#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 472476#L342 assume !(1 == ~t2_pc~0); 472478#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 472609#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 472610#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 472874#L771 assume !(0 != activate_threads_~tmp___1~0#1); 472948#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 472814#L361 assume !(1 == ~t3_pc~0); 472815#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 472846#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 472429#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 472430#L779 assume !(0 != activate_threads_~tmp___2~0#1); 472491#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 472492#L380 assume !(1 == ~t4_pc~0); 472813#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 472963#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 472572#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 472573#L787 assume !(0 != activate_threads_~tmp___3~0#1); 472859#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 472550#L399 assume !(1 == ~t5_pc~0); 472551#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 472694#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 472701#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 472685#L795 assume !(0 != activate_threads_~tmp___4~0#1); 472686#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 473053#L679 assume !(1 == ~M_E~0); 472775#L679-2 assume !(1 == ~T1_E~0); 472624#L684-1 assume !(1 == ~T2_E~0); 472625#L689-1 assume !(1 == ~T3_E~0); 472827#L694-1 assume !(1 == ~T4_E~0); 472825#L699-1 assume !(1 == ~T5_E~0); 472826#L704-1 assume !(1 == ~E_M~0); 472802#L709-1 assume !(1 == ~E_1~0); 472730#L714-1 assume !(1 == ~E_2~0); 472731#L719-1 assume !(1 == ~E_3~0); 472942#L724-1 assume !(1 == ~E_4~0); 472514#L729-1 assume !(1 == ~E_5~0); 472515#L734-1 assume { :end_inline_reset_delta_events } true; 473059#L940-2 assume !false; 533414#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 533412#L586 [2022-12-13 16:16:07,682 INFO L750 eck$LassoCheckResult]: Loop: 533412#L586 assume !false; 533409#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 533406#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 533404#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 533402#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 533398#L511 assume 0 != eval_~tmp~0#1; 533395#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 533390#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 533388#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 533386#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 533384#L530 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 533380#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 533378#L544 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 533286#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 533376#L558 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 533420#L575 assume !(0 != eval_~tmp_ndt_5~0#1); 533418#L572 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 533415#L589 assume !(0 != eval_~tmp_ndt_6~0#1); 533412#L586 [2022-12-13 16:16:07,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:07,683 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 6 times [2022-12-13 16:16:07,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:07,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336134089] [2022-12-13 16:16:07,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:07,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:07,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:07,694 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:07,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:07,716 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:07,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:07,716 INFO L85 PathProgramCache]: Analyzing trace with hash -1441440447, now seen corresponding path program 1 times [2022-12-13 16:16:07,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:07,717 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1890968122] [2022-12-13 16:16:07,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:07,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:07,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:07,720 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:07,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:07,724 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:07,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:16:07,725 INFO L85 PathProgramCache]: Analyzing trace with hash 528034119, now seen corresponding path program 1 times [2022-12-13 16:16:07,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:16:07,725 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638038099] [2022-12-13 16:16:07,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:16:07,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:16:07,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:07,735 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:07,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:07,761 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 16:16:09,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:09,195 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 16:16:09,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 16:16:09,329 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 04:16:09 BoogieIcfgContainer [2022-12-13 16:16:09,329 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 16:16:09,329 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 16:16:09,329 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 16:16:09,330 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 16:16:09,330 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 04:15:57" (3/4) ... [2022-12-13 16:16:09,332 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 16:16:09,385 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 16:16:09,385 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 16:16:09,385 INFO L158 Benchmark]: Toolchain (without parser) took 12849.03ms. Allocated memory was 138.4MB in the beginning and 4.1GB in the end (delta: 4.0GB). Free memory was 102.6MB in the beginning and 3.1GB in the end (delta: -2.9GB). Peak memory consumption was 1.0GB. Max. memory is 16.1GB. [2022-12-13 16:16:09,385 INFO L158 Benchmark]: CDTParser took 0.11ms. Allocated memory is still 138.4MB. Free memory is still 108.7MB. There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 16:16:09,385 INFO L158 Benchmark]: CACSL2BoogieTranslator took 229.89ms. Allocated memory is still 138.4MB. Free memory was 102.1MB in the beginning and 85.8MB in the end (delta: 16.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2022-12-13 16:16:09,386 INFO L158 Benchmark]: Boogie Procedure Inliner took 41.54ms. Allocated memory is still 138.4MB. Free memory was 85.8MB in the beginning and 80.8MB in the end (delta: 5.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 16:16:09,386 INFO L158 Benchmark]: Boogie Preprocessor took 37.80ms. Allocated memory is still 138.4MB. Free memory was 80.8MB in the beginning and 75.9MB in the end (delta: 4.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-12-13 16:16:09,386 INFO L158 Benchmark]: RCFGBuilder took 874.38ms. Allocated memory was 138.4MB in the beginning and 167.8MB in the end (delta: 29.4MB). Free memory was 75.9MB in the beginning and 109.3MB in the end (delta: -33.4MB). Peak memory consumption was 45.8MB. Max. memory is 16.1GB. [2022-12-13 16:16:09,386 INFO L158 Benchmark]: BuchiAutomizer took 11606.26ms. Allocated memory was 167.8MB in the beginning and 4.1GB in the end (delta: 3.9GB). Free memory was 109.3MB in the beginning and 3.1GB in the end (delta: -3.0GB). Peak memory consumption was 996.0MB. Max. memory is 16.1GB. [2022-12-13 16:16:09,386 INFO L158 Benchmark]: Witness Printer took 55.32ms. Allocated memory is still 4.1GB. Free memory was 3.1GB in the beginning and 3.1GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-12-13 16:16:09,387 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11ms. Allocated memory is still 138.4MB. Free memory is still 108.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 229.89ms. Allocated memory is still 138.4MB. Free memory was 102.1MB in the beginning and 85.8MB in the end (delta: 16.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 41.54ms. Allocated memory is still 138.4MB. Free memory was 85.8MB in the beginning and 80.8MB in the end (delta: 5.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 37.80ms. Allocated memory is still 138.4MB. Free memory was 80.8MB in the beginning and 75.9MB in the end (delta: 4.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 874.38ms. Allocated memory was 138.4MB in the beginning and 167.8MB in the end (delta: 29.4MB). Free memory was 75.9MB in the beginning and 109.3MB in the end (delta: -33.4MB). Peak memory consumption was 45.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 11606.26ms. Allocated memory was 167.8MB in the beginning and 4.1GB in the end (delta: 3.9GB). Free memory was 109.3MB in the beginning and 3.1GB in the end (delta: -3.0GB). Peak memory consumption was 996.0MB. Max. memory is 16.1GB. * Witness Printer took 55.32ms. Allocated memory is still 4.1GB. Free memory was 3.1GB in the beginning and 3.1GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 76721 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 11.4s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 3.8s. Construction of modules took 0.5s. Büchi inclusion checks took 6.2s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 2.8s AutomataMinimizationTime, 23 MinimizatonAttempts, 24011 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 1.7s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 23488 SdHoareTripleChecker+Valid, 0.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 23488 mSDsluCounter, 39044 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 18650 mSDsCounter, 312 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 665 IncrementalHoareTripleChecker+Invalid, 977 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 312 mSolverCounterUnsat, 20394 mSDtfsCounter, 665 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc5 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 506]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, token=0] [L985] int __retres1 ; [L989] CALL init_model() [L896] m_i = 1 [L897] t1_i = 1 [L898] t2_i = 1 [L899] t3_i = 1 [L900] t4_i = 1 [L901] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L989] RET init_model() [L990] CALL start_simulation() [L926] int kernel_st ; [L927] int tmp ; [L928] int tmp___0 ; [L932] kernel_st = 0 [L933] FCALL update_channels() [L934] CALL init_threads() [L426] COND TRUE m_i == 1 [L427] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L431] COND TRUE t1_i == 1 [L432] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L436] COND TRUE t2_i == 1 [L437] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L441] COND TRUE t3_i == 1 [L442] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L446] COND TRUE t4_i == 1 [L447] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L451] COND TRUE t5_i == 1 [L452] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L934] RET init_threads() [L935] CALL fire_delta_events() [L611] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L616] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L621] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L626] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L631] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L636] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L641] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L646] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L651] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L656] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L661] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L666] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L935] RET fire_delta_events() [L936] CALL activate_threads() [L744] int tmp ; [L745] int tmp___0 ; [L746] int tmp___1 ; [L747] int tmp___2 ; [L748] int tmp___3 ; [L749] int tmp___4 ; [L753] CALL, EXPR is_master_triggered() [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L314] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L316] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L753] RET, EXPR is_master_triggered() [L753] tmp = is_master_triggered() [L755] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L761] CALL, EXPR is_transmit1_triggered() [L320] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L333] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L335] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] RET, EXPR is_transmit1_triggered() [L761] tmp___0 = is_transmit1_triggered() [L763] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L769] CALL, EXPR is_transmit2_triggered() [L339] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L352] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L354] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] RET, EXPR is_transmit2_triggered() [L769] tmp___1 = is_transmit2_triggered() [L771] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L777] CALL, EXPR is_transmit3_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L371] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L373] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] RET, EXPR is_transmit3_triggered() [L777] tmp___2 = is_transmit3_triggered() [L779] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L785] CALL, EXPR is_transmit4_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L390] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L392] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] RET, EXPR is_transmit4_triggered() [L785] tmp___3 = is_transmit4_triggered() [L787] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L793] CALL, EXPR is_transmit5_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L409] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L411] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] RET, EXPR is_transmit5_triggered() [L793] tmp___4 = is_transmit5_triggered() [L795] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L936] RET activate_threads() [L937] CALL reset_delta_events() [L679] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L684] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L689] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L694] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L699] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L704] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L709] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L714] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L719] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L724] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L729] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L734] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L937] RET reset_delta_events() [L940] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L943] kernel_st = 1 [L944] CALL eval() [L502] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L506] COND TRUE 1 [L509] CALL, EXPR exists_runnable_thread() [L461] int __retres1 ; [L464] COND TRUE m_st == 0 [L465] __retres1 = 1 [L497] return (__retres1); [L509] RET, EXPR exists_runnable_thread() [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L516] COND TRUE m_st == 0 [L517] int tmp_ndt_1; [L518] tmp_ndt_1 = __VERIFIER_nondet_int() [L519] COND FALSE !(\read(tmp_ndt_1)) [L530] COND TRUE t1_st == 0 [L531] int tmp_ndt_2; [L532] tmp_ndt_2 = __VERIFIER_nondet_int() [L533] COND FALSE !(\read(tmp_ndt_2)) [L544] COND TRUE t2_st == 0 [L545] int tmp_ndt_3; [L546] tmp_ndt_3 = __VERIFIER_nondet_int() [L547] COND FALSE !(\read(tmp_ndt_3)) [L558] COND TRUE t3_st == 0 [L559] int tmp_ndt_4; [L560] tmp_ndt_4 = __VERIFIER_nondet_int() [L561] COND FALSE !(\read(tmp_ndt_4)) [L572] COND TRUE t4_st == 0 [L573] int tmp_ndt_5; [L574] tmp_ndt_5 = __VERIFIER_nondet_int() [L575] COND FALSE !(\read(tmp_ndt_5)) [L586] COND TRUE t5_st == 0 [L587] int tmp_ndt_6; [L588] tmp_ndt_6 = __VERIFIER_nondet_int() [L589] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 506]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, token=0] [L985] int __retres1 ; [L989] CALL init_model() [L896] m_i = 1 [L897] t1_i = 1 [L898] t2_i = 1 [L899] t3_i = 1 [L900] t4_i = 1 [L901] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L989] RET init_model() [L990] CALL start_simulation() [L926] int kernel_st ; [L927] int tmp ; [L928] int tmp___0 ; [L932] kernel_st = 0 [L933] FCALL update_channels() [L934] CALL init_threads() [L426] COND TRUE m_i == 1 [L427] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L431] COND TRUE t1_i == 1 [L432] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L436] COND TRUE t2_i == 1 [L437] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L441] COND TRUE t3_i == 1 [L442] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L446] COND TRUE t4_i == 1 [L447] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L451] COND TRUE t5_i == 1 [L452] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L934] RET init_threads() [L935] CALL fire_delta_events() [L611] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L616] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L621] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L626] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L631] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L636] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L641] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L646] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L651] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L656] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L661] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L666] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L935] RET fire_delta_events() [L936] CALL activate_threads() [L744] int tmp ; [L745] int tmp___0 ; [L746] int tmp___1 ; [L747] int tmp___2 ; [L748] int tmp___3 ; [L749] int tmp___4 ; [L753] CALL, EXPR is_master_triggered() [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L314] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L316] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L753] RET, EXPR is_master_triggered() [L753] tmp = is_master_triggered() [L755] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L761] CALL, EXPR is_transmit1_triggered() [L320] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L333] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L335] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] RET, EXPR is_transmit1_triggered() [L761] tmp___0 = is_transmit1_triggered() [L763] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L769] CALL, EXPR is_transmit2_triggered() [L339] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L352] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L354] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] RET, EXPR is_transmit2_triggered() [L769] tmp___1 = is_transmit2_triggered() [L771] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L777] CALL, EXPR is_transmit3_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L371] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L373] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] RET, EXPR is_transmit3_triggered() [L777] tmp___2 = is_transmit3_triggered() [L779] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L785] CALL, EXPR is_transmit4_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L390] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L392] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] RET, EXPR is_transmit4_triggered() [L785] tmp___3 = is_transmit4_triggered() [L787] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L793] CALL, EXPR is_transmit5_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L409] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L411] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] RET, EXPR is_transmit5_triggered() [L793] tmp___4 = is_transmit5_triggered() [L795] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L936] RET activate_threads() [L937] CALL reset_delta_events() [L679] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L684] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L689] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L694] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L699] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L704] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L709] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L714] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L719] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L724] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L729] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L734] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L937] RET reset_delta_events() [L940] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L943] kernel_st = 1 [L944] CALL eval() [L502] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L506] COND TRUE 1 [L509] CALL, EXPR exists_runnable_thread() [L461] int __retres1 ; [L464] COND TRUE m_st == 0 [L465] __retres1 = 1 [L497] return (__retres1); [L509] RET, EXPR exists_runnable_thread() [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L516] COND TRUE m_st == 0 [L517] int tmp_ndt_1; [L518] tmp_ndt_1 = __VERIFIER_nondet_int() [L519] COND FALSE !(\read(tmp_ndt_1)) [L530] COND TRUE t1_st == 0 [L531] int tmp_ndt_2; [L532] tmp_ndt_2 = __VERIFIER_nondet_int() [L533] COND FALSE !(\read(tmp_ndt_2)) [L544] COND TRUE t2_st == 0 [L545] int tmp_ndt_3; [L546] tmp_ndt_3 = __VERIFIER_nondet_int() [L547] COND FALSE !(\read(tmp_ndt_3)) [L558] COND TRUE t3_st == 0 [L559] int tmp_ndt_4; [L560] tmp_ndt_4 = __VERIFIER_nondet_int() [L561] COND FALSE !(\read(tmp_ndt_4)) [L572] COND TRUE t4_st == 0 [L573] int tmp_ndt_5; [L574] tmp_ndt_5 = __VERIFIER_nondet_int() [L575] COND FALSE !(\read(tmp_ndt_5)) [L586] COND TRUE t5_st == 0 [L587] int tmp_ndt_6; [L588] tmp_ndt_6 = __VERIFIER_nondet_int() [L589] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 16:16:09,465 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59038e7-960f-403c-ba8f-6e329a1a01bb/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)