./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 14:56:51,371 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 14:56:51,373 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 14:56:51,392 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 14:56:51,393 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 14:56:51,394 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 14:56:51,395 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 14:56:51,397 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 14:56:51,398 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 14:56:51,399 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 14:56:51,400 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 14:56:51,401 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 14:56:51,401 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 14:56:51,402 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 14:56:51,404 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 14:56:51,405 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 14:56:51,405 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 14:56:51,406 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 14:56:51,408 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 14:56:51,410 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 14:56:51,411 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 14:56:51,413 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 14:56:51,414 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 14:56:51,415 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 14:56:51,418 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 14:56:51,419 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 14:56:51,419 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 14:56:51,420 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 14:56:51,420 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 14:56:51,421 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 14:56:51,421 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 14:56:51,422 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 14:56:51,422 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 14:56:51,423 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 14:56:51,424 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 14:56:51,424 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 14:56:51,425 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 14:56:51,425 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 14:56:51,425 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 14:56:51,425 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 14:56:51,426 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 14:56:51,427 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 14:56:51,450 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 14:56:51,450 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 14:56:51,450 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 14:56:51,450 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 14:56:51,451 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 14:56:51,452 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 14:56:51,452 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 14:56:51,452 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 14:56:51,452 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 14:56:51,452 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 14:56:51,452 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 14:56:51,453 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 14:56:51,453 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 14:56:51,453 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 14:56:51,453 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 14:56:51,453 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 14:56:51,453 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 14:56:51,454 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 14:56:51,454 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 14:56:51,454 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 14:56:51,454 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 14:56:51,454 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 14:56:51,454 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 14:56:51,455 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 14:56:51,455 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 14:56:51,455 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 14:56:51,455 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 14:56:51,455 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 14:56:51,455 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 14:56:51,456 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 14:56:51,456 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 14:56:51,456 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 14:56:51,457 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 [2022-12-13 14:56:51,668 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 14:56:51,688 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 14:56:51,690 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 14:56:51,691 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 14:56:51,691 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 14:56:51,693 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2022-12-13 14:56:54,282 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 14:56:54,437 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 14:56:54,438 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2022-12-13 14:56:54,445 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8/data/7aa37c18b/21989f1bf3694b16a21e6f24fae26be4/FLAG11f280638 [2022-12-13 14:56:54,834 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8/data/7aa37c18b/21989f1bf3694b16a21e6f24fae26be4 [2022-12-13 14:56:54,835 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 14:56:54,836 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 14:56:54,837 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 14:56:54,837 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 14:56:54,839 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 14:56:54,840 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 02:56:54" (1/1) ... [2022-12-13 14:56:54,841 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5fe81be5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:54, skipping insertion in model container [2022-12-13 14:56:54,841 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 02:56:54" (1/1) ... [2022-12-13 14:56:54,846 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 14:56:54,876 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 14:56:54,993 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/sv-benchmarks/c/systemc/token_ring.06.cil-2.c[671,684] [2022-12-13 14:56:55,068 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 14:56:55,078 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 14:56:55,085 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/sv-benchmarks/c/systemc/token_ring.06.cil-2.c[671,684] [2022-12-13 14:56:55,113 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 14:56:55,125 INFO L208 MainTranslator]: Completed translation [2022-12-13 14:56:55,126 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:55 WrapperNode [2022-12-13 14:56:55,126 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 14:56:55,127 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 14:56:55,127 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 14:56:55,127 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 14:56:55,134 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:55" (1/1) ... [2022-12-13 14:56:55,141 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:55" (1/1) ... [2022-12-13 14:56:55,177 INFO L138 Inliner]: procedures = 40, calls = 49, calls flagged for inlining = 44, calls inlined = 113, statements flattened = 1650 [2022-12-13 14:56:55,178 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 14:56:55,178 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 14:56:55,178 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 14:56:55,178 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 14:56:55,185 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:55" (1/1) ... [2022-12-13 14:56:55,185 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:55" (1/1) ... [2022-12-13 14:56:55,189 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:55" (1/1) ... [2022-12-13 14:56:55,189 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:55" (1/1) ... [2022-12-13 14:56:55,202 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:55" (1/1) ... [2022-12-13 14:56:55,211 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:55" (1/1) ... [2022-12-13 14:56:55,213 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:55" (1/1) ... [2022-12-13 14:56:55,216 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:55" (1/1) ... [2022-12-13 14:56:55,221 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 14:56:55,222 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 14:56:55,222 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 14:56:55,222 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 14:56:55,222 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:55" (1/1) ... [2022-12-13 14:56:55,227 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 14:56:55,236 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 14:56:55,247 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 14:56:55,248 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d0a38bc-2918-4705-9ef5-000cbad92861/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 14:56:55,278 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 14:56:55,279 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 14:56:55,279 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 14:56:55,279 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 14:56:55,354 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 14:56:55,356 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 14:56:56,205 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 14:56:56,217 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 14:56:56,217 INFO L300 CfgBuilder]: Removed 9 assume(true) statements. [2022-12-13 14:56:56,220 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 02:56:56 BoogieIcfgContainer [2022-12-13 14:56:56,220 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 14:56:56,221 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 14:56:56,221 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 14:56:56,225 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 14:56:56,226 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 14:56:56,226 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 02:56:54" (1/3) ... [2022-12-13 14:56:56,227 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@725e6c3a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 02:56:56, skipping insertion in model container [2022-12-13 14:56:56,227 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 14:56:56,227 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 02:56:55" (2/3) ... [2022-12-13 14:56:56,228 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@725e6c3a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 02:56:56, skipping insertion in model container [2022-12-13 14:56:56,228 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 14:56:56,228 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 02:56:56" (3/3) ... [2022-12-13 14:56:56,229 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-2.c [2022-12-13 14:56:56,293 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 14:56:56,293 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 14:56:56,293 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 14:56:56,293 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 14:56:56,294 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 14:56:56,294 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 14:56:56,294 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 14:56:56,294 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 14:56:56,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 687 states, 686 states have (on average 1.5233236151603498) internal successors, (1045), 686 states have internal predecessors, (1045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:56,341 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 592 [2022-12-13 14:56:56,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:56:56,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:56:56,351 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:56,352 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:56,352 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 14:56:56,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 687 states, 686 states have (on average 1.5233236151603498) internal successors, (1045), 686 states have internal predecessors, (1045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:56,364 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 592 [2022-12-13 14:56:56,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:56:56,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:56:56,367 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:56,368 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:56,374 INFO L748 eck$LassoCheckResult]: Stem: 211#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 570#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 318#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 565#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 90#L475true assume !(1 == ~m_i~0);~m_st~0 := 2; 554#L475-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 317#L480-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 621#L485-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 257#L490-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 125#L495-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 458#L500-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 79#L505-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 527#L684true assume !(0 == ~M_E~0); 442#L684-2true assume !(0 == ~T1_E~0); 285#L689-1true assume !(0 == ~T2_E~0); 663#L694-1true assume !(0 == ~T3_E~0); 284#L699-1true assume !(0 == ~T4_E~0); 436#L704-1true assume !(0 == ~T5_E~0); 243#L709-1true assume !(0 == ~T6_E~0); 200#L714-1true assume 0 == ~E_M~0;~E_M~0 := 1; 402#L719-1true assume !(0 == ~E_1~0); 586#L724-1true assume !(0 == ~E_2~0); 64#L729-1true assume !(0 == ~E_3~0); 562#L734-1true assume !(0 == ~E_4~0); 493#L739-1true assume !(0 == ~E_5~0); 173#L744-1true assume !(0 == ~E_6~0); 403#L749-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42#L334true assume !(1 == ~m_pc~0); 238#L334-2true is_master_triggered_~__retres1~0#1 := 0; 504#L345true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 157#L849true assume !(0 != activate_threads_~tmp~1#1); 369#L849-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 124#L353true assume 1 == ~t1_pc~0; 594#L354true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 321#L364true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 295#L857true assume !(0 != activate_threads_~tmp___0~0#1); 93#L857-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 560#L372true assume !(1 == ~t2_pc~0); 162#L372-2true is_transmit2_triggered_~__retres1~2#1 := 0; 235#L383true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 322#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 478#L865true assume !(0 != activate_threads_~tmp___1~0#1); 37#L865-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 454#L391true assume 1 == ~t3_pc~0; 578#L392true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 113#L402true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 393#L873true assume !(0 != activate_threads_~tmp___2~0#1); 159#L873-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 475#L410true assume 1 == ~t4_pc~0; 593#L411true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 373#L421true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 480#L881true assume !(0 != activate_threads_~tmp___3~0#1); 164#L881-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 278#L429true assume !(1 == ~t5_pc~0); 67#L429-2true is_transmit5_triggered_~__retres1~5#1 := 0; 652#L440true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 184#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 343#L889true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 366#L889-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 155#L448true assume 1 == ~t6_pc~0; 87#L449true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 340#L459true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 308#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 532#L897true assume !(0 != activate_threads_~tmp___5~0#1); 641#L897-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 633#L762true assume !(1 == ~M_E~0); 188#L762-2true assume !(1 == ~T1_E~0); 591#L767-1true assume !(1 == ~T2_E~0); 542#L772-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 367#L777-1true assume !(1 == ~T4_E~0); 270#L782-1true assume !(1 == ~T5_E~0); 82#L787-1true assume !(1 == ~T6_E~0); 81#L792-1true assume !(1 == ~E_M~0); 105#L797-1true assume !(1 == ~E_1~0); 421#L802-1true assume !(1 == ~E_2~0); 241#L807-1true assume !(1 == ~E_3~0); 488#L812-1true assume 1 == ~E_4~0;~E_4~0 := 2; 612#L817-1true assume !(1 == ~E_5~0); 286#L822-1true assume !(1 == ~E_6~0); 502#L827-1true assume { :end_inline_reset_delta_events } true; 158#L1053-2true [2022-12-13 14:56:56,376 INFO L750 eck$LassoCheckResult]: Loop: 158#L1053-2true assume !false; 477#L1054true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 551#L659true assume false; 109#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 497#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 260#L684-3true assume 0 == ~M_E~0;~M_E~0 := 1; 429#L684-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 2#L689-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 186#L694-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 27#L699-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 353#L704-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 482#L709-3true assume !(0 == ~T6_E~0); 331#L714-3true assume 0 == ~E_M~0;~E_M~0 := 1; 180#L719-3true assume 0 == ~E_1~0;~E_1~0 := 1; 24#L724-3true assume 0 == ~E_2~0;~E_2~0 := 1; 312#L729-3true assume 0 == ~E_3~0;~E_3~0 := 1; 375#L734-3true assume 0 == ~E_4~0;~E_4~0 := 1; 357#L739-3true assume 0 == ~E_5~0;~E_5~0 := 1; 533#L744-3true assume 0 == ~E_6~0;~E_6~0 := 1; 484#L749-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30#L334-24true assume 1 == ~m_pc~0; 303#L335-8true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 326#L345-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 120#is_master_triggered_returnLabel#9true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16#L849-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 618#L849-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 355#L353-24true assume !(1 == ~t1_pc~0); 627#L353-26true is_transmit1_triggered_~__retres1~1#1 := 0; 548#L364-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 545#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 581#L857-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38#L857-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71#L372-24true assume 1 == ~t2_pc~0; 21#L373-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 225#L383-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 671#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 526#L865-24true assume !(0 != activate_threads_~tmp___1~0#1); 654#L865-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 202#L391-24true assume !(1 == ~t3_pc~0); 626#L391-26true is_transmit3_triggered_~__retres1~3#1 := 0; 404#L402-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 356#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 271#L873-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 248#L873-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 139#L410-24true assume 1 == ~t4_pc~0; 106#L411-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 379#L421-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 483#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 163#L881-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 80#L881-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 137#L429-24true assume !(1 == ~t5_pc~0); 588#L429-26true is_transmit5_triggered_~__retres1~5#1 := 0; 378#L440-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 249#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 108#L889-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 218#L889-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78#L448-24true assume !(1 == ~t6_pc~0); 608#L448-26true is_transmit6_triggered_~__retres1~6#1 := 0; 73#L459-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 169#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 510#L897-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 279#L897-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 501#L762-3true assume 1 == ~M_E~0;~M_E~0 := 2; 245#L762-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 572#L767-3true assume !(1 == ~T2_E~0); 660#L772-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 537#L777-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 68#L782-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 640#L787-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 386#L792-3true assume 1 == ~E_M~0;~E_M~0 := 2; 201#L797-3true assume 1 == ~E_1~0;~E_1~0 := 2; 444#L802-3true assume 1 == ~E_2~0;~E_2~0 := 2; 656#L807-3true assume !(1 == ~E_3~0); 309#L812-3true assume 1 == ~E_4~0;~E_4~0 := 2; 496#L817-3true assume 1 == ~E_5~0;~E_5~0 := 2; 396#L822-3true assume 1 == ~E_6~0;~E_6~0 := 2; 381#L827-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 216#L518-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 382#L555-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 294#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 613#L1072true assume !(0 == start_simulation_~tmp~3#1); 148#L1072-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 492#L518-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 74#L555-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 48#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 33#L1027true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 596#L1034true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 514#stop_simulation_returnLabel#1true start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 399#L1085true assume !(0 != start_simulation_~tmp___0~1#1); 158#L1053-2true [2022-12-13 14:56:56,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:56,382 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2022-12-13 14:56:56,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:56,390 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668132958] [2022-12-13 14:56:56,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:56,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:56,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:56,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:56,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:56,592 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1668132958] [2022-12-13 14:56:56,593 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1668132958] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:56,593 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:56,593 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:56,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652440646] [2022-12-13 14:56:56,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:56,598 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:56:56,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:56,599 INFO L85 PathProgramCache]: Analyzing trace with hash -1025957792, now seen corresponding path program 1 times [2022-12-13 14:56:56,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:56,599 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84374799] [2022-12-13 14:56:56,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:56,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:56,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:56,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:56,643 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:56,643 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [84374799] [2022-12-13 14:56:56,644 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [84374799] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:56,644 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:56,644 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 14:56:56,644 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1873634734] [2022-12-13 14:56:56,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:56,646 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:56:56,646 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:56:56,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:56:56,672 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:56:56,675 INFO L87 Difference]: Start difference. First operand has 687 states, 686 states have (on average 1.5233236151603498) internal successors, (1045), 686 states have internal predecessors, (1045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:56,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:56:56,723 INFO L93 Difference]: Finished difference Result 686 states and 1024 transitions. [2022-12-13 14:56:56,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1024 transitions. [2022-12-13 14:56:56,730 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-12-13 14:56:56,739 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 681 states and 1019 transitions. [2022-12-13 14:56:56,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2022-12-13 14:56:56,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2022-12-13 14:56:56,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1019 transitions. [2022-12-13 14:56:56,746 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:56:56,746 INFO L218 hiAutomatonCegarLoop]: Abstraction has 681 states and 1019 transitions. [2022-12-13 14:56:56,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1019 transitions. [2022-12-13 14:56:56,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2022-12-13 14:56:56,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4963289280469898) internal successors, (1019), 680 states have internal predecessors, (1019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:56,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1019 transitions. [2022-12-13 14:56:56,791 INFO L240 hiAutomatonCegarLoop]: Abstraction has 681 states and 1019 transitions. [2022-12-13 14:56:56,793 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:56:56,796 INFO L428 stractBuchiCegarLoop]: Abstraction has 681 states and 1019 transitions. [2022-12-13 14:56:56,796 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 14:56:56,797 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1019 transitions. [2022-12-13 14:56:56,800 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-12-13 14:56:56,800 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:56:56,801 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:56:56,803 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:56,803 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:56,803 INFO L748 eck$LassoCheckResult]: Stem: 1764#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1765#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1892#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1893#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1566#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1567#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1888#L480-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1889#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1819#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1620#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1621#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1544#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1545#L684 assume !(0 == ~M_E~0); 1990#L684-2 assume !(0 == ~T1_E~0); 1848#L689-1 assume !(0 == ~T2_E~0); 1849#L694-1 assume !(0 == ~T3_E~0); 1846#L699-1 assume !(0 == ~T4_E~0); 1847#L704-1 assume !(0 == ~T5_E~0); 1804#L709-1 assume !(0 == ~T6_E~0); 1742#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1743#L719-1 assume !(0 == ~E_1~0); 1965#L724-1 assume !(0 == ~E_2~0); 1516#L729-1 assume !(0 == ~E_3~0); 1517#L734-1 assume !(0 == ~E_4~0); 2016#L739-1 assume !(0 == ~E_5~0); 1704#L744-1 assume !(0 == ~E_6~0); 1705#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1473#L334 assume !(1 == ~m_pc~0); 1474#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1796#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1707#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1678#L849 assume !(0 != activate_threads_~tmp~1#1); 1679#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1617#L353 assume 1 == ~t1_pc~0; 1618#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1894#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1488#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1489#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1569#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1570#L372 assume !(1 == ~t2_pc~0); 1668#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1667#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1791#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1895#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1462#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1463#L391 assume 1 == ~t3_pc~0; 2001#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1387#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1411#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1412#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1682#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1683#L410 assume 1 == ~t4_pc~0; 2007#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1910#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1583#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1584#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1691#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1692#L429 assume !(1 == ~t5_pc~0); 1522#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1523#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1719#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1720#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1913#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1677#L448 assume 1 == ~t6_pc~0; 1557#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1558#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1880#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1881#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2035#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2060#L762 assume !(1 == ~M_E~0); 1723#L762-2 assume !(1 == ~T1_E~0); 1724#L767-1 assume !(1 == ~T2_E~0); 2040#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1941#L777-1 assume !(1 == ~T4_E~0); 1834#L782-1 assume !(1 == ~T5_E~0); 1548#L787-1 assume !(1 == ~T6_E~0); 1546#L792-1 assume !(1 == ~E_M~0); 1547#L797-1 assume !(1 == ~E_1~0); 1589#L802-1 assume !(1 == ~E_2~0); 1800#L807-1 assume !(1 == ~E_3~0); 1801#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2011#L817-1 assume !(1 == ~E_5~0); 1852#L822-1 assume !(1 == ~E_6~0); 1853#L827-1 assume { :end_inline_reset_delta_events } true; 1680#L1053-2 [2022-12-13 14:56:56,804 INFO L750 eck$LassoCheckResult]: Loop: 1680#L1053-2 assume !false; 1681#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1519#L659 assume !false; 1648#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1649#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1651#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1915#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1916#L570 assume !(0 != eval_~tmp~0#1); 1594#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1595#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1825#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1826#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1382#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1383#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1440#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1441#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1922#L709-3 assume !(0 == ~T6_E~0); 1907#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1716#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1433#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1434#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1885#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1928#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1929#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2009#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1447#L334-24 assume 1 == ~m_pc~0; 1448#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1587#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1612#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1419#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1420#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1925#L353-24 assume 1 == ~t1_pc~0; 1926#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1953#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2041#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2042#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1464#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1465#L372-24 assume 1 == ~t2_pc~0; 1426#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1427#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1778#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2028#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 2029#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1747#L391-24 assume 1 == ~t3_pc~0; 1748#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1966#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1923#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1835#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1810#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1647#L410-24 assume 1 == ~t4_pc~0; 1588#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1514#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1946#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1687#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1542#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1543#L429-24 assume 1 == ~t5_pc~0; 1643#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1839#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1811#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1592#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1593#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1537#L448-24 assume !(1 == ~t6_pc~0); 1538#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1531#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1532#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1698#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1842#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1843#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1808#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1809#L767-3 assume !(1 == ~T2_E~0); 2047#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2037#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1524#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1525#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1954#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1744#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1745#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1992#L807-3 assume !(1 == ~E_3~0); 1878#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1879#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1960#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1950#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1771#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1424#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1864#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1865#L1072 assume !(0 == start_simulation_~tmp~3#1); 1662#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1663#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1533#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1487#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1452#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1453#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2023#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1963#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1680#L1053-2 [2022-12-13 14:56:56,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:56,805 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2022-12-13 14:56:56,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:56,805 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127384322] [2022-12-13 14:56:56,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:56,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:56,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:56,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:56,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:56,869 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2127384322] [2022-12-13 14:56:56,869 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2127384322] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:56,869 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:56,870 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:56,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [979554614] [2022-12-13 14:56:56,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:56,870 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:56:56,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:56,871 INFO L85 PathProgramCache]: Analyzing trace with hash 1464043290, now seen corresponding path program 1 times [2022-12-13 14:56:56,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:56,871 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1182586844] [2022-12-13 14:56:56,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:56,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:56,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:56,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:56,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:56,945 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1182586844] [2022-12-13 14:56:56,946 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1182586844] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:56,946 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:56,946 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:56,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792936498] [2022-12-13 14:56:56,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:56,947 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:56:56,947 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:56:56,947 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:56:56,947 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:56:56,948 INFO L87 Difference]: Start difference. First operand 681 states and 1019 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:56,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:56:56,962 INFO L93 Difference]: Finished difference Result 681 states and 1018 transitions. [2022-12-13 14:56:56,963 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1018 transitions. [2022-12-13 14:56:56,965 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-12-13 14:56:56,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1018 transitions. [2022-12-13 14:56:56,968 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2022-12-13 14:56:56,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2022-12-13 14:56:56,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1018 transitions. [2022-12-13 14:56:56,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:56:56,972 INFO L218 hiAutomatonCegarLoop]: Abstraction has 681 states and 1018 transitions. [2022-12-13 14:56:56,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1018 transitions. [2022-12-13 14:56:56,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2022-12-13 14:56:56,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4948604992657857) internal successors, (1018), 680 states have internal predecessors, (1018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:56,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1018 transitions. [2022-12-13 14:56:56,990 INFO L240 hiAutomatonCegarLoop]: Abstraction has 681 states and 1018 transitions. [2022-12-13 14:56:56,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:56:56,991 INFO L428 stractBuchiCegarLoop]: Abstraction has 681 states and 1018 transitions. [2022-12-13 14:56:56,991 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 14:56:56,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1018 transitions. [2022-12-13 14:56:56,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-12-13 14:56:56,993 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:56:56,993 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:56:56,995 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:56,995 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:56,995 INFO L748 eck$LassoCheckResult]: Stem: 3131#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3132#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3259#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3260#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2933#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2934#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3257#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3258#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3188#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2989#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2990#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2911#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2912#L684 assume !(0 == ~M_E~0); 3359#L684-2 assume !(0 == ~T1_E~0); 3217#L689-1 assume !(0 == ~T2_E~0); 3218#L694-1 assume !(0 == ~T3_E~0); 3215#L699-1 assume !(0 == ~T4_E~0); 3216#L704-1 assume !(0 == ~T5_E~0); 3173#L709-1 assume !(0 == ~T6_E~0); 3111#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3112#L719-1 assume !(0 == ~E_1~0); 3334#L724-1 assume !(0 == ~E_2~0); 2885#L729-1 assume !(0 == ~E_3~0); 2886#L734-1 assume !(0 == ~E_4~0); 3385#L739-1 assume !(0 == ~E_5~0); 3073#L744-1 assume !(0 == ~E_6~0); 3074#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2842#L334 assume !(1 == ~m_pc~0); 2843#L334-2 is_master_triggered_~__retres1~0#1 := 0; 3165#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3075#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3047#L849 assume !(0 != activate_threads_~tmp~1#1); 3048#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2986#L353 assume 1 == ~t1_pc~0; 2987#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3263#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2857#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2858#L857 assume !(0 != activate_threads_~tmp___0~0#1); 2938#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2939#L372 assume !(1 == ~t2_pc~0); 3037#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3036#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3160#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3264#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2831#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2832#L391 assume 1 == ~t3_pc~0; 3368#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2756#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2780#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2781#L873 assume !(0 != activate_threads_~tmp___2~0#1); 3051#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3052#L410 assume 1 == ~t4_pc~0; 3375#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3278#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2952#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2953#L881 assume !(0 != activate_threads_~tmp___3~0#1); 3057#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3058#L429 assume !(1 == ~t5_pc~0); 2891#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2892#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3088#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3089#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3282#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3046#L448 assume 1 == ~t6_pc~0; 2926#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2927#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3247#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3248#L897 assume !(0 != activate_threads_~tmp___5~0#1); 3404#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3429#L762 assume !(1 == ~M_E~0); 3092#L762-2 assume !(1 == ~T1_E~0); 3093#L767-1 assume !(1 == ~T2_E~0); 3409#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3310#L777-1 assume !(1 == ~T4_E~0); 3203#L782-1 assume !(1 == ~T5_E~0); 2917#L787-1 assume !(1 == ~T6_E~0); 2915#L792-1 assume !(1 == ~E_M~0); 2916#L797-1 assume !(1 == ~E_1~0); 2957#L802-1 assume !(1 == ~E_2~0); 3169#L807-1 assume !(1 == ~E_3~0); 3170#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3380#L817-1 assume !(1 == ~E_5~0); 3219#L822-1 assume !(1 == ~E_6~0); 3220#L827-1 assume { :end_inline_reset_delta_events } true; 3049#L1053-2 [2022-12-13 14:56:57,003 INFO L750 eck$LassoCheckResult]: Loop: 3049#L1053-2 assume !false; 3050#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2888#L659 assume !false; 3017#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3018#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3020#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3284#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3285#L570 assume !(0 != eval_~tmp~0#1); 2963#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2964#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3192#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3193#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2751#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2752#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2809#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2810#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3291#L709-3 assume !(0 == ~T6_E~0); 3274#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3080#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2802#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2803#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3253#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3297#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3298#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3378#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2816#L334-24 assume 1 == ~m_pc~0; 2817#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2956#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2981#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2786#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2787#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3293#L353-24 assume 1 == ~t1_pc~0; 3294#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3322#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3410#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3411#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2833#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2834#L372-24 assume 1 == ~t2_pc~0; 2795#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2796#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3147#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3398#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 3399#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3116#L391-24 assume 1 == ~t3_pc~0; 3117#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3335#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3296#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3204#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3182#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3016#L410-24 assume !(1 == ~t4_pc~0); 2882#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 2883#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3315#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3056#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2913#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2914#L429-24 assume 1 == ~t5_pc~0; 3012#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3208#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3183#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2961#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2962#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2908#L448-24 assume !(1 == ~t6_pc~0); 2909#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 2900#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2901#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3067#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3211#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3212#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3177#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3178#L767-3 assume !(1 == ~T2_E~0); 3416#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3406#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2893#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2894#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3323#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3113#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3114#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3361#L807-3 assume !(1 == ~E_3~0); 3249#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3250#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3329#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3319#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3140#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2793#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3233#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3234#L1072 assume !(0 == start_simulation_~tmp~3#1); 3031#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3032#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2902#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2856#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 2823#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2824#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3392#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3332#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 3049#L1053-2 [2022-12-13 14:56:57,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:57,004 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2022-12-13 14:56:57,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:57,004 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934768370] [2022-12-13 14:56:57,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:57,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:57,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:57,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:57,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:57,047 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934768370] [2022-12-13 14:56:57,047 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934768370] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:57,047 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:57,048 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:57,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383823619] [2022-12-13 14:56:57,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:57,048 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:56:57,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:57,049 INFO L85 PathProgramCache]: Analyzing trace with hash 590565595, now seen corresponding path program 1 times [2022-12-13 14:56:57,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:57,049 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268971885] [2022-12-13 14:56:57,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:57,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:57,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:57,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:57,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:57,104 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268971885] [2022-12-13 14:56:57,105 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [268971885] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:57,105 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:57,105 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:57,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [460154491] [2022-12-13 14:56:57,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:57,106 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:56:57,106 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:56:57,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:56:57,106 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:56:57,107 INFO L87 Difference]: Start difference. First operand 681 states and 1018 transitions. cyclomatic complexity: 338 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:57,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:56:57,119 INFO L93 Difference]: Finished difference Result 681 states and 1017 transitions. [2022-12-13 14:56:57,119 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1017 transitions. [2022-12-13 14:56:57,121 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-12-13 14:56:57,123 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1017 transitions. [2022-12-13 14:56:57,123 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2022-12-13 14:56:57,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2022-12-13 14:56:57,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1017 transitions. [2022-12-13 14:56:57,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:56:57,125 INFO L218 hiAutomatonCegarLoop]: Abstraction has 681 states and 1017 transitions. [2022-12-13 14:56:57,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1017 transitions. [2022-12-13 14:56:57,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2022-12-13 14:56:57,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4933920704845816) internal successors, (1017), 680 states have internal predecessors, (1017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:57,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1017 transitions. [2022-12-13 14:56:57,134 INFO L240 hiAutomatonCegarLoop]: Abstraction has 681 states and 1017 transitions. [2022-12-13 14:56:57,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:56:57,135 INFO L428 stractBuchiCegarLoop]: Abstraction has 681 states and 1017 transitions. [2022-12-13 14:56:57,135 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 14:56:57,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1017 transitions. [2022-12-13 14:56:57,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-12-13 14:56:57,138 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:56:57,138 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:56:57,140 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:57,140 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:57,140 INFO L748 eck$LassoCheckResult]: Stem: 4500#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4628#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4629#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4302#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 4303#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4626#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4627#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4557#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4358#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4359#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4280#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4281#L684 assume !(0 == ~M_E~0); 4728#L684-2 assume !(0 == ~T1_E~0); 4586#L689-1 assume !(0 == ~T2_E~0); 4587#L694-1 assume !(0 == ~T3_E~0); 4584#L699-1 assume !(0 == ~T4_E~0); 4585#L704-1 assume !(0 == ~T5_E~0); 4542#L709-1 assume !(0 == ~T6_E~0); 4480#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4481#L719-1 assume !(0 == ~E_1~0); 4703#L724-1 assume !(0 == ~E_2~0); 4254#L729-1 assume !(0 == ~E_3~0); 4255#L734-1 assume !(0 == ~E_4~0); 4754#L739-1 assume !(0 == ~E_5~0); 4442#L744-1 assume !(0 == ~E_6~0); 4443#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4211#L334 assume !(1 == ~m_pc~0); 4212#L334-2 is_master_triggered_~__retres1~0#1 := 0; 4534#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4444#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4416#L849 assume !(0 != activate_threads_~tmp~1#1); 4417#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4355#L353 assume 1 == ~t1_pc~0; 4356#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4632#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4226#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4227#L857 assume !(0 != activate_threads_~tmp___0~0#1); 4307#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4308#L372 assume !(1 == ~t2_pc~0); 4406#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4405#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4529#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4633#L865 assume !(0 != activate_threads_~tmp___1~0#1); 4200#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4201#L391 assume 1 == ~t3_pc~0; 4737#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4125#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4149#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4150#L873 assume !(0 != activate_threads_~tmp___2~0#1); 4420#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4421#L410 assume 1 == ~t4_pc~0; 4745#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4647#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4321#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4322#L881 assume !(0 != activate_threads_~tmp___3~0#1); 4426#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4427#L429 assume !(1 == ~t5_pc~0); 4260#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4261#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4457#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4458#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4651#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4415#L448 assume 1 == ~t6_pc~0; 4295#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4296#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4616#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4617#L897 assume !(0 != activate_threads_~tmp___5~0#1); 4773#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4798#L762 assume !(1 == ~M_E~0); 4461#L762-2 assume !(1 == ~T1_E~0); 4462#L767-1 assume !(1 == ~T2_E~0); 4778#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4679#L777-1 assume !(1 == ~T4_E~0); 4572#L782-1 assume !(1 == ~T5_E~0); 4286#L787-1 assume !(1 == ~T6_E~0); 4284#L792-1 assume !(1 == ~E_M~0); 4285#L797-1 assume !(1 == ~E_1~0); 4326#L802-1 assume !(1 == ~E_2~0); 4538#L807-1 assume !(1 == ~E_3~0); 4539#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4749#L817-1 assume !(1 == ~E_5~0); 4590#L822-1 assume !(1 == ~E_6~0); 4591#L827-1 assume { :end_inline_reset_delta_events } true; 4418#L1053-2 [2022-12-13 14:56:57,141 INFO L750 eck$LassoCheckResult]: Loop: 4418#L1053-2 assume !false; 4419#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4257#L659 assume !false; 4386#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4387#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4389#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4653#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4654#L570 assume !(0 != eval_~tmp~0#1); 4332#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4333#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4563#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4564#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4120#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4121#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4178#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4179#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4660#L709-3 assume !(0 == ~T6_E~0); 4643#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4449#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4171#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4172#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4622#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4666#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4667#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4747#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4185#L334-24 assume 1 == ~m_pc~0; 4186#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4325#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4350#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4155#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4156#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4662#L353-24 assume 1 == ~t1_pc~0; 4663#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4691#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4779#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4780#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4202#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4203#L372-24 assume 1 == ~t2_pc~0; 4164#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4165#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4516#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4767#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 4768#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4485#L391-24 assume 1 == ~t3_pc~0; 4486#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4704#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4665#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4573#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4551#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4385#L410-24 assume 1 == ~t4_pc~0; 4327#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4252#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4684#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4425#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4282#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4283#L429-24 assume 1 == ~t5_pc~0; 4381#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4577#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4552#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4330#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4331#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4277#L448-24 assume !(1 == ~t6_pc~0); 4278#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 4269#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4270#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4436#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4580#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4581#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4546#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4547#L767-3 assume !(1 == ~T2_E~0); 4785#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4775#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4262#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4263#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4692#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4482#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4483#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4730#L807-3 assume !(1 == ~E_3~0); 4618#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4619#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4698#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4688#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4509#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4162#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4602#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4603#L1072 assume !(0 == start_simulation_~tmp~3#1); 4400#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4401#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4271#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4225#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 4192#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4193#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4761#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4701#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 4418#L1053-2 [2022-12-13 14:56:57,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:57,141 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2022-12-13 14:56:57,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:57,141 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919906326] [2022-12-13 14:56:57,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:57,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:57,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:57,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:57,176 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:57,176 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919906326] [2022-12-13 14:56:57,176 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [919906326] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:57,177 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:57,177 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:57,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854867406] [2022-12-13 14:56:57,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:57,177 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:56:57,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:57,178 INFO L85 PathProgramCache]: Analyzing trace with hash 1464043290, now seen corresponding path program 2 times [2022-12-13 14:56:57,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:57,178 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510537585] [2022-12-13 14:56:57,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:57,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:57,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:57,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:57,225 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:57,225 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [510537585] [2022-12-13 14:56:57,225 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [510537585] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:57,225 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:57,226 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:57,226 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1030699293] [2022-12-13 14:56:57,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:57,226 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:56:57,226 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:56:57,227 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:56:57,227 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:56:57,227 INFO L87 Difference]: Start difference. First operand 681 states and 1017 transitions. cyclomatic complexity: 337 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:57,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:56:57,246 INFO L93 Difference]: Finished difference Result 681 states and 1016 transitions. [2022-12-13 14:56:57,246 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1016 transitions. [2022-12-13 14:56:57,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-12-13 14:56:57,253 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1016 transitions. [2022-12-13 14:56:57,253 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2022-12-13 14:56:57,254 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2022-12-13 14:56:57,254 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1016 transitions. [2022-12-13 14:56:57,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:56:57,255 INFO L218 hiAutomatonCegarLoop]: Abstraction has 681 states and 1016 transitions. [2022-12-13 14:56:57,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1016 transitions. [2022-12-13 14:56:57,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2022-12-13 14:56:57,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4919236417033774) internal successors, (1016), 680 states have internal predecessors, (1016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:57,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1016 transitions. [2022-12-13 14:56:57,267 INFO L240 hiAutomatonCegarLoop]: Abstraction has 681 states and 1016 transitions. [2022-12-13 14:56:57,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:56:57,268 INFO L428 stractBuchiCegarLoop]: Abstraction has 681 states and 1016 transitions. [2022-12-13 14:56:57,268 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 14:56:57,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1016 transitions. [2022-12-13 14:56:57,270 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-12-13 14:56:57,270 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:56:57,270 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:56:57,271 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:57,271 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:57,272 INFO L748 eck$LassoCheckResult]: Stem: 5871#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5872#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5999#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6000#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5673#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 5674#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5995#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5996#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5926#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5727#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5728#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5651#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5652#L684 assume !(0 == ~M_E~0); 6097#L684-2 assume !(0 == ~T1_E~0); 5955#L689-1 assume !(0 == ~T2_E~0); 5956#L694-1 assume !(0 == ~T3_E~0); 5953#L699-1 assume !(0 == ~T4_E~0); 5954#L704-1 assume !(0 == ~T5_E~0); 5911#L709-1 assume !(0 == ~T6_E~0); 5849#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 5850#L719-1 assume !(0 == ~E_1~0); 6072#L724-1 assume !(0 == ~E_2~0); 5623#L729-1 assume !(0 == ~E_3~0); 5624#L734-1 assume !(0 == ~E_4~0); 6123#L739-1 assume !(0 == ~E_5~0); 5811#L744-1 assume !(0 == ~E_6~0); 5812#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5580#L334 assume !(1 == ~m_pc~0); 5581#L334-2 is_master_triggered_~__retres1~0#1 := 0; 5903#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5814#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5785#L849 assume !(0 != activate_threads_~tmp~1#1); 5786#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5724#L353 assume 1 == ~t1_pc~0; 5725#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6001#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5595#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5596#L857 assume !(0 != activate_threads_~tmp___0~0#1); 5676#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5677#L372 assume !(1 == ~t2_pc~0); 5775#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5774#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5898#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6002#L865 assume !(0 != activate_threads_~tmp___1~0#1); 5569#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5570#L391 assume 1 == ~t3_pc~0; 6108#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5494#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5518#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5519#L873 assume !(0 != activate_threads_~tmp___2~0#1); 5789#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5790#L410 assume 1 == ~t4_pc~0; 6114#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6017#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5690#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5691#L881 assume !(0 != activate_threads_~tmp___3~0#1); 5798#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5799#L429 assume !(1 == ~t5_pc~0); 5629#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5630#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5826#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5827#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6020#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5784#L448 assume 1 == ~t6_pc~0; 5664#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5665#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5987#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5988#L897 assume !(0 != activate_threads_~tmp___5~0#1); 6142#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6167#L762 assume !(1 == ~M_E~0); 5830#L762-2 assume !(1 == ~T1_E~0); 5831#L767-1 assume !(1 == ~T2_E~0); 6147#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6048#L777-1 assume !(1 == ~T4_E~0); 5941#L782-1 assume !(1 == ~T5_E~0); 5655#L787-1 assume !(1 == ~T6_E~0); 5653#L792-1 assume !(1 == ~E_M~0); 5654#L797-1 assume !(1 == ~E_1~0); 5696#L802-1 assume !(1 == ~E_2~0); 5907#L807-1 assume !(1 == ~E_3~0); 5908#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6118#L817-1 assume !(1 == ~E_5~0); 5959#L822-1 assume !(1 == ~E_6~0); 5960#L827-1 assume { :end_inline_reset_delta_events } true; 5787#L1053-2 [2022-12-13 14:56:57,272 INFO L750 eck$LassoCheckResult]: Loop: 5787#L1053-2 assume !false; 5788#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5626#L659 assume !false; 5755#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5756#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5758#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6022#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6023#L570 assume !(0 != eval_~tmp~0#1); 5701#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5702#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5932#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5933#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5489#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5490#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5547#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5548#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6029#L709-3 assume !(0 == ~T6_E~0); 6014#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5823#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5540#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5541#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5992#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6035#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6036#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6116#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5554#L334-24 assume 1 == ~m_pc~0; 5555#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5694#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5719#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5526#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5527#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6030#L353-24 assume !(1 == ~t1_pc~0); 6032#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 6060#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6148#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6149#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5571#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5572#L372-24 assume 1 == ~t2_pc~0; 5533#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5534#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5885#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6135#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 6136#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5854#L391-24 assume !(1 == ~t3_pc~0); 5856#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 6073#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6033#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5942#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5917#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5754#L410-24 assume !(1 == ~t4_pc~0); 5620#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 5621#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6053#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5794#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5649#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5650#L429-24 assume 1 == ~t5_pc~0; 5750#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5946#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5918#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5699#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5700#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5644#L448-24 assume !(1 == ~t6_pc~0); 5645#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 5638#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5639#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5805#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5949#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5950#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5915#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5916#L767-3 assume !(1 == ~T2_E~0); 6154#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6144#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5631#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5632#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6061#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5851#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5852#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6099#L807-3 assume !(1 == ~E_3~0); 5985#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5986#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6067#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6057#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5878#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5531#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5971#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 5972#L1072 assume !(0 == start_simulation_~tmp~3#1); 5769#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5770#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5640#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5594#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 5559#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5560#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6130#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6070#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 5787#L1053-2 [2022-12-13 14:56:57,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:57,273 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2022-12-13 14:56:57,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:57,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431213202] [2022-12-13 14:56:57,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:57,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:57,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:57,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:57,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:57,302 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431213202] [2022-12-13 14:56:57,303 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431213202] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:57,303 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:57,303 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:57,303 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1603401477] [2022-12-13 14:56:57,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:57,303 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:56:57,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:57,304 INFO L85 PathProgramCache]: Analyzing trace with hash -933346979, now seen corresponding path program 1 times [2022-12-13 14:56:57,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:57,304 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1275456328] [2022-12-13 14:56:57,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:57,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:57,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:57,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:57,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:57,337 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1275456328] [2022-12-13 14:56:57,338 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1275456328] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:57,338 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:57,338 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:57,338 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1075972592] [2022-12-13 14:56:57,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:57,344 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:56:57,344 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:56:57,345 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:56:57,345 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:56:57,345 INFO L87 Difference]: Start difference. First operand 681 states and 1016 transitions. cyclomatic complexity: 336 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:57,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:56:57,357 INFO L93 Difference]: Finished difference Result 681 states and 1015 transitions. [2022-12-13 14:56:57,357 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1015 transitions. [2022-12-13 14:56:57,360 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-12-13 14:56:57,362 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1015 transitions. [2022-12-13 14:56:57,362 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2022-12-13 14:56:57,362 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2022-12-13 14:56:57,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1015 transitions. [2022-12-13 14:56:57,363 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:56:57,363 INFO L218 hiAutomatonCegarLoop]: Abstraction has 681 states and 1015 transitions. [2022-12-13 14:56:57,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1015 transitions. [2022-12-13 14:56:57,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2022-12-13 14:56:57,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4904552129221733) internal successors, (1015), 680 states have internal predecessors, (1015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:57,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1015 transitions. [2022-12-13 14:56:57,370 INFO L240 hiAutomatonCegarLoop]: Abstraction has 681 states and 1015 transitions. [2022-12-13 14:56:57,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:56:57,371 INFO L428 stractBuchiCegarLoop]: Abstraction has 681 states and 1015 transitions. [2022-12-13 14:56:57,371 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 14:56:57,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1015 transitions. [2022-12-13 14:56:57,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-12-13 14:56:57,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:56:57,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:56:57,374 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:57,374 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:57,374 INFO L748 eck$LassoCheckResult]: Stem: 7238#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7239#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7366#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7367#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7040#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 7041#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7364#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7365#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7295#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7096#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7097#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7018#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7019#L684 assume !(0 == ~M_E~0); 7466#L684-2 assume !(0 == ~T1_E~0); 7324#L689-1 assume !(0 == ~T2_E~0); 7325#L694-1 assume !(0 == ~T3_E~0); 7322#L699-1 assume !(0 == ~T4_E~0); 7323#L704-1 assume !(0 == ~T5_E~0); 7280#L709-1 assume !(0 == ~T6_E~0); 7218#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7219#L719-1 assume !(0 == ~E_1~0); 7441#L724-1 assume !(0 == ~E_2~0); 6992#L729-1 assume !(0 == ~E_3~0); 6993#L734-1 assume !(0 == ~E_4~0); 7492#L739-1 assume !(0 == ~E_5~0); 7180#L744-1 assume !(0 == ~E_6~0); 7181#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6949#L334 assume !(1 == ~m_pc~0); 6950#L334-2 is_master_triggered_~__retres1~0#1 := 0; 7272#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7182#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7154#L849 assume !(0 != activate_threads_~tmp~1#1); 7155#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7093#L353 assume 1 == ~t1_pc~0; 7094#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7370#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6964#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6965#L857 assume !(0 != activate_threads_~tmp___0~0#1); 7045#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7046#L372 assume !(1 == ~t2_pc~0); 7144#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7143#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7267#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7371#L865 assume !(0 != activate_threads_~tmp___1~0#1); 6938#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6939#L391 assume 1 == ~t3_pc~0; 7475#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6863#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6887#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6888#L873 assume !(0 != activate_threads_~tmp___2~0#1); 7158#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7159#L410 assume 1 == ~t4_pc~0; 7482#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7385#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7059#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7060#L881 assume !(0 != activate_threads_~tmp___3~0#1); 7164#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7165#L429 assume !(1 == ~t5_pc~0); 6998#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6999#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7195#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7196#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7389#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7153#L448 assume 1 == ~t6_pc~0; 7033#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7034#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7354#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7355#L897 assume !(0 != activate_threads_~tmp___5~0#1); 7511#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7536#L762 assume !(1 == ~M_E~0); 7199#L762-2 assume !(1 == ~T1_E~0); 7200#L767-1 assume !(1 == ~T2_E~0); 7516#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7417#L777-1 assume !(1 == ~T4_E~0); 7310#L782-1 assume !(1 == ~T5_E~0); 7024#L787-1 assume !(1 == ~T6_E~0); 7022#L792-1 assume !(1 == ~E_M~0); 7023#L797-1 assume !(1 == ~E_1~0); 7064#L802-1 assume !(1 == ~E_2~0); 7276#L807-1 assume !(1 == ~E_3~0); 7277#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7487#L817-1 assume !(1 == ~E_5~0); 7326#L822-1 assume !(1 == ~E_6~0); 7327#L827-1 assume { :end_inline_reset_delta_events } true; 7156#L1053-2 [2022-12-13 14:56:57,375 INFO L750 eck$LassoCheckResult]: Loop: 7156#L1053-2 assume !false; 7157#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6995#L659 assume !false; 7124#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7125#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7127#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7391#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7392#L570 assume !(0 != eval_~tmp~0#1); 7070#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7071#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7299#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7300#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6858#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6859#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6916#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6917#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7398#L709-3 assume !(0 == ~T6_E~0); 7381#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7187#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6909#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6910#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7360#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7404#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7405#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7485#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6923#L334-24 assume 1 == ~m_pc~0; 6924#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7063#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7088#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6893#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6894#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7400#L353-24 assume 1 == ~t1_pc~0; 7401#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7429#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7517#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7518#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6940#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6941#L372-24 assume 1 == ~t2_pc~0; 6902#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6903#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7254#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7505#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 7506#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7223#L391-24 assume 1 == ~t3_pc~0; 7224#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7442#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7403#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7311#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7289#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7123#L410-24 assume 1 == ~t4_pc~0; 7065#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6990#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7422#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7163#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7020#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7021#L429-24 assume !(1 == ~t5_pc~0); 7120#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 7315#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7290#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7068#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7069#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7015#L448-24 assume !(1 == ~t6_pc~0); 7016#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 7007#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7008#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7174#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7318#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7319#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7284#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7285#L767-3 assume !(1 == ~T2_E~0); 7523#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7513#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7000#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7001#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7430#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7220#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7221#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7468#L807-3 assume !(1 == ~E_3~0); 7356#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7357#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7436#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7426#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7247#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6900#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7340#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7341#L1072 assume !(0 == start_simulation_~tmp~3#1); 7138#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7139#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7009#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6963#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 6930#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6931#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7499#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 7439#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 7156#L1053-2 [2022-12-13 14:56:57,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:57,375 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2022-12-13 14:56:57,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:57,375 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674218806] [2022-12-13 14:56:57,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:57,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:57,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:57,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:57,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:57,397 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [674218806] [2022-12-13 14:56:57,397 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [674218806] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:57,397 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:57,397 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:57,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [130961971] [2022-12-13 14:56:57,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:57,398 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:56:57,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:57,398 INFO L85 PathProgramCache]: Analyzing trace with hash 507114907, now seen corresponding path program 1 times [2022-12-13 14:56:57,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:57,399 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417026581] [2022-12-13 14:56:57,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:57,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:57,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:57,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:57,428 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:57,428 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1417026581] [2022-12-13 14:56:57,428 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1417026581] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:57,428 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:57,428 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:57,428 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [275664894] [2022-12-13 14:56:57,428 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:57,429 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:56:57,429 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:56:57,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:56:57,429 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:56:57,430 INFO L87 Difference]: Start difference. First operand 681 states and 1015 transitions. cyclomatic complexity: 335 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:57,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:56:57,441 INFO L93 Difference]: Finished difference Result 681 states and 1014 transitions. [2022-12-13 14:56:57,441 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 681 states and 1014 transitions. [2022-12-13 14:56:57,443 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-12-13 14:56:57,445 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 681 states to 681 states and 1014 transitions. [2022-12-13 14:56:57,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 681 [2022-12-13 14:56:57,445 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 681 [2022-12-13 14:56:57,445 INFO L73 IsDeterministic]: Start isDeterministic. Operand 681 states and 1014 transitions. [2022-12-13 14:56:57,446 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:56:57,446 INFO L218 hiAutomatonCegarLoop]: Abstraction has 681 states and 1014 transitions. [2022-12-13 14:56:57,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states and 1014 transitions. [2022-12-13 14:56:57,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 681. [2022-12-13 14:56:57,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 681 states, 681 states have (on average 1.4889867841409692) internal successors, (1014), 680 states have internal predecessors, (1014), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:57,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 1014 transitions. [2022-12-13 14:56:57,453 INFO L240 hiAutomatonCegarLoop]: Abstraction has 681 states and 1014 transitions. [2022-12-13 14:56:57,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:56:57,454 INFO L428 stractBuchiCegarLoop]: Abstraction has 681 states and 1014 transitions. [2022-12-13 14:56:57,454 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 14:56:57,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 681 states and 1014 transitions. [2022-12-13 14:56:57,457 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 590 [2022-12-13 14:56:57,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:56:57,457 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:56:57,458 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:57,458 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:57,458 INFO L748 eck$LassoCheckResult]: Stem: 8607#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8608#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8735#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8736#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8409#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 8410#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8733#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8734#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8664#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8465#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8466#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8387#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8388#L684 assume !(0 == ~M_E~0); 8835#L684-2 assume !(0 == ~T1_E~0); 8693#L689-1 assume !(0 == ~T2_E~0); 8694#L694-1 assume !(0 == ~T3_E~0); 8691#L699-1 assume !(0 == ~T4_E~0); 8692#L704-1 assume !(0 == ~T5_E~0); 8649#L709-1 assume !(0 == ~T6_E~0); 8587#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8588#L719-1 assume !(0 == ~E_1~0); 8810#L724-1 assume !(0 == ~E_2~0); 8361#L729-1 assume !(0 == ~E_3~0); 8362#L734-1 assume !(0 == ~E_4~0); 8861#L739-1 assume !(0 == ~E_5~0); 8549#L744-1 assume !(0 == ~E_6~0); 8550#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8318#L334 assume !(1 == ~m_pc~0); 8319#L334-2 is_master_triggered_~__retres1~0#1 := 0; 8641#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8551#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8523#L849 assume !(0 != activate_threads_~tmp~1#1); 8524#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8462#L353 assume 1 == ~t1_pc~0; 8463#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8739#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8333#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8334#L857 assume !(0 != activate_threads_~tmp___0~0#1); 8414#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8415#L372 assume !(1 == ~t2_pc~0); 8513#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8512#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8636#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8740#L865 assume !(0 != activate_threads_~tmp___1~0#1); 8307#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8308#L391 assume 1 == ~t3_pc~0; 8844#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8232#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8256#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8257#L873 assume !(0 != activate_threads_~tmp___2~0#1); 8527#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8528#L410 assume 1 == ~t4_pc~0; 8852#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8754#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8428#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8429#L881 assume !(0 != activate_threads_~tmp___3~0#1); 8533#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8534#L429 assume !(1 == ~t5_pc~0); 8367#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8368#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8564#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8565#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8758#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8522#L448 assume 1 == ~t6_pc~0; 8402#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8403#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8723#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8724#L897 assume !(0 != activate_threads_~tmp___5~0#1); 8880#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8905#L762 assume !(1 == ~M_E~0); 8568#L762-2 assume !(1 == ~T1_E~0); 8569#L767-1 assume !(1 == ~T2_E~0); 8885#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8786#L777-1 assume !(1 == ~T4_E~0); 8679#L782-1 assume !(1 == ~T5_E~0); 8393#L787-1 assume !(1 == ~T6_E~0); 8391#L792-1 assume !(1 == ~E_M~0); 8392#L797-1 assume !(1 == ~E_1~0); 8433#L802-1 assume !(1 == ~E_2~0); 8645#L807-1 assume !(1 == ~E_3~0); 8646#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8856#L817-1 assume !(1 == ~E_5~0); 8697#L822-1 assume !(1 == ~E_6~0); 8698#L827-1 assume { :end_inline_reset_delta_events } true; 8525#L1053-2 [2022-12-13 14:56:57,458 INFO L750 eck$LassoCheckResult]: Loop: 8525#L1053-2 assume !false; 8526#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8364#L659 assume !false; 8493#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8494#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8496#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8760#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8761#L570 assume !(0 != eval_~tmp~0#1); 8439#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8440#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8670#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8671#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8227#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8228#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8285#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8286#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8767#L709-3 assume !(0 == ~T6_E~0); 8750#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8556#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8278#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8279#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8729#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8773#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8774#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8854#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8292#L334-24 assume 1 == ~m_pc~0; 8293#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8432#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8457#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8262#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8263#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8769#L353-24 assume 1 == ~t1_pc~0; 8770#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8798#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8886#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8887#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8309#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8310#L372-24 assume !(1 == ~t2_pc~0); 8273#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 8272#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8623#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8874#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 8875#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8592#L391-24 assume 1 == ~t3_pc~0; 8593#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8811#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8772#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8680#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8658#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8492#L410-24 assume 1 == ~t4_pc~0; 8434#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8359#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8791#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8532#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8389#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8390#L429-24 assume 1 == ~t5_pc~0; 8488#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8684#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8659#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8437#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8438#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8384#L448-24 assume !(1 == ~t6_pc~0); 8385#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 8376#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8377#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8543#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8687#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8688#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8653#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8654#L767-3 assume !(1 == ~T2_E~0); 8892#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8882#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8369#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8370#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8799#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8589#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8590#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8837#L807-3 assume !(1 == ~E_3~0); 8725#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8726#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8805#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8795#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8616#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8269#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8709#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 8710#L1072 assume !(0 == start_simulation_~tmp~3#1); 8507#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8508#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8378#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8332#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 8299#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8300#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8868#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8808#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 8525#L1053-2 [2022-12-13 14:56:57,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:57,458 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2022-12-13 14:56:57,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:57,459 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104524681] [2022-12-13 14:56:57,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:57,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:57,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:57,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:57,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:57,510 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2104524681] [2022-12-13 14:56:57,510 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2104524681] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:57,510 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:57,510 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:57,510 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [952547360] [2022-12-13 14:56:57,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:57,510 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:56:57,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:57,510 INFO L85 PathProgramCache]: Analyzing trace with hash 1704310619, now seen corresponding path program 1 times [2022-12-13 14:56:57,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:57,511 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333234997] [2022-12-13 14:56:57,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:57,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:57,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:57,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:57,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:57,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333234997] [2022-12-13 14:56:57,546 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333234997] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:57,546 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:57,546 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:57,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467816118] [2022-12-13 14:56:57,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:57,547 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:56:57,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:56:57,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:56:57,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:56:57,548 INFO L87 Difference]: Start difference. First operand 681 states and 1014 transitions. cyclomatic complexity: 334 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:57,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:56:57,673 INFO L93 Difference]: Finished difference Result 1170 states and 1738 transitions. [2022-12-13 14:56:57,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1738 transitions. [2022-12-13 14:56:57,679 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1064 [2022-12-13 14:56:57,682 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1738 transitions. [2022-12-13 14:56:57,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-12-13 14:56:57,683 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-12-13 14:56:57,683 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1738 transitions. [2022-12-13 14:56:57,684 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:56:57,684 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2022-12-13 14:56:57,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1738 transitions. [2022-12-13 14:56:57,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1169. [2022-12-13 14:56:57,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1169 states, 1169 states have (on average 1.485885372112917) internal successors, (1737), 1168 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:57,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1169 states to 1169 states and 1737 transitions. [2022-12-13 14:56:57,720 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1169 states and 1737 transitions. [2022-12-13 14:56:57,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:56:57,721 INFO L428 stractBuchiCegarLoop]: Abstraction has 1169 states and 1737 transitions. [2022-12-13 14:56:57,721 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 14:56:57,721 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1169 states and 1737 transitions. [2022-12-13 14:56:57,729 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1064 [2022-12-13 14:56:57,729 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:56:57,729 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:56:57,730 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:57,730 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:57,731 INFO L748 eck$LassoCheckResult]: Stem: 10468#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10469#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10600#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10601#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10270#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 10271#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10598#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10599#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10525#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10326#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10327#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10248#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10249#L684 assume !(0 == ~M_E~0); 10704#L684-2 assume !(0 == ~T1_E~0); 10556#L689-1 assume !(0 == ~T2_E~0); 10557#L694-1 assume !(0 == ~T3_E~0); 10554#L699-1 assume !(0 == ~T4_E~0); 10555#L704-1 assume !(0 == ~T5_E~0); 10510#L709-1 assume !(0 == ~T6_E~0); 10448#L714-1 assume !(0 == ~E_M~0); 10449#L719-1 assume !(0 == ~E_1~0); 10677#L724-1 assume !(0 == ~E_2~0); 10222#L729-1 assume !(0 == ~E_3~0); 10223#L734-1 assume !(0 == ~E_4~0); 10733#L739-1 assume !(0 == ~E_5~0); 10410#L744-1 assume !(0 == ~E_6~0); 10411#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10179#L334 assume !(1 == ~m_pc~0); 10180#L334-2 is_master_triggered_~__retres1~0#1 := 0; 10502#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10412#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10384#L849 assume !(0 != activate_threads_~tmp~1#1); 10385#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10323#L353 assume 1 == ~t1_pc~0; 10324#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10604#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10194#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10195#L857 assume !(0 != activate_threads_~tmp___0~0#1); 10275#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10276#L372 assume !(1 == ~t2_pc~0); 10374#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10373#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10497#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10605#L865 assume !(0 != activate_threads_~tmp___1~0#1); 10168#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10169#L391 assume 1 == ~t3_pc~0; 10713#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10093#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10117#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10118#L873 assume !(0 != activate_threads_~tmp___2~0#1); 10388#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10389#L410 assume 1 == ~t4_pc~0; 10722#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10619#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10289#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10290#L881 assume !(0 != activate_threads_~tmp___3~0#1); 10394#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10395#L429 assume !(1 == ~t5_pc~0); 10228#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10229#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10425#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10426#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10624#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10383#L448 assume 1 == ~t6_pc~0; 10263#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10264#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10588#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10589#L897 assume !(0 != activate_threads_~tmp___5~0#1); 10754#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10786#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 10429#L762-2 assume !(1 == ~T1_E~0); 10430#L767-1 assume !(1 == ~T2_E~0); 10759#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10652#L777-1 assume !(1 == ~T4_E~0); 10542#L782-1 assume !(1 == ~T5_E~0); 10254#L787-1 assume !(1 == ~T6_E~0); 10252#L792-1 assume !(1 == ~E_M~0); 10253#L797-1 assume !(1 == ~E_1~0); 10294#L802-1 assume !(1 == ~E_2~0); 10506#L807-1 assume !(1 == ~E_3~0); 10507#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10728#L817-1 assume !(1 == ~E_5~0); 10784#L822-1 assume !(1 == ~E_6~0); 10736#L827-1 assume { :end_inline_reset_delta_events } true; 10675#L1053-2 [2022-12-13 14:56:57,731 INFO L750 eck$LassoCheckResult]: Loop: 10675#L1053-2 assume !false; 10724#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10225#L659 assume !false; 10354#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10355#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10796#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10795#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10793#L570 assume !(0 != eval_~tmp~0#1); 10792#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10791#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10790#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10696#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10088#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10089#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10146#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10147#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10633#L709-3 assume !(0 == ~T6_E~0); 10615#L714-3 assume !(0 == ~E_M~0); 10417#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10139#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10140#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10594#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10639#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10640#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10726#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10153#L334-24 assume 1 == ~m_pc~0; 10154#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10293#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10318#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10123#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10124#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10635#L353-24 assume 1 == ~t1_pc~0; 10636#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10664#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10760#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10761#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10170#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10171#L372-24 assume 1 == ~t2_pc~0; 10132#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10133#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10484#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10748#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 10749#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10453#L391-24 assume 1 == ~t3_pc~0; 10454#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10678#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10638#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10543#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10519#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10353#L410-24 assume 1 == ~t4_pc~0; 10295#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10220#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10657#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10393#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10250#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10251#L429-24 assume 1 == ~t5_pc~0; 10349#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10547#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10520#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10298#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10299#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10245#L448-24 assume !(1 == ~t6_pc~0); 10246#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 10237#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10238#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10404#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10550#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10551#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10514#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10515#L767-3 assume !(1 == ~T2_E~0); 10770#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10756#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10230#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10231#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10665#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10450#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10451#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10706#L807-3 assume !(1 == ~E_3~0); 10590#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10591#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10671#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10661#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10477#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10130#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10572#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 10573#L1072 assume !(0 == start_simulation_~tmp~3#1); 10368#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10369#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10239#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10193#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 10160#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10161#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10741#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 10674#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 10675#L1053-2 [2022-12-13 14:56:57,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:57,731 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2022-12-13 14:56:57,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:57,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [922083720] [2022-12-13 14:56:57,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:57,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:57,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:57,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:57,786 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:57,786 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [922083720] [2022-12-13 14:56:57,787 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [922083720] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:57,787 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:57,787 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:57,787 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1869275046] [2022-12-13 14:56:57,787 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:57,787 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:56:57,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:57,788 INFO L85 PathProgramCache]: Analyzing trace with hash 1491108892, now seen corresponding path program 1 times [2022-12-13 14:56:57,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:57,788 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [887045114] [2022-12-13 14:56:57,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:57,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:57,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:57,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:57,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:57,827 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [887045114] [2022-12-13 14:56:57,827 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [887045114] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:57,828 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:57,828 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:57,828 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [121996965] [2022-12-13 14:56:57,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:57,828 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:56:57,828 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:56:57,829 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:56:57,829 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:56:57,829 INFO L87 Difference]: Start difference. First operand 1169 states and 1737 transitions. cyclomatic complexity: 570 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:57,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:56:57,993 INFO L93 Difference]: Finished difference Result 3123 states and 4559 transitions. [2022-12-13 14:56:57,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3123 states and 4559 transitions. [2022-12-13 14:56:58,011 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2908 [2022-12-13 14:56:58,025 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3123 states to 3123 states and 4559 transitions. [2022-12-13 14:56:58,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3123 [2022-12-13 14:56:58,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3123 [2022-12-13 14:56:58,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3123 states and 4559 transitions. [2022-12-13 14:56:58,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:56:58,033 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3123 states and 4559 transitions. [2022-12-13 14:56:58,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3123 states and 4559 transitions. [2022-12-13 14:56:58,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3123 to 2935. [2022-12-13 14:56:58,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2935 states, 2935 states have (on average 1.466098807495741) internal successors, (4303), 2934 states have internal predecessors, (4303), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:58,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2935 states to 2935 states and 4303 transitions. [2022-12-13 14:56:58,074 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2935 states and 4303 transitions. [2022-12-13 14:56:58,075 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:56:58,075 INFO L428 stractBuchiCegarLoop]: Abstraction has 2935 states and 4303 transitions. [2022-12-13 14:56:58,075 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 14:56:58,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2935 states and 4303 transitions. [2022-12-13 14:56:58,088 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2822 [2022-12-13 14:56:58,089 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:56:58,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:56:58,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:58,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:58,090 INFO L748 eck$LassoCheckResult]: Stem: 14801#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 14802#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 14959#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14960#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14576#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 14577#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14957#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14958#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14866#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14635#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14636#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14554#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14555#L684 assume !(0 == ~M_E~0); 15099#L684-2 assume !(0 == ~T1_E~0); 14904#L689-1 assume !(0 == ~T2_E~0); 14905#L694-1 assume !(0 == ~T3_E~0); 14902#L699-1 assume !(0 == ~T4_E~0); 14903#L704-1 assume !(0 == ~T5_E~0); 14847#L709-1 assume !(0 == ~T6_E~0); 14776#L714-1 assume !(0 == ~E_M~0); 14777#L719-1 assume !(0 == ~E_1~0); 15054#L724-1 assume !(0 == ~E_2~0); 14525#L729-1 assume !(0 == ~E_3~0); 14526#L734-1 assume !(0 == ~E_4~0); 15147#L739-1 assume !(0 == ~E_5~0); 14732#L744-1 assume !(0 == ~E_6~0); 14733#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14479#L334 assume !(1 == ~m_pc~0); 14480#L334-2 is_master_triggered_~__retres1~0#1 := 0; 14839#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14736#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14704#L849 assume !(0 != activate_threads_~tmp~1#1); 14705#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14633#L353 assume !(1 == ~t1_pc~0); 14634#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14965#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14493#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14494#L857 assume !(0 != activate_threads_~tmp___0~0#1); 14581#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14582#L372 assume !(1 == ~t2_pc~0); 14692#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14691#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14834#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14966#L865 assume !(0 != activate_threads_~tmp___1~0#1); 14468#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14469#L391 assume 1 == ~t3_pc~0; 15112#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14395#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14418#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14419#L873 assume !(0 != activate_threads_~tmp___2~0#1); 14708#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14709#L410 assume 1 == ~t4_pc~0; 15127#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14982#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14598#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14599#L881 assume !(0 != activate_threads_~tmp___3~0#1); 14716#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14717#L429 assume !(1 == ~t5_pc~0); 14531#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14532#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14751#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14752#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14990#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14701#L448 assume 1 == ~t6_pc~0; 14569#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14570#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14944#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14945#L897 assume !(0 != activate_threads_~tmp___5~0#1); 15184#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15269#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 14757#L762-2 assume !(1 == ~T1_E~0); 14758#L767-1 assume !(1 == ~T2_E~0); 15198#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15019#L777-1 assume !(1 == ~T4_E~0); 14886#L782-1 assume !(1 == ~T5_E~0); 14560#L787-1 assume !(1 == ~T6_E~0); 14558#L792-1 assume !(1 == ~E_M~0); 14559#L797-1 assume !(1 == ~E_1~0); 14603#L802-1 assume !(1 == ~E_2~0); 14843#L807-1 assume !(1 == ~E_3~0); 14844#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15141#L817-1 assume !(1 == ~E_5~0); 14906#L822-1 assume !(1 == ~E_6~0); 14907#L827-1 assume { :end_inline_reset_delta_events } true; 17033#L1053-2 [2022-12-13 14:56:58,091 INFO L750 eck$LassoCheckResult]: Loop: 17033#L1053-2 assume !false; 15129#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14528#L659 assume !false; 14667#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14668#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15299#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15300#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15043#L570 assume !(0 != eval_~tmp~0#1); 14609#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14610#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14870#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14871#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14390#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14391#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14447#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14448#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14999#L709-3 assume !(0 == ~T6_E~0); 14978#L714-3 assume !(0 == ~E_M~0); 14742#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14438#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14439#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14950#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15005#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15006#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15136#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14454#L334-24 assume !(1 == ~m_pc~0); 14455#L334-26 is_master_triggered_~__retres1~0#1 := 0; 14602#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14627#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14424#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14425#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15002#L353-24 assume !(1 == ~t1_pc~0); 15003#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 15205#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15201#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15202#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14470#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14471#L372-24 assume 1 == ~t2_pc~0; 14433#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14434#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14820#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15176#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 15177#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14783#L391-24 assume 1 == ~t3_pc~0; 14784#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15055#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15004#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14887#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14856#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14664#L410-24 assume !(1 == ~t4_pc~0); 14665#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 17180#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17179#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17178#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17177#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17176#L429-24 assume 1 == ~t5_pc~0; 17174#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17173#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17172#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17171#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17170#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17169#L448-24 assume 1 == ~t6_pc~0; 17168#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17166#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17165#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17164#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17163#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17162#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15152#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17161#L767-3 assume !(1 == ~T2_E~0); 17160#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17159#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17158#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17157#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17156#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15036#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17155#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17154#L807-3 assume !(1 == ~E_3~0); 17153#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17152#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17151#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17150#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 17148#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 17142#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 17141#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 17140#L1072 assume !(0 == start_simulation_~tmp~3#1); 15200#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 17133#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 17132#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 17131#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 17130#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17129#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15160#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 15161#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 17033#L1053-2 [2022-12-13 14:56:58,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:58,091 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2022-12-13 14:56:58,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:58,091 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1908937008] [2022-12-13 14:56:58,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:58,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:58,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:58,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:58,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:58,154 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1908937008] [2022-12-13 14:56:58,154 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1908937008] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:58,154 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:58,154 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:58,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1401014946] [2022-12-13 14:56:58,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:58,155 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:56:58,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:58,155 INFO L85 PathProgramCache]: Analyzing trace with hash -386220834, now seen corresponding path program 1 times [2022-12-13 14:56:58,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:58,156 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [203523319] [2022-12-13 14:56:58,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:58,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:58,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:58,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:58,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:58,193 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [203523319] [2022-12-13 14:56:58,193 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [203523319] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:58,193 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:58,194 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:58,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501073019] [2022-12-13 14:56:58,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:58,194 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:56:58,194 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:56:58,194 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:56:58,195 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:56:58,195 INFO L87 Difference]: Start difference. First operand 2935 states and 4303 transitions. cyclomatic complexity: 1372 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:58,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:56:58,380 INFO L93 Difference]: Finished difference Result 8042 states and 11650 transitions. [2022-12-13 14:56:58,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8042 states and 11650 transitions. [2022-12-13 14:56:58,411 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7680 [2022-12-13 14:56:58,434 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8042 states to 8042 states and 11650 transitions. [2022-12-13 14:56:58,434 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8042 [2022-12-13 14:56:58,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8042 [2022-12-13 14:56:58,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8042 states and 11650 transitions. [2022-12-13 14:56:58,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:56:58,447 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8042 states and 11650 transitions. [2022-12-13 14:56:58,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8042 states and 11650 transitions. [2022-12-13 14:56:58,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8042 to 7638. [2022-12-13 14:56:58,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7638 states, 7638 states have (on average 1.4548311076197957) internal successors, (11112), 7637 states have internal predecessors, (11112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:58,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7638 states to 7638 states and 11112 transitions. [2022-12-13 14:56:58,621 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7638 states and 11112 transitions. [2022-12-13 14:56:58,621 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:56:58,621 INFO L428 stractBuchiCegarLoop]: Abstraction has 7638 states and 11112 transitions. [2022-12-13 14:56:58,622 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 14:56:58,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7638 states and 11112 transitions. [2022-12-13 14:56:58,644 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7506 [2022-12-13 14:56:58,645 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:56:58,645 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:56:58,645 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:58,645 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:58,646 INFO L748 eck$LassoCheckResult]: Stem: 25770#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 25771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 25916#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25917#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25562#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 25563#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25914#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25915#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25831#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25619#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25620#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25539#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25540#L684 assume !(0 == ~M_E~0); 26044#L684-2 assume !(0 == ~T1_E~0); 25867#L689-1 assume !(0 == ~T2_E~0); 25868#L694-1 assume !(0 == ~T3_E~0); 25865#L699-1 assume !(0 == ~T4_E~0); 25866#L704-1 assume !(0 == ~T5_E~0); 25817#L709-1 assume !(0 == ~T6_E~0); 25752#L714-1 assume !(0 == ~E_M~0); 25753#L719-1 assume !(0 == ~E_1~0); 26008#L724-1 assume !(0 == ~E_2~0); 25511#L729-1 assume !(0 == ~E_3~0); 25512#L734-1 assume !(0 == ~E_4~0); 26092#L739-1 assume !(0 == ~E_5~0); 25710#L744-1 assume !(0 == ~E_6~0); 25711#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25466#L334 assume !(1 == ~m_pc~0); 25467#L334-2 is_master_triggered_~__retres1~0#1 := 0; 25808#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25712#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25682#L849 assume !(0 != activate_threads_~tmp~1#1); 25683#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25617#L353 assume !(1 == ~t1_pc~0); 25618#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25920#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25480#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25481#L857 assume !(0 != activate_threads_~tmp___0~0#1); 25567#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25568#L372 assume !(1 == ~t2_pc~0); 25671#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 25670#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25802#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25921#L865 assume !(0 != activate_threads_~tmp___1~0#1); 25455#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25456#L391 assume !(1 == ~t3_pc~0); 25381#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25382#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25405#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25406#L873 assume !(0 != activate_threads_~tmp___2~0#1); 25686#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25687#L410 assume 1 == ~t4_pc~0; 26074#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25934#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25582#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25583#L881 assume !(0 != activate_threads_~tmp___3~0#1); 25694#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25695#L429 assume !(1 == ~t5_pc~0); 25517#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25518#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25727#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25728#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25942#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25679#L448 assume 1 == ~t6_pc~0; 25555#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25556#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25903#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25904#L897 assume !(0 != activate_threads_~tmp___5~0#1); 26120#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26177#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 25733#L762-2 assume !(1 == ~T1_E~0); 25734#L767-1 assume !(1 == ~T2_E~0); 26127#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26128#L777-1 assume !(1 == ~T4_E~0); 25847#L782-1 assume !(1 == ~T5_E~0); 25848#L787-1 assume !(1 == ~T6_E~0); 25543#L792-1 assume !(1 == ~E_M~0); 25544#L797-1 assume !(1 == ~E_1~0); 26028#L802-1 assume !(1 == ~E_2~0); 26029#L807-1 assume !(1 == ~E_3~0); 26086#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 26087#L817-1 assume !(1 == ~E_5~0); 25869#L822-1 assume !(1 == ~E_6~0); 25870#L827-1 assume { :end_inline_reset_delta_events } true; 30347#L1053-2 [2022-12-13 14:56:58,646 INFO L750 eck$LassoCheckResult]: Loop: 30347#L1053-2 assume !false; 30348#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30334#L659 assume !false; 30335#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 30326#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 30321#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 30314#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30315#L570 assume !(0 != eval_~tmp~0#1); 30853#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30851#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30848#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30845#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30842#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30839#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30836#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30833#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30831#L709-3 assume !(0 == ~T6_E~0); 30828#L714-3 assume !(0 == ~E_M~0); 30825#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30822#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30819#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30816#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30812#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30808#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30805#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30802#L334-24 assume !(1 == ~m_pc~0); 30799#L334-26 is_master_triggered_~__retres1~0#1 := 0; 30796#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30793#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30790#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30787#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30784#L353-24 assume !(1 == ~t1_pc~0); 30781#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 30778#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30774#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30770#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30767#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30762#L372-24 assume !(1 == ~t2_pc~0); 30763#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 32541#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32540#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32539#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 32538#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32537#L391-24 assume !(1 == ~t3_pc~0); 32536#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 32535#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32534#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32533#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32532#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32531#L410-24 assume !(1 == ~t4_pc~0); 32529#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 32528#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32527#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 32526#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32525#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32524#L429-24 assume 1 == ~t5_pc~0; 32522#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32521#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32520#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32519#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32518#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32517#L448-24 assume !(1 == ~t6_pc~0); 32515#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 32514#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32513#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32512#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32511#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32510#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32445#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32509#L767-3 assume !(1 == ~T2_E~0); 32508#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32507#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32506#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32505#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32435#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32434#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32433#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32432#L807-3 assume !(1 == ~E_3~0); 32431#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32430#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32429#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32428#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 32426#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 32420#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 32419#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 32417#L1072 assume !(0 == start_simulation_~tmp~3#1); 32415#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 30549#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 30544#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 30542#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 30539#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30538#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30535#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 30536#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 30347#L1053-2 [2022-12-13 14:56:58,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:58,646 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2022-12-13 14:56:58,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:58,646 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291011483] [2022-12-13 14:56:58,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:58,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:58,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:58,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:58,679 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:58,680 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [291011483] [2022-12-13 14:56:58,680 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [291011483] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:58,680 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:58,680 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 14:56:58,680 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [939744817] [2022-12-13 14:56:58,680 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:58,680 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:56:58,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:58,681 INFO L85 PathProgramCache]: Analyzing trace with hash 471614817, now seen corresponding path program 1 times [2022-12-13 14:56:58,681 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:58,681 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683406731] [2022-12-13 14:56:58,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:58,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:58,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:58,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:58,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:58,720 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683406731] [2022-12-13 14:56:58,720 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [683406731] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:58,720 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:58,720 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:58,720 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [201891970] [2022-12-13 14:56:58,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:58,721 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:56:58,721 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:56:58,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:56:58,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:56:58,721 INFO L87 Difference]: Start difference. First operand 7638 states and 11112 transitions. cyclomatic complexity: 3482 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:58,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:56:58,828 INFO L93 Difference]: Finished difference Result 14179 states and 20558 transitions. [2022-12-13 14:56:58,828 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14179 states and 20558 transitions. [2022-12-13 14:56:58,892 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13982 [2022-12-13 14:56:58,967 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14179 states to 14179 states and 20558 transitions. [2022-12-13 14:56:58,967 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14179 [2022-12-13 14:56:58,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14179 [2022-12-13 14:56:58,981 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14179 states and 20558 transitions. [2022-12-13 14:56:58,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:56:58,992 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14179 states and 20558 transitions. [2022-12-13 14:56:59,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14179 states and 20558 transitions. [2022-12-13 14:56:59,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14179 to 14143. [2022-12-13 14:56:59,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14143 states, 14143 states have (on average 1.4510358481227463) internal successors, (20522), 14142 states have internal predecessors, (20522), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:59,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14143 states to 14143 states and 20522 transitions. [2022-12-13 14:56:59,185 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14143 states and 20522 transitions. [2022-12-13 14:56:59,185 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:56:59,186 INFO L428 stractBuchiCegarLoop]: Abstraction has 14143 states and 20522 transitions. [2022-12-13 14:56:59,186 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 14:56:59,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14143 states and 20522 transitions. [2022-12-13 14:56:59,261 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13946 [2022-12-13 14:56:59,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:56:59,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:56:59,263 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:59,263 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:56:59,263 INFO L748 eck$LassoCheckResult]: Stem: 47589#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 47590#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 47732#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47733#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47382#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 47383#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47730#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47731#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47647#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47438#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47439#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47359#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47360#L684 assume !(0 == ~M_E~0); 47860#L684-2 assume !(0 == ~T1_E~0); 47684#L689-1 assume !(0 == ~T2_E~0); 47685#L694-1 assume !(0 == ~T3_E~0); 47682#L699-1 assume !(0 == ~T4_E~0); 47683#L704-1 assume !(0 == ~T5_E~0); 47632#L709-1 assume !(0 == ~T6_E~0); 47569#L714-1 assume !(0 == ~E_M~0); 47570#L719-1 assume !(0 == ~E_1~0); 47831#L724-1 assume !(0 == ~E_2~0); 47333#L729-1 assume !(0 == ~E_3~0); 47334#L734-1 assume !(0 == ~E_4~0); 47901#L739-1 assume !(0 == ~E_5~0); 47527#L744-1 assume !(0 == ~E_6~0); 47528#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47290#L334 assume !(1 == ~m_pc~0); 47291#L334-2 is_master_triggered_~__retres1~0#1 := 0; 47623#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47530#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 47499#L849 assume !(0 != activate_threads_~tmp~1#1); 47500#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47436#L353 assume !(1 == ~t1_pc~0); 47437#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47736#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47304#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 47305#L857 assume !(0 != activate_threads_~tmp___0~0#1); 47387#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47388#L372 assume !(1 == ~t2_pc~0); 47490#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47489#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47618#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 47737#L865 assume !(0 != activate_threads_~tmp___1~0#1); 47279#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47280#L391 assume !(1 == ~t3_pc~0); 47205#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47206#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47229#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47230#L873 assume !(0 != activate_threads_~tmp___2~0#1); 47503#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47504#L410 assume !(1 == ~t4_pc~0); 47749#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47750#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47401#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47402#L881 assume !(0 != activate_threads_~tmp___3~0#1); 47510#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47511#L429 assume !(1 == ~t5_pc~0); 47339#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 47340#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47545#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47546#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47758#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47498#L448 assume 1 == ~t6_pc~0; 47375#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47376#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47720#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47721#L897 assume !(0 != activate_threads_~tmp___5~0#1); 47930#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47982#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 47983#L762-2 assume !(1 == ~T1_E~0); 54448#L767-1 assume !(1 == ~T2_E~0); 47938#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47939#L777-1 assume !(1 == ~T4_E~0); 47665#L782-1 assume !(1 == ~T5_E~0); 47666#L787-1 assume !(1 == ~T6_E~0); 47363#L792-1 assume !(1 == ~E_M~0); 47364#L797-1 assume !(1 == ~E_1~0); 47843#L802-1 assume !(1 == ~E_2~0); 47844#L807-1 assume !(1 == ~E_3~0); 47895#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 47896#L817-1 assume !(1 == ~E_5~0); 47686#L822-1 assume !(1 == ~E_6~0); 47687#L827-1 assume { :end_inline_reset_delta_events } true; 53038#L1053-2 [2022-12-13 14:56:59,263 INFO L750 eck$LassoCheckResult]: Loop: 53038#L1053-2 assume !false; 53039#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52631#L659 assume !false; 52632#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 52318#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 52313#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 52306#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 52307#L570 assume !(0 != eval_~tmp~0#1); 53890#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54527#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54526#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54524#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54522#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54520#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54518#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54430#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54429#L709-3 assume !(0 == ~T6_E~0); 54428#L714-3 assume !(0 == ~E_M~0); 54427#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54426#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54425#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54424#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54422#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54420#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54418#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54416#L334-24 assume !(1 == ~m_pc~0); 54414#L334-26 is_master_triggered_~__retres1~0#1 := 0; 54412#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54411#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54410#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 54402#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54400#L353-24 assume !(1 == ~t1_pc~0); 54398#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 54396#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54394#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54393#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54392#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54391#L372-24 assume 1 == ~t2_pc~0; 54389#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54388#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54387#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54386#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 54378#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54376#L391-24 assume !(1 == ~t3_pc~0); 54374#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 54372#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54370#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54368#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54366#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54364#L410-24 assume !(1 == ~t4_pc~0); 54363#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 54362#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54361#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54360#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54359#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54358#L429-24 assume 1 == ~t5_pc~0; 54355#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54353#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54351#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54349#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54347#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54345#L448-24 assume !(1 == ~t6_pc~0); 54342#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 54340#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54338#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54335#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54331#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54328#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53581#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54325#L767-3 assume !(1 == ~T2_E~0); 54323#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54321#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54319#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54317#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54315#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53565#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54310#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54306#L807-3 assume !(1 == ~E_3~0); 54302#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54298#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54293#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54290#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 53172#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 53167#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 53159#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 53160#L1072 assume !(0 == start_simulation_~tmp~3#1); 53146#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 53147#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 54015#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 54014#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 54013#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54012#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54011#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 53040#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 53038#L1053-2 [2022-12-13 14:56:59,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:59,264 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2022-12-13 14:56:59,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:59,264 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820567664] [2022-12-13 14:56:59,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:59,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:59,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:59,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:59,318 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:59,318 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1820567664] [2022-12-13 14:56:59,318 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1820567664] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:59,318 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:59,318 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:56:59,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838067094] [2022-12-13 14:56:59,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:59,319 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:56:59,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:56:59,319 INFO L85 PathProgramCache]: Analyzing trace with hash 231347488, now seen corresponding path program 1 times [2022-12-13 14:56:59,319 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:56:59,319 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030704296] [2022-12-13 14:56:59,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:56:59,319 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:56:59,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:56:59,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:56:59,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:56:59,343 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1030704296] [2022-12-13 14:56:59,344 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1030704296] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:56:59,344 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:56:59,344 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:56:59,344 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856115313] [2022-12-13 14:56:59,344 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:56:59,344 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:56:59,344 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:56:59,344 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 14:56:59,344 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 14:56:59,344 INFO L87 Difference]: Start difference. First operand 14143 states and 20522 transitions. cyclomatic complexity: 6395 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:56:59,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:56:59,650 INFO L93 Difference]: Finished difference Result 33842 states and 49567 transitions. [2022-12-13 14:56:59,650 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33842 states and 49567 transitions. [2022-12-13 14:56:59,784 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 33388 [2022-12-13 14:56:59,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33842 states to 33842 states and 49567 transitions. [2022-12-13 14:56:59,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33842 [2022-12-13 14:56:59,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33842 [2022-12-13 14:56:59,927 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33842 states and 49567 transitions. [2022-12-13 14:56:59,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:56:59,948 INFO L218 hiAutomatonCegarLoop]: Abstraction has 33842 states and 49567 transitions. [2022-12-13 14:56:59,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33842 states and 49567 transitions. [2022-12-13 14:57:00,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33842 to 14752. [2022-12-13 14:57:00,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14752 states, 14752 states have (on average 1.4324159436008677) internal successors, (21131), 14751 states have internal predecessors, (21131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:00,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14752 states to 14752 states and 21131 transitions. [2022-12-13 14:57:00,287 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14752 states and 21131 transitions. [2022-12-13 14:57:00,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 14:57:00,288 INFO L428 stractBuchiCegarLoop]: Abstraction has 14752 states and 21131 transitions. [2022-12-13 14:57:00,288 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 14:57:00,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14752 states and 21131 transitions. [2022-12-13 14:57:00,337 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14552 [2022-12-13 14:57:00,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:00,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:00,338 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:00,338 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:00,338 INFO L748 eck$LassoCheckResult]: Stem: 95591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 95592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 95729#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95730#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95385#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 95386#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95725#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95726#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95649#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95439#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95440#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 95360#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95361#L684 assume !(0 == ~M_E~0); 95858#L684-2 assume !(0 == ~T1_E~0); 95683#L689-1 assume !(0 == ~T2_E~0); 95684#L694-1 assume !(0 == ~T3_E~0); 95681#L699-1 assume !(0 == ~T4_E~0); 95682#L704-1 assume !(0 == ~T5_E~0); 95634#L709-1 assume !(0 == ~T6_E~0); 95567#L714-1 assume !(0 == ~E_M~0); 95568#L719-1 assume !(0 == ~E_1~0); 95825#L724-1 assume !(0 == ~E_2~0); 95332#L729-1 assume !(0 == ~E_3~0); 95333#L734-1 assume !(0 == ~E_4~0); 95899#L739-1 assume !(0 == ~E_5~0); 95524#L744-1 assume !(0 == ~E_6~0); 95525#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95289#L334 assume !(1 == ~m_pc~0); 95290#L334-2 is_master_triggered_~__retres1~0#1 := 0; 95623#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95527#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 95497#L849 assume !(0 != activate_threads_~tmp~1#1); 95498#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95435#L353 assume !(1 == ~t1_pc~0); 95436#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95731#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95303#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 95304#L857 assume !(0 != activate_threads_~tmp___0~0#1); 95387#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95388#L372 assume !(1 == ~t2_pc~0); 95486#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 95485#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95618#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95732#L865 assume !(0 != activate_threads_~tmp___1~0#1); 95278#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95279#L391 assume !(1 == ~t3_pc~0); 95203#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95204#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95227#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95228#L873 assume !(0 != activate_threads_~tmp___2~0#1); 95501#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95502#L410 assume !(1 == ~t4_pc~0); 95747#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 95748#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95401#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 95402#L881 assume !(0 != activate_threads_~tmp___3~0#1); 95511#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95512#L429 assume !(1 == ~t5_pc~0); 95338#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 95339#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95993#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 95753#L889 assume !(0 != activate_threads_~tmp___4~0#1); 95754#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95496#L448 assume 1 == ~t6_pc~0; 95375#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 95376#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95717#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95718#L897 assume !(0 != activate_threads_~tmp___5~0#1); 95928#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95983#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 95984#L762-2 assume !(1 == ~T1_E~0); 95958#L767-1 assume !(1 == ~T2_E~0); 95959#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 95787#L777-1 assume !(1 == ~T4_E~0); 95788#L782-1 assume !(1 == ~T5_E~0); 95365#L787-1 assume !(1 == ~T6_E~0); 95366#L792-1 assume !(1 == ~E_M~0); 95363#L797-1 assume !(1 == ~E_1~0); 95407#L802-1 assume !(1 == ~E_2~0); 95627#L807-1 assume !(1 == ~E_3~0); 95628#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 95976#L817-1 assume !(1 == ~E_5~0); 95977#L822-1 assume !(1 == ~E_6~0); 95904#L827-1 assume { :end_inline_reset_delta_events } true; 95905#L1053-2 [2022-12-13 14:57:00,339 INFO L750 eck$LassoCheckResult]: Loop: 95905#L1053-2 assume !false; 98691#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 98684#L659 assume !false; 98681#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 98682#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 105219#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 105218#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 105216#L570 assume !(0 != eval_~tmp~0#1); 105217#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 105346#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 105345#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 105344#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 105343#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 105342#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 105341#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 105340#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 105339#L709-3 assume !(0 == ~T6_E~0); 105338#L714-3 assume !(0 == ~E_M~0); 105337#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 105336#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 105335#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 105334#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 105333#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 105332#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 105331#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99842#L334-24 assume !(1 == ~m_pc~0); 99843#L334-26 is_master_triggered_~__retres1~0#1 := 0; 99838#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99839#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 99834#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 99835#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99830#L353-24 assume !(1 == ~t1_pc~0); 99831#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 99827#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99828#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 99823#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 99824#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99818#L372-24 assume !(1 == ~t2_pc~0); 99819#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 99813#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99814#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 99809#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 99810#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99805#L391-24 assume !(1 == ~t3_pc~0); 99806#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 99801#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99802#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 99797#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 99798#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99793#L410-24 assume !(1 == ~t4_pc~0); 99794#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 99789#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99790#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 99785#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 99786#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 99780#L429-24 assume 1 == ~t5_pc~0; 99781#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 99772#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99773#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 99766#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 99764#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 99762#L448-24 assume 1 == ~t6_pc~0; 99679#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 99676#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 99674#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 99671#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 99669#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99667#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 99665#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 99663#L767-3 assume !(1 == ~T2_E~0); 99661#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 99660#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 99658#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 99577#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 99495#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 99488#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 99479#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 99392#L807-3 assume !(1 == ~E_3~0); 99389#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 99305#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 99300#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 99296#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 98926#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 98838#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 98836#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 98833#L1072 assume !(0 == start_simulation_~tmp~3#1); 98809#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 98784#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 98764#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 98763#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 98762#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98761#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98731#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 98730#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 95905#L1053-2 [2022-12-13 14:57:00,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:00,339 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2022-12-13 14:57:00,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:00,339 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241568734] [2022-12-13 14:57:00,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:00,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:00,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:00,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:00,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:00,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1241568734] [2022-12-13 14:57:00,387 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1241568734] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:00,387 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:00,387 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:00,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55600722] [2022-12-13 14:57:00,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:00,388 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:57:00,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:00,388 INFO L85 PathProgramCache]: Analyzing trace with hash 2048172576, now seen corresponding path program 1 times [2022-12-13 14:57:00,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:00,389 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1766762547] [2022-12-13 14:57:00,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:00,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:00,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:00,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:00,427 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:00,427 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1766762547] [2022-12-13 14:57:00,427 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1766762547] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:00,427 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:00,427 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:00,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [762247893] [2022-12-13 14:57:00,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:00,428 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:00,428 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:00,428 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:57:00,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:57:00,428 INFO L87 Difference]: Start difference. First operand 14752 states and 21131 transitions. cyclomatic complexity: 6395 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:00,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:00,713 INFO L93 Difference]: Finished difference Result 41693 states and 59140 transitions. [2022-12-13 14:57:00,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41693 states and 59140 transitions. [2022-12-13 14:57:00,861 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40302 [2022-12-13 14:57:00,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41693 states to 41693 states and 59140 transitions. [2022-12-13 14:57:00,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41693 [2022-12-13 14:57:01,002 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41693 [2022-12-13 14:57:01,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41693 states and 59140 transitions. [2022-12-13 14:57:01,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:01,018 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41693 states and 59140 transitions. [2022-12-13 14:57:01,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41693 states and 59140 transitions. [2022-12-13 14:57:01,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41693 to 40509. [2022-12-13 14:57:01,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40509 states, 40509 states have (on average 1.4232392801599645) internal successors, (57654), 40508 states have internal predecessors, (57654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:01,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40509 states to 40509 states and 57654 transitions. [2022-12-13 14:57:01,447 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40509 states and 57654 transitions. [2022-12-13 14:57:01,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:57:01,448 INFO L428 stractBuchiCegarLoop]: Abstraction has 40509 states and 57654 transitions. [2022-12-13 14:57:01,448 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 14:57:01,448 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40509 states and 57654 transitions. [2022-12-13 14:57:01,549 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40158 [2022-12-13 14:57:01,550 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:01,550 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:01,551 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:01,551 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:01,551 INFO L748 eck$LassoCheckResult]: Stem: 152048#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 152049#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 152196#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 152197#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 151838#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 151839#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 152192#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 152193#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 152108#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 151900#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 151901#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 151816#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 151817#L684 assume !(0 == ~M_E~0); 152335#L684-2 assume !(0 == ~T1_E~0); 152143#L689-1 assume !(0 == ~T2_E~0); 152144#L694-1 assume !(0 == ~T3_E~0); 152141#L699-1 assume !(0 == ~T4_E~0); 152142#L704-1 assume !(0 == ~T5_E~0); 152095#L709-1 assume !(0 == ~T6_E~0); 152023#L714-1 assume !(0 == ~E_M~0); 152024#L719-1 assume !(0 == ~E_1~0); 152295#L724-1 assume !(0 == ~E_2~0); 151785#L729-1 assume !(0 == ~E_3~0); 151786#L734-1 assume !(0 == ~E_4~0); 152375#L739-1 assume !(0 == ~E_5~0); 151983#L744-1 assume !(0 == ~E_6~0); 151984#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 151741#L334 assume !(1 == ~m_pc~0); 151742#L334-2 is_master_triggered_~__retres1~0#1 := 0; 152085#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 151986#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 151957#L849 assume !(0 != activate_threads_~tmp~1#1); 151958#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 151896#L353 assume !(1 == ~t1_pc~0); 151897#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 152199#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 151755#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 151756#L857 assume !(0 != activate_threads_~tmp___0~0#1); 151840#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 151841#L372 assume !(1 == ~t2_pc~0); 151948#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 151947#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 152079#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 152200#L865 assume !(0 != activate_threads_~tmp___1~0#1); 151730#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 151731#L391 assume !(1 == ~t3_pc~0); 151658#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 151659#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 151681#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 151682#L873 assume !(0 != activate_threads_~tmp___2~0#1); 151961#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 151962#L410 assume !(1 == ~t4_pc~0); 152215#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 152216#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 151855#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 151856#L881 assume !(0 != activate_threads_~tmp___3~0#1); 151970#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 151971#L429 assume !(1 == ~t5_pc~0); 151791#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 151792#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 151999#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 152000#L889 assume !(0 != activate_threads_~tmp___4~0#1); 152221#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 151956#L448 assume !(1 == ~t6_pc~0); 151879#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 151880#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 152183#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 152184#L897 assume !(0 != activate_threads_~tmp___5~0#1); 152403#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152460#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 152461#L762-2 assume !(1 == ~T1_E~0); 152435#L767-1 assume !(1 == ~T2_E~0); 152436#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 152254#L777-1 assume !(1 == ~T4_E~0); 152255#L782-1 assume !(1 == ~T5_E~0); 151821#L787-1 assume !(1 == ~T6_E~0); 151822#L792-1 assume !(1 == ~E_M~0); 151819#L797-1 assume !(1 == ~E_1~0); 151863#L802-1 assume !(1 == ~E_2~0); 152089#L807-1 assume !(1 == ~E_3~0); 152090#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 152451#L817-1 assume !(1 == ~E_5~0); 152452#L822-1 assume !(1 == ~E_6~0); 152379#L827-1 assume { :end_inline_reset_delta_events } true; 152380#L1053-2 [2022-12-13 14:57:01,552 INFO L750 eck$LassoCheckResult]: Loop: 152380#L1053-2 assume !false; 157685#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 157552#L659 assume !false; 157553#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 157524#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 157519#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 182614#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 182612#L570 assume !(0 != eval_~tmp~0#1); 159148#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 159146#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 159144#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 159142#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 159140#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 159138#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 159136#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 159134#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 159132#L709-3 assume !(0 == ~T6_E~0); 159130#L714-3 assume !(0 == ~E_M~0); 159128#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 159126#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 159124#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 159122#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 159118#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 159115#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 159112#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159109#L334-24 assume !(1 == ~m_pc~0); 159106#L334-26 is_master_triggered_~__retres1~0#1 := 0; 159103#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159099#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 159095#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 159089#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159084#L353-24 assume !(1 == ~t1_pc~0); 159079#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 159074#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159068#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 159062#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 159055#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159056#L372-24 assume 1 == ~t2_pc~0; 182954#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 182953#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 182952#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 182951#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 182950#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 182949#L391-24 assume !(1 == ~t3_pc~0); 182948#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 182947#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 182946#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 182945#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 182944#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 182943#L410-24 assume !(1 == ~t4_pc~0); 182942#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 182941#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 182940#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 182939#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 182938#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 182937#L429-24 assume !(1 == ~t5_pc~0); 182935#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 182934#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 182933#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 158460#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 158457#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 158455#L448-24 assume !(1 == ~t6_pc~0); 158453#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 158451#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 158449#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 158447#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 158445#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 158443#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 158441#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 158439#L767-3 assume !(1 == ~T2_E~0); 158437#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 158435#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 158433#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 158431#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 158429#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 158426#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 158427#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 182911#L807-3 assume !(1 == ~E_3~0); 182909#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 182907#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 182905#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 182903#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 182901#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 182895#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 182894#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 182893#L1072 assume !(0 == start_simulation_~tmp~3#1); 182892#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 180111#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 158323#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 158324#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 182773#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 182772#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 182771#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 182770#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 152380#L1053-2 [2022-12-13 14:57:01,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:01,552 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2022-12-13 14:57:01,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:01,552 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321805323] [2022-12-13 14:57:01,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:01,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:01,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:01,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:01,604 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:01,604 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321805323] [2022-12-13 14:57:01,605 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321805323] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:01,605 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:01,605 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 14:57:01,605 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1729604337] [2022-12-13 14:57:01,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:01,606 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:57:01,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:01,606 INFO L85 PathProgramCache]: Analyzing trace with hash -1569586397, now seen corresponding path program 1 times [2022-12-13 14:57:01,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:01,606 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037201102] [2022-12-13 14:57:01,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:01,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:01,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:01,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:01,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:01,653 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037201102] [2022-12-13 14:57:01,653 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1037201102] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:01,653 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:01,653 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:01,653 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1522608384] [2022-12-13 14:57:01,653 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:01,654 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:01,654 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:01,654 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:57:01,654 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:57:01,655 INFO L87 Difference]: Start difference. First operand 40509 states and 57654 transitions. cyclomatic complexity: 17177 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:01,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:01,867 INFO L93 Difference]: Finished difference Result 60176 states and 85801 transitions. [2022-12-13 14:57:01,867 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60176 states and 85801 transitions. [2022-12-13 14:57:02,101 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 59708 [2022-12-13 14:57:02,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60176 states to 60176 states and 85801 transitions. [2022-12-13 14:57:02,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60176 [2022-12-13 14:57:02,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60176 [2022-12-13 14:57:02,216 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60176 states and 85801 transitions. [2022-12-13 14:57:02,246 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:02,246 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60176 states and 85801 transitions. [2022-12-13 14:57:02,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60176 states and 85801 transitions. [2022-12-13 14:57:02,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60176 to 42180. [2022-12-13 14:57:02,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42180 states, 42180 states have (on average 1.4284257942152678) internal successors, (60251), 42179 states have internal predecessors, (60251), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:02,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42180 states to 42180 states and 60251 transitions. [2022-12-13 14:57:02,682 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42180 states and 60251 transitions. [2022-12-13 14:57:02,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:57:02,682 INFO L428 stractBuchiCegarLoop]: Abstraction has 42180 states and 60251 transitions. [2022-12-13 14:57:02,683 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 14:57:02,683 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42180 states and 60251 transitions. [2022-12-13 14:57:02,781 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 41843 [2022-12-13 14:57:02,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:02,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:02,783 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:02,783 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:02,783 INFO L748 eck$LassoCheckResult]: Stem: 252740#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 252741#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 252886#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 252887#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 252525#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 252526#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 252884#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 252885#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 252801#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 252585#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 252586#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 252506#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 252507#L684 assume !(0 == ~M_E~0); 253011#L684-2 assume !(0 == ~T1_E~0); 252836#L689-1 assume !(0 == ~T2_E~0); 252837#L694-1 assume !(0 == ~T3_E~0); 252834#L699-1 assume !(0 == ~T4_E~0); 252835#L704-1 assume !(0 == ~T5_E~0); 252786#L709-1 assume !(0 == ~T6_E~0); 252720#L714-1 assume !(0 == ~E_M~0); 252721#L719-1 assume !(0 == ~E_1~0); 252977#L724-1 assume !(0 == ~E_2~0); 252477#L729-1 assume !(0 == ~E_3~0); 252478#L734-1 assume !(0 == ~E_4~0); 253051#L739-1 assume !(0 == ~E_5~0); 252675#L744-1 assume !(0 == ~E_6~0); 252676#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 252433#L334 assume !(1 == ~m_pc~0); 252434#L334-2 is_master_triggered_~__retres1~0#1 := 0; 252778#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 252678#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 252647#L849 assume !(0 != activate_threads_~tmp~1#1); 252648#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 252583#L353 assume !(1 == ~t1_pc~0); 252584#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 252890#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 252447#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 252448#L857 assume !(0 != activate_threads_~tmp___0~0#1); 252530#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 252531#L372 assume !(1 == ~t2_pc~0); 252636#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 252635#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 252772#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 252891#L865 assume !(0 != activate_threads_~tmp___1~0#1); 252422#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 252423#L391 assume !(1 == ~t3_pc~0); 252350#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 252351#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 252373#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 252374#L873 assume !(0 != activate_threads_~tmp___2~0#1); 252651#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 252652#L410 assume !(1 == ~t4_pc~0); 252903#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 252904#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252544#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 252545#L881 assume !(0 != activate_threads_~tmp___3~0#1); 252659#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 252660#L429 assume !(1 == ~t5_pc~0); 252483#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 252484#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 252693#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 252694#L889 assume !(0 != activate_threads_~tmp___4~0#1); 252909#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 252644#L448 assume !(1 == ~t6_pc~0); 252566#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 252567#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 252874#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 252875#L897 assume !(0 != activate_threads_~tmp___5~0#1); 253083#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 253145#L762 assume !(1 == ~M_E~0); 252701#L762-2 assume !(1 == ~T1_E~0); 252702#L767-1 assume !(1 == ~T2_E~0); 253090#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 252940#L777-1 assume !(1 == ~T4_E~0); 252816#L782-1 assume !(1 == ~T5_E~0); 252512#L787-1 assume !(1 == ~T6_E~0); 252510#L792-1 assume !(1 == ~E_M~0); 252511#L797-1 assume !(1 == ~E_1~0); 252549#L802-1 assume !(1 == ~E_2~0); 252782#L807-1 assume !(1 == ~E_3~0); 252783#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 253046#L817-1 assume !(1 == ~E_5~0); 252838#L822-1 assume !(1 == ~E_6~0); 252839#L827-1 assume { :end_inline_reset_delta_events } true; 253057#L1053-2 [2022-12-13 14:57:02,783 INFO L750 eck$LassoCheckResult]: Loop: 253057#L1053-2 assume !false; 271551#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 271543#L659 assume !false; 271353#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 271296#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 259520#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 259518#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 259504#L570 assume !(0 != eval_~tmp~0#1); 259506#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 260115#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 260114#L684-3 assume !(0 == ~M_E~0); 260113#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 260112#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 260111#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 260110#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 260109#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 260107#L709-3 assume !(0 == ~T6_E~0); 260105#L714-3 assume !(0 == ~E_M~0); 260103#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 260101#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 260099#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 260097#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 260095#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 260088#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 260086#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 260084#L334-24 assume !(1 == ~m_pc~0); 260081#L334-26 is_master_triggered_~__retres1~0#1 := 0; 260082#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 271063#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 271057#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 271047#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 271043#L353-24 assume !(1 == ~t1_pc~0); 271037#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 271025#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 260056#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 260052#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 260053#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 270839#L372-24 assume !(1 == ~t2_pc~0); 270836#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 270832#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270829#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 270826#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 270823#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 270820#L391-24 assume !(1 == ~t3_pc~0); 270817#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 270814#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 270810#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 270806#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 270803#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 270398#L410-24 assume !(1 == ~t4_pc~0); 270392#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 270386#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 270380#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 270374#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 259966#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 259961#L429-24 assume 1 == ~t5_pc~0; 259955#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 259949#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 259943#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 259935#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 259928#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 259922#L448-24 assume !(1 == ~t6_pc~0); 259915#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 259908#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 259903#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 259897#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 259892#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 259888#L762-3 assume !(1 == ~M_E~0); 258867#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 259880#L767-3 assume !(1 == ~T2_E~0); 259875#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 259868#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 259869#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 259856#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 259851#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 259822#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 259820#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 259819#L807-3 assume !(1 == ~E_3~0); 259818#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 259817#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 259816#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 259815#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 259542#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 259537#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 267903#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 267877#L1072 assume !(0 == start_simulation_~tmp~3#1); 259786#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 259787#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 271589#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 271587#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 271583#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 271581#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 271579#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 271574#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 253057#L1053-2 [2022-12-13 14:57:02,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:02,784 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2022-12-13 14:57:02,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:02,784 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113168208] [2022-12-13 14:57:02,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:02,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:02,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:02,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:02,871 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:02,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113168208] [2022-12-13 14:57:02,872 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1113168208] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:02,872 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:02,872 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:02,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1286969978] [2022-12-13 14:57:02,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:02,872 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:57:02,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:02,873 INFO L85 PathProgramCache]: Analyzing trace with hash 515711905, now seen corresponding path program 1 times [2022-12-13 14:57:02,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:02,873 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [532743794] [2022-12-13 14:57:02,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:02,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:02,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:02,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:02,895 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:02,895 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [532743794] [2022-12-13 14:57:02,895 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [532743794] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:02,895 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:02,896 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:02,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389638757] [2022-12-13 14:57:02,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:02,896 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:02,896 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:02,897 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:57:02,897 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:57:02,897 INFO L87 Difference]: Start difference. First operand 42180 states and 60251 transitions. cyclomatic complexity: 18087 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:03,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:03,083 INFO L93 Difference]: Finished difference Result 68061 states and 96660 transitions. [2022-12-13 14:57:03,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68061 states and 96660 transitions. [2022-12-13 14:57:03,347 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 67527 [2022-12-13 14:57:03,484 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68061 states to 68061 states and 96660 transitions. [2022-12-13 14:57:03,484 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68061 [2022-12-13 14:57:03,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68061 [2022-12-13 14:57:03,514 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68061 states and 96660 transitions. [2022-12-13 14:57:03,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:03,547 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68061 states and 96660 transitions. [2022-12-13 14:57:03,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68061 states and 96660 transitions. [2022-12-13 14:57:03,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68061 to 49132. [2022-12-13 14:57:04,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49132 states, 49132 states have (on average 1.4234104046242775) internal successors, (69935), 49131 states have internal predecessors, (69935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:04,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49132 states to 49132 states and 69935 transitions. [2022-12-13 14:57:04,090 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49132 states and 69935 transitions. [2022-12-13 14:57:04,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:57:04,091 INFO L428 stractBuchiCegarLoop]: Abstraction has 49132 states and 69935 transitions. [2022-12-13 14:57:04,091 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 14:57:04,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49132 states and 69935 transitions. [2022-12-13 14:57:04,216 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48733 [2022-12-13 14:57:04,216 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:04,216 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:04,217 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:04,217 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:04,218 INFO L748 eck$LassoCheckResult]: Stem: 362990#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 362991#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 363139#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 363140#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 362773#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 362774#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 363137#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 363138#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 363055#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 362835#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 362836#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 362754#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 362755#L684 assume !(0 == ~M_E~0); 363280#L684-2 assume !(0 == ~T1_E~0); 363089#L689-1 assume !(0 == ~T2_E~0); 363090#L694-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 363087#L699-1 assume !(0 == ~T4_E~0); 363088#L704-1 assume !(0 == ~T5_E~0); 363040#L709-1 assume !(0 == ~T6_E~0); 363041#L714-1 assume !(0 == ~E_M~0); 363485#L719-1 assume !(0 == ~E_1~0); 363404#L724-1 assume !(0 == ~E_2~0); 362727#L729-1 assume !(0 == ~E_3~0); 362728#L734-1 assume !(0 == ~E_4~0); 363483#L739-1 assume !(0 == ~E_5~0); 362923#L744-1 assume !(0 == ~E_6~0); 362924#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 363249#L334 assume !(1 == ~m_pc~0); 363481#L334-2 is_master_triggered_~__retres1~0#1 := 0; 363480#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 362926#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 362927#L849 assume !(0 != activate_threads_~tmp~1#1); 363206#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 362833#L353 assume !(1 == ~t1_pc~0); 362834#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 363310#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 362698#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 362699#L857 assume !(0 != activate_threads_~tmp___0~0#1); 362778#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 362779#L372 assume !(1 == ~t2_pc~0); 362885#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 362884#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 363025#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 363476#L865 assume !(0 != activate_threads_~tmp___1~0#1); 362673#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 362674#L391 assume !(1 == ~t3_pc~0); 363294#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 363474#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 363473#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 363472#L873 assume !(0 != activate_threads_~tmp___2~0#1); 362900#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 362901#L410 assume !(1 == ~t4_pc~0); 363307#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 363211#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 362793#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 362794#L881 assume !(0 != activate_threads_~tmp___3~0#1); 363311#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 363078#L429 assume !(1 == ~t5_pc~0); 362733#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 362734#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 362940#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 362941#L889 assume !(0 != activate_threads_~tmp___4~0#1); 363168#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 362893#L448 assume !(1 == ~t6_pc~0); 362816#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 362817#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 363127#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 363128#L897 assume !(0 != activate_threads_~tmp___5~0#1); 363440#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363441#L762 assume !(1 == ~M_E~0); 363460#L762-2 assume !(1 == ~T1_E~0); 363405#L767-1 assume !(1 == ~T2_E~0); 363406#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 363202#L777-1 assume !(1 == ~T4_E~0); 363071#L782-1 assume !(1 == ~T5_E~0); 362760#L787-1 assume !(1 == ~T6_E~0); 362758#L792-1 assume !(1 == ~E_M~0); 362759#L797-1 assume !(1 == ~E_1~0); 362799#L802-1 assume !(1 == ~E_2~0); 363035#L807-1 assume !(1 == ~E_3~0); 363036#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 363321#L817-1 assume !(1 == ~E_5~0); 363091#L822-1 assume !(1 == ~E_6~0); 363092#L827-1 assume { :end_inline_reset_delta_events } true; 363336#L1053-2 [2022-12-13 14:57:04,218 INFO L750 eck$LassoCheckResult]: Loop: 363336#L1053-2 assume !false; 389009#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 389007#L659 assume !false; 389005#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 389000#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 388993#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 388991#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 388988#L570 assume !(0 != eval_~tmp~0#1); 388986#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 388984#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 388982#L684-3 assume !(0 == ~M_E~0); 388981#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 388980#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 388978#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 388977#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 388976#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 388975#L709-3 assume !(0 == ~T6_E~0); 388974#L714-3 assume !(0 == ~E_M~0); 388973#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 388972#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 388971#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 388970#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 388969#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 388968#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 388967#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 388966#L334-24 assume !(1 == ~m_pc~0); 388965#L334-26 is_master_triggered_~__retres1~0#1 := 0; 388964#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 388963#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 388962#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 388961#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 388960#L353-24 assume !(1 == ~t1_pc~0); 388959#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 388958#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 388957#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 388956#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 388955#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 388954#L372-24 assume !(1 == ~t2_pc~0); 388953#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 388951#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 388950#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 388949#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 388948#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 388947#L391-24 assume !(1 == ~t3_pc~0); 388946#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 388945#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 388944#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 388943#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 388942#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 388941#L410-24 assume !(1 == ~t4_pc~0); 388940#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 388939#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 388938#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 388937#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 388936#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 388935#L429-24 assume 1 == ~t5_pc~0; 388933#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 388931#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 388929#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 388927#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 388926#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 388925#L448-24 assume !(1 == ~t6_pc~0); 388924#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 388923#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 388922#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 388921#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 388920#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 388919#L762-3 assume !(1 == ~M_E~0); 378018#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 388918#L767-3 assume !(1 == ~T2_E~0); 388916#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 388914#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 388911#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 388909#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 388907#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 388905#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 388903#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 388901#L807-3 assume !(1 == ~E_3~0); 388900#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 388898#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 388896#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 388894#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 388887#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 388880#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 388878#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 378071#L1072 assume !(0 == start_simulation_~tmp~3#1); 378072#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 391706#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 391705#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 391704#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 391703#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 391702#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 391701#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 391700#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 363336#L1053-2 [2022-12-13 14:57:04,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:04,218 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2022-12-13 14:57:04,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:04,219 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796263879] [2022-12-13 14:57:04,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:04,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:04,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:04,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:04,316 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:04,316 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [796263879] [2022-12-13 14:57:04,317 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [796263879] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:04,317 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:04,317 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:04,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922957820] [2022-12-13 14:57:04,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:04,317 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:57:04,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:04,318 INFO L85 PathProgramCache]: Analyzing trace with hash 515711905, now seen corresponding path program 2 times [2022-12-13 14:57:04,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:04,318 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418143712] [2022-12-13 14:57:04,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:04,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:04,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:04,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:04,340 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:04,340 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418143712] [2022-12-13 14:57:04,340 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418143712] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:04,340 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:04,340 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:04,340 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591106560] [2022-12-13 14:57:04,340 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:04,341 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:04,341 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:04,341 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:57:04,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:57:04,341 INFO L87 Difference]: Start difference. First operand 49132 states and 69935 transitions. cyclomatic complexity: 20819 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:04,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:04,503 INFO L93 Difference]: Finished difference Result 61098 states and 86575 transitions. [2022-12-13 14:57:04,503 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61098 states and 86575 transitions. [2022-12-13 14:57:04,690 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 60637 [2022-12-13 14:57:04,805 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61098 states to 61098 states and 86575 transitions. [2022-12-13 14:57:04,805 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61098 [2022-12-13 14:57:04,834 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61098 [2022-12-13 14:57:04,834 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61098 states and 86575 transitions. [2022-12-13 14:57:04,859 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:04,859 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61098 states and 86575 transitions. [2022-12-13 14:57:04,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61098 states and 86575 transitions. [2022-12-13 14:57:05,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61098 to 42180. [2022-12-13 14:57:05,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42180 states, 42180 states have (on average 1.420697012802276) internal successors, (59925), 42179 states have internal predecessors, (59925), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:05,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42180 states to 42180 states and 59925 transitions. [2022-12-13 14:57:05,261 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42180 states and 59925 transitions. [2022-12-13 14:57:05,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:57:05,262 INFO L428 stractBuchiCegarLoop]: Abstraction has 42180 states and 59925 transitions. [2022-12-13 14:57:05,262 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 14:57:05,262 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42180 states and 59925 transitions. [2022-12-13 14:57:05,380 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 41843 [2022-12-13 14:57:05,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:05,380 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:05,381 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:05,381 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:05,382 INFO L748 eck$LassoCheckResult]: Stem: 473232#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 473233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 473376#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 473377#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 473015#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 473016#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 473374#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 473375#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 473294#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 473077#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 473078#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 472996#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 472997#L684 assume !(0 == ~M_E~0); 473508#L684-2 assume !(0 == ~T1_E~0); 473327#L689-1 assume !(0 == ~T2_E~0); 473328#L694-1 assume !(0 == ~T3_E~0); 473325#L699-1 assume !(0 == ~T4_E~0); 473326#L704-1 assume !(0 == ~T5_E~0); 473277#L709-1 assume !(0 == ~T6_E~0); 473212#L714-1 assume !(0 == ~E_M~0); 473213#L719-1 assume !(0 == ~E_1~0); 473476#L724-1 assume !(0 == ~E_2~0); 472967#L729-1 assume !(0 == ~E_3~0); 472968#L734-1 assume !(0 == ~E_4~0); 473550#L739-1 assume !(0 == ~E_5~0); 473168#L744-1 assume !(0 == ~E_6~0); 473169#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 472924#L334 assume !(1 == ~m_pc~0); 472925#L334-2 is_master_triggered_~__retres1~0#1 := 0; 473268#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 473172#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 473142#L849 assume !(0 != activate_threads_~tmp~1#1); 473143#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 473075#L353 assume !(1 == ~t1_pc~0); 473076#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 473380#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 472938#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 472939#L857 assume !(0 != activate_threads_~tmp___0~0#1); 473020#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 473021#L372 assume !(1 == ~t2_pc~0); 473130#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 473129#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 473262#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 473381#L865 assume !(0 != activate_threads_~tmp___1~0#1); 472913#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 472914#L391 assume !(1 == ~t3_pc~0); 472841#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 472842#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 472864#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 472865#L873 assume !(0 != activate_threads_~tmp___2~0#1); 473146#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 473147#L410 assume !(1 == ~t4_pc~0); 473395#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 473396#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 473034#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 473035#L881 assume !(0 != activate_threads_~tmp___3~0#1); 473152#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 473153#L429 assume !(1 == ~t5_pc~0); 472973#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 472974#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 473186#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 473187#L889 assume !(0 != activate_threads_~tmp___4~0#1); 473402#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 473139#L448 assume !(1 == ~t6_pc~0); 473057#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 473058#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 473364#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 473365#L897 assume !(0 != activate_threads_~tmp___5~0#1); 473576#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 473643#L762 assume !(1 == ~M_E~0); 473193#L762-2 assume !(1 == ~T1_E~0); 473194#L767-1 assume !(1 == ~T2_E~0); 473586#L772-1 assume !(1 == ~T3_E~0); 473433#L777-1 assume !(1 == ~T4_E~0); 473310#L782-1 assume !(1 == ~T5_E~0); 473002#L787-1 assume !(1 == ~T6_E~0); 473000#L792-1 assume !(1 == ~E_M~0); 473001#L797-1 assume !(1 == ~E_1~0); 473040#L802-1 assume !(1 == ~E_2~0); 473272#L807-1 assume !(1 == ~E_3~0); 473273#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 473544#L817-1 assume !(1 == ~E_5~0); 473329#L822-1 assume !(1 == ~E_6~0); 473330#L827-1 assume { :end_inline_reset_delta_events } true; 473557#L1053-2 [2022-12-13 14:57:05,382 INFO L750 eck$LassoCheckResult]: Loop: 473557#L1053-2 assume !false; 498945#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 498943#L659 assume !false; 498940#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 498935#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 498928#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 498924#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 498921#L570 assume !(0 != eval_~tmp~0#1); 498922#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 505579#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 505578#L684-3 assume !(0 == ~M_E~0); 505577#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 505575#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 505574#L694-3 assume !(0 == ~T3_E~0); 505573#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 505572#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 505571#L709-3 assume !(0 == ~T6_E~0); 505570#L714-3 assume !(0 == ~E_M~0); 505569#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 505568#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 505566#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 505564#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 505562#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 505560#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 505558#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 505556#L334-24 assume !(1 == ~m_pc~0); 505553#L334-26 is_master_triggered_~__retres1~0#1 := 0; 505550#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 505548#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 505546#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 505544#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 505542#L353-24 assume !(1 == ~t1_pc~0); 505540#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 505537#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 505535#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 505533#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 505531#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 505529#L372-24 assume !(1 == ~t2_pc~0); 505527#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 505524#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 505522#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 505520#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 505518#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 505516#L391-24 assume !(1 == ~t3_pc~0); 505513#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 505511#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 505509#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 505507#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 505505#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 505503#L410-24 assume !(1 == ~t4_pc~0); 505501#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 505499#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 505497#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 505495#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 505493#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 505491#L429-24 assume 1 == ~t5_pc~0; 505489#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 505490#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 505576#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 505480#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 505478#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 505474#L448-24 assume !(1 == ~t6_pc~0); 505472#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 505470#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 505468#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 505465#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 505463#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 505461#L762-3 assume !(1 == ~M_E~0); 485427#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 505459#L767-3 assume !(1 == ~T2_E~0); 505457#L772-3 assume !(1 == ~T3_E~0); 505455#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 505453#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 505451#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 505450#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 505448#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 505446#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 505444#L807-3 assume !(1 == ~E_3~0); 505442#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 505440#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 505438#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 505436#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 505421#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 505414#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 505412#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 485538#L1072 assume !(0 == start_simulation_~tmp~3#1); 485539#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 499043#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 499042#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 499041#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 499040#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 499038#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 499036#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 499034#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 473557#L1053-2 [2022-12-13 14:57:05,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:05,383 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2022-12-13 14:57:05,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:05,383 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864937876] [2022-12-13 14:57:05,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:05,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:05,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:05,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:05,430 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:05,430 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864937876] [2022-12-13 14:57:05,430 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1864937876] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:05,430 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:05,430 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:05,431 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707659303] [2022-12-13 14:57:05,431 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:05,431 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:57:05,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:05,431 INFO L85 PathProgramCache]: Analyzing trace with hash -676139679, now seen corresponding path program 1 times [2022-12-13 14:57:05,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:05,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775491715] [2022-12-13 14:57:05,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:05,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:05,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:05,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:05,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:05,458 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775491715] [2022-12-13 14:57:05,458 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775491715] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:05,458 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:05,458 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:05,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609297547] [2022-12-13 14:57:05,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:05,459 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:05,459 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:05,459 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:57:05,459 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:57:05,460 INFO L87 Difference]: Start difference. First operand 42180 states and 59925 transitions. cyclomatic complexity: 17761 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:05,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:05,718 INFO L93 Difference]: Finished difference Result 67544 states and 95082 transitions. [2022-12-13 14:57:05,718 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67544 states and 95082 transitions. [2022-12-13 14:57:06,025 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 67000 [2022-12-13 14:57:06,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67544 states to 67544 states and 95082 transitions. [2022-12-13 14:57:06,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67544 [2022-12-13 14:57:06,150 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67544 [2022-12-13 14:57:06,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67544 states and 95082 transitions. [2022-12-13 14:57:06,173 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:06,173 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67544 states and 95082 transitions. [2022-12-13 14:57:06,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67544 states and 95082 transitions. [2022-12-13 14:57:06,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67544 to 49132. [2022-12-13 14:57:06,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49132 states, 49132 states have (on average 1.4107709842872262) internal successors, (69314), 49131 states have internal predecessors, (69314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:06,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49132 states to 49132 states and 69314 transitions. [2022-12-13 14:57:06,586 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49132 states and 69314 transitions. [2022-12-13 14:57:06,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:57:06,587 INFO L428 stractBuchiCegarLoop]: Abstraction has 49132 states and 69314 transitions. [2022-12-13 14:57:06,588 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 14:57:06,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49132 states and 69314 transitions. [2022-12-13 14:57:06,694 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48733 [2022-12-13 14:57:06,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:06,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:06,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:06,696 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:06,696 INFO L748 eck$LassoCheckResult]: Stem: 582965#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 582966#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 583111#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 583112#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 582752#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 582753#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 583107#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 583108#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 583028#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 582813#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 582814#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 582731#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 582732#L684 assume !(0 == ~M_E~0); 583251#L684-2 assume !(0 == ~T1_E~0); 583062#L689-1 assume !(0 == ~T2_E~0); 583063#L694-1 assume !(0 == ~T3_E~0); 583060#L699-1 assume !(0 == ~T4_E~0); 583061#L704-1 assume !(0 == ~T5_E~0); 583014#L709-1 assume !(0 == ~T6_E~0); 582943#L714-1 assume !(0 == ~E_M~0); 582944#L719-1 assume !(0 == ~E_1~0); 583212#L724-1 assume !(0 == ~E_2~0); 582702#L729-1 assume !(0 == ~E_3~0); 582703#L734-1 assume 0 == ~E_4~0;~E_4~0 := 1; 583342#L739-1 assume !(0 == ~E_5~0); 582900#L744-1 assume !(0 == ~E_6~0); 582901#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 583214#L334 assume !(1 == ~m_pc~0); 583434#L334-2 is_master_triggered_~__retres1~0#1 := 0; 583433#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 582903#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 582904#L849 assume !(0 != activate_threads_~tmp~1#1); 583432#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 583431#L353 assume !(1 == ~t1_pc~0); 583430#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 583113#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 582672#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 582673#L857 assume !(0 != activate_threads_~tmp___0~0#1); 583428#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 583339#L372 assume !(1 == ~t2_pc~0); 583340#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 583427#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 583114#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 583115#L865 assume !(0 != activate_threads_~tmp___1~0#1); 583279#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 583425#L391 assume !(1 == ~t3_pc~0); 583424#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 583423#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 583422#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 583421#L873 assume !(0 != activate_threads_~tmp___2~0#1); 582878#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 582879#L410 assume !(1 == ~t4_pc~0); 583278#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 583419#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 583418#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 583417#L881 assume !(0 != activate_threads_~tmp___3~0#1); 582887#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 582888#L429 assume !(1 == ~t5_pc~0); 582708#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 582709#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 583436#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 583139#L889 assume !(0 != activate_threads_~tmp___4~0#1); 583140#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 583173#L448 assume !(1 == ~t6_pc~0); 583409#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 583135#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 583136#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 583319#L897 assume !(0 != activate_threads_~tmp___5~0#1); 583320#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 583377#L762 assume !(1 == ~M_E~0); 582926#L762-2 assume !(1 == ~T1_E~0); 582927#L767-1 assume !(1 == ~T2_E~0); 583325#L772-1 assume !(1 == ~T3_E~0); 583174#L777-1 assume !(1 == ~T4_E~0); 583175#L782-1 assume !(1 == ~T5_E~0); 582735#L787-1 assume !(1 == ~T6_E~0); 582736#L792-1 assume !(1 == ~E_M~0); 583406#L797-1 assume !(1 == ~E_1~0); 583405#L802-1 assume !(1 == ~E_2~0); 583404#L807-1 assume !(1 == ~E_3~0); 583403#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 583291#L817-1 assume !(1 == ~E_5~0); 583066#L822-1 assume !(1 == ~E_6~0); 583067#L827-1 assume { :end_inline_reset_delta_events } true; 583299#L1053-2 [2022-12-13 14:57:06,696 INFO L750 eck$LassoCheckResult]: Loop: 583299#L1053-2 assume !false; 603611#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 603610#L659 assume !false; 603608#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 603602#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 603595#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 603593#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 603591#L570 assume !(0 != eval_~tmp~0#1); 603590#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 603589#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 600506#L684-3 assume !(0 == ~M_E~0); 600503#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 600499#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 600497#L694-3 assume !(0 == ~T3_E~0); 600492#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 600491#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 600483#L709-3 assume !(0 == ~T6_E~0); 600481#L714-3 assume !(0 == ~E_M~0); 600479#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 600478#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 600477#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 600475#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 600474#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 600473#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 600471#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 600469#L334-24 assume !(1 == ~m_pc~0); 600467#L334-26 is_master_triggered_~__retres1~0#1 := 0; 600465#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 600463#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 600461#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 600459#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 600457#L353-24 assume !(1 == ~t1_pc~0); 600455#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 600453#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 600451#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 600449#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 600447#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 600445#L372-24 assume !(1 == ~t2_pc~0); 600443#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 600439#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 600437#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 600435#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 600433#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 600431#L391-24 assume !(1 == ~t3_pc~0); 600429#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 600427#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 600425#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 600423#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 600421#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 600419#L410-24 assume !(1 == ~t4_pc~0); 600417#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 600415#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 600413#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 600411#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 600409#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 600407#L429-24 assume !(1 == ~t5_pc~0); 600405#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 600401#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 600397#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 600393#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 600389#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 600387#L448-24 assume !(1 == ~t6_pc~0); 600385#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 600383#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 600381#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 600379#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 600377#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 600375#L762-3 assume !(1 == ~M_E~0); 600372#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 600371#L767-3 assume !(1 == ~T2_E~0); 600370#L772-3 assume !(1 == ~T3_E~0); 600369#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 600368#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 600367#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 600366#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 600365#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 600364#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 600363#L807-3 assume !(1 == ~E_3~0); 600362#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 600359#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 600356#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 600353#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 600339#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 600331#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 600327#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 600323#L1072 assume !(0 == start_simulation_~tmp~3#1); 600324#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 603664#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 603662#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 603660#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 603658#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 603656#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 603653#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 603651#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 583299#L1053-2 [2022-12-13 14:57:06,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:06,696 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2022-12-13 14:57:06,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:06,696 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753373666] [2022-12-13 14:57:06,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:06,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:06,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:06,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:06,729 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:06,729 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753373666] [2022-12-13 14:57:06,729 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1753373666] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:06,729 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:06,729 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:06,729 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1133479679] [2022-12-13 14:57:06,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:06,730 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:57:06,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:06,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1817893732, now seen corresponding path program 1 times [2022-12-13 14:57:06,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:06,730 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945976890] [2022-12-13 14:57:06,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:06,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:06,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:06,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:06,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:06,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1945976890] [2022-12-13 14:57:06,754 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1945976890] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:06,754 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:06,754 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:06,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [30568185] [2022-12-13 14:57:06,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:06,754 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:06,755 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:06,755 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:57:06,755 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:57:06,755 INFO L87 Difference]: Start difference. First operand 49132 states and 69314 transitions. cyclomatic complexity: 20198 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:06,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:06,955 INFO L93 Difference]: Finished difference Result 60187 states and 84509 transitions. [2022-12-13 14:57:06,955 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60187 states and 84509 transitions. [2022-12-13 14:57:07,137 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 59708 [2022-12-13 14:57:07,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60187 states to 60187 states and 84509 transitions. [2022-12-13 14:57:07,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60187 [2022-12-13 14:57:07,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60187 [2022-12-13 14:57:07,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60187 states and 84509 transitions. [2022-12-13 14:57:07,305 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:07,305 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60187 states and 84509 transitions. [2022-12-13 14:57:07,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60187 states and 84509 transitions. [2022-12-13 14:57:07,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60187 to 42180. [2022-12-13 14:57:07,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42180 states, 42180 states have (on average 1.4059743954480797) internal successors, (59304), 42179 states have internal predecessors, (59304), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:07,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42180 states to 42180 states and 59304 transitions. [2022-12-13 14:57:07,799 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42180 states and 59304 transitions. [2022-12-13 14:57:07,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:57:07,800 INFO L428 stractBuchiCegarLoop]: Abstraction has 42180 states and 59304 transitions. [2022-12-13 14:57:07,800 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 14:57:07,800 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42180 states and 59304 transitions. [2022-12-13 14:57:07,891 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 41843 [2022-12-13 14:57:07,891 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:07,891 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:07,892 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:07,892 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:07,892 INFO L748 eck$LassoCheckResult]: Stem: 692294#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 692295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 692441#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 692442#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 692080#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 692081#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 692437#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 692438#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 692358#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 692140#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 692141#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 692060#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 692061#L684 assume !(0 == ~M_E~0); 692574#L684-2 assume !(0 == ~T1_E~0); 692391#L689-1 assume !(0 == ~T2_E~0); 692392#L694-1 assume !(0 == ~T3_E~0); 692389#L699-1 assume !(0 == ~T4_E~0); 692390#L704-1 assume !(0 == ~T5_E~0); 692344#L709-1 assume !(0 == ~T6_E~0); 692272#L714-1 assume !(0 == ~E_M~0); 692273#L719-1 assume !(0 == ~E_1~0); 692539#L724-1 assume !(0 == ~E_2~0); 692031#L729-1 assume !(0 == ~E_3~0); 692032#L734-1 assume !(0 == ~E_4~0); 692617#L739-1 assume !(0 == ~E_5~0); 692228#L744-1 assume !(0 == ~E_6~0); 692229#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 691988#L334 assume !(1 == ~m_pc~0); 691989#L334-2 is_master_triggered_~__retres1~0#1 := 0; 692333#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 692231#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 692200#L849 assume !(0 != activate_threads_~tmp~1#1); 692201#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 692136#L353 assume !(1 == ~t1_pc~0); 692137#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 692444#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 692002#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 692003#L857 assume !(0 != activate_threads_~tmp___0~0#1); 692082#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 692083#L372 assume !(1 == ~t2_pc~0); 692188#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 692187#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 692328#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 692445#L865 assume !(0 != activate_threads_~tmp___1~0#1); 691977#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 691978#L391 assume !(1 == ~t3_pc~0); 691904#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 691905#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 691927#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 691928#L873 assume !(0 != activate_threads_~tmp___2~0#1); 692204#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 692205#L410 assume !(1 == ~t4_pc~0); 692461#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 692462#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 692097#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 692098#L881 assume !(0 != activate_threads_~tmp___3~0#1); 692214#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 692215#L429 assume !(1 == ~t5_pc~0); 692037#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 692038#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 692244#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 692245#L889 assume !(0 != activate_threads_~tmp___4~0#1); 692468#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 692199#L448 assume !(1 == ~t6_pc~0); 692118#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 692119#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 692426#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 692427#L897 assume !(0 != activate_threads_~tmp___5~0#1); 692646#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 692708#L762 assume !(1 == ~M_E~0); 692253#L762-2 assume !(1 == ~T1_E~0); 692254#L767-1 assume !(1 == ~T2_E~0); 692653#L772-1 assume !(1 == ~T3_E~0); 692501#L777-1 assume !(1 == ~T4_E~0); 692374#L782-1 assume !(1 == ~T5_E~0); 692064#L787-1 assume !(1 == ~T6_E~0); 692062#L792-1 assume !(1 == ~E_M~0); 692063#L797-1 assume !(1 == ~E_1~0); 692103#L802-1 assume !(1 == ~E_2~0); 692337#L807-1 assume !(1 == ~E_3~0); 692338#L812-1 assume !(1 == ~E_4~0); 692613#L817-1 assume !(1 == ~E_5~0); 692395#L822-1 assume !(1 == ~E_6~0); 692396#L827-1 assume { :end_inline_reset_delta_events } true; 692622#L1053-2 [2022-12-13 14:57:07,892 INFO L750 eck$LassoCheckResult]: Loop: 692622#L1053-2 assume !false; 710258#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 709105#L659 assume !false; 709093#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 707398#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 707392#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 707391#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 707389#L570 assume !(0 != eval_~tmp~0#1); 707388#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 707387#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 707386#L684-3 assume !(0 == ~M_E~0); 707385#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 707384#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 707383#L694-3 assume !(0 == ~T3_E~0); 707382#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 707381#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 707380#L709-3 assume !(0 == ~T6_E~0); 707379#L714-3 assume !(0 == ~E_M~0); 707378#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 707377#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 707376#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 707375#L734-3 assume !(0 == ~E_4~0); 707374#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 707373#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 707372#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 707371#L334-24 assume !(1 == ~m_pc~0); 707370#L334-26 is_master_triggered_~__retres1~0#1 := 0; 707369#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 707368#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 707367#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 707366#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 707365#L353-24 assume !(1 == ~t1_pc~0); 707364#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 707363#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 707362#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 707361#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 707360#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 707359#L372-24 assume !(1 == ~t2_pc~0); 707358#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 707356#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 707355#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 707354#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 707353#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 707352#L391-24 assume !(1 == ~t3_pc~0); 707351#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 707350#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 707349#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 707348#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 707347#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 707346#L410-24 assume !(1 == ~t4_pc~0); 707345#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 707344#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 707343#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 707342#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 707341#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 707340#L429-24 assume 1 == ~t5_pc~0; 707338#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 707337#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 707336#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 707334#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 707333#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 707332#L448-24 assume !(1 == ~t6_pc~0); 707331#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 707330#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 707329#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 707328#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 707327#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 707326#L762-3 assume !(1 == ~M_E~0); 705521#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 707325#L767-3 assume !(1 == ~T2_E~0); 707324#L772-3 assume !(1 == ~T3_E~0); 707323#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 707322#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 707321#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 707320#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 707319#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 707318#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 707317#L807-3 assume !(1 == ~E_3~0); 707316#L812-3 assume !(1 == ~E_4~0); 707315#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 707314#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 707306#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 707302#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 707296#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 707295#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 707021#L1072 assume !(0 == start_simulation_~tmp~3#1); 707022#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 711808#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 711807#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 711805#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 711802#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 711799#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 711798#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 711797#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 692622#L1053-2 [2022-12-13 14:57:07,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:07,892 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2022-12-13 14:57:07,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:07,893 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214065868] [2022-12-13 14:57:07,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:07,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:07,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:07,901 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:07,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:07,937 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:07,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:07,938 INFO L85 PathProgramCache]: Analyzing trace with hash 686716705, now seen corresponding path program 1 times [2022-12-13 14:57:07,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:07,938 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [115876897] [2022-12-13 14:57:07,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:07,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:07,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:07,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:07,965 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:07,965 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [115876897] [2022-12-13 14:57:07,965 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [115876897] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:07,966 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:07,966 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:07,966 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1480298685] [2022-12-13 14:57:07,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:07,966 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:07,966 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:07,966 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:57:07,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:57:07,967 INFO L87 Difference]: Start difference. First operand 42180 states and 59304 transitions. cyclomatic complexity: 17140 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:08,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:08,074 INFO L93 Difference]: Finished difference Result 49132 states and 68824 transitions. [2022-12-13 14:57:08,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49132 states and 68824 transitions. [2022-12-13 14:57:08,209 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48733 [2022-12-13 14:57:08,294 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49132 states to 49132 states and 68824 transitions. [2022-12-13 14:57:08,294 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49132 [2022-12-13 14:57:08,315 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49132 [2022-12-13 14:57:08,316 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49132 states and 68824 transitions. [2022-12-13 14:57:08,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:08,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49132 states and 68824 transitions. [2022-12-13 14:57:08,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49132 states and 68824 transitions. [2022-12-13 14:57:08,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49132 to 49132. [2022-12-13 14:57:08,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49132 states, 49132 states have (on average 1.4007978506879426) internal successors, (68824), 49131 states have internal predecessors, (68824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:08,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49132 states to 49132 states and 68824 transitions. [2022-12-13 14:57:08,675 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49132 states and 68824 transitions. [2022-12-13 14:57:08,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:57:08,676 INFO L428 stractBuchiCegarLoop]: Abstraction has 49132 states and 68824 transitions. [2022-12-13 14:57:08,676 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 14:57:08,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49132 states and 68824 transitions. [2022-12-13 14:57:08,780 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48733 [2022-12-13 14:57:08,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:08,780 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:08,781 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:08,781 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:08,781 INFO L748 eck$LassoCheckResult]: Stem: 783610#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 783611#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 783765#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 783766#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 783397#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 783398#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 783763#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 783764#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 783675#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 783457#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 783458#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 783378#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 783379#L684 assume !(0 == ~M_E~0); 783894#L684-2 assume !(0 == ~T1_E~0); 783710#L689-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 783711#L694-1 assume !(0 == ~T3_E~0); 784042#L699-1 assume !(0 == ~T4_E~0); 784090#L704-1 assume !(0 == ~T5_E~0); 784089#L709-1 assume !(0 == ~T6_E~0); 783591#L714-1 assume !(0 == ~E_M~0); 783592#L719-1 assume !(0 == ~E_1~0); 783861#L724-1 assume !(0 == ~E_2~0); 784087#L729-1 assume !(0 == ~E_3~0); 783996#L734-1 assume !(0 == ~E_4~0); 783938#L739-1 assume !(0 == ~E_5~0); 783939#L744-1 assume !(0 == ~E_6~0); 784085#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 783306#L334 assume !(1 == ~m_pc~0); 783307#L334-2 is_master_triggered_~__retres1~0#1 := 0; 783649#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 783946#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 783520#L849 assume !(0 != activate_threads_~tmp~1#1); 783521#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 783455#L353 assume !(1 == ~t1_pc~0); 783456#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 783925#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 784079#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 783731#L857 assume !(0 != activate_threads_~tmp___0~0#1); 783402#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 783403#L372 assume !(1 == ~t2_pc~0); 783508#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 783507#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 783643#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 784076#L865 assume !(0 != activate_threads_~tmp___1~0#1); 783295#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 783296#L391 assume !(1 == ~t3_pc~0); 783908#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 784074#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 784073#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 784072#L873 assume !(0 != activate_threads_~tmp___2~0#1); 783524#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 783525#L410 assume !(1 == ~t4_pc~0); 783783#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 783784#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 783416#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 783417#L881 assume !(0 != activate_threads_~tmp___3~0#1); 783926#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 783698#L429 assume !(1 == ~t5_pc~0); 783699#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 784063#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 784061#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 784059#L889 assume !(0 != activate_threads_~tmp___4~0#1); 784058#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 783517#L448 assume !(1 == ~t6_pc~0); 783438#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 783439#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 783789#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 783968#L897 assume !(0 != activate_threads_~tmp___5~0#1); 783969#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 784033#L762 assume !(1 == ~M_E~0); 783573#L762-2 assume !(1 == ~T1_E~0); 783574#L767-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 783977#L772-1 assume !(1 == ~T3_E~0); 783822#L777-1 assume !(1 == ~T4_E~0); 783691#L782-1 assume !(1 == ~T5_E~0); 783384#L787-1 assume !(1 == ~T6_E~0); 783382#L792-1 assume !(1 == ~E_M~0); 783383#L797-1 assume !(1 == ~E_1~0); 783421#L802-1 assume !(1 == ~E_2~0); 783653#L807-1 assume !(1 == ~E_3~0); 783654#L812-1 assume !(1 == ~E_4~0); 783933#L817-1 assume !(1 == ~E_5~0); 783713#L822-1 assume !(1 == ~E_6~0); 783714#L827-1 assume { :end_inline_reset_delta_events } true; 783945#L1053-2 [2022-12-13 14:57:08,781 INFO L750 eck$LassoCheckResult]: Loop: 783945#L1053-2 assume !false; 820911#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 820902#L659 assume !false; 820899#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 814148#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 814138#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 814133#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 814127#L570 assume !(0 != eval_~tmp~0#1); 814128#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 822457#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 822455#L684-3 assume !(0 == ~M_E~0); 822453#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 822450#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 822447#L694-3 assume !(0 == ~T3_E~0); 822445#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 822443#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 822441#L709-3 assume !(0 == ~T6_E~0); 822439#L714-3 assume !(0 == ~E_M~0); 822437#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 822435#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 822433#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 822431#L734-3 assume !(0 == ~E_4~0); 822429#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 822427#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 822425#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 822423#L334-24 assume !(1 == ~m_pc~0); 822421#L334-26 is_master_triggered_~__retres1~0#1 := 0; 822419#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 822417#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 822415#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 822413#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 822411#L353-24 assume !(1 == ~t1_pc~0); 822409#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 822407#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 822405#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 822403#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 822401#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 822399#L372-24 assume 1 == ~t2_pc~0; 822396#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 822393#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 822391#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 822389#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 822387#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 822385#L391-24 assume !(1 == ~t3_pc~0); 822383#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 822381#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 822379#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 822377#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 822375#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 822373#L410-24 assume !(1 == ~t4_pc~0); 822371#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 822369#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 822367#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 822365#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 822363#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 822361#L429-24 assume 1 == ~t5_pc~0; 822358#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 822355#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 822353#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 822347#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 822345#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 822343#L448-24 assume !(1 == ~t6_pc~0); 822341#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 822339#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 822337#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 822335#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 822333#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 822332#L762-3 assume !(1 == ~M_E~0); 822327#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 822325#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 822322#L772-3 assume !(1 == ~T3_E~0); 822320#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 822318#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 822316#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 822314#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 822312#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 822270#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 822266#L807-3 assume !(1 == ~E_3~0); 822262#L812-3 assume !(1 == ~E_4~0); 822257#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 822253#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 822250#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 822236#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 822227#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 822223#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 822218#L1072 assume !(0 == start_simulation_~tmp~3#1); 822214#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 821469#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 820991#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 820987#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 820985#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 820983#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 820981#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 820978#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 783945#L1053-2 [2022-12-13 14:57:08,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:08,782 INFO L85 PathProgramCache]: Analyzing trace with hash 2077618825, now seen corresponding path program 1 times [2022-12-13 14:57:08,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:08,782 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1601811749] [2022-12-13 14:57:08,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:08,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:08,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:08,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:08,815 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:08,815 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1601811749] [2022-12-13 14:57:08,815 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1601811749] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:08,816 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:08,816 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:08,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [263408622] [2022-12-13 14:57:08,816 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:08,816 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:57:08,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:08,817 INFO L85 PathProgramCache]: Analyzing trace with hash 305900766, now seen corresponding path program 1 times [2022-12-13 14:57:08,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:08,817 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729900163] [2022-12-13 14:57:08,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:08,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:08,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:08,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:08,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:08,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [729900163] [2022-12-13 14:57:08,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [729900163] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:08,846 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:08,846 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:08,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1653067743] [2022-12-13 14:57:08,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:08,846 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:08,846 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:08,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:57:08,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:57:08,847 INFO L87 Difference]: Start difference. First operand 49132 states and 68824 transitions. cyclomatic complexity: 19708 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:09,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:09,150 INFO L93 Difference]: Finished difference Result 61110 states and 85570 transitions. [2022-12-13 14:57:09,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61110 states and 85570 transitions. [2022-12-13 14:57:09,390 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 60637 [2022-12-13 14:57:09,536 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61110 states to 61110 states and 85570 transitions. [2022-12-13 14:57:09,536 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61110 [2022-12-13 14:57:09,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61110 [2022-12-13 14:57:09,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61110 states and 85570 transitions. [2022-12-13 14:57:09,598 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:09,598 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61110 states and 85570 transitions. [2022-12-13 14:57:09,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61110 states and 85570 transitions. [2022-12-13 14:57:09,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61110 to 42180. [2022-12-13 14:57:09,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42180 states, 42180 states have (on average 1.4033902323376009) internal successors, (59195), 42179 states have internal predecessors, (59195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:10,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42180 states to 42180 states and 59195 transitions. [2022-12-13 14:57:10,065 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42180 states and 59195 transitions. [2022-12-13 14:57:10,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:57:10,066 INFO L428 stractBuchiCegarLoop]: Abstraction has 42180 states and 59195 transitions. [2022-12-13 14:57:10,066 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 14:57:10,066 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42180 states and 59195 transitions. [2022-12-13 14:57:10,184 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 41843 [2022-12-13 14:57:10,184 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:10,184 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:10,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:10,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:10,186 INFO L748 eck$LassoCheckResult]: Stem: 893858#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 893859#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 894006#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 894007#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 893645#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 893646#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 894004#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 894005#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 893922#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 893707#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 893708#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 893626#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 893627#L684 assume !(0 == ~M_E~0); 894142#L684-2 assume !(0 == ~T1_E~0); 893958#L689-1 assume !(0 == ~T2_E~0); 893959#L694-1 assume !(0 == ~T3_E~0); 893956#L699-1 assume !(0 == ~T4_E~0); 893957#L704-1 assume !(0 == ~T5_E~0); 893907#L709-1 assume !(0 == ~T6_E~0); 893840#L714-1 assume !(0 == ~E_M~0); 893841#L719-1 assume !(0 == ~E_1~0); 894105#L724-1 assume !(0 == ~E_2~0); 893599#L729-1 assume !(0 == ~E_3~0); 893600#L734-1 assume !(0 == ~E_4~0); 894182#L739-1 assume !(0 == ~E_5~0); 893797#L744-1 assume !(0 == ~E_6~0); 893798#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 893557#L334 assume !(1 == ~m_pc~0); 893558#L334-2 is_master_triggered_~__retres1~0#1 := 0; 893898#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 893800#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 893770#L849 assume !(0 != activate_threads_~tmp~1#1); 893771#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 893705#L353 assume !(1 == ~t1_pc~0); 893706#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 894011#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 893571#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 893572#L857 assume !(0 != activate_threads_~tmp___0~0#1); 893650#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 893651#L372 assume !(1 == ~t2_pc~0); 893759#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 893758#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 893892#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 894012#L865 assume !(0 != activate_threads_~tmp___1~0#1); 893546#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 893547#L391 assume !(1 == ~t3_pc~0); 893474#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 893475#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 893497#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 893498#L873 assume !(0 != activate_threads_~tmp___2~0#1); 893774#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 893775#L410 assume !(1 == ~t4_pc~0); 894027#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 894028#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 893664#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 893665#L881 assume !(0 != activate_threads_~tmp___3~0#1); 893781#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 893782#L429 assume !(1 == ~t5_pc~0); 893605#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 893606#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 893814#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 893815#L889 assume !(0 != activate_threads_~tmp___4~0#1); 894033#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 893767#L448 assume !(1 == ~t6_pc~0); 893688#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 893689#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 893992#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 893993#L897 assume !(0 != activate_threads_~tmp___5~0#1); 894212#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 894274#L762 assume !(1 == ~M_E~0); 893820#L762-2 assume !(1 == ~T1_E~0); 893821#L767-1 assume !(1 == ~T2_E~0); 894221#L772-1 assume !(1 == ~T3_E~0); 894065#L777-1 assume !(1 == ~T4_E~0); 893938#L782-1 assume !(1 == ~T5_E~0); 893632#L787-1 assume !(1 == ~T6_E~0); 893630#L792-1 assume !(1 == ~E_M~0); 893631#L797-1 assume !(1 == ~E_1~0); 893670#L802-1 assume !(1 == ~E_2~0); 893902#L807-1 assume !(1 == ~E_3~0); 893903#L812-1 assume !(1 == ~E_4~0); 894176#L817-1 assume !(1 == ~E_5~0); 893960#L822-1 assume !(1 == ~E_6~0); 893961#L827-1 assume { :end_inline_reset_delta_events } true; 894187#L1053-2 [2022-12-13 14:57:10,186 INFO L750 eck$LassoCheckResult]: Loop: 894187#L1053-2 assume !false; 923002#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 923000#L659 assume !false; 922998#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 922990#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 922983#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 922981#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 922979#L570 assume !(0 != eval_~tmp~0#1); 922980#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 926777#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 926775#L684-3 assume !(0 == ~M_E~0); 926773#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 926771#L689-3 assume !(0 == ~T2_E~0); 926769#L694-3 assume !(0 == ~T3_E~0); 926767#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 926765#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 926763#L709-3 assume !(0 == ~T6_E~0); 926761#L714-3 assume !(0 == ~E_M~0); 926759#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 926757#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 926749#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 926747#L734-3 assume !(0 == ~E_4~0); 926745#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 926742#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 926740#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 926738#L334-24 assume !(1 == ~m_pc~0); 926736#L334-26 is_master_triggered_~__retres1~0#1 := 0; 926734#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 926732#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 926730#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 926728#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 926726#L353-24 assume !(1 == ~t1_pc~0); 926724#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 926722#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 926720#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 926718#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 926716#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 926714#L372-24 assume 1 == ~t2_pc~0; 926710#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 926708#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 926706#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 926704#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 926693#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 926686#L391-24 assume !(1 == ~t3_pc~0); 926679#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 926675#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 926004#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 926003#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 926002#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 926000#L410-24 assume !(1 == ~t4_pc~0); 925999#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 925998#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 925997#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 925996#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 925994#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 925992#L429-24 assume 1 == ~t5_pc~0; 925990#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 925991#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 926001#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 925980#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 925978#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 925976#L448-24 assume !(1 == ~t6_pc~0); 925973#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 925972#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 925948#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 925945#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 925943#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 925941#L762-3 assume !(1 == ~M_E~0); 908347#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 925938#L767-3 assume !(1 == ~T2_E~0); 925936#L772-3 assume !(1 == ~T3_E~0); 925933#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 925931#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 925929#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 925927#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 925925#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 925922#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 925919#L807-3 assume !(1 == ~E_3~0); 925917#L812-3 assume !(1 == ~E_4~0); 925915#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 925913#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 925911#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 925906#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 925899#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 925897#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 908470#L1072 assume !(0 == start_simulation_~tmp~3#1); 908471#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 923108#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 923107#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 923106#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 923105#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 923104#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 923103#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 923102#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 894187#L1053-2 [2022-12-13 14:57:10,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:10,186 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2022-12-13 14:57:10,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:10,187 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1784101101] [2022-12-13 14:57:10,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:10,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:10,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:10,196 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:10,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:10,216 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:10,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:10,217 INFO L85 PathProgramCache]: Analyzing trace with hash 2013207326, now seen corresponding path program 1 times [2022-12-13 14:57:10,217 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:10,217 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652448813] [2022-12-13 14:57:10,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:10,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:10,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:10,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:10,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:10,241 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652448813] [2022-12-13 14:57:10,241 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [652448813] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:10,241 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:10,241 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:10,242 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039511690] [2022-12-13 14:57:10,242 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:10,242 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:10,242 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:10,242 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:57:10,242 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:57:10,242 INFO L87 Difference]: Start difference. First operand 42180 states and 59195 transitions. cyclomatic complexity: 17031 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:10,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:10,468 INFO L93 Difference]: Finished difference Result 66103 states and 92328 transitions. [2022-12-13 14:57:10,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66103 states and 92328 transitions. [2022-12-13 14:57:10,720 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 65512 [2022-12-13 14:57:10,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66103 states to 66103 states and 92328 transitions. [2022-12-13 14:57:10,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66103 [2022-12-13 14:57:10,915 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66103 [2022-12-13 14:57:10,915 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66103 states and 92328 transitions. [2022-12-13 14:57:10,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:10,948 INFO L218 hiAutomatonCegarLoop]: Abstraction has 66103 states and 92328 transitions. [2022-12-13 14:57:10,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66103 states and 92328 transitions. [2022-12-13 14:57:11,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66103 to 66031. [2022-12-13 14:57:11,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66031 states, 66031 states have (on average 1.3971619390892156) internal successors, (92256), 66030 states have internal predecessors, (92256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:11,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66031 states to 66031 states and 92256 transitions. [2022-12-13 14:57:11,724 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66031 states and 92256 transitions. [2022-12-13 14:57:11,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:57:11,725 INFO L428 stractBuchiCegarLoop]: Abstraction has 66031 states and 92256 transitions. [2022-12-13 14:57:11,725 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 14:57:11,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66031 states and 92256 transitions. [2022-12-13 14:57:11,832 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 65440 [2022-12-13 14:57:11,833 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:11,833 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:11,833 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:11,833 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:11,834 INFO L748 eck$LassoCheckResult]: Stem: 1002160#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1002161#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1002320#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1002321#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1001939#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1001940#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1002318#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1002319#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1002230#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1002003#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1002004#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1001919#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1001920#L684 assume !(0 == ~M_E~0); 1002464#L684-2 assume !(0 == ~T1_E~0); 1002268#L689-1 assume !(0 == ~T2_E~0); 1002269#L694-1 assume !(0 == ~T3_E~0); 1002266#L699-1 assume !(0 == ~T4_E~0); 1002267#L704-1 assume !(0 == ~T5_E~0); 1002214#L709-1 assume !(0 == ~T6_E~0); 1002139#L714-1 assume !(0 == ~E_M~0); 1002140#L719-1 assume !(0 == ~E_1~0); 1002427#L724-1 assume !(0 == ~E_2~0); 1001890#L729-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1001891#L734-1 assume !(0 == ~E_4~0); 1002694#L739-1 assume !(0 == ~E_5~0); 1002095#L744-1 assume !(0 == ~E_6~0); 1002096#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1001846#L334 assume !(1 == ~m_pc~0); 1001847#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1002206#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1002098#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1002099#L849 assume !(0 != activate_threads_~tmp~1#1); 1002688#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1002687#L353 assume !(1 == ~t1_pc~0); 1002686#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1002325#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1001860#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1001861#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1002684#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1002574#L372 assume !(1 == ~t2_pc~0); 1002575#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1002683#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1002326#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1002327#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1002500#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1002681#L391 assume !(1 == ~t3_pc~0); 1002680#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1002679#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1002678#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1002677#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1002071#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1002072#L410 assume !(1 == ~t4_pc~0); 1002496#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1002675#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1002674#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1002673#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1002079#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1002080#L429 assume !(1 == ~t5_pc~0); 1001897#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1001898#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1002695#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1002349#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1002350#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1002384#L448 assume !(1 == ~t6_pc~0); 1002665#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1002664#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1002306#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1002307#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1002630#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1002631#L762 assume !(1 == ~M_E~0); 1002663#L762-2 assume !(1 == ~T1_E~0); 1002595#L767-1 assume !(1 == ~T2_E~0); 1002596#L772-1 assume !(1 == ~T3_E~0); 1002662#L777-1 assume !(1 == ~T4_E~0); 1002247#L782-1 assume !(1 == ~T5_E~0); 1002248#L787-1 assume !(1 == ~T6_E~0); 1001923#L792-1 assume !(1 == ~E_M~0); 1001924#L797-1 assume !(1 == ~E_1~0); 1001965#L802-1 assume !(1 == ~E_2~0); 1002210#L807-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1002211#L812-1 assume !(1 == ~E_4~0); 1002511#L817-1 assume !(1 == ~E_5~0); 1002270#L822-1 assume !(1 == ~E_6~0); 1002271#L827-1 assume { :end_inline_reset_delta_events } true; 1002526#L1053-2 [2022-12-13 14:57:11,834 INFO L750 eck$LassoCheckResult]: Loop: 1002526#L1053-2 assume !false; 1029655#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1009783#L659 assume !false; 1029654#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1029652#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1029646#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1029645#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1029643#L570 assume !(0 != eval_~tmp~0#1); 1029644#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1030195#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1030193#L684-3 assume !(0 == ~M_E~0); 1030191#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1030189#L689-3 assume !(0 == ~T2_E~0); 1030187#L694-3 assume !(0 == ~T3_E~0); 1030185#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1030183#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1030179#L709-3 assume !(0 == ~T6_E~0); 1030175#L714-3 assume !(0 == ~E_M~0); 1030171#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1030166#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1030160#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1030154#L734-3 assume !(0 == ~E_4~0); 1030148#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1030142#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1030136#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1030131#L334-24 assume !(1 == ~m_pc~0); 1030126#L334-26 is_master_triggered_~__retres1~0#1 := 0; 1030121#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1030116#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1030104#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1030099#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1030094#L353-24 assume !(1 == ~t1_pc~0); 1030088#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1030084#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1030079#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1030074#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1030066#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1030061#L372-24 assume !(1 == ~t2_pc~0); 1030056#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1030050#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1030045#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1030040#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 1030035#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1030030#L391-24 assume !(1 == ~t3_pc~0); 1030025#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1030020#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1030015#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1030009#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1030004#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1029999#L410-24 assume !(1 == ~t4_pc~0); 1029993#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1029987#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1029981#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1029976#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1029969#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1029939#L429-24 assume !(1 == ~t5_pc~0); 1029935#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 1029933#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1029931#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1029929#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 1029917#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1029909#L448-24 assume !(1 == ~t6_pc~0); 1029901#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1029893#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1029884#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1029875#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1029867#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1029858#L762-3 assume !(1 == ~M_E~0); 1029848#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1029842#L767-3 assume !(1 == ~T2_E~0); 1029837#L772-3 assume !(1 == ~T3_E~0); 1029830#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1029823#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1029816#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1029809#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1029803#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1029797#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1029791#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1029785#L812-3 assume !(1 == ~E_4~0); 1029780#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1029775#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1029769#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1029727#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1029716#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1029711#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1029705#L1072 assume !(0 == start_simulation_~tmp~3#1); 1029700#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1029690#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1029684#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1029679#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1029675#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1029669#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1029666#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1029661#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1002526#L1053-2 [2022-12-13 14:57:11,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:11,834 INFO L85 PathProgramCache]: Analyzing trace with hash -1576815991, now seen corresponding path program 1 times [2022-12-13 14:57:11,834 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:11,834 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039526564] [2022-12-13 14:57:11,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:11,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:11,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:11,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:11,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:11,862 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2039526564] [2022-12-13 14:57:11,862 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2039526564] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:11,862 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:11,862 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:11,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1646980747] [2022-12-13 14:57:11,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:11,863 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:57:11,863 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:11,863 INFO L85 PathProgramCache]: Analyzing trace with hash 2040888672, now seen corresponding path program 1 times [2022-12-13 14:57:11,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:11,863 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550512876] [2022-12-13 14:57:11,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:11,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:11,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:11,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:11,902 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:11,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [550512876] [2022-12-13 14:57:11,903 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [550512876] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:11,903 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:11,903 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:57:11,903 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [245028275] [2022-12-13 14:57:11,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:11,903 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:11,903 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:11,904 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 14:57:11,904 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 14:57:11,904 INFO L87 Difference]: Start difference. First operand 66031 states and 92256 transitions. cyclomatic complexity: 26241 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:12,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:12,139 INFO L93 Difference]: Finished difference Result 90273 states and 126090 transitions. [2022-12-13 14:57:12,139 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90273 states and 126090 transitions. [2022-12-13 14:57:12,452 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 86708 [2022-12-13 14:57:12,582 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90273 states to 90273 states and 126090 transitions. [2022-12-13 14:57:12,582 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90273 [2022-12-13 14:57:12,612 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90273 [2022-12-13 14:57:12,613 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90273 states and 126090 transitions. [2022-12-13 14:57:12,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:12,642 INFO L218 hiAutomatonCegarLoop]: Abstraction has 90273 states and 126090 transitions. [2022-12-13 14:57:12,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90273 states and 126090 transitions. [2022-12-13 14:57:13,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90273 to 63695. [2022-12-13 14:57:13,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63695 states, 63695 states have (on average 1.396498940262187) internal successors, (88950), 63694 states have internal predecessors, (88950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:13,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63695 states to 63695 states and 88950 transitions. [2022-12-13 14:57:13,376 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63695 states and 88950 transitions. [2022-12-13 14:57:13,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 14:57:13,377 INFO L428 stractBuchiCegarLoop]: Abstraction has 63695 states and 88950 transitions. [2022-12-13 14:57:13,377 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 14:57:13,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63695 states and 88950 transitions. [2022-12-13 14:57:13,566 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 63166 [2022-12-13 14:57:13,566 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:13,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:13,567 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:13,567 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:13,568 INFO L748 eck$LassoCheckResult]: Stem: 1158463#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1158464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1158612#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1158613#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1158253#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1158254#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1158610#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1158611#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1158530#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1158312#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1158313#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1158234#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1158235#L684 assume !(0 == ~M_E~0); 1158733#L684-2 assume !(0 == ~T1_E~0); 1158565#L689-1 assume !(0 == ~T2_E~0); 1158566#L694-1 assume !(0 == ~T3_E~0); 1158563#L699-1 assume !(0 == ~T4_E~0); 1158564#L704-1 assume !(0 == ~T5_E~0); 1158515#L709-1 assume !(0 == ~T6_E~0); 1158445#L714-1 assume !(0 == ~E_M~0); 1158446#L719-1 assume !(0 == ~E_1~0); 1158702#L724-1 assume !(0 == ~E_2~0); 1158207#L729-1 assume !(0 == ~E_3~0); 1158208#L734-1 assume !(0 == ~E_4~0); 1158772#L739-1 assume !(0 == ~E_5~0); 1158403#L744-1 assume !(0 == ~E_6~0); 1158404#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1158163#L334 assume !(1 == ~m_pc~0); 1158164#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1158507#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1158406#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1158377#L849 assume !(0 != activate_threads_~tmp~1#1); 1158378#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1158310#L353 assume !(1 == ~t1_pc~0); 1158311#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1158616#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1158177#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1158178#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1158258#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1158259#L372 assume !(1 == ~t2_pc~0); 1158365#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1158364#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1158501#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1158617#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1158152#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1158153#L391 assume !(1 == ~t3_pc~0); 1158079#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1158080#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1158102#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1158103#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1158381#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1158382#L410 assume !(1 == ~t4_pc~0); 1158631#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1158632#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1158272#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1158273#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1158387#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1158388#L429 assume !(1 == ~t5_pc~0); 1158213#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1158214#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1158420#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1158421#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1158637#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1158374#L448 assume !(1 == ~t6_pc~0); 1158294#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1158295#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1158599#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1158600#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1158798#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1158854#L762 assume !(1 == ~M_E~0); 1158425#L762-2 assume !(1 == ~T1_E~0); 1158426#L767-1 assume !(1 == ~T2_E~0); 1158804#L772-1 assume !(1 == ~T3_E~0); 1158667#L777-1 assume !(1 == ~T4_E~0); 1158546#L782-1 assume !(1 == ~T5_E~0); 1158240#L787-1 assume !(1 == ~T6_E~0); 1158238#L792-1 assume !(1 == ~E_M~0); 1158239#L797-1 assume !(1 == ~E_1~0); 1158278#L802-1 assume !(1 == ~E_2~0); 1158511#L807-1 assume !(1 == ~E_3~0); 1158512#L812-1 assume !(1 == ~E_4~0); 1158766#L817-1 assume !(1 == ~E_5~0); 1158567#L822-1 assume !(1 == ~E_6~0); 1158568#L827-1 assume { :end_inline_reset_delta_events } true; 1158777#L1053-2 [2022-12-13 14:57:13,568 INFO L750 eck$LassoCheckResult]: Loop: 1158777#L1053-2 assume !false; 1192086#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1191940#L659 assume !false; 1191935#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1191900#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1191889#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1191882#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1191877#L570 assume !(0 != eval_~tmp~0#1); 1191872#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1191868#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1191864#L684-3 assume !(0 == ~M_E~0); 1191858#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1191853#L689-3 assume !(0 == ~T2_E~0); 1191809#L694-3 assume !(0 == ~T3_E~0); 1191804#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1191799#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1191793#L709-3 assume !(0 == ~T6_E~0); 1191787#L714-3 assume !(0 == ~E_M~0); 1191779#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1191772#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1191765#L729-3 assume !(0 == ~E_3~0); 1191758#L734-3 assume !(0 == ~E_4~0); 1191751#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1191743#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1191735#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1191726#L334-24 assume !(1 == ~m_pc~0); 1191717#L334-26 is_master_triggered_~__retres1~0#1 := 0; 1191707#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1191697#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1191688#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1191678#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1191671#L353-24 assume !(1 == ~t1_pc~0); 1191663#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1191656#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1191645#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1191636#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1191629#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1191624#L372-24 assume 1 == ~t2_pc~0; 1191616#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1191610#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1191604#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1191599#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 1191593#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1191587#L391-24 assume !(1 == ~t3_pc~0); 1191581#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1191575#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1191569#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1191565#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1191552#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1191541#L410-24 assume !(1 == ~t4_pc~0); 1191537#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1191533#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1191476#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1191473#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1191463#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1191459#L429-24 assume 1 == ~t5_pc~0; 1191452#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1191446#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1191440#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1191434#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1191429#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1191423#L448-24 assume !(1 == ~t6_pc~0); 1191417#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1191414#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1191409#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1191404#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1191398#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1191393#L762-3 assume !(1 == ~M_E~0); 1188923#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1191382#L767-3 assume !(1 == ~T2_E~0); 1191375#L772-3 assume !(1 == ~T3_E~0); 1191368#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1191361#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1191355#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1191349#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1191343#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1191330#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1191317#L807-3 assume !(1 == ~E_3~0); 1191308#L812-3 assume !(1 == ~E_4~0); 1191300#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1191294#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1191290#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1190803#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1190795#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1190792#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1189059#L1072 assume !(0 == start_simulation_~tmp~3#1); 1189060#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1194678#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1194676#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1194674#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1194665#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1194648#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1194249#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1194246#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1158777#L1053-2 [2022-12-13 14:57:13,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:13,568 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2022-12-13 14:57:13,568 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:13,568 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [355801300] [2022-12-13 14:57:13,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:13,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:13,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:13,577 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:13,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:13,598 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:13,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:13,599 INFO L85 PathProgramCache]: Analyzing trace with hash -1394537124, now seen corresponding path program 1 times [2022-12-13 14:57:13,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:13,599 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140136613] [2022-12-13 14:57:13,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:13,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:13,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:13,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:13,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:13,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1140136613] [2022-12-13 14:57:13,635 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1140136613] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:13,635 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:13,635 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:57:13,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1257379139] [2022-12-13 14:57:13,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:13,635 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:13,635 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:13,636 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 14:57:13,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 14:57:13,636 INFO L87 Difference]: Start difference. First operand 63695 states and 88950 transitions. cyclomatic complexity: 25271 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:14,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:14,052 INFO L93 Difference]: Finished difference Result 112483 states and 155340 transitions. [2022-12-13 14:57:14,052 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 112483 states and 155340 transitions. [2022-12-13 14:57:14,396 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 111514 [2022-12-13 14:57:14,683 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 112483 states to 112483 states and 155340 transitions. [2022-12-13 14:57:14,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 112483 [2022-12-13 14:57:14,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 112483 [2022-12-13 14:57:14,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 112483 states and 155340 transitions. [2022-12-13 14:57:14,747 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:14,747 INFO L218 hiAutomatonCegarLoop]: Abstraction has 112483 states and 155340 transitions. [2022-12-13 14:57:14,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112483 states and 155340 transitions. [2022-12-13 14:57:15,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112483 to 64235. [2022-12-13 14:57:15,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64235 states, 64235 states have (on average 1.3931657196232583) internal successors, (89490), 64234 states have internal predecessors, (89490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:15,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64235 states to 64235 states and 89490 transitions. [2022-12-13 14:57:15,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64235 states and 89490 transitions. [2022-12-13 14:57:15,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 14:57:15,361 INFO L428 stractBuchiCegarLoop]: Abstraction has 64235 states and 89490 transitions. [2022-12-13 14:57:15,362 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 14:57:15,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64235 states and 89490 transitions. [2022-12-13 14:57:15,601 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 63706 [2022-12-13 14:57:15,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:15,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:15,602 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:15,602 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:15,602 INFO L748 eck$LassoCheckResult]: Stem: 1334667#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1334668#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1334823#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1334824#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1334452#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1334453#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1334819#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1334820#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1334730#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1334514#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1334515#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1334432#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1334433#L684 assume !(0 == ~M_E~0); 1334967#L684-2 assume !(0 == ~T1_E~0); 1334768#L689-1 assume !(0 == ~T2_E~0); 1334769#L694-1 assume !(0 == ~T3_E~0); 1334766#L699-1 assume !(0 == ~T4_E~0); 1334767#L704-1 assume !(0 == ~T5_E~0); 1334716#L709-1 assume !(0 == ~T6_E~0); 1334646#L714-1 assume !(0 == ~E_M~0); 1334647#L719-1 assume !(0 == ~E_1~0); 1334930#L724-1 assume !(0 == ~E_2~0); 1334400#L729-1 assume !(0 == ~E_3~0); 1334401#L734-1 assume !(0 == ~E_4~0); 1335012#L739-1 assume !(0 == ~E_5~0); 1334603#L744-1 assume !(0 == ~E_6~0); 1334604#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1334357#L334 assume !(1 == ~m_pc~0); 1334358#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1334705#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1334606#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1334574#L849 assume !(0 != activate_threads_~tmp~1#1); 1334575#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1334510#L353 assume !(1 == ~t1_pc~0); 1334511#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1334826#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1334371#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1334372#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1334454#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1334455#L372 assume !(1 == ~t2_pc~0); 1334563#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1334562#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1334699#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1334827#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1334345#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1334346#L391 assume !(1 == ~t3_pc~0); 1334273#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1334274#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1334296#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1334297#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1334578#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1334579#L410 assume !(1 == ~t4_pc~0); 1334846#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1334847#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1334469#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1334470#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1334589#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1334590#L429 assume !(1 == ~t5_pc~0); 1334406#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1334407#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1334621#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1334622#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1334851#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1334573#L448 assume !(1 == ~t6_pc~0); 1334493#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1334494#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1334807#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1334808#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1335042#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1335107#L762 assume !(1 == ~M_E~0); 1334629#L762-2 assume !(1 == ~T1_E~0); 1334630#L767-1 assume !(1 == ~T2_E~0); 1335051#L772-1 assume !(1 == ~T3_E~0); 1334891#L777-1 assume !(1 == ~T4_E~0); 1334746#L782-1 assume !(1 == ~T5_E~0); 1334436#L787-1 assume !(1 == ~T6_E~0); 1334434#L792-1 assume !(1 == ~E_M~0); 1334435#L797-1 assume !(1 == ~E_1~0); 1334477#L802-1 assume !(1 == ~E_2~0); 1334709#L807-1 assume !(1 == ~E_3~0); 1334710#L812-1 assume !(1 == ~E_4~0); 1335008#L817-1 assume !(1 == ~E_5~0); 1334770#L822-1 assume !(1 == ~E_6~0); 1334771#L827-1 assume { :end_inline_reset_delta_events } true; 1335016#L1053-2 [2022-12-13 14:57:15,603 INFO L750 eck$LassoCheckResult]: Loop: 1335016#L1053-2 assume !false; 1364776#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1339003#L659 assume !false; 1364775#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1364773#L518 assume !(0 == ~m_st~0); 1364774#L522 assume !(0 == ~t1_st~0); 1364769#L526 assume !(0 == ~t2_st~0); 1364770#L530 assume !(0 == ~t3_st~0); 1364772#L534 assume !(0 == ~t4_st~0); 1364767#L538 assume !(0 == ~t5_st~0); 1364768#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1364771#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1349708#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1349709#L570 assume !(0 != eval_~tmp~0#1); 1364764#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1364763#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1364762#L684-3 assume !(0 == ~M_E~0); 1364761#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1364760#L689-3 assume !(0 == ~T2_E~0); 1364759#L694-3 assume !(0 == ~T3_E~0); 1364758#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1364757#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1364756#L709-3 assume !(0 == ~T6_E~0); 1364755#L714-3 assume !(0 == ~E_M~0); 1364754#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1364753#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1364752#L729-3 assume !(0 == ~E_3~0); 1364751#L734-3 assume !(0 == ~E_4~0); 1364750#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1364749#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1364748#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1364747#L334-24 assume !(1 == ~m_pc~0); 1364746#L334-26 is_master_triggered_~__retres1~0#1 := 0; 1364745#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1364744#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1364743#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1364742#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1364741#L353-24 assume !(1 == ~t1_pc~0); 1364740#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1364739#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1364738#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1364737#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1364736#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1364735#L372-24 assume 1 == ~t2_pc~0; 1364733#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1364732#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1364731#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1364730#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 1364729#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1364728#L391-24 assume !(1 == ~t3_pc~0); 1364727#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1364726#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1364725#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1364724#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1364723#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1364722#L410-24 assume !(1 == ~t4_pc~0); 1364721#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1364720#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1364719#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1364718#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1364717#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1364716#L429-24 assume 1 == ~t5_pc~0; 1364714#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1364712#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1364710#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1364708#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1364707#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1364706#L448-24 assume !(1 == ~t6_pc~0); 1364705#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1364704#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1364703#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1364702#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1364701#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1364700#L762-3 assume !(1 == ~M_E~0); 1364552#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1364699#L767-3 assume !(1 == ~T2_E~0); 1364698#L772-3 assume !(1 == ~T3_E~0); 1364697#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1364696#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1364695#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1364694#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1364693#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1364692#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1364691#L807-3 assume !(1 == ~E_3~0); 1364690#L812-3 assume !(1 == ~E_4~0); 1364689#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1364688#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1364687#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1364685#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1364679#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1364678#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1364676#L1072 assume !(0 == start_simulation_~tmp~3#1); 1364677#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1364783#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1364782#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1364781#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1364780#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1364779#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1364778#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1364777#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1335016#L1053-2 [2022-12-13 14:57:15,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:15,603 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2022-12-13 14:57:15,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:15,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1524615854] [2022-12-13 14:57:15,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:15,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:15,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:15,613 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:15,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:15,641 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:15,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:15,642 INFO L85 PathProgramCache]: Analyzing trace with hash 632339179, now seen corresponding path program 1 times [2022-12-13 14:57:15,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:15,642 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921355014] [2022-12-13 14:57:15,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:15,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:15,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:15,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:15,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:15,671 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921355014] [2022-12-13 14:57:15,671 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1921355014] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:15,672 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:15,672 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:57:15,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203256313] [2022-12-13 14:57:15,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:15,672 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:15,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:15,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 14:57:15,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 14:57:15,673 INFO L87 Difference]: Start difference. First operand 64235 states and 89490 transitions. cyclomatic complexity: 25271 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:16,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:16,061 INFO L93 Difference]: Finished difference Result 125824 states and 173716 transitions. [2022-12-13 14:57:16,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125824 states and 173716 transitions. [2022-12-13 14:57:16,461 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 124808 [2022-12-13 14:57:16,859 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125824 states to 125824 states and 173716 transitions. [2022-12-13 14:57:16,859 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125824 [2022-12-13 14:57:16,908 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125824 [2022-12-13 14:57:16,908 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125824 states and 173716 transitions. [2022-12-13 14:57:16,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:16,959 INFO L218 hiAutomatonCegarLoop]: Abstraction has 125824 states and 173716 transitions. [2022-12-13 14:57:17,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125824 states and 173716 transitions. [2022-12-13 14:57:17,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125824 to 66842. [2022-12-13 14:57:17,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66842 states, 66842 states have (on average 1.3778313036713443) internal successors, (92097), 66841 states have internal predecessors, (92097), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:17,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66842 states to 66842 states and 92097 transitions. [2022-12-13 14:57:17,723 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66842 states and 92097 transitions. [2022-12-13 14:57:17,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-12-13 14:57:17,724 INFO L428 stractBuchiCegarLoop]: Abstraction has 66842 states and 92097 transitions. [2022-12-13 14:57:17,725 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 14:57:17,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66842 states and 92097 transitions. [2022-12-13 14:57:17,982 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 66310 [2022-12-13 14:57:17,982 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:17,982 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:17,982 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:17,983 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:17,983 INFO L748 eck$LassoCheckResult]: Stem: 1524729#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1524730#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1524884#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1524885#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1524523#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1524524#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1524882#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1524883#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1524798#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1524583#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1524584#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1524504#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1524505#L684 assume !(0 == ~M_E~0); 1525023#L684-2 assume !(0 == ~T1_E~0); 1524832#L689-1 assume !(0 == ~T2_E~0); 1524833#L694-1 assume !(0 == ~T3_E~0); 1524830#L699-1 assume !(0 == ~T4_E~0); 1524831#L704-1 assume !(0 == ~T5_E~0); 1524783#L709-1 assume !(0 == ~T6_E~0); 1524709#L714-1 assume !(0 == ~E_M~0); 1524710#L719-1 assume !(0 == ~E_1~0); 1524985#L724-1 assume !(0 == ~E_2~0); 1524474#L729-1 assume !(0 == ~E_3~0); 1524475#L734-1 assume !(0 == ~E_4~0); 1525065#L739-1 assume !(0 == ~E_5~0); 1524668#L744-1 assume !(0 == ~E_6~0); 1524669#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1524429#L334 assume !(1 == ~m_pc~0); 1524430#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1524774#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1524670#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1524641#L849 assume !(0 != activate_threads_~tmp~1#1); 1524642#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1524581#L353 assume !(1 == ~t1_pc~0); 1524582#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1524890#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1524443#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1524444#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1524528#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1524529#L372 assume !(1 == ~t2_pc~0); 1524632#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1524651#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1524768#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1525184#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1524418#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1524419#L391 assume !(1 == ~t3_pc~0); 1524346#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1524347#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1524369#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1524370#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1524645#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1524646#L410 assume !(1 == ~t4_pc~0); 1524907#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1524908#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1524543#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1524544#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1524653#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1524654#L429 assume !(1 == ~t5_pc~0); 1524480#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1524481#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1524684#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1524685#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1524913#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1524640#L448 assume !(1 == ~t6_pc~0); 1524565#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1524566#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1524870#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1524871#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1525097#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1525157#L762 assume !(1 == ~M_E~0); 1524689#L762-2 assume !(1 == ~T1_E~0); 1524690#L767-1 assume !(1 == ~T2_E~0); 1525105#L772-1 assume !(1 == ~T3_E~0); 1524949#L777-1 assume !(1 == ~T4_E~0); 1524814#L782-1 assume !(1 == ~T5_E~0); 1524510#L787-1 assume !(1 == ~T6_E~0); 1524508#L792-1 assume !(1 == ~E_M~0); 1524509#L797-1 assume !(1 == ~E_1~0); 1524548#L802-1 assume !(1 == ~E_2~0); 1524778#L807-1 assume !(1 == ~E_3~0); 1524779#L812-1 assume !(1 == ~E_4~0); 1525060#L817-1 assume !(1 == ~E_5~0); 1524834#L822-1 assume !(1 == ~E_6~0); 1524835#L827-1 assume { :end_inline_reset_delta_events } true; 1525071#L1053-2 [2022-12-13 14:57:17,983 INFO L750 eck$LassoCheckResult]: Loop: 1525071#L1053-2 assume !false; 1558540#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1558529#L659 assume !false; 1558528#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1558524#L518 assume !(0 == ~m_st~0); 1558525#L522 assume !(0 == ~t1_st~0); 1558521#L526 assume !(0 == ~t2_st~0); 1558522#L530 assume !(0 == ~t3_st~0); 1558523#L534 assume !(0 == ~t4_st~0); 1558520#L538 assume !(0 == ~t5_st~0); 1558519#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1558515#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1558512#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1558509#L570 assume !(0 != eval_~tmp~0#1); 1558507#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1558505#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1558503#L684-3 assume !(0 == ~M_E~0); 1558499#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1558498#L689-3 assume !(0 == ~T2_E~0); 1558497#L694-3 assume !(0 == ~T3_E~0); 1558495#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1558493#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1558491#L709-3 assume !(0 == ~T6_E~0); 1558489#L714-3 assume !(0 == ~E_M~0); 1558487#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1558485#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1558483#L729-3 assume !(0 == ~E_3~0); 1558481#L734-3 assume !(0 == ~E_4~0); 1558479#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1558477#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1558475#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1558472#L334-24 assume !(1 == ~m_pc~0); 1558468#L334-26 is_master_triggered_~__retres1~0#1 := 0; 1558463#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1558456#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1558451#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1558446#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1558441#L353-24 assume !(1 == ~t1_pc~0); 1558436#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1558430#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1558426#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1558422#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1558418#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1558417#L372-24 assume 1 == ~t2_pc~0; 1558416#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1558414#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1558412#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1558410#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1558397#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1558390#L391-24 assume !(1 == ~t3_pc~0); 1558384#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1558378#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1558372#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1558358#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1558344#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1558338#L410-24 assume !(1 == ~t4_pc~0); 1558331#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1558327#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1558322#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1558317#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1558311#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1558305#L429-24 assume !(1 == ~t5_pc~0); 1558299#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 1558292#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1558277#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1558270#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 1558263#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1558257#L448-24 assume !(1 == ~t6_pc~0); 1558252#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1558246#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1558241#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1558235#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1558230#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1558226#L762-3 assume !(1 == ~M_E~0); 1555827#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1558214#L767-3 assume !(1 == ~T2_E~0); 1558208#L772-3 assume !(1 == ~T3_E~0); 1558202#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1558197#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1558196#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1558195#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1558194#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1558193#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1558191#L807-3 assume !(1 == ~E_3~0); 1558189#L812-3 assume !(1 == ~E_4~0); 1558187#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1558185#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1556998#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1556960#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1556954#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1556952#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1556949#L1072 assume !(0 == start_simulation_~tmp~3#1); 1556950#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1558590#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1558585#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1558580#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1558576#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1558572#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1558563#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1558557#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1525071#L1053-2 [2022-12-13 14:57:17,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:17,983 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 5 times [2022-12-13 14:57:17,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:17,983 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734103681] [2022-12-13 14:57:17,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:17,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:17,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:17,989 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:17,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:18,014 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:18,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:18,014 INFO L85 PathProgramCache]: Analyzing trace with hash -1612495380, now seen corresponding path program 1 times [2022-12-13 14:57:18,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:18,015 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842745526] [2022-12-13 14:57:18,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:18,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:18,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:18,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:18,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:18,087 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842745526] [2022-12-13 14:57:18,087 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842745526] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:18,087 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:18,087 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 14:57:18,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027504815] [2022-12-13 14:57:18,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:18,087 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:18,087 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:18,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 14:57:18,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 14:57:18,088 INFO L87 Difference]: Start difference. First operand 66842 states and 92097 transitions. cyclomatic complexity: 25271 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:18,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:18,450 INFO L93 Difference]: Finished difference Result 118298 states and 161908 transitions. [2022-12-13 14:57:18,450 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118298 states and 161908 transitions. [2022-12-13 14:57:18,826 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 117638 [2022-12-13 14:57:19,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118298 states to 118298 states and 161908 transitions. [2022-12-13 14:57:19,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118298 [2022-12-13 14:57:19,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118298 [2022-12-13 14:57:19,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118298 states and 161908 transitions. [2022-12-13 14:57:19,252 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:19,252 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118298 states and 161908 transitions. [2022-12-13 14:57:19,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118298 states and 161908 transitions. [2022-12-13 14:57:19,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118298 to 67946. [2022-12-13 14:57:19,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67946 states, 67946 states have (on average 1.364318723692344) internal successors, (92700), 67945 states have internal predecessors, (92700), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:19,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67946 states to 67946 states and 92700 transitions. [2022-12-13 14:57:19,935 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67946 states and 92700 transitions. [2022-12-13 14:57:19,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 14:57:19,936 INFO L428 stractBuchiCegarLoop]: Abstraction has 67946 states and 92700 transitions. [2022-12-13 14:57:19,936 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 14:57:19,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67946 states and 92700 transitions. [2022-12-13 14:57:20,084 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 67414 [2022-12-13 14:57:20,084 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:20,085 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:20,085 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:20,085 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:20,085 INFO L748 eck$LassoCheckResult]: Stem: 1709886#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1709887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1710038#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1710039#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1709673#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1709674#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1710036#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1710037#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1709952#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1709735#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1709736#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1709654#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1709655#L684 assume !(0 == ~M_E~0); 1710171#L684-2 assume !(0 == ~T1_E~0); 1709987#L689-1 assume !(0 == ~T2_E~0); 1709988#L694-1 assume !(0 == ~T3_E~0); 1709985#L699-1 assume !(0 == ~T4_E~0); 1709986#L704-1 assume !(0 == ~T5_E~0); 1709937#L709-1 assume !(0 == ~T6_E~0); 1709867#L714-1 assume !(0 == ~E_M~0); 1709868#L719-1 assume !(0 == ~E_1~0); 1710139#L724-1 assume !(0 == ~E_2~0); 1709627#L729-1 assume !(0 == ~E_3~0); 1709628#L734-1 assume !(0 == ~E_4~0); 1710214#L739-1 assume !(0 == ~E_5~0); 1709824#L744-1 assume !(0 == ~E_6~0); 1709825#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1709583#L334 assume !(1 == ~m_pc~0); 1709584#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1709928#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1709827#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1709796#L849 assume !(0 != activate_threads_~tmp~1#1); 1709797#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1709733#L353 assume !(1 == ~t1_pc~0); 1709734#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1710042#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1709597#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1709598#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1709678#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1709679#L372 assume !(1 == ~t2_pc~0); 1709787#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1709805#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1709923#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1710333#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1709572#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1709573#L391 assume !(1 == ~t3_pc~0); 1709499#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1709500#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1709522#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1709523#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1709800#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1709801#L410 assume !(1 == ~t4_pc~0); 1710058#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1710059#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1709694#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1709695#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1709807#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1709808#L429 assume !(1 == ~t5_pc~0); 1709633#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1709634#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1709840#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1709841#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1710065#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1709795#L448 assume !(1 == ~t6_pc~0); 1709715#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1709716#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1710025#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1710026#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1710242#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1710308#L762 assume !(1 == ~M_E~0); 1709847#L762-2 assume !(1 == ~T1_E~0); 1709848#L767-1 assume !(1 == ~T2_E~0); 1710250#L772-1 assume !(1 == ~T3_E~0); 1710097#L777-1 assume !(1 == ~T4_E~0); 1709969#L782-1 assume !(1 == ~T5_E~0); 1709660#L787-1 assume !(1 == ~T6_E~0); 1709658#L792-1 assume !(1 == ~E_M~0); 1709659#L797-1 assume !(1 == ~E_1~0); 1709699#L802-1 assume !(1 == ~E_2~0); 1709932#L807-1 assume !(1 == ~E_3~0); 1709933#L812-1 assume !(1 == ~E_4~0); 1710208#L817-1 assume !(1 == ~E_5~0); 1709989#L822-1 assume !(1 == ~E_6~0); 1709990#L827-1 assume { :end_inline_reset_delta_events } true; 1710219#L1053-2 [2022-12-13 14:57:20,086 INFO L750 eck$LassoCheckResult]: Loop: 1710219#L1053-2 assume !false; 1723724#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1720878#L659 assume !false; 1723723#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1723721#L518 assume !(0 == ~m_st~0); 1723722#L522 assume !(0 == ~t1_st~0); 1723717#L526 assume !(0 == ~t2_st~0); 1723718#L530 assume !(0 == ~t3_st~0); 1723720#L534 assume !(0 == ~t4_st~0); 1723715#L538 assume !(0 == ~t5_st~0); 1723716#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1723719#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1727522#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1727519#L570 assume !(0 != eval_~tmp~0#1); 1727520#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1736762#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1736761#L684-3 assume !(0 == ~M_E~0); 1736760#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1736759#L689-3 assume !(0 == ~T2_E~0); 1736758#L694-3 assume !(0 == ~T3_E~0); 1736757#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1736756#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1736755#L709-3 assume !(0 == ~T6_E~0); 1736754#L714-3 assume !(0 == ~E_M~0); 1736753#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1736752#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1736751#L729-3 assume !(0 == ~E_3~0); 1736750#L734-3 assume !(0 == ~E_4~0); 1736749#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1736748#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1736747#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1736746#L334-24 assume !(1 == ~m_pc~0); 1736745#L334-26 is_master_triggered_~__retres1~0#1 := 0; 1736744#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1736743#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1736742#L849-24 assume !(0 != activate_threads_~tmp~1#1); 1736741#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1736740#L353-24 assume !(1 == ~t1_pc~0); 1736739#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1736738#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1736737#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1736736#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1736735#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1736734#L372-24 assume !(1 == ~t2_pc~0); 1727471#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1727468#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1727469#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1727441#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 1727442#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1727433#L391-24 assume !(1 == ~t3_pc~0); 1727434#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1727426#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1727427#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1727419#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1727420#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1736711#L410-24 assume !(1 == ~t4_pc~0); 1736710#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1727405#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1727406#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1727396#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1727397#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1727389#L429-24 assume 1 == ~t5_pc~0; 1727387#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1727388#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1727482#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1727373#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1727370#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1727367#L448-24 assume !(1 == ~t6_pc~0); 1727364#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1727361#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1727358#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1727354#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1727351#L897-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1727348#L762-3 assume !(1 == ~M_E~0); 1727343#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1727340#L767-3 assume !(1 == ~T2_E~0); 1727337#L772-3 assume !(1 == ~T3_E~0); 1727333#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1727329#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1727326#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1727323#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1727319#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1727316#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1727313#L807-3 assume !(1 == ~E_3~0); 1727311#L812-3 assume !(1 == ~E_4~0); 1727308#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1727305#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1727303#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1727186#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1727035#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1727027#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1723740#L1072 assume !(0 == start_simulation_~tmp~3#1); 1723738#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1723731#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1723730#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1723729#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1723728#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1723727#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1723726#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1723725#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1710219#L1053-2 [2022-12-13 14:57:20,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:20,086 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 6 times [2022-12-13 14:57:20,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:20,086 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405918970] [2022-12-13 14:57:20,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:20,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:20,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:20,094 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:20,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:20,106 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:20,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:20,106 INFO L85 PathProgramCache]: Analyzing trace with hash -813573330, now seen corresponding path program 1 times [2022-12-13 14:57:20,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:20,106 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1730770839] [2022-12-13 14:57:20,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:20,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:20,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:20,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:20,126 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:20,126 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1730770839] [2022-12-13 14:57:20,126 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1730770839] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:20,126 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:20,126 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:20,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1135598870] [2022-12-13 14:57:20,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:20,127 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 14:57:20,127 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:20,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:57:20,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:57:20,127 INFO L87 Difference]: Start difference. First operand 67946 states and 92700 transitions. cyclomatic complexity: 24770 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:20,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:20,351 INFO L93 Difference]: Finished difference Result 104059 states and 140150 transitions. [2022-12-13 14:57:20,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 104059 states and 140150 transitions. [2022-12-13 14:57:20,829 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 103533 [2022-12-13 14:57:21,020 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 104059 states to 104059 states and 140150 transitions. [2022-12-13 14:57:21,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 104059 [2022-12-13 14:57:21,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 104059 [2022-12-13 14:57:21,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104059 states and 140150 transitions. [2022-12-13 14:57:21,103 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:21,104 INFO L218 hiAutomatonCegarLoop]: Abstraction has 104059 states and 140150 transitions. [2022-12-13 14:57:21,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104059 states and 140150 transitions. [2022-12-13 14:57:21,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104059 to 101003. [2022-12-13 14:57:21,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101003 states, 101003 states have (on average 1.3489302297951546) internal successors, (136246), 101002 states have internal predecessors, (136246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:22,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101003 states to 101003 states and 136246 transitions. [2022-12-13 14:57:22,108 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101003 states and 136246 transitions. [2022-12-13 14:57:22,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:57:22,109 INFO L428 stractBuchiCegarLoop]: Abstraction has 101003 states and 136246 transitions. [2022-12-13 14:57:22,109 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 14:57:22,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101003 states and 136246 transitions. [2022-12-13 14:57:22,395 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 100477 [2022-12-13 14:57:22,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:22,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:22,396 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:22,396 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:22,396 INFO L748 eck$LassoCheckResult]: Stem: 1881908#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1881909#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1882069#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1882070#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1881688#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1881689#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1882065#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1882066#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1881975#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1881748#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1881749#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1881668#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1881669#L684 assume !(0 == ~M_E~0); 1882224#L684-2 assume !(0 == ~T1_E~0); 1882014#L689-1 assume !(0 == ~T2_E~0); 1882015#L694-1 assume !(0 == ~T3_E~0); 1882012#L699-1 assume !(0 == ~T4_E~0); 1882013#L704-1 assume !(0 == ~T5_E~0); 1881957#L709-1 assume !(0 == ~T6_E~0); 1881883#L714-1 assume !(0 == ~E_M~0); 1881884#L719-1 assume !(0 == ~E_1~0); 1882175#L724-1 assume !(0 == ~E_2~0); 1881639#L729-1 assume !(0 == ~E_3~0); 1881640#L734-1 assume !(0 == ~E_4~0); 1882269#L739-1 assume !(0 == ~E_5~0); 1881838#L744-1 assume !(0 == ~E_6~0); 1881839#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1881594#L334 assume !(1 == ~m_pc~0); 1881595#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1881946#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1881843#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1881810#L849 assume !(0 != activate_threads_~tmp~1#1); 1881811#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1881744#L353 assume !(1 == ~t1_pc~0); 1881745#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1882071#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1881608#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1881609#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1881690#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1881691#L372 assume !(1 == ~t2_pc~0); 1881800#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1881819#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1881940#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1882420#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1881583#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1881584#L391 assume !(1 == ~t3_pc~0); 1881510#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1881511#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1881533#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1881534#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1881814#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1881815#L410 assume !(1 == ~t4_pc~0); 1882088#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1882089#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1881705#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1881706#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1881824#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1881825#L429 assume !(1 == ~t5_pc~0); 1881645#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1881646#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1881857#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1881858#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1882096#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1881809#L448 assume !(1 == ~t6_pc~0); 1881728#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1881729#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1882055#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1882056#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1882304#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1882379#L762 assume !(1 == ~M_E~0); 1881865#L762-2 assume !(1 == ~T1_E~0); 1881866#L767-1 assume !(1 == ~T2_E~0); 1882314#L772-1 assume !(1 == ~T3_E~0); 1882135#L777-1 assume !(1 == ~T4_E~0); 1881993#L782-1 assume !(1 == ~T5_E~0); 1881672#L787-1 assume !(1 == ~T6_E~0); 1881670#L792-1 assume !(1 == ~E_M~0); 1881671#L797-1 assume !(1 == ~E_1~0); 1881712#L802-1 assume !(1 == ~E_2~0); 1881950#L807-1 assume !(1 == ~E_3~0); 1881951#L812-1 assume !(1 == ~E_4~0); 1882266#L817-1 assume !(1 == ~E_5~0); 1882018#L822-1 assume !(1 == ~E_6~0); 1882019#L827-1 assume { :end_inline_reset_delta_events } true; 1882274#L1053-2 assume !false; 1894280#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1894281#L659 [2022-12-13 14:57:22,396 INFO L750 eck$LassoCheckResult]: Loop: 1894281#L659 assume !false; 1914410#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1914408#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1914407#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1914406#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1914405#L570 assume 0 != eval_~tmp~0#1; 1914403#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1914402#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1914401#L575 assume !(0 == ~t1_st~0); 1914399#L589 assume !(0 == ~t2_st~0); 1914395#L603 assume !(0 == ~t3_st~0); 1914392#L617 assume !(0 == ~t4_st~0); 1914391#L631 assume !(0 == ~t5_st~0); 1914413#L645 assume !(0 == ~t6_st~0); 1894281#L659 [2022-12-13 14:57:22,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:22,397 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 1 times [2022-12-13 14:57:22,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:22,397 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911127470] [2022-12-13 14:57:22,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:22,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:22,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:22,406 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:22,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:22,422 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:22,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:22,422 INFO L85 PathProgramCache]: Analyzing trace with hash -1118388806, now seen corresponding path program 1 times [2022-12-13 14:57:22,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:22,423 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040692027] [2022-12-13 14:57:22,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:22,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:22,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:22,426 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:22,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:22,429 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:22,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:22,429 INFO L85 PathProgramCache]: Analyzing trace with hash 544337892, now seen corresponding path program 1 times [2022-12-13 14:57:22,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:22,430 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917609973] [2022-12-13 14:57:22,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:22,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:22,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:22,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:22,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:22,458 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917609973] [2022-12-13 14:57:22,458 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917609973] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:22,458 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:22,459 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:22,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1995717779] [2022-12-13 14:57:22,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:22,542 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:22,543 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:57:22,543 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:57:22,543 INFO L87 Difference]: Start difference. First operand 101003 states and 136246 transitions. cyclomatic complexity: 35273 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:23,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:23,083 INFO L93 Difference]: Finished difference Result 191242 states and 255589 transitions. [2022-12-13 14:57:23,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191242 states and 255589 transitions. [2022-12-13 14:57:23,634 INFO L131 ngComponentsAnalysis]: Automaton has 54 accepting balls. 184666 [2022-12-13 14:57:24,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191242 states to 191242 states and 255589 transitions. [2022-12-13 14:57:24,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191242 [2022-12-13 14:57:24,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191242 [2022-12-13 14:57:24,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191242 states and 255589 transitions. [2022-12-13 14:57:24,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:24,171 INFO L218 hiAutomatonCegarLoop]: Abstraction has 191242 states and 255589 transitions. [2022-12-13 14:57:24,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191242 states and 255589 transitions. [2022-12-13 14:57:25,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191242 to 186677. [2022-12-13 14:57:25,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186677 states, 186677 states have (on average 1.3385419735693203) internal successors, (249875), 186676 states have internal predecessors, (249875), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:26,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186677 states to 186677 states and 249875 transitions. [2022-12-13 14:57:26,079 INFO L240 hiAutomatonCegarLoop]: Abstraction has 186677 states and 249875 transitions. [2022-12-13 14:57:26,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:57:26,080 INFO L428 stractBuchiCegarLoop]: Abstraction has 186677 states and 249875 transitions. [2022-12-13 14:57:26,080 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-12-13 14:57:26,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186677 states and 249875 transitions. [2022-12-13 14:57:26,482 INFO L131 ngComponentsAnalysis]: Automaton has 54 accepting balls. 180101 [2022-12-13 14:57:26,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:26,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:26,482 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:26,482 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:26,483 INFO L748 eck$LassoCheckResult]: Stem: 2174165#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2174166#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2174332#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2174333#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2173942#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2173943#L475-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 2174328#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2174329#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2174237#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2174238#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2174511#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2174512#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2174577#L684 assume !(0 == ~M_E~0); 2174578#L684-2 assume !(0 == ~T1_E~0); 2174276#L689-1 assume !(0 == ~T2_E~0); 2174277#L694-1 assume !(0 == ~T3_E~0); 2174274#L699-1 assume !(0 == ~T4_E~0); 2174275#L704-1 assume !(0 == ~T5_E~0); 2174220#L709-1 assume !(0 == ~T6_E~0); 2174221#L714-1 assume !(0 == ~E_M~0); 2174447#L719-1 assume !(0 == ~E_1~0); 2174448#L724-1 assume !(0 == ~E_2~0); 2173890#L729-1 assume !(0 == ~E_3~0); 2173891#L734-1 assume !(0 == ~E_4~0); 2174546#L739-1 assume !(0 == ~E_5~0); 2174547#L744-1 assume !(0 == ~E_6~0); 2174450#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2174451#L334 assume !(1 == ~m_pc~0); 2174207#L334-2 is_master_triggered_~__retres1~0#1 := 0; 2174208#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2174102#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2174103#L849 assume !(0 != activate_threads_~tmp~1#1); 2174404#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2174405#L353 assume !(1 == ~t1_pc~0); 2174534#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2174535#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2173860#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2173861#L857 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2174298#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2174612#L372 assume !(1 == ~t2_pc~0); 2174613#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2174201#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2174202#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2174713#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2174530#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2174507#L391 assume !(1 == ~t3_pc~0); 2174508#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2173984#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2173985#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2174437#L873 assume !(0 != activate_threads_~tmp___2~0#1); 2174438#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2174526#L410 assume !(1 == ~t4_pc~0); 2174527#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2174410#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2174411#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2174536#L881 assume !(0 != activate_threads_~tmp___3~0#1); 2174537#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2174265#L429 assume !(1 == ~t5_pc~0); 2174266#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2174693#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2174694#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2174362#L889 assume !(0 != activate_threads_~tmp___4~0#1); 2174363#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2174068#L448 assume !(1 == ~t6_pc~0); 2174069#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2174358#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2174359#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2174583#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2174584#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2174673#L762 assume !(1 == ~M_E~0); 2174674#L762-2 assume !(1 == ~T1_E~0); 2174640#L767-1 assume !(1 == ~T2_E~0); 2174641#L772-1 assume !(1 == ~T3_E~0); 2174402#L777-1 assume !(1 == ~T4_E~0); 2174403#L782-1 assume !(1 == ~T5_E~0); 2173925#L787-1 assume !(1 == ~T6_E~0); 2173926#L792-1 assume !(1 == ~E_M~0); 2173967#L797-1 assume !(1 == ~E_1~0); 2173968#L802-1 assume !(1 == ~E_2~0); 2174213#L807-1 assume !(1 == ~E_3~0); 2174214#L812-1 assume !(1 == ~E_4~0); 2174659#L817-1 assume !(1 == ~E_5~0); 2174660#L822-1 assume !(1 == ~E_6~0); 2174555#L827-1 assume { :end_inline_reset_delta_events } true; 2174556#L1053-2 assume !false; 2189224#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2189216#L659 [2022-12-13 14:57:26,483 INFO L750 eck$LassoCheckResult]: Loop: 2189216#L659 assume !false; 2189209#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2189204#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2189200#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2189194#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2189189#L570 assume 0 != eval_~tmp~0#1; 2189190#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2202789#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 2189172#L575 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2189161#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 2189156#L589 assume !(0 == ~t2_st~0); 2189085#L603 assume !(0 == ~t3_st~0); 2189062#L617 assume !(0 == ~t4_st~0); 2189240#L631 assume !(0 == ~t5_st~0); 2189227#L645 assume !(0 == ~t6_st~0); 2189216#L659 [2022-12-13 14:57:26,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:26,483 INFO L85 PathProgramCache]: Analyzing trace with hash 1481595819, now seen corresponding path program 1 times [2022-12-13 14:57:26,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:26,483 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1306189609] [2022-12-13 14:57:26,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:26,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:26,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:26,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:26,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:26,500 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1306189609] [2022-12-13 14:57:26,500 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1306189609] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:26,500 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:26,500 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:26,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1648616331] [2022-12-13 14:57:26,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:26,501 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 14:57:26,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:26,501 INFO L85 PathProgramCache]: Analyzing trace with hash 751632524, now seen corresponding path program 1 times [2022-12-13 14:57:26,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:26,501 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887436750] [2022-12-13 14:57:26,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:26,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:26,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:26,505 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:26,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:26,508 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:26,596 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:26,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:57:26,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:57:26,596 INFO L87 Difference]: Start difference. First operand 186677 states and 249875 transitions. cyclomatic complexity: 63252 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:27,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:27,050 INFO L93 Difference]: Finished difference Result 150321 states and 201379 transitions. [2022-12-13 14:57:27,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 150321 states and 201379 transitions. [2022-12-13 14:57:27,514 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 149513 [2022-12-13 14:57:27,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 150321 states to 150321 states and 201379 transitions. [2022-12-13 14:57:27,923 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 150321 [2022-12-13 14:57:27,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 150321 [2022-12-13 14:57:27,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 150321 states and 201379 transitions. [2022-12-13 14:57:28,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:28,035 INFO L218 hiAutomatonCegarLoop]: Abstraction has 150321 states and 201379 transitions. [2022-12-13 14:57:28,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150321 states and 201379 transitions. [2022-12-13 14:57:29,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150321 to 150321. [2022-12-13 14:57:29,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 150321 states, 150321 states have (on average 1.3396597947059958) internal successors, (201379), 150320 states have internal predecessors, (201379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:29,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150321 states to 150321 states and 201379 transitions. [2022-12-13 14:57:29,449 INFO L240 hiAutomatonCegarLoop]: Abstraction has 150321 states and 201379 transitions. [2022-12-13 14:57:29,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:57:29,450 INFO L428 stractBuchiCegarLoop]: Abstraction has 150321 states and 201379 transitions. [2022-12-13 14:57:29,450 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-12-13 14:57:29,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 150321 states and 201379 transitions. [2022-12-13 14:57:29,927 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 149513 [2022-12-13 14:57:29,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:29,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:29,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:29,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:29,928 INFO L748 eck$LassoCheckResult]: Stem: 2511149#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2511150#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2511306#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2511307#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2510941#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2510942#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2511304#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2511305#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2511214#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2511000#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2511001#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2510922#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2510923#L684 assume !(0 == ~M_E~0); 2511445#L684-2 assume !(0 == ~T1_E~0); 2511254#L689-1 assume !(0 == ~T2_E~0); 2511255#L694-1 assume !(0 == ~T3_E~0); 2511252#L699-1 assume !(0 == ~T4_E~0); 2511253#L704-1 assume !(0 == ~T5_E~0); 2511199#L709-1 assume !(0 == ~T6_E~0); 2511131#L714-1 assume !(0 == ~E_M~0); 2511132#L719-1 assume !(0 == ~E_1~0); 2511405#L724-1 assume !(0 == ~E_2~0); 2510895#L729-1 assume !(0 == ~E_3~0); 2510896#L734-1 assume !(0 == ~E_4~0); 2511489#L739-1 assume !(0 == ~E_5~0); 2511091#L744-1 assume !(0 == ~E_6~0); 2511092#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2510850#L334 assume !(1 == ~m_pc~0); 2510851#L334-2 is_master_triggered_~__retres1~0#1 := 0; 2511189#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2511093#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2511063#L849 assume !(0 != activate_threads_~tmp~1#1); 2511064#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2510998#L353 assume !(1 == ~t1_pc~0); 2510999#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2511310#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2510864#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2510865#L857 assume !(0 != activate_threads_~tmp___0~0#1); 2510946#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2510947#L372 assume !(1 == ~t2_pc~0); 2511052#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2511072#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2511183#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2511608#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2510838#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2510839#L391 assume !(1 == ~t3_pc~0); 2510767#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2510768#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2510790#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2510791#L873 assume !(0 != activate_threads_~tmp___2~0#1); 2511067#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2511068#L410 assume !(1 == ~t4_pc~0); 2511325#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2511326#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2510960#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2510961#L881 assume !(0 != activate_threads_~tmp___3~0#1); 2511074#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2511075#L429 assume !(1 == ~t5_pc~0); 2510901#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2510902#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2511107#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2511108#L889 assume !(0 != activate_threads_~tmp___4~0#1); 2511331#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2511060#L448 assume !(1 == ~t6_pc~0); 2510982#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2510983#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2511292#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2511293#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2511517#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2511582#L762 assume !(1 == ~M_E~0); 2511112#L762-2 assume !(1 == ~T1_E~0); 2511113#L767-1 assume !(1 == ~T2_E~0); 2511526#L772-1 assume !(1 == ~T3_E~0); 2511366#L777-1 assume !(1 == ~T4_E~0); 2511232#L782-1 assume !(1 == ~T5_E~0); 2510928#L787-1 assume !(1 == ~T6_E~0); 2510926#L792-1 assume !(1 == ~E_M~0); 2510927#L797-1 assume !(1 == ~E_1~0); 2510965#L802-1 assume !(1 == ~E_2~0); 2511194#L807-1 assume !(1 == ~E_3~0); 2511195#L812-1 assume !(1 == ~E_4~0); 2511483#L817-1 assume !(1 == ~E_5~0); 2511256#L822-1 assume !(1 == ~E_6~0); 2511257#L827-1 assume { :end_inline_reset_delta_events } true; 2511494#L1053-2 assume !false; 2565284#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2565282#L659 [2022-12-13 14:57:29,928 INFO L750 eck$LassoCheckResult]: Loop: 2565282#L659 assume !false; 2565280#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2565227#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2565228#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2565385#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2565384#L570 assume 0 != eval_~tmp~0#1; 2565382#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2565380#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 2565378#L575 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2565376#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 2565374#L589 assume !(0 == ~t2_st~0); 2565369#L603 assume !(0 == ~t3_st~0); 2563064#L617 assume !(0 == ~t4_st~0); 2565290#L631 assume !(0 == ~t5_st~0); 2565286#L645 assume !(0 == ~t6_st~0); 2565282#L659 [2022-12-13 14:57:29,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:29,929 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 2 times [2022-12-13 14:57:29,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:29,929 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012646513] [2022-12-13 14:57:29,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:29,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:29,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:29,935 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:29,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:29,947 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:29,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:29,947 INFO L85 PathProgramCache]: Analyzing trace with hash 751632524, now seen corresponding path program 2 times [2022-12-13 14:57:29,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:29,948 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [47383314] [2022-12-13 14:57:29,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:29,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:29,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:29,950 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:29,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:29,952 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:29,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:29,952 INFO L85 PathProgramCache]: Analyzing trace with hash 756552610, now seen corresponding path program 1 times [2022-12-13 14:57:29,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:29,952 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2036388531] [2022-12-13 14:57:29,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:29,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:29,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:29,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:29,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:29,975 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2036388531] [2022-12-13 14:57:29,975 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2036388531] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:29,975 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:29,975 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:29,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766033017] [2022-12-13 14:57:29,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:30,063 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:30,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:57:30,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:57:30,063 INFO L87 Difference]: Start difference. First operand 150321 states and 201379 transitions. cyclomatic complexity: 51088 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:30,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:30,830 INFO L93 Difference]: Finished difference Result 282140 states and 376399 transitions. [2022-12-13 14:57:30,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 282140 states and 376399 transitions. [2022-12-13 14:57:31,666 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 280618 [2022-12-13 14:57:32,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 282140 states to 282140 states and 376399 transitions. [2022-12-13 14:57:32,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 282140 [2022-12-13 14:57:32,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 282140 [2022-12-13 14:57:32,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 282140 states and 376399 transitions. [2022-12-13 14:57:32,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:32,444 INFO L218 hiAutomatonCegarLoop]: Abstraction has 282140 states and 376399 transitions. [2022-12-13 14:57:32,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282140 states and 376399 transitions. [2022-12-13 14:57:34,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282140 to 268502. [2022-12-13 14:57:34,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 268502 states, 268502 states have (on average 1.3430626215074748) internal successors, (360615), 268501 states have internal predecessors, (360615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:35,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 268502 states to 268502 states and 360615 transitions. [2022-12-13 14:57:35,205 INFO L240 hiAutomatonCegarLoop]: Abstraction has 268502 states and 360615 transitions. [2022-12-13 14:57:35,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:57:35,207 INFO L428 stractBuchiCegarLoop]: Abstraction has 268502 states and 360615 transitions. [2022-12-13 14:57:35,207 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-12-13 14:57:35,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 268502 states and 360615 transitions. [2022-12-13 14:57:35,786 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 266980 [2022-12-13 14:57:35,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:35,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:35,786 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:35,786 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:35,786 INFO L748 eck$LassoCheckResult]: Stem: 2943627#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2943628#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2943792#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2943793#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2943407#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2943408#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2943790#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2943791#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2943699#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2943472#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2943473#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2943388#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2943389#L684 assume !(0 == ~M_E~0); 2943948#L684-2 assume !(0 == ~T1_E~0); 2943739#L689-1 assume !(0 == ~T2_E~0); 2943740#L694-1 assume !(0 == ~T3_E~0); 2943737#L699-1 assume !(0 == ~T4_E~0); 2943738#L704-1 assume !(0 == ~T5_E~0); 2943682#L709-1 assume !(0 == ~T6_E~0); 2943609#L714-1 assume !(0 == ~E_M~0); 2943610#L719-1 assume !(0 == ~E_1~0); 2943909#L724-1 assume !(0 == ~E_2~0); 2943360#L729-1 assume !(0 == ~E_3~0); 2943361#L734-1 assume !(0 == ~E_4~0); 2943995#L739-1 assume !(0 == ~E_5~0); 2943566#L744-1 assume !(0 == ~E_6~0); 2943567#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2943318#L334 assume !(1 == ~m_pc~0); 2943319#L334-2 is_master_triggered_~__retres1~0#1 := 0; 2943672#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2943570#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2943538#L849 assume !(0 != activate_threads_~tmp~1#1); 2943539#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2943470#L353 assume !(1 == ~t1_pc~0); 2943471#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2943796#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2943332#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2943333#L857 assume !(0 != activate_threads_~tmp___0~0#1); 2943412#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2943413#L372 assume !(1 == ~t2_pc~0); 2943529#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2943546#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2943667#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2944158#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2943307#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2943308#L391 assume !(1 == ~t3_pc~0); 2943236#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2943237#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2943259#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2943260#L873 assume !(0 != activate_threads_~tmp___2~0#1); 2943542#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2943543#L410 assume !(1 == ~t4_pc~0); 2943812#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2943813#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2943429#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2943430#L881 assume !(0 != activate_threads_~tmp___3~0#1); 2943548#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2943549#L429 assume !(1 == ~t5_pc~0); 2943366#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2943367#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2943582#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2943583#L889 assume !(0 != activate_threads_~tmp___4~0#1); 2943821#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2943537#L448 assume !(1 == ~t6_pc~0); 2943452#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2943453#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2943776#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2943777#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2944034#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2944118#L762 assume !(1 == ~M_E~0); 2943587#L762-2 assume !(1 == ~T1_E~0); 2943588#L767-1 assume !(1 == ~T2_E~0); 2944046#L772-1 assume !(1 == ~T3_E~0); 2943862#L777-1 assume !(1 == ~T4_E~0); 2943716#L782-1 assume !(1 == ~T5_E~0); 2943394#L787-1 assume !(1 == ~T6_E~0); 2943392#L792-1 assume !(1 == ~E_M~0); 2943393#L797-1 assume !(1 == ~E_1~0); 2943435#L802-1 assume !(1 == ~E_2~0); 2943677#L807-1 assume !(1 == ~E_3~0); 2943678#L812-1 assume !(1 == ~E_4~0); 2943990#L817-1 assume !(1 == ~E_5~0); 2943741#L822-1 assume !(1 == ~E_6~0); 2943742#L827-1 assume { :end_inline_reset_delta_events } true; 2944001#L1053-2 assume !false; 2972030#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2972031#L659 [2022-12-13 14:57:35,787 INFO L750 eck$LassoCheckResult]: Loop: 2972031#L659 assume !false; 2982618#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2982619#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2982611#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2982612#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2982604#L570 assume 0 != eval_~tmp~0#1; 2982605#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2982595#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 2982596#L575 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2958954#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 2958955#L589 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2968962#L606 assume !(0 != eval_~tmp_ndt_3~0#1); 2989007#L603 assume !(0 == ~t3_st~0); 2989002#L617 assume !(0 == ~t4_st~0); 2989001#L631 assume !(0 == ~t5_st~0); 2982628#L645 assume !(0 == ~t6_st~0); 2972031#L659 [2022-12-13 14:57:35,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:35,787 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 3 times [2022-12-13 14:57:35,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:35,787 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719916718] [2022-12-13 14:57:35,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:35,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:35,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:35,793 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:35,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:35,805 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:35,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:35,806 INFO L85 PathProgramCache]: Analyzing trace with hash 197462168, now seen corresponding path program 1 times [2022-12-13 14:57:35,806 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:35,806 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91882298] [2022-12-13 14:57:35,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:35,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:35,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:35,808 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:35,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:35,810 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:35,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:35,811 INFO L85 PathProgramCache]: Analyzing trace with hash 349984834, now seen corresponding path program 1 times [2022-12-13 14:57:35,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:35,811 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059084473] [2022-12-13 14:57:35,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:35,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:35,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:35,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:35,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:35,831 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059084473] [2022-12-13 14:57:35,831 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059084473] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:35,831 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:35,831 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:35,831 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665529545] [2022-12-13 14:57:35,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:35,918 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:35,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:57:35,918 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:57:35,919 INFO L87 Difference]: Start difference. First operand 268502 states and 360615 transitions. cyclomatic complexity: 92143 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:37,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:37,062 INFO L93 Difference]: Finished difference Result 451530 states and 605117 transitions. [2022-12-13 14:57:37,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 451530 states and 605117 transitions. [2022-12-13 14:57:38,887 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 448856 [2022-12-13 14:57:39,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 451530 states to 451530 states and 605117 transitions. [2022-12-13 14:57:39,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 451530 [2022-12-13 14:57:39,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 451530 [2022-12-13 14:57:39,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 451530 states and 605117 transitions. [2022-12-13 14:57:40,169 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:40,169 INFO L218 hiAutomatonCegarLoop]: Abstraction has 451530 states and 605117 transitions. [2022-12-13 14:57:40,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451530 states and 605117 transitions. [2022-12-13 14:57:43,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451530 to 440786. [2022-12-13 14:57:43,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 440786 states, 440786 states have (on average 1.342340727700063) internal successors, (591685), 440785 states have internal predecessors, (591685), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:44,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 440786 states to 440786 states and 591685 transitions. [2022-12-13 14:57:44,211 INFO L240 hiAutomatonCegarLoop]: Abstraction has 440786 states and 591685 transitions. [2022-12-13 14:57:44,211 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:57:44,212 INFO L428 stractBuchiCegarLoop]: Abstraction has 440786 states and 591685 transitions. [2022-12-13 14:57:44,212 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-12-13 14:57:44,212 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 440786 states and 591685 transitions. [2022-12-13 14:57:45,350 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 438112 [2022-12-13 14:57:45,350 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:45,350 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:45,351 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:45,351 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:45,351 INFO L748 eck$LassoCheckResult]: Stem: 3663661#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3663662#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3663832#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3663833#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3663448#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 3663449#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3663830#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3663831#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3663737#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3663511#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3663512#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3663429#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3663430#L684 assume !(0 == ~M_E~0); 3663984#L684-2 assume !(0 == ~T1_E~0); 3663779#L689-1 assume !(0 == ~T2_E~0); 3663780#L694-1 assume !(0 == ~T3_E~0); 3663777#L699-1 assume !(0 == ~T4_E~0); 3663778#L704-1 assume !(0 == ~T5_E~0); 3663718#L709-1 assume !(0 == ~T6_E~0); 3663642#L714-1 assume !(0 == ~E_M~0); 3663643#L719-1 assume !(0 == ~E_1~0); 3663939#L724-1 assume !(0 == ~E_2~0); 3663401#L729-1 assume !(0 == ~E_3~0); 3663402#L734-1 assume !(0 == ~E_4~0); 3664038#L739-1 assume !(0 == ~E_5~0); 3663600#L744-1 assume !(0 == ~E_6~0); 3663601#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3663358#L334 assume !(1 == ~m_pc~0); 3663359#L334-2 is_master_triggered_~__retres1~0#1 := 0; 3663708#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3663603#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3663573#L849 assume !(0 != activate_threads_~tmp~1#1); 3663574#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3663509#L353 assume !(1 == ~t1_pc~0); 3663510#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3663836#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3663372#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3663373#L857 assume !(0 != activate_threads_~tmp___0~0#1); 3663453#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3663454#L372 assume !(1 == ~t2_pc~0); 3663563#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3663582#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3663703#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3664204#L865 assume !(0 != activate_threads_~tmp___1~0#1); 3663347#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3663348#L391 assume !(1 == ~t3_pc~0); 3663276#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3663277#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3663299#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3663300#L873 assume !(0 != activate_threads_~tmp___2~0#1); 3663577#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3663578#L410 assume !(1 == ~t4_pc~0); 3663854#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3663855#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3663470#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3663471#L881 assume !(0 != activate_threads_~tmp___3~0#1); 3663584#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3663585#L429 assume !(1 == ~t5_pc~0); 3663407#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3663408#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3663616#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3663617#L889 assume !(0 != activate_threads_~tmp___4~0#1); 3663862#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3663572#L448 assume !(1 == ~t6_pc~0); 3663493#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3663494#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3663818#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3663819#L897 assume !(0 != activate_threads_~tmp___5~0#1); 3664082#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3664168#L762 assume !(1 == ~M_E~0); 3663621#L762-2 assume !(1 == ~T1_E~0); 3663622#L767-1 assume !(1 == ~T2_E~0); 3664093#L772-1 assume !(1 == ~T3_E~0); 3663898#L777-1 assume !(1 == ~T4_E~0); 3663753#L782-1 assume !(1 == ~T5_E~0); 3663435#L787-1 assume !(1 == ~T6_E~0); 3663433#L792-1 assume !(1 == ~E_M~0); 3663434#L797-1 assume !(1 == ~E_1~0); 3663476#L802-1 assume !(1 == ~E_2~0); 3663713#L807-1 assume !(1 == ~E_3~0); 3663714#L812-1 assume !(1 == ~E_4~0); 3664032#L817-1 assume !(1 == ~E_5~0); 3663781#L822-1 assume !(1 == ~E_6~0); 3663782#L827-1 assume { :end_inline_reset_delta_events } true; 3664045#L1053-2 assume !false; 3742189#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3742190#L659 [2022-12-13 14:57:45,352 INFO L750 eck$LassoCheckResult]: Loop: 3742190#L659 assume !false; 4015356#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4015355#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4015354#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4015353#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4015352#L570 assume 0 != eval_~tmp~0#1; 4015351#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 4015350#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 4015349#L575 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 4015347#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 4015346#L589 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 4015338#L606 assume !(0 != eval_~tmp_ndt_3~0#1); 4015345#L603 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 4015420#L620 assume !(0 != eval_~tmp_ndt_4~0#1); 4015419#L617 assume !(0 == ~t4_st~0); 4015362#L631 assume !(0 == ~t5_st~0); 4015359#L645 assume !(0 == ~t6_st~0); 3742190#L659 [2022-12-13 14:57:45,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:45,352 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 4 times [2022-12-13 14:57:45,352 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:45,352 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140235943] [2022-12-13 14:57:45,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:45,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:45,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:45,361 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:45,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:45,374 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:45,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:45,375 INFO L85 PathProgramCache]: Analyzing trace with hash 1635288494, now seen corresponding path program 1 times [2022-12-13 14:57:45,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:45,375 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [964077357] [2022-12-13 14:57:45,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:45,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:45,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:45,379 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:45,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:45,382 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:45,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:45,382 INFO L85 PathProgramCache]: Analyzing trace with hash 2068523844, now seen corresponding path program 1 times [2022-12-13 14:57:45,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:45,383 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1727570369] [2022-12-13 14:57:45,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:45,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:45,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:45,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:45,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:45,409 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1727570369] [2022-12-13 14:57:45,410 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1727570369] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:45,410 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:45,410 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:45,410 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677354566] [2022-12-13 14:57:45,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:45,523 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:45,524 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:57:45,524 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:57:45,524 INFO L87 Difference]: Start difference. First operand 440786 states and 591685 transitions. cyclomatic complexity: 150929 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:46,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:46,987 INFO L93 Difference]: Finished difference Result 534240 states and 712955 transitions. [2022-12-13 14:57:46,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 534240 states and 712955 transitions. [2022-12-13 14:57:48,771 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 531776 [2022-12-13 14:57:49,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 534240 states to 534240 states and 712955 transitions. [2022-12-13 14:57:49,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 534240 [2022-12-13 14:57:49,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 534240 [2022-12-13 14:57:49,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 534240 states and 712955 transitions. [2022-12-13 14:57:50,084 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:57:50,084 INFO L218 hiAutomatonCegarLoop]: Abstraction has 534240 states and 712955 transitions. [2022-12-13 14:57:50,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 534240 states and 712955 transitions. [2022-12-13 14:57:53,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 534240 to 516732. [2022-12-13 14:57:53,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 516732 states, 516732 states have (on average 1.3380069358971383) internal successors, (691391), 516731 states have internal predecessors, (691391), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:54,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 516732 states to 516732 states and 691391 transitions. [2022-12-13 14:57:54,827 INFO L240 hiAutomatonCegarLoop]: Abstraction has 516732 states and 691391 transitions. [2022-12-13 14:57:54,828 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 14:57:54,828 INFO L428 stractBuchiCegarLoop]: Abstraction has 516732 states and 691391 transitions. [2022-12-13 14:57:54,828 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-12-13 14:57:54,828 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 516732 states and 691391 transitions. [2022-12-13 14:57:56,401 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 514268 [2022-12-13 14:57:56,401 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 14:57:56,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 14:57:56,402 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:56,402 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 14:57:56,403 INFO L748 eck$LassoCheckResult]: Stem: 4638704#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4638705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4638870#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4638871#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4638487#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 4638488#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4638866#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4638867#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4638774#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4638547#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4638548#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4638466#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4638467#L684 assume !(0 == ~M_E~0); 4639034#L684-2 assume !(0 == ~T1_E~0); 4638813#L689-1 assume !(0 == ~T2_E~0); 4638814#L694-1 assume !(0 == ~T3_E~0); 4638811#L699-1 assume !(0 == ~T4_E~0); 4638812#L704-1 assume !(0 == ~T5_E~0); 4638759#L709-1 assume !(0 == ~T6_E~0); 4638681#L714-1 assume !(0 == ~E_M~0); 4638682#L719-1 assume !(0 == ~E_1~0); 4638983#L724-1 assume !(0 == ~E_2~0); 4638436#L729-1 assume !(0 == ~E_3~0); 4638437#L734-1 assume !(0 == ~E_4~0); 4639091#L739-1 assume !(0 == ~E_5~0); 4638636#L744-1 assume !(0 == ~E_6~0); 4638637#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4638393#L334 assume !(1 == ~m_pc~0); 4638394#L334-2 is_master_triggered_~__retres1~0#1 := 0; 4638747#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4638641#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4638607#L849 assume !(0 != activate_threads_~tmp~1#1); 4638608#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4638543#L353 assume !(1 == ~t1_pc~0); 4638544#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4638872#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4638407#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4638408#L857 assume !(0 != activate_threads_~tmp___0~0#1); 4638489#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4638490#L372 assume !(1 == ~t2_pc~0); 4638596#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4638616#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4638741#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4639258#L865 assume !(0 != activate_threads_~tmp___1~0#1); 4638381#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4638382#L391 assume !(1 == ~t3_pc~0); 4638310#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4638311#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4638333#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4638334#L873 assume !(0 != activate_threads_~tmp___2~0#1); 4638611#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4638612#L410 assume !(1 == ~t4_pc~0); 4638894#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4638895#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4638504#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4638505#L881 assume !(0 != activate_threads_~tmp___3~0#1); 4638622#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4638623#L429 assume !(1 == ~t5_pc~0); 4638442#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4638443#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4638652#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4638653#L889 assume !(0 != activate_threads_~tmp___4~0#1); 4638902#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4638606#L448 assume !(1 == ~t6_pc~0); 4638527#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4638528#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4638854#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4638855#L897 assume !(0 != activate_threads_~tmp___5~0#1); 4639129#L897-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4639216#L762 assume !(1 == ~M_E~0); 4638660#L762-2 assume !(1 == ~T1_E~0); 4638661#L767-1 assume !(1 == ~T2_E~0); 4639140#L772-1 assume !(1 == ~T3_E~0); 4638944#L777-1 assume !(1 == ~T4_E~0); 4638790#L782-1 assume !(1 == ~T5_E~0); 4638470#L787-1 assume !(1 == ~T6_E~0); 4638468#L792-1 assume !(1 == ~E_M~0); 4638469#L797-1 assume !(1 == ~E_1~0); 4638511#L802-1 assume !(1 == ~E_2~0); 4638752#L807-1 assume !(1 == ~E_3~0); 4638753#L812-1 assume !(1 == ~E_4~0); 4639088#L817-1 assume !(1 == ~E_5~0); 4638817#L822-1 assume !(1 == ~E_6~0); 4638818#L827-1 assume { :end_inline_reset_delta_events } true; 4639099#L1053-2 assume !false; 4731643#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4731644#L659 [2022-12-13 14:57:56,403 INFO L750 eck$LassoCheckResult]: Loop: 4731644#L659 assume !false; 4990595#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4990594#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4990593#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4990592#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4990591#L570 assume 0 != eval_~tmp~0#1; 4990590#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 4990589#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 4990588#L575 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 4990587#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 4990453#L589 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 4990451#L606 assume !(0 != eval_~tmp_ndt_3~0#1); 4990450#L603 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 4990448#L620 assume !(0 != eval_~tmp_ndt_4~0#1); 4990449#L617 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 4990656#L634 assume !(0 != eval_~tmp_ndt_5~0#1); 4990601#L631 assume !(0 == ~t5_st~0); 4990598#L645 assume !(0 == ~t6_st~0); 4731644#L659 [2022-12-13 14:57:56,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:56,403 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 5 times [2022-12-13 14:57:56,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:56,403 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [486450950] [2022-12-13 14:57:56,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:56,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:56,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:56,412 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:56,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:56,426 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:56,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:56,427 INFO L85 PathProgramCache]: Analyzing trace with hash -851825802, now seen corresponding path program 1 times [2022-12-13 14:57:56,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:56,427 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1029175016] [2022-12-13 14:57:56,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:56,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:56,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:56,430 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 14:57:56,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 14:57:56,432 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 14:57:56,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 14:57:56,433 INFO L85 PathProgramCache]: Analyzing trace with hash -306431840, now seen corresponding path program 1 times [2022-12-13 14:57:56,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 14:57:56,433 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1185957437] [2022-12-13 14:57:56,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 14:57:56,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 14:57:56,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 14:57:56,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 14:57:56,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 14:57:56,458 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1185957437] [2022-12-13 14:57:56,458 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1185957437] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 14:57:56,458 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 14:57:56,458 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 14:57:56,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1751791018] [2022-12-13 14:57:56,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 14:57:56,588 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 14:57:56,589 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 14:57:56,589 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 14:57:56,589 INFO L87 Difference]: Start difference. First operand 516732 states and 691391 transitions. cyclomatic complexity: 174689 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 14:57:58,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 14:57:58,852 INFO L93 Difference]: Finished difference Result 897128 states and 1200917 transitions. [2022-12-13 14:57:58,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 897128 states and 1200917 transitions. [2022-12-13 14:58:02,140 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 892294 [2022-12-13 14:58:03,839 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 897128 states to 897128 states and 1200917 transitions. [2022-12-13 14:58:03,839 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 897128 [2022-12-13 14:58:04,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 897128 [2022-12-13 14:58:04,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 897128 states and 1200917 transitions. [2022-12-13 14:58:04,408 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 14:58:04,409 INFO L218 hiAutomatonCegarLoop]: Abstraction has 897128 states and 1200917 transitions. [2022-12-13 14:58:04,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 897128 states and 1200917 transitions. [2022-12-13 14:58:10,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 897128 to 873732. [2022-12-13 14:58:11,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 873732 states, 873732 states have (on average 1.3432826083970828) internal successors, (1173669), 873731 states have internal predecessors, (1173669), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)