./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 19:42:10,519 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 19:42:10,521 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 19:42:10,541 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 19:42:10,541 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 19:42:10,542 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 19:42:10,543 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 19:42:10,545 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 19:42:10,547 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 19:42:10,548 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 19:42:10,549 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 19:42:10,550 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 19:42:10,550 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 19:42:10,551 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 19:42:10,552 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 19:42:10,553 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 19:42:10,554 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 19:42:10,555 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 19:42:10,557 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 19:42:10,558 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 19:42:10,560 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 19:42:10,561 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 19:42:10,562 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 19:42:10,563 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 19:42:10,567 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 19:42:10,567 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 19:42:10,567 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 19:42:10,568 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 19:42:10,569 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 19:42:10,570 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 19:42:10,570 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 19:42:10,571 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 19:42:10,571 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 19:42:10,572 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 19:42:10,573 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 19:42:10,573 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 19:42:10,574 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 19:42:10,574 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 19:42:10,574 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 19:42:10,575 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 19:42:10,576 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 19:42:10,576 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 19:42:10,598 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 19:42:10,598 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 19:42:10,599 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 19:42:10,599 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 19:42:10,600 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 19:42:10,600 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 19:42:10,600 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 19:42:10,601 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 19:42:10,601 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 19:42:10,601 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 19:42:10,601 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 19:42:10,601 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 19:42:10,602 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 19:42:10,602 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 19:42:10,602 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 19:42:10,602 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 19:42:10,602 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 19:42:10,603 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 19:42:10,603 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 19:42:10,603 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 19:42:10,603 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 19:42:10,603 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 19:42:10,604 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 19:42:10,604 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 19:42:10,604 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 19:42:10,604 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 19:42:10,604 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 19:42:10,604 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 19:42:10,604 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 19:42:10,605 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 19:42:10,605 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 19:42:10,605 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 19:42:10,606 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 [2022-12-13 19:42:10,770 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 19:42:10,786 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 19:42:10,788 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 19:42:10,789 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 19:42:10,789 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 19:42:10,790 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2022-12-13 19:42:13,397 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 19:42:13,590 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 19:42:13,591 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2022-12-13 19:42:13,602 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8/data/99336f377/65b2f74b10b84886b1b6928cbeca9a4a/FLAG495c044d7 [2022-12-13 19:42:13,615 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8/data/99336f377/65b2f74b10b84886b1b6928cbeca9a4a [2022-12-13 19:42:13,618 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 19:42:13,619 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 19:42:13,621 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 19:42:13,621 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 19:42:13,624 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 19:42:13,625 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 07:42:13" (1/1) ... [2022-12-13 19:42:13,626 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@621719c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13, skipping insertion in model container [2022-12-13 19:42:13,626 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 07:42:13" (1/1) ... [2022-12-13 19:42:13,634 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 19:42:13,672 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 19:42:13,813 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/sv-benchmarks/c/systemc/token_ring.08.cil-1.c[671,684] [2022-12-13 19:42:13,900 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 19:42:13,913 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 19:42:13,922 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/sv-benchmarks/c/systemc/token_ring.08.cil-1.c[671,684] [2022-12-13 19:42:13,958 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 19:42:13,977 INFO L208 MainTranslator]: Completed translation [2022-12-13 19:42:13,977 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13 WrapperNode [2022-12-13 19:42:13,977 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 19:42:13,978 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 19:42:13,979 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 19:42:13,979 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 19:42:13,986 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13" (1/1) ... [2022-12-13 19:42:13,996 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13" (1/1) ... [2022-12-13 19:42:14,046 INFO L138 Inliner]: procedures = 44, calls = 55, calls flagged for inlining = 50, calls inlined = 157, statements flattened = 2358 [2022-12-13 19:42:14,047 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 19:42:14,047 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 19:42:14,047 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 19:42:14,047 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 19:42:14,057 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13" (1/1) ... [2022-12-13 19:42:14,057 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13" (1/1) ... [2022-12-13 19:42:14,065 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13" (1/1) ... [2022-12-13 19:42:14,065 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13" (1/1) ... [2022-12-13 19:42:14,088 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13" (1/1) ... [2022-12-13 19:42:14,108 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13" (1/1) ... [2022-12-13 19:42:14,112 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13" (1/1) ... [2022-12-13 19:42:14,118 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13" (1/1) ... [2022-12-13 19:42:14,126 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 19:42:14,127 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 19:42:14,127 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 19:42:14,128 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 19:42:14,128 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13" (1/1) ... [2022-12-13 19:42:14,135 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 19:42:14,145 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 19:42:14,156 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 19:42:14,158 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b16b74fe-2ba7-4722-aebb-e391ef03cbf7/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 19:42:14,193 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 19:42:14,193 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 19:42:14,193 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 19:42:14,193 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 19:42:14,273 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 19:42:14,275 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 19:42:15,249 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 19:42:15,263 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 19:42:15,263 INFO L300 CfgBuilder]: Removed 11 assume(true) statements. [2022-12-13 19:42:15,266 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:42:15 BoogieIcfgContainer [2022-12-13 19:42:15,266 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 19:42:15,267 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 19:42:15,267 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 19:42:15,271 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 19:42:15,272 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:42:15,272 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 07:42:13" (1/3) ... [2022-12-13 19:42:15,273 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7a4a8ff3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 07:42:15, skipping insertion in model container [2022-12-13 19:42:15,273 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:42:15,273 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 07:42:13" (2/3) ... [2022-12-13 19:42:15,273 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7a4a8ff3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 07:42:15, skipping insertion in model container [2022-12-13 19:42:15,273 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 19:42:15,274 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 07:42:15" (3/3) ... [2022-12-13 19:42:15,275 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-1.c [2022-12-13 19:42:15,338 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 19:42:15,338 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 19:42:15,338 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 19:42:15,338 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 19:42:15,338 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 19:42:15,338 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 19:42:15,338 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 19:42:15,338 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 19:42:15,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 999 states, 998 states have (on average 1.5140280561122244) internal successors, (1511), 998 states have internal predecessors, (1511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:15,390 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 880 [2022-12-13 19:42:15,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:15,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:15,400 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:15,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:15,400 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 19:42:15,402 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 999 states, 998 states have (on average 1.5140280561122244) internal successors, (1511), 998 states have internal predecessors, (1511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:15,414 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 880 [2022-12-13 19:42:15,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:15,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:15,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:15,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:15,425 INFO L748 eck$LassoCheckResult]: Stem: 150#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 912#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 734#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 908#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 858#L597true assume !(1 == ~m_i~0);~m_st~0 := 2; 439#L597-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 978#L602-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 158#L607-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 486#L612-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 126#L617-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 278#L622-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 962#L627-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 260#L632-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 560#L637-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 496#L854true assume !(0 == ~M_E~0); 324#L854-2true assume !(0 == ~T1_E~0); 630#L859-1true assume !(0 == ~T2_E~0); 65#L864-1true assume !(0 == ~T3_E~0); 120#L869-1true assume !(0 == ~T4_E~0); 868#L874-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 806#L879-1true assume !(0 == ~T6_E~0); 316#L884-1true assume !(0 == ~T7_E~0); 8#L889-1true assume !(0 == ~T8_E~0); 166#L894-1true assume !(0 == ~E_M~0); 973#L899-1true assume !(0 == ~E_1~0); 501#L904-1true assume !(0 == ~E_2~0); 271#L909-1true assume !(0 == ~E_3~0); 430#L914-1true assume 0 == ~E_4~0;~E_4~0 := 1; 455#L919-1true assume !(0 == ~E_5~0); 213#L924-1true assume !(0 == ~E_6~0); 112#L929-1true assume !(0 == ~E_7~0); 825#L934-1true assume !(0 == ~E_8~0); 258#L939-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16#L418true assume !(1 == ~m_pc~0); 895#L418-2true is_master_triggered_~__retres1~0#1 := 0; 707#L429true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 633#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 617#L1061true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 524#L1061-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 881#L437true assume 1 == ~t1_pc~0; 966#L438true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 623#L448true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 183#L1069true assume !(0 != activate_threads_~tmp___0~0#1); 817#L1069-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 608#L456true assume !(1 == ~t2_pc~0); 428#L456-2true is_transmit2_triggered_~__retres1~2#1 := 0; 873#L467true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 235#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 650#L1077true assume !(0 != activate_threads_~tmp___1~0#1); 350#L1077-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63#L475true assume 1 == ~t3_pc~0; 291#L476true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 94#L486true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 788#L1085true assume !(0 != activate_threads_~tmp___2~0#1); 185#L1085-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 703#L494true assume !(1 == ~t4_pc~0); 209#L494-2true is_transmit4_triggered_~__retres1~4#1 := 0; 409#L505true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 945#L1093true assume !(0 != activate_threads_~tmp___3~0#1); 452#L1093-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 92#L513true assume 1 == ~t5_pc~0; 576#L514true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 903#L524true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 636#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68#L1101true assume !(0 != activate_threads_~tmp___4~0#1); 886#L1101-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49#L532true assume !(1 == ~t6_pc~0); 399#L532-2true is_transmit6_triggered_~__retres1~6#1 := 0; 296#L543true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 222#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 841#L1109true assume !(0 != activate_threads_~tmp___5~0#1); 170#L1109-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 654#L551true assume 1 == ~t7_pc~0; 664#L552true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 457#L562true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 926#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 997#L1117true assume !(0 != activate_threads_~tmp___6~0#1); 937#L1117-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 285#L570true assume 1 == ~t8_pc~0; 371#L571true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 740#L581true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 577#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 368#L1125true assume !(0 != activate_threads_~tmp___7~0#1); 60#L1125-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 627#L952true assume 1 == ~M_E~0;~M_E~0 := 2; 37#L952-2true assume !(1 == ~T1_E~0); 588#L957-1true assume !(1 == ~T2_E~0); 890#L962-1true assume !(1 == ~T3_E~0); 383#L967-1true assume !(1 == ~T4_E~0); 860#L972-1true assume !(1 == ~T5_E~0); 657#L977-1true assume !(1 == ~T6_E~0); 942#L982-1true assume !(1 == ~T7_E~0); 123#L987-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 127#L992-1true assume !(1 == ~E_M~0); 348#L997-1true assume !(1 == ~E_1~0); 812#L1002-1true assume !(1 == ~E_2~0); 338#L1007-1true assume !(1 == ~E_3~0); 9#L1012-1true assume !(1 == ~E_4~0); 557#L1017-1true assume !(1 == ~E_5~0); 341#L1022-1true assume !(1 == ~E_6~0); 362#L1027-1true assume 1 == ~E_7~0;~E_7~0 := 2; 814#L1032-1true assume !(1 == ~E_8~0); 479#L1037-1true assume { :end_inline_reset_delta_events } true; 580#L1303-2true [2022-12-13 19:42:15,427 INFO L750 eck$LassoCheckResult]: Loop: 580#L1303-2true assume !false; 618#L1304true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 893#L829true assume false; 581#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 367#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 467#L854-3true assume 0 == ~M_E~0;~M_E~0 := 1; 445#L854-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 957#L859-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 918#L864-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 800#L869-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 297#L874-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 349#L879-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 382#L884-3true assume !(0 == ~T7_E~0); 334#L889-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 107#L894-3true assume 0 == ~E_M~0;~E_M~0 := 1; 491#L899-3true assume 0 == ~E_1~0;~E_1~0 := 1; 125#L904-3true assume 0 == ~E_2~0;~E_2~0 := 1; 314#L909-3true assume 0 == ~E_3~0;~E_3~0 := 1; 97#L914-3true assume 0 == ~E_4~0;~E_4~0 := 1; 118#L919-3true assume 0 == ~E_5~0;~E_5~0 := 1; 721#L924-3true assume !(0 == ~E_6~0); 530#L929-3true assume 0 == ~E_7~0;~E_7~0 := 1; 432#L934-3true assume 0 == ~E_8~0;~E_8~0 := 1; 659#L939-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 562#L418-30true assume !(1 == ~m_pc~0); 376#L418-32true is_master_triggered_~__retres1~0#1 := 0; 573#L429-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 244#is_master_triggered_returnLabel#11true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 830#L1061-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 141#L1061-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 211#L437-30true assume 1 == ~t1_pc~0; 470#L438-10true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 366#L448-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 394#is_transmit1_triggered_returnLabel#11true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 901#L1069-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 874#L1069-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 188#L456-30true assume 1 == ~t2_pc~0; 709#L457-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 519#L467-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 187#is_transmit2_triggered_returnLabel#11true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 86#L1077-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 279#L1077-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 757#L475-30true assume 1 == ~t3_pc~0; 649#L476-10true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 444#L486-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 381#is_transmit3_triggered_returnLabel#11true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 892#L1085-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 201#L1085-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 989#L494-30true assume !(1 == ~t4_pc~0); 99#L494-32true is_transmit4_triggered_~__retres1~4#1 := 0; 3#L505-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 824#is_transmit4_triggered_returnLabel#11true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 911#L1093-30true assume !(0 != activate_threads_~tmp___3~0#1); 687#L1093-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 948#L513-30true assume 1 == ~t5_pc~0; 979#L514-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 332#L524-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 466#is_transmit5_triggered_returnLabel#11true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 545#L1101-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 787#L1101-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 288#L532-30true assume 1 == ~t6_pc~0; 949#L533-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62#L543-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74#is_transmit6_triggered_returnLabel#11true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 620#L1109-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 102#L1109-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 129#L551-30true assume 1 == ~t7_pc~0; 160#L552-10true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 634#L562-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 533#is_transmit7_triggered_returnLabel#11true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10#L1117-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 186#L1117-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 749#L570-30true assume 1 == ~t8_pc~0; 625#L571-10true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 128#L581-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 965#is_transmit8_triggered_returnLabel#11true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35#L1125-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 231#L1125-32true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 256#L952-3true assume 1 == ~M_E~0;~M_E~0 := 2; 950#L952-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 743#L957-3true assume !(1 == ~T2_E~0); 760#L962-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 606#L967-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 791#L972-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 500#L977-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 986#L982-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 969#L987-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 221#L992-3true assume 1 == ~E_M~0;~E_M~0 := 2; 357#L997-3true assume !(1 == ~E_1~0); 219#L1002-3true assume 1 == ~E_2~0;~E_2~0 := 2; 456#L1007-3true assume 1 == ~E_3~0;~E_3~0 := 2; 114#L1012-3true assume 1 == ~E_4~0;~E_4~0 := 2; 165#L1017-3true assume 1 == ~E_5~0;~E_5~0 := 2; 315#L1022-3true assume 1 == ~E_6~0;~E_6~0 := 2; 339#L1027-3true assume 1 == ~E_7~0;~E_7~0 := 2; 23#L1032-3true assume 1 == ~E_8~0;~E_8~0 := 2; 426#L1037-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 136#L650-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 759#L697-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 200#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 821#L1322true assume !(0 == start_simulation_~tmp~3#1); 241#L1322-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 58#L650-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 744#L697-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 24#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 17#L1277true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 502#L1284true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 380#stop_simulation_returnLabel#1true start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 662#L1335true assume !(0 != start_simulation_~tmp___0~1#1); 580#L1303-2true [2022-12-13 19:42:15,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:15,431 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2022-12-13 19:42:15,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:15,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287260963] [2022-12-13 19:42:15,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:15,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:15,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:15,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:15,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:15,645 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1287260963] [2022-12-13 19:42:15,645 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1287260963] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:15,646 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:15,646 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:15,647 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958876698] [2022-12-13 19:42:15,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:15,652 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:15,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:15,653 INFO L85 PathProgramCache]: Analyzing trace with hash -148249102, now seen corresponding path program 1 times [2022-12-13 19:42:15,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:15,653 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144438017] [2022-12-13 19:42:15,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:15,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:15,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:15,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:15,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:15,690 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144438017] [2022-12-13 19:42:15,690 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144438017] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:15,690 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:15,690 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:42:15,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1239121617] [2022-12-13 19:42:15,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:15,691 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:15,692 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:15,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:15,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:15,718 INFO L87 Difference]: Start difference. First operand has 999 states, 998 states have (on average 1.5140280561122244) internal successors, (1511), 998 states have internal predecessors, (1511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:15,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:15,782 INFO L93 Difference]: Finished difference Result 998 states and 1486 transitions. [2022-12-13 19:42:15,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1486 transitions. [2022-12-13 19:42:15,792 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:15,802 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 993 states and 1481 transitions. [2022-12-13 19:42:15,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-12-13 19:42:15,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-12-13 19:42:15,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1481 transitions. [2022-12-13 19:42:15,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:15,811 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1481 transitions. [2022-12-13 19:42:15,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1481 transitions. [2022-12-13 19:42:15,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-12-13 19:42:15,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4914400805639476) internal successors, (1481), 992 states have internal predecessors, (1481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:15,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1481 transitions. [2022-12-13 19:42:15,866 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1481 transitions. [2022-12-13 19:42:15,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:15,871 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1481 transitions. [2022-12-13 19:42:15,871 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 19:42:15,871 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1481 transitions. [2022-12-13 19:42:15,876 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:15,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:15,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:15,879 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:15,879 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:15,880 INFO L748 eck$LassoCheckResult]: Stem: 2318#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2319#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2944#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2945#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2983#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 2737#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2738#L602-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2335#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2336#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2270#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2271#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2530#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2503#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2504#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2787#L854 assume !(0 == ~M_E~0); 2593#L854-2 assume !(0 == ~T1_E~0); 2594#L859-1 assume !(0 == ~T2_E~0); 2150#L864-1 assume !(0 == ~T3_E~0); 2151#L869-1 assume !(0 == ~T4_E~0); 2261#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2969#L879-1 assume !(0 == ~T6_E~0); 2582#L884-1 assume !(0 == ~T7_E~0); 2021#L889-1 assume !(0 == ~T8_E~0); 2022#L894-1 assume !(0 == ~E_M~0); 2348#L899-1 assume !(0 == ~E_1~0); 2793#L904-1 assume !(0 == ~E_2~0); 2520#L909-1 assume !(0 == ~E_3~0); 2521#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2728#L919-1 assume !(0 == ~E_5~0); 2426#L924-1 assume !(0 == ~E_6~0); 2243#L929-1 assume !(0 == ~E_7~0); 2244#L934-1 assume !(0 == ~E_8~0); 2500#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2038#L418 assume !(1 == ~m_pc~0); 2013#L418-2 is_master_triggered_~__retres1~0#1 := 0; 2012#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2898#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2884#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2817#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2818#L437 assume 1 == ~t1_pc~0; 2986#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2891#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2059#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2060#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 2376#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2874#L456 assume !(1 == ~t2_pc~0); 2299#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2298#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2458#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2459#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 2631#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2144#L475 assume 1 == ~t3_pc~0; 2145#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2208#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2029#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2030#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 2379#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2380#L494 assume !(1 == ~t4_pc~0); 2420#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2421#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2160#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2161#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 2752#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2203#L513 assume 1 == ~t5_pc~0; 2204#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2422#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2900#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2157#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 2158#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2113#L532 assume !(1 == ~t6_pc~0); 2114#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2262#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2440#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2441#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 2352#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2353#L551 assume 1 == ~t7_pc~0; 2910#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2754#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2755#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2995#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 2996#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2540#L570 assume 1 == ~t8_pc~0; 2541#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2657#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2849#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2653#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 2138#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2139#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 2085#L952-2 assume !(1 == ~T1_E~0); 2086#L957-1 assume !(1 == ~T2_E~0); 2855#L962-1 assume !(1 == ~T3_E~0); 2669#L967-1 assume !(1 == ~T4_E~0); 2670#L972-1 assume !(1 == ~T5_E~0); 2913#L977-1 assume !(1 == ~T6_E~0); 2914#L982-1 assume !(1 == ~T7_E~0); 2264#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2265#L992-1 assume !(1 == ~E_M~0); 2272#L997-1 assume !(1 == ~E_1~0); 2629#L1002-1 assume !(1 == ~E_2~0); 2614#L1007-1 assume !(1 == ~E_3~0); 2023#L1012-1 assume !(1 == ~E_4~0); 2024#L1017-1 assume !(1 == ~E_5~0); 2617#L1022-1 assume !(1 == ~E_6~0); 2618#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2643#L1032-1 assume !(1 == ~E_8~0); 2775#L1037-1 assume { :end_inline_reset_delta_events } true; 2776#L1303-2 [2022-12-13 19:42:15,880 INFO L750 eck$LassoCheckResult]: Loop: 2776#L1303-2 assume !false; 2851#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2474#L829 assume !false; 2814#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2402#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2338#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2480#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2481#L712 assume !(0 != eval_~tmp~0#1); 2743#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2651#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2652#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2744#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2745#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2994#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2968#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2558#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2559#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2630#L884-3 assume !(0 == ~T7_E~0); 2608#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2234#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2235#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2268#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2269#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2213#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2214#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2257#L924-3 assume !(0 == ~E_6~0); 2820#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2730#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2731#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2839#L418-30 assume 1 == ~m_pc~0; 2100#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2101#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2471#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2472#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2300#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2301#L437-30 assume !(1 == ~t1_pc~0); 2423#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2649#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2650#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2687#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2985#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2383#L456-30 assume 1 == ~t2_pc~0; 2384#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2812#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2382#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2191#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2192#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2531#L475-30 assume !(1 == ~t3_pc~0); 2067#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2068#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2667#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2668#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2406#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2407#L494-30 assume !(1 == ~t4_pc~0); 2218#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2009#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2010#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2973#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 2922#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2923#L513-30 assume 1 == ~t5_pc~0; 2997#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2537#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2606#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2764#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2831#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2548#L532-30 assume !(1 == ~t6_pc~0); 2549#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2142#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2143#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2167#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2223#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2224#L551-30 assume 1 == ~t7_pc~0; 2275#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2340#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2821#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2025#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2026#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2381#L570-30 assume !(1 == ~t8_pc~0); 2736#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2273#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2274#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2081#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2082#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2452#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2497#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2949#L957-3 assume !(1 == ~T2_E~0); 2950#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2872#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2873#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2791#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2792#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2998#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2438#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2439#L997-3 assume !(1 == ~E_1~0); 2434#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2435#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2247#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2248#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2347#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2581#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2053#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2054#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2289#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2290#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2404#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2405#L1322 assume !(0 == start_simulation_~tmp~3#1); 2466#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2132#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2133#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2055#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2039#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2040#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2665#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2666#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 2776#L1303-2 [2022-12-13 19:42:15,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:15,881 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2022-12-13 19:42:15,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:15,882 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1513970869] [2022-12-13 19:42:15,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:15,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:15,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:15,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:15,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:15,960 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1513970869] [2022-12-13 19:42:15,961 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1513970869] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:15,961 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:15,961 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:15,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078064978] [2022-12-13 19:42:15,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:15,962 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:15,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:15,963 INFO L85 PathProgramCache]: Analyzing trace with hash -1527834734, now seen corresponding path program 1 times [2022-12-13 19:42:15,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:15,963 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426818493] [2022-12-13 19:42:15,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:15,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:15,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:16,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:16,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:16,065 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [426818493] [2022-12-13 19:42:16,065 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [426818493] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:16,066 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:16,066 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:16,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1311317846] [2022-12-13 19:42:16,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:16,066 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:16,067 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:16,067 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:16,067 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:16,067 INFO L87 Difference]: Start difference. First operand 993 states and 1481 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:16,085 INFO L93 Difference]: Finished difference Result 993 states and 1480 transitions. [2022-12-13 19:42:16,085 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1480 transitions. [2022-12-13 19:42:16,090 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,093 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1480 transitions. [2022-12-13 19:42:16,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-12-13 19:42:16,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-12-13 19:42:16,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1480 transitions. [2022-12-13 19:42:16,094 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:16,095 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1480 transitions. [2022-12-13 19:42:16,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1480 transitions. [2022-12-13 19:42:16,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-12-13 19:42:16,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4904330312185297) internal successors, (1480), 992 states have internal predecessors, (1480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1480 transitions. [2022-12-13 19:42:16,107 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1480 transitions. [2022-12-13 19:42:16,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:16,108 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1480 transitions. [2022-12-13 19:42:16,108 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 19:42:16,108 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1480 transitions. [2022-12-13 19:42:16,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:16,112 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:16,113 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,113 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,114 INFO L748 eck$LassoCheckResult]: Stem: 4311#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4312#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4937#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4938#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4976#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 4730#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4731#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4328#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4329#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4263#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4264#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4523#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4496#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4497#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4780#L854 assume !(0 == ~M_E~0); 4586#L854-2 assume !(0 == ~T1_E~0); 4587#L859-1 assume !(0 == ~T2_E~0); 4143#L864-1 assume !(0 == ~T3_E~0); 4144#L869-1 assume !(0 == ~T4_E~0); 4254#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4962#L879-1 assume !(0 == ~T6_E~0); 4575#L884-1 assume !(0 == ~T7_E~0); 4014#L889-1 assume !(0 == ~T8_E~0); 4015#L894-1 assume !(0 == ~E_M~0); 4341#L899-1 assume !(0 == ~E_1~0); 4786#L904-1 assume !(0 == ~E_2~0); 4513#L909-1 assume !(0 == ~E_3~0); 4514#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4721#L919-1 assume !(0 == ~E_5~0); 4419#L924-1 assume !(0 == ~E_6~0); 4236#L929-1 assume !(0 == ~E_7~0); 4237#L934-1 assume !(0 == ~E_8~0); 4493#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4031#L418 assume !(1 == ~m_pc~0); 4006#L418-2 is_master_triggered_~__retres1~0#1 := 0; 4005#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4891#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4877#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4810#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4811#L437 assume 1 == ~t1_pc~0; 4979#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4884#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4052#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4053#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 4369#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4867#L456 assume !(1 == ~t2_pc~0); 4292#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4291#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4451#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4452#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 4624#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4137#L475 assume 1 == ~t3_pc~0; 4138#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4201#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4022#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4023#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 4372#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4373#L494 assume !(1 == ~t4_pc~0); 4413#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4414#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4153#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4154#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 4745#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4196#L513 assume 1 == ~t5_pc~0; 4197#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4415#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4893#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4150#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 4151#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4106#L532 assume !(1 == ~t6_pc~0); 4107#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4255#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4433#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4434#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 4345#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4346#L551 assume 1 == ~t7_pc~0; 4903#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4747#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4748#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4988#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 4989#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4533#L570 assume 1 == ~t8_pc~0; 4534#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4650#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4842#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4646#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 4131#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4132#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 4078#L952-2 assume !(1 == ~T1_E~0); 4079#L957-1 assume !(1 == ~T2_E~0); 4848#L962-1 assume !(1 == ~T3_E~0); 4662#L967-1 assume !(1 == ~T4_E~0); 4663#L972-1 assume !(1 == ~T5_E~0); 4906#L977-1 assume !(1 == ~T6_E~0); 4907#L982-1 assume !(1 == ~T7_E~0); 4257#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4258#L992-1 assume !(1 == ~E_M~0); 4265#L997-1 assume !(1 == ~E_1~0); 4622#L1002-1 assume !(1 == ~E_2~0); 4607#L1007-1 assume !(1 == ~E_3~0); 4016#L1012-1 assume !(1 == ~E_4~0); 4017#L1017-1 assume !(1 == ~E_5~0); 4610#L1022-1 assume !(1 == ~E_6~0); 4611#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4636#L1032-1 assume !(1 == ~E_8~0); 4768#L1037-1 assume { :end_inline_reset_delta_events } true; 4769#L1303-2 [2022-12-13 19:42:16,114 INFO L750 eck$LassoCheckResult]: Loop: 4769#L1303-2 assume !false; 4844#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4467#L829 assume !false; 4807#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4395#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4331#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4473#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4474#L712 assume !(0 != eval_~tmp~0#1); 4736#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4644#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4645#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4737#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4738#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4987#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4961#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4551#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4552#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4623#L884-3 assume !(0 == ~T7_E~0); 4601#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4227#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4228#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4261#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4262#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4206#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4207#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4250#L924-3 assume !(0 == ~E_6~0); 4813#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4723#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4724#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4832#L418-30 assume 1 == ~m_pc~0; 4093#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4094#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4464#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4465#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4293#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4294#L437-30 assume !(1 == ~t1_pc~0); 4416#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 4642#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4643#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4680#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4978#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4376#L456-30 assume 1 == ~t2_pc~0; 4377#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4805#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4375#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4184#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4185#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4524#L475-30 assume 1 == ~t3_pc~0; 4899#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4061#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4660#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4661#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4399#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4400#L494-30 assume !(1 == ~t4_pc~0); 4211#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4002#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4003#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4966#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 4915#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4916#L513-30 assume !(1 == ~t5_pc~0); 4529#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 4530#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4599#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4757#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4824#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4541#L532-30 assume !(1 == ~t6_pc~0); 4542#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 4135#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4136#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4160#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4216#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4217#L551-30 assume 1 == ~t7_pc~0; 4268#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4333#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4814#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4018#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4019#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4374#L570-30 assume 1 == ~t8_pc~0; 4885#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4266#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4267#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4074#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4075#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4445#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4490#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4942#L957-3 assume !(1 == ~T2_E~0); 4943#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4865#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4866#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4784#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4785#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4991#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4431#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4432#L997-3 assume !(1 == ~E_1~0); 4427#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4428#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4240#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4241#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4340#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4574#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4046#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4047#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4282#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4283#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4398#L1322 assume !(0 == start_simulation_~tmp~3#1); 4459#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4125#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4126#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4048#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 4032#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4033#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4658#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4659#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 4769#L1303-2 [2022-12-13 19:42:16,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:16,115 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2022-12-13 19:42:16,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:16,115 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335488321] [2022-12-13 19:42:16,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:16,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:16,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:16,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:16,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:16,166 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335488321] [2022-12-13 19:42:16,166 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [335488321] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:16,166 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:16,167 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:16,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673390342] [2022-12-13 19:42:16,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:16,167 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:16,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:16,168 INFO L85 PathProgramCache]: Analyzing trace with hash -1603750319, now seen corresponding path program 1 times [2022-12-13 19:42:16,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:16,168 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798632573] [2022-12-13 19:42:16,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:16,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:16,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:16,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:16,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:16,232 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798632573] [2022-12-13 19:42:16,232 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1798632573] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:16,232 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:16,233 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:16,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [248502377] [2022-12-13 19:42:16,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:16,233 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:16,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:16,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:16,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:16,234 INFO L87 Difference]: Start difference. First operand 993 states and 1480 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:16,251 INFO L93 Difference]: Finished difference Result 993 states and 1479 transitions. [2022-12-13 19:42:16,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1479 transitions. [2022-12-13 19:42:16,254 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1479 transitions. [2022-12-13 19:42:16,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-12-13 19:42:16,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-12-13 19:42:16,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1479 transitions. [2022-12-13 19:42:16,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:16,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1479 transitions. [2022-12-13 19:42:16,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1479 transitions. [2022-12-13 19:42:16,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-12-13 19:42:16,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4894259818731117) internal successors, (1479), 992 states have internal predecessors, (1479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1479 transitions. [2022-12-13 19:42:16,270 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1479 transitions. [2022-12-13 19:42:16,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:16,271 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1479 transitions. [2022-12-13 19:42:16,271 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 19:42:16,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1479 transitions. [2022-12-13 19:42:16,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:16,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:16,283 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,283 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,283 INFO L748 eck$LassoCheckResult]: Stem: 6304#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6305#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6930#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6931#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6969#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 6723#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6724#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6321#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6322#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6256#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6257#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6516#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6489#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6490#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6773#L854 assume !(0 == ~M_E~0); 6579#L854-2 assume !(0 == ~T1_E~0); 6580#L859-1 assume !(0 == ~T2_E~0); 6136#L864-1 assume !(0 == ~T3_E~0); 6137#L869-1 assume !(0 == ~T4_E~0); 6247#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6955#L879-1 assume !(0 == ~T6_E~0); 6568#L884-1 assume !(0 == ~T7_E~0); 6007#L889-1 assume !(0 == ~T8_E~0); 6008#L894-1 assume !(0 == ~E_M~0); 6334#L899-1 assume !(0 == ~E_1~0); 6779#L904-1 assume !(0 == ~E_2~0); 6506#L909-1 assume !(0 == ~E_3~0); 6507#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6714#L919-1 assume !(0 == ~E_5~0); 6412#L924-1 assume !(0 == ~E_6~0); 6229#L929-1 assume !(0 == ~E_7~0); 6230#L934-1 assume !(0 == ~E_8~0); 6486#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6024#L418 assume !(1 == ~m_pc~0); 5999#L418-2 is_master_triggered_~__retres1~0#1 := 0; 5998#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6884#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6870#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6803#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6804#L437 assume 1 == ~t1_pc~0; 6972#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6877#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6045#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6046#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 6362#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6860#L456 assume !(1 == ~t2_pc~0); 6285#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6284#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6444#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6445#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 6617#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6130#L475 assume 1 == ~t3_pc~0; 6131#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6194#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6015#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6016#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 6365#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6366#L494 assume !(1 == ~t4_pc~0); 6406#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6407#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6146#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6147#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 6738#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6189#L513 assume 1 == ~t5_pc~0; 6190#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6408#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6886#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6143#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 6144#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6099#L532 assume !(1 == ~t6_pc~0); 6100#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6248#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6426#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6427#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 6338#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6339#L551 assume 1 == ~t7_pc~0; 6896#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6740#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6741#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6981#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 6982#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6526#L570 assume 1 == ~t8_pc~0; 6527#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6643#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6835#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6639#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 6124#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6125#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 6071#L952-2 assume !(1 == ~T1_E~0); 6072#L957-1 assume !(1 == ~T2_E~0); 6841#L962-1 assume !(1 == ~T3_E~0); 6655#L967-1 assume !(1 == ~T4_E~0); 6656#L972-1 assume !(1 == ~T5_E~0); 6899#L977-1 assume !(1 == ~T6_E~0); 6900#L982-1 assume !(1 == ~T7_E~0); 6250#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6251#L992-1 assume !(1 == ~E_M~0); 6258#L997-1 assume !(1 == ~E_1~0); 6615#L1002-1 assume !(1 == ~E_2~0); 6600#L1007-1 assume !(1 == ~E_3~0); 6009#L1012-1 assume !(1 == ~E_4~0); 6010#L1017-1 assume !(1 == ~E_5~0); 6603#L1022-1 assume !(1 == ~E_6~0); 6604#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 6629#L1032-1 assume !(1 == ~E_8~0); 6761#L1037-1 assume { :end_inline_reset_delta_events } true; 6762#L1303-2 [2022-12-13 19:42:16,284 INFO L750 eck$LassoCheckResult]: Loop: 6762#L1303-2 assume !false; 6837#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6460#L829 assume !false; 6800#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6388#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6324#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6466#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6467#L712 assume !(0 != eval_~tmp~0#1); 6729#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6637#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6638#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6730#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6731#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6980#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6954#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6544#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6545#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6616#L884-3 assume !(0 == ~T7_E~0); 6594#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6220#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6221#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6254#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6255#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6199#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6200#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6243#L924-3 assume !(0 == ~E_6~0); 6806#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6716#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6717#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6825#L418-30 assume 1 == ~m_pc~0; 6086#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6087#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6457#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6458#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6286#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6287#L437-30 assume !(1 == ~t1_pc~0); 6409#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 6635#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6636#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6673#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6971#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6369#L456-30 assume 1 == ~t2_pc~0; 6370#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6798#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6368#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6177#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6178#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6517#L475-30 assume !(1 == ~t3_pc~0); 6053#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 6054#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6653#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6654#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6392#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6393#L494-30 assume !(1 == ~t4_pc~0); 6204#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 5995#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5996#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6959#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 6908#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6909#L513-30 assume 1 == ~t5_pc~0; 6983#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6523#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6592#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6750#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6817#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6534#L532-30 assume !(1 == ~t6_pc~0); 6535#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 6128#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6129#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6153#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6209#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6210#L551-30 assume 1 == ~t7_pc~0; 6261#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6326#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6807#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6011#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6012#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6367#L570-30 assume !(1 == ~t8_pc~0); 6722#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 6259#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6260#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6067#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6068#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6438#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6483#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6935#L957-3 assume !(1 == ~T2_E~0); 6936#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6858#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6859#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6777#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6778#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6984#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6424#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6425#L997-3 assume !(1 == ~E_1~0); 6420#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6421#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6233#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6234#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6333#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6567#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6039#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6040#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6275#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6276#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6390#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6391#L1322 assume !(0 == start_simulation_~tmp~3#1); 6452#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6118#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6119#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6041#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 6025#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6026#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6651#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6652#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 6762#L1303-2 [2022-12-13 19:42:16,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:16,284 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2022-12-13 19:42:16,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:16,285 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566649349] [2022-12-13 19:42:16,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:16,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:16,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:16,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:16,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:16,327 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1566649349] [2022-12-13 19:42:16,327 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1566649349] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:16,327 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:16,328 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:16,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626597981] [2022-12-13 19:42:16,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:16,328 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:16,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:16,329 INFO L85 PathProgramCache]: Analyzing trace with hash -1527834734, now seen corresponding path program 2 times [2022-12-13 19:42:16,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:16,329 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500431690] [2022-12-13 19:42:16,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:16,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:16,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:16,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:16,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:16,382 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500431690] [2022-12-13 19:42:16,382 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [500431690] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:16,382 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:16,382 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:16,383 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1653127252] [2022-12-13 19:42:16,383 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:16,383 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:16,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:16,383 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:16,384 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:16,384 INFO L87 Difference]: Start difference. First operand 993 states and 1479 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:16,407 INFO L93 Difference]: Finished difference Result 993 states and 1478 transitions. [2022-12-13 19:42:16,407 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1478 transitions. [2022-12-13 19:42:16,413 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1478 transitions. [2022-12-13 19:42:16,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-12-13 19:42:16,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-12-13 19:42:16,418 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1478 transitions. [2022-12-13 19:42:16,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:16,420 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1478 transitions. [2022-12-13 19:42:16,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1478 transitions. [2022-12-13 19:42:16,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-12-13 19:42:16,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4884189325276937) internal successors, (1478), 992 states have internal predecessors, (1478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1478 transitions. [2022-12-13 19:42:16,438 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1478 transitions. [2022-12-13 19:42:16,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:16,439 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1478 transitions. [2022-12-13 19:42:16,439 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 19:42:16,439 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1478 transitions. [2022-12-13 19:42:16,443 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:16,443 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:16,445 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,445 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,446 INFO L748 eck$LassoCheckResult]: Stem: 8297#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8298#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8923#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8924#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8962#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 8716#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8717#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8314#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8315#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8249#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8250#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8509#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8482#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8483#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8766#L854 assume !(0 == ~M_E~0); 8572#L854-2 assume !(0 == ~T1_E~0); 8573#L859-1 assume !(0 == ~T2_E~0); 8129#L864-1 assume !(0 == ~T3_E~0); 8130#L869-1 assume !(0 == ~T4_E~0); 8240#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8948#L879-1 assume !(0 == ~T6_E~0); 8561#L884-1 assume !(0 == ~T7_E~0); 8000#L889-1 assume !(0 == ~T8_E~0); 8001#L894-1 assume !(0 == ~E_M~0); 8327#L899-1 assume !(0 == ~E_1~0); 8772#L904-1 assume !(0 == ~E_2~0); 8499#L909-1 assume !(0 == ~E_3~0); 8500#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8707#L919-1 assume !(0 == ~E_5~0); 8405#L924-1 assume !(0 == ~E_6~0); 8222#L929-1 assume !(0 == ~E_7~0); 8223#L934-1 assume !(0 == ~E_8~0); 8479#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8017#L418 assume !(1 == ~m_pc~0); 7992#L418-2 is_master_triggered_~__retres1~0#1 := 0; 7991#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8877#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8863#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8796#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8797#L437 assume 1 == ~t1_pc~0; 8965#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8870#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8038#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8039#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 8355#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8853#L456 assume !(1 == ~t2_pc~0); 8278#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8277#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8437#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8438#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 8610#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8123#L475 assume 1 == ~t3_pc~0; 8124#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8187#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8008#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8009#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 8358#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8359#L494 assume !(1 == ~t4_pc~0); 8399#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8400#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8139#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8140#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 8731#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8182#L513 assume 1 == ~t5_pc~0; 8183#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8401#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8879#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8136#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 8137#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8092#L532 assume !(1 == ~t6_pc~0); 8093#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8241#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8419#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8420#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 8331#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8332#L551 assume 1 == ~t7_pc~0; 8889#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8733#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8734#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8974#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 8975#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8519#L570 assume 1 == ~t8_pc~0; 8520#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8636#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8828#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8632#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 8117#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8118#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 8064#L952-2 assume !(1 == ~T1_E~0); 8065#L957-1 assume !(1 == ~T2_E~0); 8834#L962-1 assume !(1 == ~T3_E~0); 8648#L967-1 assume !(1 == ~T4_E~0); 8649#L972-1 assume !(1 == ~T5_E~0); 8892#L977-1 assume !(1 == ~T6_E~0); 8893#L982-1 assume !(1 == ~T7_E~0); 8243#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8244#L992-1 assume !(1 == ~E_M~0); 8251#L997-1 assume !(1 == ~E_1~0); 8608#L1002-1 assume !(1 == ~E_2~0); 8593#L1007-1 assume !(1 == ~E_3~0); 8002#L1012-1 assume !(1 == ~E_4~0); 8003#L1017-1 assume !(1 == ~E_5~0); 8596#L1022-1 assume !(1 == ~E_6~0); 8597#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 8622#L1032-1 assume !(1 == ~E_8~0); 8754#L1037-1 assume { :end_inline_reset_delta_events } true; 8755#L1303-2 [2022-12-13 19:42:16,446 INFO L750 eck$LassoCheckResult]: Loop: 8755#L1303-2 assume !false; 8830#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8453#L829 assume !false; 8793#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8381#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8317#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8459#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8460#L712 assume !(0 != eval_~tmp~0#1); 8722#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8630#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8631#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8723#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8724#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8973#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8947#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8537#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8538#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8609#L884-3 assume !(0 == ~T7_E~0); 8587#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8213#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8214#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8247#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8248#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8192#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8193#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8236#L924-3 assume !(0 == ~E_6~0); 8799#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8709#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8710#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8818#L418-30 assume !(1 == ~m_pc~0); 8081#L418-32 is_master_triggered_~__retres1~0#1 := 0; 8080#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8450#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8451#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8279#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8280#L437-30 assume !(1 == ~t1_pc~0); 8402#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 8628#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8629#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8666#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8964#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8362#L456-30 assume 1 == ~t2_pc~0; 8363#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8791#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8361#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8170#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8171#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8510#L475-30 assume 1 == ~t3_pc~0; 8885#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8047#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8646#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8647#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8385#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8386#L494-30 assume !(1 == ~t4_pc~0); 8197#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 7988#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7989#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8952#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 8901#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8902#L513-30 assume 1 == ~t5_pc~0; 8976#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8516#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8585#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8743#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8810#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8527#L532-30 assume !(1 == ~t6_pc~0); 8528#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 8121#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8122#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8146#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8202#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8203#L551-30 assume 1 == ~t7_pc~0; 8254#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8319#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8800#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8004#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8005#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8360#L570-30 assume 1 == ~t8_pc~0; 8871#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8252#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8253#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8060#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8061#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8431#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8476#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8928#L957-3 assume !(1 == ~T2_E~0); 8929#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8851#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8852#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8770#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8771#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8977#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8417#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8418#L997-3 assume !(1 == ~E_1~0); 8413#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8414#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8226#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8227#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8326#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8560#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8032#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8033#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8268#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8269#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8383#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8384#L1322 assume !(0 == start_simulation_~tmp~3#1); 8445#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8111#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8112#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8034#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 8018#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8019#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8644#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8645#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 8755#L1303-2 [2022-12-13 19:42:16,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:16,446 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2022-12-13 19:42:16,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:16,447 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464507626] [2022-12-13 19:42:16,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:16,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:16,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:16,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:16,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:16,473 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464507626] [2022-12-13 19:42:16,473 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1464507626] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:16,473 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:16,473 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:16,473 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1637126117] [2022-12-13 19:42:16,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:16,474 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:16,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:16,474 INFO L85 PathProgramCache]: Analyzing trace with hash -1712808303, now seen corresponding path program 1 times [2022-12-13 19:42:16,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:16,474 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882555859] [2022-12-13 19:42:16,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:16,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:16,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:16,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:16,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:16,509 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882555859] [2022-12-13 19:42:16,509 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882555859] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:16,510 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:16,510 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:16,510 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1158961891] [2022-12-13 19:42:16,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:16,510 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:16,510 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:16,511 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:16,511 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:16,511 INFO L87 Difference]: Start difference. First operand 993 states and 1478 transitions. cyclomatic complexity: 486 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:16,526 INFO L93 Difference]: Finished difference Result 993 states and 1477 transitions. [2022-12-13 19:42:16,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1477 transitions. [2022-12-13 19:42:16,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1477 transitions. [2022-12-13 19:42:16,532 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-12-13 19:42:16,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-12-13 19:42:16,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1477 transitions. [2022-12-13 19:42:16,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:16,533 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1477 transitions. [2022-12-13 19:42:16,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1477 transitions. [2022-12-13 19:42:16,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-12-13 19:42:16,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.487411883182276) internal successors, (1477), 992 states have internal predecessors, (1477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1477 transitions. [2022-12-13 19:42:16,557 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1477 transitions. [2022-12-13 19:42:16,558 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:16,558 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1477 transitions. [2022-12-13 19:42:16,558 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 19:42:16,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1477 transitions. [2022-12-13 19:42:16,563 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,563 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:16,563 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:16,565 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,565 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,565 INFO L748 eck$LassoCheckResult]: Stem: 10290#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10291#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10916#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10917#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10955#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 10709#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10710#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10307#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10308#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10242#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10243#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10502#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10475#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10476#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10759#L854 assume !(0 == ~M_E~0); 10565#L854-2 assume !(0 == ~T1_E~0); 10566#L859-1 assume !(0 == ~T2_E~0); 10122#L864-1 assume !(0 == ~T3_E~0); 10123#L869-1 assume !(0 == ~T4_E~0); 10233#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10941#L879-1 assume !(0 == ~T6_E~0); 10554#L884-1 assume !(0 == ~T7_E~0); 9993#L889-1 assume !(0 == ~T8_E~0); 9994#L894-1 assume !(0 == ~E_M~0); 10320#L899-1 assume !(0 == ~E_1~0); 10765#L904-1 assume !(0 == ~E_2~0); 10492#L909-1 assume !(0 == ~E_3~0); 10493#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 10700#L919-1 assume !(0 == ~E_5~0); 10398#L924-1 assume !(0 == ~E_6~0); 10215#L929-1 assume !(0 == ~E_7~0); 10216#L934-1 assume !(0 == ~E_8~0); 10472#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10010#L418 assume !(1 == ~m_pc~0); 9985#L418-2 is_master_triggered_~__retres1~0#1 := 0; 9984#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10870#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10856#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10789#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10790#L437 assume 1 == ~t1_pc~0; 10958#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10863#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10031#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10032#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 10348#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10846#L456 assume !(1 == ~t2_pc~0); 10271#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10270#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10430#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10431#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 10603#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10116#L475 assume 1 == ~t3_pc~0; 10117#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10180#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10001#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10002#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 10351#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10352#L494 assume !(1 == ~t4_pc~0); 10392#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10393#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10132#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10133#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 10724#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10175#L513 assume 1 == ~t5_pc~0; 10176#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10394#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10872#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10129#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 10130#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10085#L532 assume !(1 == ~t6_pc~0); 10086#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10234#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10412#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10413#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 10324#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10325#L551 assume 1 == ~t7_pc~0; 10882#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10726#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10727#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10967#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 10968#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10512#L570 assume 1 == ~t8_pc~0; 10513#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10629#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10821#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10625#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 10110#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10111#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 10057#L952-2 assume !(1 == ~T1_E~0); 10058#L957-1 assume !(1 == ~T2_E~0); 10827#L962-1 assume !(1 == ~T3_E~0); 10641#L967-1 assume !(1 == ~T4_E~0); 10642#L972-1 assume !(1 == ~T5_E~0); 10885#L977-1 assume !(1 == ~T6_E~0); 10886#L982-1 assume !(1 == ~T7_E~0); 10236#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10237#L992-1 assume !(1 == ~E_M~0); 10244#L997-1 assume !(1 == ~E_1~0); 10601#L1002-1 assume !(1 == ~E_2~0); 10586#L1007-1 assume !(1 == ~E_3~0); 9995#L1012-1 assume !(1 == ~E_4~0); 9996#L1017-1 assume !(1 == ~E_5~0); 10589#L1022-1 assume !(1 == ~E_6~0); 10590#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10615#L1032-1 assume !(1 == ~E_8~0); 10747#L1037-1 assume { :end_inline_reset_delta_events } true; 10748#L1303-2 [2022-12-13 19:42:16,565 INFO L750 eck$LassoCheckResult]: Loop: 10748#L1303-2 assume !false; 10823#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10446#L829 assume !false; 10786#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10374#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10310#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10452#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10453#L712 assume !(0 != eval_~tmp~0#1); 10715#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10624#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10716#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10717#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10966#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10940#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10530#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10531#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10602#L884-3 assume !(0 == ~T7_E~0); 10580#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10206#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10207#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10240#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10241#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10185#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10186#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10229#L924-3 assume !(0 == ~E_6~0); 10792#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10702#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10703#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10811#L418-30 assume 1 == ~m_pc~0; 10072#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10073#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10443#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10444#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10272#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10273#L437-30 assume !(1 == ~t1_pc~0); 10395#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 10621#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10622#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10659#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10957#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10355#L456-30 assume 1 == ~t2_pc~0; 10356#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10784#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10354#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10163#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10164#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10503#L475-30 assume !(1 == ~t3_pc~0); 10039#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 10040#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10639#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10640#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10378#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10379#L494-30 assume 1 == ~t4_pc~0; 10369#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9981#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9982#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10945#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 10894#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10895#L513-30 assume 1 == ~t5_pc~0; 10969#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10509#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10578#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10736#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10803#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10520#L532-30 assume !(1 == ~t6_pc~0); 10521#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 10114#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10115#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10139#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10195#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10196#L551-30 assume 1 == ~t7_pc~0; 10247#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10312#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10793#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9997#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9998#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10353#L570-30 assume 1 == ~t8_pc~0; 10864#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10245#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10246#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10053#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10054#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10424#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10469#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10921#L957-3 assume !(1 == ~T2_E~0); 10922#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10844#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10845#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10763#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10764#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10970#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10410#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10411#L997-3 assume !(1 == ~E_1~0); 10406#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10407#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10219#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10220#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10319#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10553#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10025#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10026#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10261#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10262#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10376#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10377#L1322 assume !(0 == start_simulation_~tmp~3#1); 10438#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10104#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10105#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10027#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 10011#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10012#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10637#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10638#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 10748#L1303-2 [2022-12-13 19:42:16,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:16,566 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2022-12-13 19:42:16,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:16,566 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531167333] [2022-12-13 19:42:16,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:16,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:16,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:16,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:16,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:16,592 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1531167333] [2022-12-13 19:42:16,592 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1531167333] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:16,592 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:16,592 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:16,592 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1776829516] [2022-12-13 19:42:16,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:16,593 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:16,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:16,593 INFO L85 PathProgramCache]: Analyzing trace with hash 613340432, now seen corresponding path program 1 times [2022-12-13 19:42:16,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:16,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [366462022] [2022-12-13 19:42:16,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:16,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:16,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:16,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:16,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:16,627 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [366462022] [2022-12-13 19:42:16,627 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [366462022] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:16,627 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:16,627 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:16,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [208849067] [2022-12-13 19:42:16,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:16,628 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:16,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:16,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:16,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:16,629 INFO L87 Difference]: Start difference. First operand 993 states and 1477 transitions. cyclomatic complexity: 485 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:16,649 INFO L93 Difference]: Finished difference Result 993 states and 1476 transitions. [2022-12-13 19:42:16,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1476 transitions. [2022-12-13 19:42:16,655 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1476 transitions. [2022-12-13 19:42:16,659 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-12-13 19:42:16,660 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-12-13 19:42:16,660 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1476 transitions. [2022-12-13 19:42:16,662 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:16,662 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1476 transitions. [2022-12-13 19:42:16,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1476 transitions. [2022-12-13 19:42:16,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-12-13 19:42:16,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.486404833836858) internal successors, (1476), 992 states have internal predecessors, (1476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1476 transitions. [2022-12-13 19:42:16,677 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1476 transitions. [2022-12-13 19:42:16,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:16,678 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1476 transitions. [2022-12-13 19:42:16,678 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 19:42:16,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1476 transitions. [2022-12-13 19:42:16,683 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:16,683 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:16,685 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,685 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,685 INFO L748 eck$LassoCheckResult]: Stem: 12283#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12284#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12909#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12910#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12948#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 12702#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12703#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12300#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12301#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12235#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12236#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12495#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12468#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12469#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12752#L854 assume !(0 == ~M_E~0); 12558#L854-2 assume !(0 == ~T1_E~0); 12559#L859-1 assume !(0 == ~T2_E~0); 12115#L864-1 assume !(0 == ~T3_E~0); 12116#L869-1 assume !(0 == ~T4_E~0); 12226#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12934#L879-1 assume !(0 == ~T6_E~0); 12547#L884-1 assume !(0 == ~T7_E~0); 11986#L889-1 assume !(0 == ~T8_E~0); 11987#L894-1 assume !(0 == ~E_M~0); 12313#L899-1 assume !(0 == ~E_1~0); 12758#L904-1 assume !(0 == ~E_2~0); 12485#L909-1 assume !(0 == ~E_3~0); 12486#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12693#L919-1 assume !(0 == ~E_5~0); 12391#L924-1 assume !(0 == ~E_6~0); 12208#L929-1 assume !(0 == ~E_7~0); 12209#L934-1 assume !(0 == ~E_8~0); 12465#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12003#L418 assume !(1 == ~m_pc~0); 11978#L418-2 is_master_triggered_~__retres1~0#1 := 0; 11977#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12863#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12849#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12782#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12783#L437 assume 1 == ~t1_pc~0; 12951#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12856#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12024#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12025#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 12341#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12839#L456 assume !(1 == ~t2_pc~0); 12264#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12263#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12423#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12424#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 12596#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12109#L475 assume 1 == ~t3_pc~0; 12110#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12173#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11994#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11995#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 12344#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12345#L494 assume !(1 == ~t4_pc~0); 12385#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12386#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12125#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12126#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 12717#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12168#L513 assume 1 == ~t5_pc~0; 12169#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12387#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12865#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12122#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 12123#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12078#L532 assume !(1 == ~t6_pc~0); 12079#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12227#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12405#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12406#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 12317#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12318#L551 assume 1 == ~t7_pc~0; 12875#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12719#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12720#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12960#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 12961#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12505#L570 assume 1 == ~t8_pc~0; 12506#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12622#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12814#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12618#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 12103#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12104#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 12050#L952-2 assume !(1 == ~T1_E~0); 12051#L957-1 assume !(1 == ~T2_E~0); 12820#L962-1 assume !(1 == ~T3_E~0); 12634#L967-1 assume !(1 == ~T4_E~0); 12635#L972-1 assume !(1 == ~T5_E~0); 12878#L977-1 assume !(1 == ~T6_E~0); 12879#L982-1 assume !(1 == ~T7_E~0); 12229#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12230#L992-1 assume !(1 == ~E_M~0); 12237#L997-1 assume !(1 == ~E_1~0); 12594#L1002-1 assume !(1 == ~E_2~0); 12579#L1007-1 assume !(1 == ~E_3~0); 11988#L1012-1 assume !(1 == ~E_4~0); 11989#L1017-1 assume !(1 == ~E_5~0); 12582#L1022-1 assume !(1 == ~E_6~0); 12583#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12608#L1032-1 assume !(1 == ~E_8~0); 12740#L1037-1 assume { :end_inline_reset_delta_events } true; 12741#L1303-2 [2022-12-13 19:42:16,685 INFO L750 eck$LassoCheckResult]: Loop: 12741#L1303-2 assume !false; 12816#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12439#L829 assume !false; 12779#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12367#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12303#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12445#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12446#L712 assume !(0 != eval_~tmp~0#1); 12708#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12616#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12617#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12709#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12710#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12959#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12933#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12523#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12524#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12595#L884-3 assume !(0 == ~T7_E~0); 12573#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12199#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12200#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12233#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12234#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12178#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12179#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12222#L924-3 assume !(0 == ~E_6~0); 12785#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12695#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12696#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12804#L418-30 assume 1 == ~m_pc~0; 12065#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12066#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12436#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12437#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12265#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12266#L437-30 assume !(1 == ~t1_pc~0); 12388#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 12614#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12615#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12652#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12950#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12348#L456-30 assume 1 == ~t2_pc~0; 12349#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12777#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12347#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12156#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12157#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12496#L475-30 assume !(1 == ~t3_pc~0); 12032#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 12033#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12632#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12633#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12371#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12372#L494-30 assume !(1 == ~t4_pc~0); 12183#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 11974#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11975#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12938#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 12887#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12888#L513-30 assume 1 == ~t5_pc~0; 12962#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12502#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12571#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12729#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12796#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12513#L532-30 assume !(1 == ~t6_pc~0); 12514#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 12107#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12108#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12132#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12188#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12189#L551-30 assume 1 == ~t7_pc~0; 12240#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12305#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12786#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11990#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11991#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12346#L570-30 assume 1 == ~t8_pc~0; 12857#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12238#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12239#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12046#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12047#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12417#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12462#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12914#L957-3 assume !(1 == ~T2_E~0); 12915#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12837#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12838#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12756#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12757#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12963#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12403#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12404#L997-3 assume !(1 == ~E_1~0); 12399#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12400#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12212#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12213#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12312#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12546#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12018#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12019#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12254#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12255#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12369#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12370#L1322 assume !(0 == start_simulation_~tmp~3#1); 12431#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12097#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12098#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12020#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 12004#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12005#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12630#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 12631#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 12741#L1303-2 [2022-12-13 19:42:16,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:16,686 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2022-12-13 19:42:16,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:16,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218562777] [2022-12-13 19:42:16,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:16,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:16,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:16,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:16,722 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:16,722 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218562777] [2022-12-13 19:42:16,722 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1218562777] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:16,722 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:16,722 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:16,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1582495405] [2022-12-13 19:42:16,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:16,723 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:16,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:16,723 INFO L85 PathProgramCache]: Analyzing trace with hash 1641872593, now seen corresponding path program 1 times [2022-12-13 19:42:16,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:16,724 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189131249] [2022-12-13 19:42:16,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:16,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:16,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:16,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:16,760 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:16,760 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189131249] [2022-12-13 19:42:16,761 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189131249] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:16,761 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:16,761 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:16,761 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1122973853] [2022-12-13 19:42:16,761 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:16,761 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:16,762 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:16,762 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:16,762 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:16,762 INFO L87 Difference]: Start difference. First operand 993 states and 1476 transitions. cyclomatic complexity: 484 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:16,802 INFO L93 Difference]: Finished difference Result 993 states and 1475 transitions. [2022-12-13 19:42:16,802 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1475 transitions. [2022-12-13 19:42:16,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,809 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1475 transitions. [2022-12-13 19:42:16,809 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-12-13 19:42:16,809 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-12-13 19:42:16,809 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1475 transitions. [2022-12-13 19:42:16,811 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:16,811 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1475 transitions. [2022-12-13 19:42:16,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1475 transitions. [2022-12-13 19:42:16,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-12-13 19:42:16,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.48539778449144) internal successors, (1475), 992 states have internal predecessors, (1475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1475 transitions. [2022-12-13 19:42:16,825 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1475 transitions. [2022-12-13 19:42:16,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:16,826 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1475 transitions. [2022-12-13 19:42:16,826 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 19:42:16,826 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1475 transitions. [2022-12-13 19:42:16,832 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:16,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:16,834 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,834 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,835 INFO L748 eck$LassoCheckResult]: Stem: 14276#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14277#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14902#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14903#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14941#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 14695#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14696#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14293#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14294#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14228#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14229#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14488#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14461#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14462#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14745#L854 assume !(0 == ~M_E~0); 14551#L854-2 assume !(0 == ~T1_E~0); 14552#L859-1 assume !(0 == ~T2_E~0); 14108#L864-1 assume !(0 == ~T3_E~0); 14109#L869-1 assume !(0 == ~T4_E~0); 14219#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14927#L879-1 assume !(0 == ~T6_E~0); 14540#L884-1 assume !(0 == ~T7_E~0); 13979#L889-1 assume !(0 == ~T8_E~0); 13980#L894-1 assume !(0 == ~E_M~0); 14306#L899-1 assume !(0 == ~E_1~0); 14751#L904-1 assume !(0 == ~E_2~0); 14478#L909-1 assume !(0 == ~E_3~0); 14479#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14686#L919-1 assume !(0 == ~E_5~0); 14384#L924-1 assume !(0 == ~E_6~0); 14201#L929-1 assume !(0 == ~E_7~0); 14202#L934-1 assume !(0 == ~E_8~0); 14458#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13996#L418 assume !(1 == ~m_pc~0); 13971#L418-2 is_master_triggered_~__retres1~0#1 := 0; 13970#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14856#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14842#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14775#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14776#L437 assume 1 == ~t1_pc~0; 14944#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14849#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14017#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14018#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 14334#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14832#L456 assume !(1 == ~t2_pc~0); 14257#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14256#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14416#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14417#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 14589#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14102#L475 assume 1 == ~t3_pc~0; 14103#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14166#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13987#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13988#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 14337#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14338#L494 assume !(1 == ~t4_pc~0); 14378#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14379#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14118#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14119#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 14710#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14161#L513 assume 1 == ~t5_pc~0; 14162#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14380#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14858#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14115#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 14116#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14071#L532 assume !(1 == ~t6_pc~0); 14072#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14220#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14398#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14399#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 14310#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14311#L551 assume 1 == ~t7_pc~0; 14868#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14712#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14713#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14953#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 14954#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14498#L570 assume 1 == ~t8_pc~0; 14499#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14615#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14807#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14611#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 14096#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14097#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 14043#L952-2 assume !(1 == ~T1_E~0); 14044#L957-1 assume !(1 == ~T2_E~0); 14813#L962-1 assume !(1 == ~T3_E~0); 14627#L967-1 assume !(1 == ~T4_E~0); 14628#L972-1 assume !(1 == ~T5_E~0); 14871#L977-1 assume !(1 == ~T6_E~0); 14872#L982-1 assume !(1 == ~T7_E~0); 14222#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14223#L992-1 assume !(1 == ~E_M~0); 14230#L997-1 assume !(1 == ~E_1~0); 14587#L1002-1 assume !(1 == ~E_2~0); 14572#L1007-1 assume !(1 == ~E_3~0); 13981#L1012-1 assume !(1 == ~E_4~0); 13982#L1017-1 assume !(1 == ~E_5~0); 14575#L1022-1 assume !(1 == ~E_6~0); 14576#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14601#L1032-1 assume !(1 == ~E_8~0); 14733#L1037-1 assume { :end_inline_reset_delta_events } true; 14734#L1303-2 [2022-12-13 19:42:16,835 INFO L750 eck$LassoCheckResult]: Loop: 14734#L1303-2 assume !false; 14809#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14432#L829 assume !false; 14772#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14360#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14296#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14438#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14439#L712 assume !(0 != eval_~tmp~0#1); 14701#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14609#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14610#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14702#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14703#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14952#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14926#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14516#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14517#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14588#L884-3 assume !(0 == ~T7_E~0); 14566#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14192#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14193#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14226#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14227#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14171#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14172#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14215#L924-3 assume !(0 == ~E_6~0); 14778#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14688#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14689#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14797#L418-30 assume 1 == ~m_pc~0; 14058#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14059#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14429#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14430#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14258#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14259#L437-30 assume !(1 == ~t1_pc~0); 14381#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 14607#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14608#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14645#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14943#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14341#L456-30 assume 1 == ~t2_pc~0; 14342#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14770#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14340#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14149#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14150#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14489#L475-30 assume 1 == ~t3_pc~0; 14864#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14026#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14625#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14626#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14364#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14365#L494-30 assume !(1 == ~t4_pc~0); 14176#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 13967#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13968#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14931#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 14880#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14881#L513-30 assume 1 == ~t5_pc~0; 14955#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14495#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14564#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14722#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14789#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14506#L532-30 assume !(1 == ~t6_pc~0); 14507#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 14100#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14101#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14125#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14181#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14182#L551-30 assume 1 == ~t7_pc~0; 14233#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14298#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14779#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13983#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13984#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14339#L570-30 assume 1 == ~t8_pc~0; 14850#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14231#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14232#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14039#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14040#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14410#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14455#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14907#L957-3 assume !(1 == ~T2_E~0); 14908#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14830#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14831#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14749#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14750#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14956#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14396#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14397#L997-3 assume !(1 == ~E_1~0); 14392#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14393#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14205#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14206#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14305#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14539#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14011#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14012#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14247#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14248#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14362#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14363#L1322 assume !(0 == start_simulation_~tmp~3#1); 14424#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14090#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14091#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14013#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 13997#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13998#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14623#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14624#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 14734#L1303-2 [2022-12-13 19:42:16,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:16,835 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2022-12-13 19:42:16,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:16,836 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391026506] [2022-12-13 19:42:16,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:16,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:16,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:16,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:16,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:16,869 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1391026506] [2022-12-13 19:42:16,870 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1391026506] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:16,870 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:16,870 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:16,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [474967820] [2022-12-13 19:42:16,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:16,871 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:16,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:16,871 INFO L85 PathProgramCache]: Analyzing trace with hash -495621680, now seen corresponding path program 1 times [2022-12-13 19:42:16,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:16,871 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109385539] [2022-12-13 19:42:16,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:16,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:16,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:16,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:16,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:16,910 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109385539] [2022-12-13 19:42:16,910 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2109385539] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:16,910 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:16,910 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:16,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2134212876] [2022-12-13 19:42:16,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:16,911 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:16,911 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:16,911 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:16,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:16,912 INFO L87 Difference]: Start difference. First operand 993 states and 1475 transitions. cyclomatic complexity: 483 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:16,929 INFO L93 Difference]: Finished difference Result 993 states and 1474 transitions. [2022-12-13 19:42:16,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1474 transitions. [2022-12-13 19:42:16,932 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1474 transitions. [2022-12-13 19:42:16,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-12-13 19:42:16,935 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-12-13 19:42:16,935 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1474 transitions. [2022-12-13 19:42:16,935 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:16,936 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1474 transitions. [2022-12-13 19:42:16,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1474 transitions. [2022-12-13 19:42:16,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-12-13 19:42:16,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4843907351460222) internal successors, (1474), 992 states have internal predecessors, (1474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:16,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1474 transitions. [2022-12-13 19:42:16,946 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1474 transitions. [2022-12-13 19:42:16,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:16,947 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1474 transitions. [2022-12-13 19:42:16,947 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 19:42:16,947 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1474 transitions. [2022-12-13 19:42:16,952 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-12-13 19:42:16,952 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:16,952 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:16,954 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,954 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:16,954 INFO L748 eck$LassoCheckResult]: Stem: 16269#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16270#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 16895#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16896#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16934#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 16688#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16689#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16286#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16287#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16221#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16222#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16481#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16454#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16455#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16738#L854 assume !(0 == ~M_E~0); 16544#L854-2 assume !(0 == ~T1_E~0); 16545#L859-1 assume !(0 == ~T2_E~0); 16101#L864-1 assume !(0 == ~T3_E~0); 16102#L869-1 assume !(0 == ~T4_E~0); 16212#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16920#L879-1 assume !(0 == ~T6_E~0); 16533#L884-1 assume !(0 == ~T7_E~0); 15972#L889-1 assume !(0 == ~T8_E~0); 15973#L894-1 assume !(0 == ~E_M~0); 16299#L899-1 assume !(0 == ~E_1~0); 16744#L904-1 assume !(0 == ~E_2~0); 16471#L909-1 assume !(0 == ~E_3~0); 16472#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16679#L919-1 assume !(0 == ~E_5~0); 16377#L924-1 assume !(0 == ~E_6~0); 16194#L929-1 assume !(0 == ~E_7~0); 16195#L934-1 assume !(0 == ~E_8~0); 16451#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15989#L418 assume !(1 == ~m_pc~0); 15964#L418-2 is_master_triggered_~__retres1~0#1 := 0; 15963#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16849#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16835#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16768#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16769#L437 assume 1 == ~t1_pc~0; 16937#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16842#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16010#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16011#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 16327#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16825#L456 assume !(1 == ~t2_pc~0); 16250#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16249#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16409#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16410#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 16582#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16095#L475 assume 1 == ~t3_pc~0; 16096#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16159#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15980#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15981#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 16330#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16331#L494 assume !(1 == ~t4_pc~0); 16371#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16372#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16111#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16112#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 16703#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16154#L513 assume 1 == ~t5_pc~0; 16155#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16373#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16851#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16108#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 16109#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16064#L532 assume !(1 == ~t6_pc~0); 16065#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16213#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16391#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16392#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 16303#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16304#L551 assume 1 == ~t7_pc~0; 16861#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16705#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16706#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16946#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 16947#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16491#L570 assume 1 == ~t8_pc~0; 16492#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16608#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16800#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16604#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 16089#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16090#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 16036#L952-2 assume !(1 == ~T1_E~0); 16037#L957-1 assume !(1 == ~T2_E~0); 16806#L962-1 assume !(1 == ~T3_E~0); 16620#L967-1 assume !(1 == ~T4_E~0); 16621#L972-1 assume !(1 == ~T5_E~0); 16864#L977-1 assume !(1 == ~T6_E~0); 16865#L982-1 assume !(1 == ~T7_E~0); 16215#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16216#L992-1 assume !(1 == ~E_M~0); 16223#L997-1 assume !(1 == ~E_1~0); 16580#L1002-1 assume !(1 == ~E_2~0); 16565#L1007-1 assume !(1 == ~E_3~0); 15974#L1012-1 assume !(1 == ~E_4~0); 15975#L1017-1 assume !(1 == ~E_5~0); 16568#L1022-1 assume !(1 == ~E_6~0); 16569#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16594#L1032-1 assume !(1 == ~E_8~0); 16726#L1037-1 assume { :end_inline_reset_delta_events } true; 16727#L1303-2 [2022-12-13 19:42:16,955 INFO L750 eck$LassoCheckResult]: Loop: 16727#L1303-2 assume !false; 16802#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16425#L829 assume !false; 16765#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16353#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16289#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16431#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16432#L712 assume !(0 != eval_~tmp~0#1); 16694#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16602#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16603#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16695#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16696#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16945#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16919#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16509#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16510#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16581#L884-3 assume !(0 == ~T7_E~0); 16559#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16185#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16186#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16219#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16220#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16164#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16165#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16208#L924-3 assume !(0 == ~E_6~0); 16771#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16681#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16682#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16790#L418-30 assume 1 == ~m_pc~0; 16051#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16052#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16422#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16423#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16251#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16252#L437-30 assume !(1 == ~t1_pc~0); 16374#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 16600#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16601#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16638#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16936#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16334#L456-30 assume !(1 == ~t2_pc~0); 16336#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 16763#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16333#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16142#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16143#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16482#L475-30 assume !(1 == ~t3_pc~0); 16018#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 16019#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16618#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16619#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16357#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16358#L494-30 assume !(1 == ~t4_pc~0); 16169#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 15960#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15961#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16924#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 16873#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16874#L513-30 assume 1 == ~t5_pc~0; 16948#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16488#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16557#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16715#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16782#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16499#L532-30 assume !(1 == ~t6_pc~0); 16500#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 16093#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16094#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16118#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16174#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16175#L551-30 assume 1 == ~t7_pc~0; 16226#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16291#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16772#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15976#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15977#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16332#L570-30 assume 1 == ~t8_pc~0; 16843#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16224#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16225#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16032#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16033#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16403#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16448#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16900#L957-3 assume !(1 == ~T2_E~0); 16901#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16823#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16824#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16742#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16743#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16949#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16389#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16390#L997-3 assume !(1 == ~E_1~0); 16385#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16386#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16198#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16199#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16298#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16532#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16004#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16005#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16240#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16241#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16355#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 16356#L1322 assume !(0 == start_simulation_~tmp~3#1); 16417#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16083#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16084#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16006#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 15990#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15991#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16616#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 16617#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 16727#L1303-2 [2022-12-13 19:42:16,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:16,955 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2022-12-13 19:42:16,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:16,955 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904629232] [2022-12-13 19:42:16,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:16,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:16,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:17,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:17,015 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:17,015 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904629232] [2022-12-13 19:42:17,015 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1904629232] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:17,015 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:17,015 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:17,016 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [967392572] [2022-12-13 19:42:17,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:17,016 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:17,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:17,016 INFO L85 PathProgramCache]: Analyzing trace with hash -521106670, now seen corresponding path program 1 times [2022-12-13 19:42:17,016 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:17,017 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359456300] [2022-12-13 19:42:17,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:17,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:17,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:17,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:17,064 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:17,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359456300] [2022-12-13 19:42:17,064 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359456300] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:17,065 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:17,065 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:17,065 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [835721066] [2022-12-13 19:42:17,065 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:17,065 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:17,065 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:17,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:42:17,066 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:42:17,066 INFO L87 Difference]: Start difference. First operand 993 states and 1474 transitions. cyclomatic complexity: 482 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:17,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:17,184 INFO L93 Difference]: Finished difference Result 1806 states and 2671 transitions. [2022-12-13 19:42:17,185 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1806 states and 2671 transitions. [2022-12-13 19:42:17,193 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1673 [2022-12-13 19:42:17,200 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1806 states to 1806 states and 2671 transitions. [2022-12-13 19:42:17,201 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1806 [2022-12-13 19:42:17,202 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1806 [2022-12-13 19:42:17,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1806 states and 2671 transitions. [2022-12-13 19:42:17,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:17,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1806 states and 2671 transitions. [2022-12-13 19:42:17,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1806 states and 2671 transitions. [2022-12-13 19:42:17,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1806 to 1806. [2022-12-13 19:42:17,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1806 states, 1806 states have (on average 1.4789590254706533) internal successors, (2671), 1805 states have internal predecessors, (2671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:17,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1806 states to 1806 states and 2671 transitions. [2022-12-13 19:42:17,240 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1806 states and 2671 transitions. [2022-12-13 19:42:17,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:42:17,241 INFO L428 stractBuchiCegarLoop]: Abstraction has 1806 states and 2671 transitions. [2022-12-13 19:42:17,241 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 19:42:17,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1806 states and 2671 transitions. [2022-12-13 19:42:17,247 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1673 [2022-12-13 19:42:17,247 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:17,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:17,249 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:17,249 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:17,249 INFO L748 eck$LassoCheckResult]: Stem: 19078#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19079#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 19738#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19739#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19791#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 19503#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19504#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19095#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19096#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19030#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19031#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19292#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19265#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19266#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19557#L854 assume !(0 == ~M_E~0); 19357#L854-2 assume !(0 == ~T1_E~0); 19358#L859-1 assume !(0 == ~T2_E~0); 18910#L864-1 assume !(0 == ~T3_E~0); 18911#L869-1 assume !(0 == ~T4_E~0); 19021#L874-1 assume !(0 == ~T5_E~0); 19774#L879-1 assume !(0 == ~T6_E~0); 19346#L884-1 assume !(0 == ~T7_E~0); 18781#L889-1 assume !(0 == ~T8_E~0); 18782#L894-1 assume !(0 == ~E_M~0); 19108#L899-1 assume !(0 == ~E_1~0); 19563#L904-1 assume !(0 == ~E_2~0); 19282#L909-1 assume !(0 == ~E_3~0); 19283#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19494#L919-1 assume !(0 == ~E_5~0); 19186#L924-1 assume !(0 == ~E_6~0); 19003#L929-1 assume !(0 == ~E_7~0); 19004#L934-1 assume !(0 == ~E_8~0); 19262#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18798#L418 assume !(1 == ~m_pc~0); 18773#L418-2 is_master_triggered_~__retres1~0#1 := 0; 18772#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19686#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19669#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19590#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19591#L437 assume 1 == ~t1_pc~0; 19795#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19677#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18819#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18820#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 19136#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19659#L456 assume !(1 == ~t2_pc~0); 19059#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19058#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19218#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19219#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 19396#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18904#L475 assume 1 == ~t3_pc~0; 18905#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18968#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18789#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18790#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 19139#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19140#L494 assume !(1 == ~t4_pc~0); 19180#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19181#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18920#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18921#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 19518#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18963#L513 assume 1 == ~t5_pc~0; 18964#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19182#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19688#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18917#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 18918#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18873#L532 assume !(1 == ~t6_pc~0); 18874#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19022#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19200#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19201#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 19112#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19113#L551 assume 1 == ~t7_pc~0; 19698#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19520#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19521#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19807#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 19809#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19302#L570 assume 1 == ~t8_pc~0; 19303#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19422#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19628#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19418#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 18898#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18899#L952 assume !(1 == ~M_E~0); 19681#L952-2 assume !(1 == ~T1_E~0); 19637#L957-1 assume !(1 == ~T2_E~0); 19638#L962-1 assume !(1 == ~T3_E~0); 19434#L967-1 assume !(1 == ~T4_E~0); 19435#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19701#L977-1 assume !(1 == ~T6_E~0); 19702#L982-1 assume !(1 == ~T7_E~0); 19810#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20488#L992-1 assume !(1 == ~E_M~0); 20487#L997-1 assume !(1 == ~E_1~0); 20486#L1002-1 assume !(1 == ~E_2~0); 20485#L1007-1 assume !(1 == ~E_3~0); 20484#L1012-1 assume !(1 == ~E_4~0); 20483#L1017-1 assume !(1 == ~E_5~0); 20482#L1022-1 assume !(1 == ~E_6~0); 20481#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 20480#L1032-1 assume !(1 == ~E_8~0); 19860#L1037-1 assume { :end_inline_reset_delta_events } true; 19630#L1303-2 [2022-12-13 19:42:17,249 INFO L750 eck$LassoCheckResult]: Loop: 19630#L1303-2 assume !false; 19631#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19829#L829 assume !false; 19587#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19162#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19098#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19819#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19817#L712 assume !(0 != eval_~tmp~0#1); 19632#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19416#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19417#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19510#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19511#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19805#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19806#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20146#L874-3 assume !(0 == ~T5_E~0); 20144#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20142#L884-3 assume !(0 == ~T7_E~0); 20140#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20138#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20136#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20135#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20132#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20130#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20128#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20126#L924-3 assume !(0 == ~E_6~0); 20124#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20122#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20119#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20117#L418-30 assume 1 == ~m_pc~0; 20114#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20112#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20110#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20108#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20105#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20103#L437-30 assume !(1 == ~t1_pc~0); 20100#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 20098#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20096#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20095#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20094#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20093#L456-30 assume 1 == ~t2_pc~0; 20091#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20090#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20089#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20088#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20087#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20086#L475-30 assume !(1 == ~t3_pc~0); 20084#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 20083#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20082#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20081#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20080#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20079#L494-30 assume 1 == ~t4_pc~0; 20077#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20076#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20075#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20074#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 20073#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20072#L513-30 assume 1 == ~t5_pc~0; 20070#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20069#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20068#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20067#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20066#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20065#L532-30 assume 1 == ~t6_pc~0; 20064#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20062#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20061#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20060#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20059#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20058#L551-30 assume 1 == ~t7_pc~0; 20056#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20055#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20054#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20053#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20052#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20051#L570-30 assume !(1 == ~t8_pc~0); 20049#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 20048#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20047#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20046#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20045#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20044#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19258#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20043#L957-3 assume !(1 == ~T2_E~0); 20042#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20041#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20040#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19768#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20039#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20038#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20037#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20036#L997-3 assume !(1 == ~E_1~0); 20035#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20034#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20031#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20029#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20027#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20025#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20023#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20021#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19965#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19963#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19961#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 19958#L1322 assume !(0 == start_simulation_~tmp~3#1); 19579#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 18892#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18893#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19868#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 19866#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19862#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19861#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 19859#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 19630#L1303-2 [2022-12-13 19:42:17,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:17,250 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2022-12-13 19:42:17,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:17,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221610633] [2022-12-13 19:42:17,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:17,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:17,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:17,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:17,310 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:17,310 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221610633] [2022-12-13 19:42:17,310 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [221610633] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:17,311 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:17,311 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:17,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1760213493] [2022-12-13 19:42:17,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:17,311 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:17,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:17,312 INFO L85 PathProgramCache]: Analyzing trace with hash 1301437970, now seen corresponding path program 1 times [2022-12-13 19:42:17,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:17,312 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303068872] [2022-12-13 19:42:17,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:17,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:17,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:17,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:17,358 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:17,358 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303068872] [2022-12-13 19:42:17,358 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1303068872] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:17,358 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:17,358 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:17,358 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2137786344] [2022-12-13 19:42:17,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:17,359 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:17,359 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:17,359 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:42:17,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:42:17,359 INFO L87 Difference]: Start difference. First operand 1806 states and 2671 transitions. cyclomatic complexity: 867 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:17,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:17,482 INFO L93 Difference]: Finished difference Result 3286 states and 4848 transitions. [2022-12-13 19:42:17,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3286 states and 4848 transitions. [2022-12-13 19:42:17,492 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3133 [2022-12-13 19:42:17,500 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3286 states to 3286 states and 4848 transitions. [2022-12-13 19:42:17,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3286 [2022-12-13 19:42:17,502 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3286 [2022-12-13 19:42:17,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3286 states and 4848 transitions. [2022-12-13 19:42:17,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:17,505 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3286 states and 4848 transitions. [2022-12-13 19:42:17,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3286 states and 4848 transitions. [2022-12-13 19:42:17,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3286 to 3284. [2022-12-13 19:42:17,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3284 states, 3284 states have (on average 1.4756394640682096) internal successors, (4846), 3283 states have internal predecessors, (4846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:17,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3284 states to 3284 states and 4846 transitions. [2022-12-13 19:42:17,563 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3284 states and 4846 transitions. [2022-12-13 19:42:17,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:42:17,564 INFO L428 stractBuchiCegarLoop]: Abstraction has 3284 states and 4846 transitions. [2022-12-13 19:42:17,564 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 19:42:17,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3284 states and 4846 transitions. [2022-12-13 19:42:17,570 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3133 [2022-12-13 19:42:17,570 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:17,570 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:17,571 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:17,571 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:17,571 INFO L748 eck$LassoCheckResult]: Stem: 24184#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 24185#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 24836#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24837#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24883#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 24609#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24610#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24201#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24202#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24136#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24137#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24399#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24372#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24373#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24662#L854 assume !(0 == ~M_E~0); 24462#L854-2 assume !(0 == ~T1_E~0); 24463#L859-1 assume !(0 == ~T2_E~0); 24014#L864-1 assume !(0 == ~T3_E~0); 24015#L869-1 assume !(0 == ~T4_E~0); 24126#L874-1 assume !(0 == ~T5_E~0); 24866#L879-1 assume !(0 == ~T6_E~0); 24451#L884-1 assume !(0 == ~T7_E~0); 23883#L889-1 assume !(0 == ~T8_E~0); 23884#L894-1 assume !(0 == ~E_M~0); 24215#L899-1 assume !(0 == ~E_1~0); 24668#L904-1 assume !(0 == ~E_2~0); 24389#L909-1 assume !(0 == ~E_3~0); 24390#L914-1 assume !(0 == ~E_4~0); 24600#L919-1 assume !(0 == ~E_5~0); 24293#L924-1 assume !(0 == ~E_6~0); 24108#L929-1 assume !(0 == ~E_7~0); 24109#L934-1 assume !(0 == ~E_8~0); 24369#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23901#L418 assume !(1 == ~m_pc~0); 23875#L418-2 is_master_triggered_~__retres1~0#1 := 0; 23874#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24784#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24769#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24694#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24695#L437 assume 1 == ~t1_pc~0; 24890#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24776#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23922#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23923#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 24243#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24759#L456 assume !(1 == ~t2_pc~0); 24165#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24164#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24326#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24327#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 24501#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24008#L475 assume 1 == ~t3_pc~0; 24009#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24073#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23892#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23893#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 24246#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24247#L494 assume !(1 == ~t4_pc~0); 24287#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24288#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24024#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24025#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 24624#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24068#L513 assume 1 == ~t5_pc~0; 24069#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24289#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24786#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24021#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 24022#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23977#L532 assume !(1 == ~t6_pc~0); 23978#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24127#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24308#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24309#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 24219#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24220#L551 assume 1 == ~t7_pc~0; 24796#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24626#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24627#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24905#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 24907#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24409#L570 assume 1 == ~t8_pc~0; 24410#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24528#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24732#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24524#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 24002#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24003#L952 assume !(1 == ~M_E~0); 23949#L952-2 assume !(1 == ~T1_E~0); 23950#L957-1 assume !(1 == ~T2_E~0); 24892#L962-1 assume !(1 == ~T3_E~0); 24893#L967-1 assume !(1 == ~T4_E~0); 25213#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24799#L977-1 assume !(1 == ~T6_E~0); 24800#L982-1 assume !(1 == ~T7_E~0); 25223#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25221#L992-1 assume !(1 == ~E_M~0); 25219#L997-1 assume !(1 == ~E_1~0); 25217#L1002-1 assume !(1 == ~E_2~0); 25216#L1007-1 assume !(1 == ~E_3~0); 25030#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 24990#L1017-1 assume !(1 == ~E_5~0); 24987#L1022-1 assume !(1 == ~E_6~0); 24970#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 24954#L1032-1 assume !(1 == ~E_8~0); 24945#L1037-1 assume { :end_inline_reset_delta_events } true; 24938#L1303-2 [2022-12-13 19:42:17,572 INFO L750 eck$LassoCheckResult]: Loop: 24938#L1303-2 assume !false; 24933#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24931#L829 assume !false; 24930#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 24925#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 24920#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 24919#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 24917#L712 assume !(0 != eval_~tmp~0#1); 24916#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24915#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24914#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24616#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24617#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24904#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24865#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24427#L874-3 assume !(0 == ~T5_E~0); 24428#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24500#L884-3 assume !(0 == ~T7_E~0); 24540#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26876#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26875#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26874#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26873#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26872#L914-3 assume !(0 == ~E_4~0); 26871#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26870#L924-3 assume !(0 == ~E_6~0); 26869#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26868#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26867#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26866#L418-30 assume 1 == ~m_pc~0; 26864#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26863#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26862#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26861#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26860#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26859#L437-30 assume !(1 == ~t1_pc~0); 26857#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 26856#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26855#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26854#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26853#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26852#L456-30 assume 1 == ~t2_pc~0; 25529#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25527#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25525#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25523#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25521#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25520#L475-30 assume !(1 == ~t3_pc~0); 25518#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 25517#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25516#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25513#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25511#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25509#L494-30 assume 1 == ~t4_pc~0; 25506#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25504#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25502#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25501#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 25500#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25499#L513-30 assume 1 == ~t5_pc~0; 25496#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25494#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25492#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25489#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25487#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25485#L532-30 assume !(1 == ~t6_pc~0); 25425#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 25423#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25383#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25355#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25353#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25351#L551-30 assume 1 == ~t7_pc~0; 25348#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25346#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25344#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25343#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25342#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25341#L570-30 assume !(1 == ~t8_pc~0); 25338#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 25299#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25296#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25294#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25292#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25290#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24365#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25270#L957-3 assume !(1 == ~T2_E~0); 25263#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25257#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25246#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25242#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25238#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25235#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25232#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25229#L997-3 assume !(1 == ~E_1~0); 25215#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25214#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25212#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25209#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25207#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25205#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25203#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25201#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25191#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25189#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25188#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 25187#L1322 assume !(0 == start_simulation_~tmp~3#1); 24684#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25028#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25020#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25019#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 24986#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24968#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24953#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 24944#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 24938#L1303-2 [2022-12-13 19:42:17,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:17,572 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2022-12-13 19:42:17,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:17,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140971347] [2022-12-13 19:42:17,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:17,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:17,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:17,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:17,612 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:17,612 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2140971347] [2022-12-13 19:42:17,612 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2140971347] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:17,612 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:17,612 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:42:17,612 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [770967138] [2022-12-13 19:42:17,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:17,612 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:17,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:17,613 INFO L85 PathProgramCache]: Analyzing trace with hash 829059285, now seen corresponding path program 1 times [2022-12-13 19:42:17,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:17,613 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911727926] [2022-12-13 19:42:17,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:17,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:17,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:17,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:17,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:17,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911727926] [2022-12-13 19:42:17,641 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [911727926] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:17,641 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:17,641 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:17,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [454227432] [2022-12-13 19:42:17,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:17,641 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:17,641 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:17,642 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:42:17,642 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:42:17,642 INFO L87 Difference]: Start difference. First operand 3284 states and 4846 transitions. cyclomatic complexity: 1566 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:17,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:17,828 INFO L93 Difference]: Finished difference Result 9426 states and 13840 transitions. [2022-12-13 19:42:17,828 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9426 states and 13840 transitions. [2022-12-13 19:42:17,876 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9048 [2022-12-13 19:42:17,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9426 states to 9426 states and 13840 transitions. [2022-12-13 19:42:17,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9426 [2022-12-13 19:42:17,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9426 [2022-12-13 19:42:17,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9426 states and 13840 transitions. [2022-12-13 19:42:17,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:17,909 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9426 states and 13840 transitions. [2022-12-13 19:42:17,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9426 states and 13840 transitions. [2022-12-13 19:42:17,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9426 to 3404. [2022-12-13 19:42:17,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3404 states, 3404 states have (on average 1.4588719153936545) internal successors, (4966), 3403 states have internal predecessors, (4966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:17,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3404 states to 3404 states and 4966 transitions. [2022-12-13 19:42:17,978 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3404 states and 4966 transitions. [2022-12-13 19:42:17,979 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 19:42:17,979 INFO L428 stractBuchiCegarLoop]: Abstraction has 3404 states and 4966 transitions. [2022-12-13 19:42:17,979 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 19:42:17,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3404 states and 4966 transitions. [2022-12-13 19:42:17,986 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3250 [2022-12-13 19:42:17,987 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:17,987 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:17,988 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:17,988 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:17,989 INFO L748 eck$LassoCheckResult]: Stem: 36905#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 36906#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 37616#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37617#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37684#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 37351#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37352#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36923#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36924#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36859#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36860#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37126#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37099#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37100#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37409#L854 assume !(0 == ~M_E~0); 37196#L854-2 assume !(0 == ~T1_E~0); 37197#L859-1 assume !(0 == ~T2_E~0); 36736#L864-1 assume !(0 == ~T3_E~0); 36737#L869-1 assume !(0 == ~T4_E~0); 36848#L874-1 assume !(0 == ~T5_E~0); 37663#L879-1 assume !(0 == ~T6_E~0); 37184#L884-1 assume !(0 == ~T7_E~0); 36606#L889-1 assume !(0 == ~T8_E~0); 36607#L894-1 assume !(0 == ~E_M~0); 36939#L899-1 assume !(0 == ~E_1~0); 37416#L904-1 assume !(0 == ~E_2~0); 37117#L909-1 assume !(0 == ~E_3~0); 37118#L914-1 assume !(0 == ~E_4~0); 37342#L919-1 assume !(0 == ~E_5~0); 37017#L924-1 assume !(0 == ~E_6~0); 36834#L929-1 assume !(0 == ~E_7~0); 36835#L934-1 assume !(0 == ~E_8~0); 37096#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36623#L418 assume !(1 == ~m_pc~0); 36598#L418-2 is_master_triggered_~__retres1~0#1 := 0; 37597#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37598#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37534#L1061 assume !(0 != activate_threads_~tmp~1#1); 37442#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37443#L437 assume 1 == ~t1_pc~0; 37694#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37541#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36647#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36648#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 36967#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37523#L456 assume !(1 == ~t2_pc~0); 36886#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36885#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37051#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37052#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 37237#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36730#L475 assume 1 == ~t3_pc~0; 36731#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36797#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36614#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36615#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 36970#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36971#L494 assume !(1 == ~t4_pc~0); 37011#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37012#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36746#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36747#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 37366#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36790#L513 assume 1 == ~t5_pc~0; 36791#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37014#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37554#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36743#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 36744#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36699#L532 assume !(1 == ~t6_pc~0); 36700#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36849#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37033#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37034#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 36943#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36944#L551 assume 1 == ~t7_pc~0; 37566#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37368#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37369#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37714#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 37718#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37138#L570 assume 1 == ~t8_pc~0; 37139#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37264#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37491#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37262#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 36728#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36729#L952 assume !(1 == ~M_E~0); 36671#L952-2 assume !(1 == ~T1_E~0); 36672#L957-1 assume !(1 == ~T2_E~0); 37502#L962-1 assume !(1 == ~T3_E~0); 37697#L967-1 assume !(1 == ~T4_E~0); 38555#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38505#L977-1 assume !(1 == ~T6_E~0); 38432#L982-1 assume !(1 == ~T7_E~0); 38430#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38429#L992-1 assume !(1 == ~E_M~0); 38428#L997-1 assume !(1 == ~E_1~0); 38425#L1002-1 assume !(1 == ~E_2~0); 38423#L1007-1 assume !(1 == ~E_3~0); 38421#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 36609#L1017-1 assume !(1 == ~E_5~0); 37933#L1022-1 assume !(1 == ~E_6~0); 37908#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 37906#L1032-1 assume !(1 == ~E_8~0); 37886#L1037-1 assume { :end_inline_reset_delta_events } true; 37884#L1303-2 [2022-12-13 19:42:17,989 INFO L750 eck$LassoCheckResult]: Loop: 37884#L1303-2 assume !false; 37796#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37794#L829 assume !false; 37793#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37788#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37783#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37782#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37780#L712 assume !(0 != eval_~tmp~0#1); 37779#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37778#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37777#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37358#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37359#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37710#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37660#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37157#L874-3 assume !(0 == ~T5_E~0); 37158#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39905#L884-3 assume !(0 == ~T7_E~0); 39903#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39900#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 39898#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39896#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39894#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39892#L914-3 assume !(0 == ~E_4~0); 39890#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39889#L924-3 assume !(0 == ~E_6~0); 39888#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 39885#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39882#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37477#L418-30 assume 1 == ~m_pc~0; 37478#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37758#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37759#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37755#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36887#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36888#L437-30 assume !(1 == ~t1_pc~0); 37015#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 37256#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37257#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37298#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37689#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37690#L456-30 assume 1 == ~t2_pc~0; 39860#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39858#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39856#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 39854#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39852#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39850#L475-30 assume !(1 == ~t3_pc~0); 39846#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 39844#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39842#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39840#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39839#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39838#L494-30 assume 1 == ~t4_pc~0; 39836#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39835#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39834#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39833#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 39832#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39831#L513-30 assume 1 == ~t5_pc~0; 39829#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39828#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39827#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39826#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39825#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39824#L532-30 assume !(1 == ~t6_pc~0); 39822#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 39821#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39820#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39819#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39818#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39817#L551-30 assume 1 == ~t7_pc~0; 39815#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39814#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39813#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39812#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39811#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39810#L570-30 assume !(1 == ~t8_pc~0); 39808#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 39807#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39806#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39805#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39804#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39803#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37092#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39802#L957-3 assume !(1 == ~T2_E~0); 39801#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39800#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39799#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37653#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39798#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39797#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39796#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 39795#L997-3 assume !(1 == ~E_1~0); 39636#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38190#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38188#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38184#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38181#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38179#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38168#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38165#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38154#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38150#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38146#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 38143#L1322 assume !(0 == start_simulation_~tmp~3#1); 37432#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38136#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38126#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38121#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 37931#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37907#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37905#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 37885#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 37884#L1303-2 [2022-12-13 19:42:17,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:17,989 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2022-12-13 19:42:17,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:17,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2057990655] [2022-12-13 19:42:17,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:17,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:17,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:18,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:18,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:18,032 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2057990655] [2022-12-13 19:42:18,032 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2057990655] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:18,032 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:18,032 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:18,032 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517134438] [2022-12-13 19:42:18,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:18,033 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:18,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:18,033 INFO L85 PathProgramCache]: Analyzing trace with hash 829059285, now seen corresponding path program 2 times [2022-12-13 19:42:18,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:18,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006744519] [2022-12-13 19:42:18,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:18,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:18,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:18,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:18,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:18,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2006744519] [2022-12-13 19:42:18,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2006744519] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:18,076 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:18,076 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:18,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1745257450] [2022-12-13 19:42:18,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:18,076 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:18,076 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:18,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:42:18,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:42:18,077 INFO L87 Difference]: Start difference. First operand 3404 states and 4966 transitions. cyclomatic complexity: 1566 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:18,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:18,252 INFO L93 Difference]: Finished difference Result 9349 states and 13457 transitions. [2022-12-13 19:42:18,253 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9349 states and 13457 transitions. [2022-12-13 19:42:18,278 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8920 [2022-12-13 19:42:18,302 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9349 states to 9349 states and 13457 transitions. [2022-12-13 19:42:18,303 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9349 [2022-12-13 19:42:18,309 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9349 [2022-12-13 19:42:18,309 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9349 states and 13457 transitions. [2022-12-13 19:42:18,317 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:18,317 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9349 states and 13457 transitions. [2022-12-13 19:42:18,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9349 states and 13457 transitions. [2022-12-13 19:42:18,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9349 to 8861. [2022-12-13 19:42:18,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8861 states, 8861 states have (on average 1.4432908249633225) internal successors, (12789), 8860 states have internal predecessors, (12789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:18,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8861 states to 8861 states and 12789 transitions. [2022-12-13 19:42:18,434 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8861 states and 12789 transitions. [2022-12-13 19:42:18,434 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:42:18,434 INFO L428 stractBuchiCegarLoop]: Abstraction has 8861 states and 12789 transitions. [2022-12-13 19:42:18,434 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 19:42:18,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8861 states and 12789 transitions. [2022-12-13 19:42:18,453 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8692 [2022-12-13 19:42:18,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:18,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:18,454 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:18,454 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:18,454 INFO L748 eck$LassoCheckResult]: Stem: 49675#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 49676#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 50623#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50624#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50778#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 50196#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50197#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49692#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49693#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49623#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49624#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49916#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49885#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49886#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50280#L854 assume !(0 == ~M_E~0); 49996#L854-2 assume !(0 == ~T1_E~0); 49997#L859-1 assume !(0 == ~T2_E~0); 49500#L864-1 assume !(0 == ~T3_E~0); 49501#L869-1 assume !(0 == ~T4_E~0); 49613#L874-1 assume !(0 == ~T5_E~0); 50722#L879-1 assume !(0 == ~T6_E~0); 49982#L884-1 assume !(0 == ~T7_E~0); 49366#L889-1 assume !(0 == ~T8_E~0); 49367#L894-1 assume !(0 == ~E_M~0); 49709#L899-1 assume !(0 == ~E_1~0); 50287#L904-1 assume !(0 == ~E_2~0); 49903#L909-1 assume !(0 == ~E_3~0); 49904#L914-1 assume !(0 == ~E_4~0); 50183#L919-1 assume !(0 == ~E_5~0); 49794#L924-1 assume !(0 == ~E_6~0); 49594#L929-1 assume !(0 == ~E_7~0); 49595#L934-1 assume !(0 == ~E_8~0); 49882#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49384#L418 assume !(1 == ~m_pc~0); 49385#L418-2 is_master_triggered_~__retres1~0#1 := 0; 50582#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50480#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50458#L1061 assume !(0 != activate_threads_~tmp~1#1); 50326#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50327#L437 assume !(1 == ~t1_pc~0); 50694#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50468#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49406#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49407#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 49739#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50444#L456 assume !(1 == ~t2_pc~0); 49653#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49652#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49835#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49836#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 50043#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49494#L475 assume 1 == ~t3_pc~0; 49495#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49559#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49375#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49376#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 49742#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49743#L494 assume !(1 == ~t4_pc~0); 49789#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49790#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49510#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49511#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 50213#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49554#L513 assume 1 == ~t5_pc~0; 49555#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49791#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50484#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49507#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 49508#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49461#L532 assume !(1 == ~t6_pc~0); 49462#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49614#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49811#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49812#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 49715#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49716#L551 assume 1 == ~t7_pc~0; 50507#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50218#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50219#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50828#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 50841#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49930#L570 assume 1 == ~t8_pc~0; 49931#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50079#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50402#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50074#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 49488#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49489#L952 assume !(1 == ~M_E~0); 50474#L952-2 assume !(1 == ~T1_E~0); 55039#L957-1 assume !(1 == ~T2_E~0); 50801#L962-1 assume !(1 == ~T3_E~0); 50802#L967-1 assume !(1 == ~T4_E~0); 54812#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50510#L977-1 assume !(1 == ~T6_E~0); 50511#L982-1 assume !(1 == ~T7_E~0); 49617#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49618#L992-1 assume !(1 == ~E_M~0); 49625#L997-1 assume !(1 == ~E_1~0); 50040#L1002-1 assume !(1 == ~E_2~0); 50020#L1007-1 assume !(1 == ~E_3~0); 50021#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 49369#L1017-1 assume !(1 == ~E_5~0); 57421#L1022-1 assume !(1 == ~E_6~0); 57420#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 57419#L1032-1 assume !(1 == ~E_8~0); 57418#L1037-1 assume { :end_inline_reset_delta_events } true; 57416#L1303-2 [2022-12-13 19:42:18,454 INFO L750 eck$LassoCheckResult]: Loop: 57416#L1303-2 assume !false; 57414#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57413#L829 assume !false; 57412#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 49768#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 49695#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 49861#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 49862#L712 assume !(0 != eval_~tmp~0#1); 57402#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57400#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57397#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 57394#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 57395#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50818#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50819#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49950#L874-3 assume !(0 == ~T5_E~0); 49951#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50101#L884-3 assume !(0 == ~T7_E~0); 50102#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49585#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49586#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49621#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49622#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49564#L914-3 assume !(0 == ~E_4~0); 49565#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50606#L924-3 assume !(0 == ~E_6~0); 50607#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50186#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50187#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50380#L418-30 assume !(1 == ~m_pc~0); 50381#L418-32 is_master_triggered_~__retres1~0#1 := 0; 57244#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57245#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 57240#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 57241#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57236#L437-30 assume !(1 == ~t1_pc~0); 57237#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 57232#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57233#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 57228#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57229#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57223#L456-30 assume 1 == ~t2_pc~0; 57224#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 57216#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57217#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 57210#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57211#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57204#L475-30 assume 1 == ~t3_pc~0; 57205#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57195#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57196#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 57186#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57187#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57179#L494-30 assume !(1 == ~t4_pc~0); 57180#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 57170#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57171#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 57162#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 57163#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57151#L513-30 assume 1 == ~t5_pc~0; 57152#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 57142#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57143#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57007#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57008#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57002#L532-30 assume !(1 == ~t6_pc~0); 57003#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 56997#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56998#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56993#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56994#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49628#L551-30 assume 1 == ~t7_pc~0; 49629#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50481#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50482#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49370#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49371#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50644#L570-30 assume !(1 == ~t8_pc~0); 50645#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 57467#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57466#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57465#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57464#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57463#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49878#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57462#L957-3 assume !(1 == ~T2_E~0); 57461#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57460#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57459#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50700#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57458#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57457#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57456#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 57455#L997-3 assume !(1 == ~E_1~0); 57454#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57453#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57452#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56238#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57451#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57450#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 57449#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 57448#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 57439#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 57438#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 57437#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 57436#L1322 assume !(0 == start_simulation_~tmp~3#1); 50305#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 57434#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 57426#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 57425#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 57424#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57423#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57422#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 57417#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 57416#L1303-2 [2022-12-13 19:42:18,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:18,455 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2022-12-13 19:42:18,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:18,455 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123281561] [2022-12-13 19:42:18,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:18,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:18,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:18,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:18,494 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:18,494 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [123281561] [2022-12-13 19:42:18,494 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [123281561] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:18,494 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:18,494 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:18,494 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [438643557] [2022-12-13 19:42:18,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:18,495 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:18,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:18,495 INFO L85 PathProgramCache]: Analyzing trace with hash 1740039768, now seen corresponding path program 1 times [2022-12-13 19:42:18,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:18,495 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027149739] [2022-12-13 19:42:18,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:18,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:18,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:18,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:18,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:18,522 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027149739] [2022-12-13 19:42:18,522 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027149739] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:18,522 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:18,522 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:18,522 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1177108999] [2022-12-13 19:42:18,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:18,523 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:18,523 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:18,523 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:42:18,523 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:42:18,523 INFO L87 Difference]: Start difference. First operand 8861 states and 12789 transitions. cyclomatic complexity: 3936 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:18,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:18,807 INFO L93 Difference]: Finished difference Result 25208 states and 35974 transitions. [2022-12-13 19:42:18,807 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25208 states and 35974 transitions. [2022-12-13 19:42:18,902 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24428 [2022-12-13 19:42:18,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25208 states to 25208 states and 35974 transitions. [2022-12-13 19:42:18,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25208 [2022-12-13 19:42:18,964 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25208 [2022-12-13 19:42:18,964 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25208 states and 35974 transitions. [2022-12-13 19:42:18,976 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:18,976 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25208 states and 35974 transitions. [2022-12-13 19:42:18,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25208 states and 35974 transitions. [2022-12-13 19:42:19,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25208 to 24378. [2022-12-13 19:42:19,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24378 states, 24378 states have (on average 1.4299778488801378) internal successors, (34860), 24377 states have internal predecessors, (34860), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:19,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24378 states to 24378 states and 34860 transitions. [2022-12-13 19:42:19,409 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24378 states and 34860 transitions. [2022-12-13 19:42:19,410 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:42:19,410 INFO L428 stractBuchiCegarLoop]: Abstraction has 24378 states and 34860 transitions. [2022-12-13 19:42:19,410 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 19:42:19,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24378 states and 34860 transitions. [2022-12-13 19:42:19,466 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24170 [2022-12-13 19:42:19,466 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:19,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:19,467 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:19,467 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:19,468 INFO L748 eck$LassoCheckResult]: Stem: 83745#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 83746#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 84454#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84455#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84524#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 84185#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84186#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83767#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83768#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83695#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 83696#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 83962#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 83934#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 83935#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84245#L854 assume !(0 == ~M_E~0); 84035#L854-2 assume !(0 == ~T1_E~0); 84036#L859-1 assume !(0 == ~T2_E~0); 83573#L864-1 assume !(0 == ~T3_E~0); 83574#L869-1 assume !(0 == ~T4_E~0); 83684#L874-1 assume !(0 == ~T5_E~0); 84498#L879-1 assume !(0 == ~T6_E~0); 84017#L884-1 assume !(0 == ~T7_E~0); 83445#L889-1 assume !(0 == ~T8_E~0); 83446#L894-1 assume !(0 == ~E_M~0); 83778#L899-1 assume !(0 == ~E_1~0); 84251#L904-1 assume !(0 == ~E_2~0); 83954#L909-1 assume !(0 == ~E_3~0); 83955#L914-1 assume !(0 == ~E_4~0); 84173#L919-1 assume !(0 == ~E_5~0); 83854#L924-1 assume !(0 == ~E_6~0); 83670#L929-1 assume !(0 == ~E_7~0); 83671#L934-1 assume !(0 == ~E_8~0); 83933#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83462#L418 assume !(1 == ~m_pc~0); 83463#L418-2 is_master_triggered_~__retres1~0#1 := 0; 84441#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84387#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 84372#L1061 assume !(0 != activate_threads_~tmp~1#1); 84276#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84277#L437 assume !(1 == ~t1_pc~0); 84488#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 84379#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83487#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 83488#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 83803#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84364#L456 assume !(1 == ~t2_pc~0); 83725#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 83724#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83887#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 83888#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 84069#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83568#L475 assume !(1 == ~t3_pc~0); 83569#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 83633#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83453#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 83454#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 83806#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83807#L494 assume !(1 == ~t4_pc~0); 83847#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 83848#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83583#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 83584#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 84200#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83628#L513 assume 1 == ~t5_pc~0; 83629#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83853#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84389#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83580#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 83581#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83539#L532 assume !(1 == ~t6_pc~0); 83540#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 83685#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83870#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 83871#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 83780#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83781#L551 assume 1 == ~t7_pc~0; 84405#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 84202#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84203#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84549#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 84554#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 83973#L570 assume 1 == ~t8_pc~0; 83974#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 84098#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84325#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84095#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 83566#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83567#L952 assume !(1 == ~M_E~0); 84383#L952-2 assume !(1 == ~T1_E~0); 84335#L957-1 assume !(1 == ~T2_E~0); 84336#L962-1 assume !(1 == ~T3_E~0); 84113#L967-1 assume !(1 == ~T4_E~0); 84114#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 84408#L977-1 assume !(1 == ~T6_E~0); 84409#L982-1 assume !(1 == ~T7_E~0); 83687#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 83688#L992-1 assume !(1 == ~E_M~0); 84066#L997-1 assume !(1 == ~E_1~0); 84067#L1002-1 assume !(1 == ~E_2~0); 84050#L1007-1 assume !(1 == ~E_3~0); 84051#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 83448#L1017-1 assume !(1 == ~E_5~0); 84057#L1022-1 assume !(1 == ~E_6~0); 84058#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 84082#L1032-1 assume !(1 == ~E_8~0); 84234#L1037-1 assume { :end_inline_reset_delta_events } true; 84235#L1303-2 [2022-12-13 19:42:19,468 INFO L750 eck$LassoCheckResult]: Loop: 84235#L1303-2 assume !false; 106101#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 106100#L829 assume !false; 106095#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 106096#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 106664#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 106663#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 106661#L712 assume !(0 != eval_~tmp~0#1); 106662#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 107385#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 107383#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 107382#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 107381#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 107379#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 107377#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 107375#L874-3 assume !(0 == ~T5_E~0); 107373#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 107371#L884-3 assume !(0 == ~T7_E~0); 107369#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 107367#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 107365#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 107363#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 107361#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 107359#L914-3 assume !(0 == ~E_4~0); 107357#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 107355#L924-3 assume !(0 == ~E_6~0); 107353#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 107351#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 107349#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 107347#L418-30 assume !(1 == ~m_pc~0); 107345#L418-32 is_master_triggered_~__retres1~0#1 := 0; 107343#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107341#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 107339#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 107337#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 107334#L437-30 assume !(1 == ~t1_pc~0); 107335#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 107558#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 107557#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 107556#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 107555#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107554#L456-30 assume !(1 == ~t2_pc~0); 107553#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 107551#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107550#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 107549#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 107548#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107547#L475-30 assume !(1 == ~t3_pc~0); 107546#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 107545#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 107544#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 107543#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 107542#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 107541#L494-30 assume !(1 == ~t4_pc~0); 107539#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 107537#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 107536#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 107535#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 107534#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 107533#L513-30 assume 1 == ~t5_pc~0; 107531#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 107530#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 107529#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 107528#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 107527#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 107526#L532-30 assume 1 == ~t6_pc~0; 107525#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 107523#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 107522#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 107521#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 107520#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 107519#L551-30 assume 1 == ~t7_pc~0; 83761#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 83762#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84282#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83449#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 83450#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 83808#L570-30 assume !(1 == ~t8_pc~0); 84184#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 83693#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83694#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 83505#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 83506#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83881#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 83928#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 84461#L957-3 assume !(1 == ~T2_E~0); 84462#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 84358#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 84359#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 100537#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 107489#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 107488#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 107487#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 107486#L997-3 assume !(1 == ~E_1~0); 107485#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 107484#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 107483#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 94620#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 107482#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 107481#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 107480#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 107479#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 107470#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 107469#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 106522#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 84505#L1322 assume !(0 == start_simulation_~tmp~3#1); 84266#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 106279#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 107001#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 106991#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 106257#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 106256#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 106255#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 106251#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 84235#L1303-2 [2022-12-13 19:42:19,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:19,468 INFO L85 PathProgramCache]: Analyzing trace with hash -1079871162, now seen corresponding path program 1 times [2022-12-13 19:42:19,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:19,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531888221] [2022-12-13 19:42:19,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:19,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:19,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:19,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:19,503 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:19,503 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [531888221] [2022-12-13 19:42:19,503 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [531888221] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:19,503 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:19,503 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:42:19,504 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618200614] [2022-12-13 19:42:19,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:19,504 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:19,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:19,504 INFO L85 PathProgramCache]: Analyzing trace with hash 246351449, now seen corresponding path program 1 times [2022-12-13 19:42:19,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:19,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454040768] [2022-12-13 19:42:19,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:19,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:19,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:19,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:19,534 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:19,534 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [454040768] [2022-12-13 19:42:19,534 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [454040768] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:19,534 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:19,535 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:19,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1137192213] [2022-12-13 19:42:19,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:19,535 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:19,535 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:19,536 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:19,537 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:19,540 INFO L87 Difference]: Start difference. First operand 24378 states and 34860 transitions. cyclomatic complexity: 10498 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:19,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:19,718 INFO L93 Difference]: Finished difference Result 45992 states and 65497 transitions. [2022-12-13 19:42:19,718 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45992 states and 65497 transitions. [2022-12-13 19:42:19,872 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45653 [2022-12-13 19:42:19,966 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45992 states to 45992 states and 65497 transitions. [2022-12-13 19:42:19,967 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45992 [2022-12-13 19:42:19,985 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45992 [2022-12-13 19:42:19,986 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45992 states and 65497 transitions. [2022-12-13 19:42:20,008 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:20,008 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45992 states and 65497 transitions. [2022-12-13 19:42:20,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45992 states and 65497 transitions. [2022-12-13 19:42:20,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45992 to 45920. [2022-12-13 19:42:20,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45920 states, 45920 states have (on average 1.4247604529616724) internal successors, (65425), 45919 states have internal predecessors, (65425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:20,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45920 states to 45920 states and 65425 transitions. [2022-12-13 19:42:20,451 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45920 states and 65425 transitions. [2022-12-13 19:42:20,452 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:20,452 INFO L428 stractBuchiCegarLoop]: Abstraction has 45920 states and 65425 transitions. [2022-12-13 19:42:20,452 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 19:42:20,452 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45920 states and 65425 transitions. [2022-12-13 19:42:20,602 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45581 [2022-12-13 19:42:20,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:20,603 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:20,603 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:20,603 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:20,604 INFO L748 eck$LassoCheckResult]: Stem: 154122#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 154123#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 154851#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 154852#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 154923#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 154566#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 154567#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 154142#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 154143#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 154073#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 154074#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 154341#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 154311#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 154312#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 154630#L854 assume !(0 == ~M_E~0); 154415#L854-2 assume !(0 == ~T1_E~0); 154416#L859-1 assume !(0 == ~T2_E~0); 153951#L864-1 assume !(0 == ~T3_E~0); 153952#L869-1 assume !(0 == ~T4_E~0); 154062#L874-1 assume !(0 == ~T5_E~0); 154899#L879-1 assume !(0 == ~T6_E~0); 154399#L884-1 assume !(0 == ~T7_E~0); 153821#L889-1 assume !(0 == ~T8_E~0); 153822#L894-1 assume !(0 == ~E_M~0); 154154#L899-1 assume !(0 == ~E_1~0); 154637#L904-1 assume !(0 == ~E_2~0); 154332#L909-1 assume !(0 == ~E_3~0); 154333#L914-1 assume !(0 == ~E_4~0); 154553#L919-1 assume !(0 == ~E_5~0); 154232#L924-1 assume !(0 == ~E_6~0); 154048#L929-1 assume !(0 == ~E_7~0); 154049#L934-1 assume !(0 == ~E_8~0); 154308#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 153838#L418 assume !(1 == ~m_pc~0); 153839#L418-2 is_master_triggered_~__retres1~0#1 := 0; 154833#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154772#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 154757#L1061 assume !(0 != activate_threads_~tmp~1#1); 154663#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 154664#L437 assume !(1 == ~t1_pc~0); 154884#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 154764#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153860#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 153861#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 154179#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 154750#L456 assume !(1 == ~t2_pc~0); 154102#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 154101#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 154266#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 154267#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 154450#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153946#L475 assume !(1 == ~t3_pc~0); 153947#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 154011#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153829#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 153830#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 154182#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154183#L494 assume !(1 == ~t4_pc~0); 154226#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 154227#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153961#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 153962#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 154581#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 154007#L513 assume !(1 == ~t5_pc~0); 154008#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 154231#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 154774#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 153958#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 153959#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 153915#L532 assume !(1 == ~t6_pc~0); 153916#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 154063#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 154248#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 154249#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 154156#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 154157#L551 assume 1 == ~t7_pc~0; 154792#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 154583#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 154584#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 154953#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 154957#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 154351#L570 assume 1 == ~t8_pc~0; 154352#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 154478#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 154713#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 154475#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 153944#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153945#L952 assume !(1 == ~M_E~0); 154769#L952-2 assume !(1 == ~T1_E~0); 154724#L957-1 assume !(1 == ~T2_E~0); 154725#L962-1 assume !(1 == ~T3_E~0); 154492#L967-1 assume !(1 == ~T4_E~0); 154493#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 168348#L977-1 assume !(1 == ~T6_E~0); 168342#L982-1 assume !(1 == ~T7_E~0); 168201#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 168199#L992-1 assume !(1 == ~E_M~0); 168197#L997-1 assume !(1 == ~E_1~0); 168196#L1002-1 assume !(1 == ~E_2~0); 168168#L1007-1 assume !(1 == ~E_3~0); 168158#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 153824#L1017-1 assume !(1 == ~E_5~0); 173539#L1022-1 assume !(1 == ~E_6~0); 173535#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 173533#L1032-1 assume !(1 == ~E_8~0); 173531#L1037-1 assume { :end_inline_reset_delta_events } true; 173529#L1303-2 [2022-12-13 19:42:20,604 INFO L750 eck$LassoCheckResult]: Loop: 173529#L1303-2 assume !false; 173501#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 173498#L829 assume !false; 173495#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 173449#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 173441#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 173436#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 173430#L712 assume !(0 != eval_~tmp~0#1); 173431#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 175505#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 175504#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 175502#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 175500#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 175498#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 175496#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 175494#L874-3 assume !(0 == ~T5_E~0); 175492#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 175490#L884-3 assume !(0 == ~T7_E~0); 175488#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 175486#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 175484#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 175482#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 175480#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 175478#L914-3 assume !(0 == ~E_4~0); 175475#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 175469#L924-3 assume !(0 == ~E_6~0); 175467#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 174281#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 174271#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 174269#L418-30 assume !(1 == ~m_pc~0); 174267#L418-32 is_master_triggered_~__retres1~0#1 := 0; 174265#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174263#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 174261#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 174259#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 174258#L437-30 assume !(1 == ~t1_pc~0); 174257#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 174256#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 174255#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 174247#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 174230#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174208#L456-30 assume 1 == ~t2_pc~0; 174103#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 174101#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 174099#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 174067#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 174057#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 174055#L475-30 assume !(1 == ~t3_pc~0); 174053#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 174050#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 174048#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 174046#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 174044#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 174042#L494-30 assume 1 == ~t4_pc~0; 174039#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 174037#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 174035#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 174033#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 174031#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 174029#L513-30 assume !(1 == ~t5_pc~0); 174027#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 174025#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 174023#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 174021#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 174019#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 174017#L532-30 assume !(1 == ~t6_pc~0); 174014#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 174012#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 174010#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 174008#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 174006#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 174004#L551-30 assume !(1 == ~t7_pc~0); 174002#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 173999#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 173997#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 173995#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 173993#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 173991#L570-30 assume !(1 == ~t8_pc~0); 173988#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 173986#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 173984#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 173982#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 173964#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 173956#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 167978#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 173943#L957-3 assume !(1 == ~T2_E~0); 173934#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 173831#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 173773#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 173764#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 173757#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 173750#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 173742#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 173733#L997-3 assume !(1 == ~E_1~0); 173725#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 173718#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 173711#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 167948#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 173697#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 173688#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 173675#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 173671#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 173629#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 173627#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 173613#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 173602#L1322 assume !(0 == start_simulation_~tmp~3#1); 173587#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 173566#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 173557#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 173554#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 173552#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 173550#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 173548#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 173530#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 173529#L1303-2 [2022-12-13 19:42:20,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:20,605 INFO L85 PathProgramCache]: Analyzing trace with hash 818659143, now seen corresponding path program 1 times [2022-12-13 19:42:20,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:20,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [272149734] [2022-12-13 19:42:20,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:20,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:20,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:20,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:20,646 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:20,646 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [272149734] [2022-12-13 19:42:20,647 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [272149734] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:20,647 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:20,647 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:20,647 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [769246877] [2022-12-13 19:42:20,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:20,647 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:20,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:20,647 INFO L85 PathProgramCache]: Analyzing trace with hash -655563750, now seen corresponding path program 1 times [2022-12-13 19:42:20,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:20,647 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278714627] [2022-12-13 19:42:20,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:20,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:20,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:20,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:20,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:20,677 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [278714627] [2022-12-13 19:42:20,677 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [278714627] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:20,677 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:20,677 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:20,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996845634] [2022-12-13 19:42:20,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:20,677 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:20,677 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:20,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:42:20,677 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:42:20,677 INFO L87 Difference]: Start difference. First operand 45920 states and 65425 transitions. cyclomatic complexity: 19537 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:21,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:21,148 INFO L93 Difference]: Finished difference Result 127061 states and 179748 transitions. [2022-12-13 19:42:21,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127061 states and 179748 transitions. [2022-12-13 19:42:21,601 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 123987 [2022-12-13 19:42:21,893 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127061 states to 127061 states and 179748 transitions. [2022-12-13 19:42:21,893 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127061 [2022-12-13 19:42:21,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127061 [2022-12-13 19:42:21,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127061 states and 179748 transitions. [2022-12-13 19:42:22,008 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:22,008 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127061 states and 179748 transitions. [2022-12-13 19:42:22,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127061 states and 179748 transitions. [2022-12-13 19:42:22,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127061 to 123549. [2022-12-13 19:42:23,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123549 states, 123549 states have (on average 1.4182227294433787) internal successors, (175220), 123548 states have internal predecessors, (175220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:23,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123549 states to 123549 states and 175220 transitions. [2022-12-13 19:42:23,244 INFO L240 hiAutomatonCegarLoop]: Abstraction has 123549 states and 175220 transitions. [2022-12-13 19:42:23,244 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:42:23,245 INFO L428 stractBuchiCegarLoop]: Abstraction has 123549 states and 175220 transitions. [2022-12-13 19:42:23,245 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 19:42:23,245 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123549 states and 175220 transitions. [2022-12-13 19:42:23,638 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 122907 [2022-12-13 19:42:23,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:23,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:23,640 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:23,640 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:23,640 INFO L748 eck$LassoCheckResult]: Stem: 327113#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 327114#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 327878#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 327879#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 327964#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 327575#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 327576#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 327135#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 327136#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 327065#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 327066#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 327340#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 327312#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 327313#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 327645#L854 assume !(0 == ~M_E~0); 327412#L854-2 assume !(0 == ~T1_E~0); 327413#L859-1 assume !(0 == ~T2_E~0); 326942#L864-1 assume !(0 == ~T3_E~0); 326943#L869-1 assume !(0 == ~T4_E~0); 327054#L874-1 assume !(0 == ~T5_E~0); 327928#L879-1 assume !(0 == ~T6_E~0); 327396#L884-1 assume !(0 == ~T7_E~0); 326812#L889-1 assume !(0 == ~T8_E~0); 326813#L894-1 assume !(0 == ~E_M~0); 327147#L899-1 assume !(0 == ~E_1~0); 327651#L904-1 assume !(0 == ~E_2~0); 327334#L909-1 assume !(0 == ~E_3~0); 327335#L914-1 assume !(0 == ~E_4~0); 327564#L919-1 assume !(0 == ~E_5~0); 327229#L924-1 assume !(0 == ~E_6~0); 327039#L929-1 assume !(0 == ~E_7~0); 327040#L934-1 assume !(0 == ~E_8~0); 327311#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 326830#L418 assume !(1 == ~m_pc~0); 326831#L418-2 is_master_triggered_~__retres1~0#1 := 0; 327862#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 327796#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 327778#L1061 assume !(0 != activate_threads_~tmp~1#1); 327679#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 327680#L437 assume !(1 == ~t1_pc~0); 327915#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 327785#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 326854#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 326855#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 327175#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 327769#L456 assume !(1 == ~t2_pc~0); 327093#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 327092#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 327264#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 327265#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 327448#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326937#L475 assume !(1 == ~t3_pc~0); 326938#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 327001#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 326821#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 326822#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 327178#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 327179#L494 assume !(1 == ~t4_pc~0); 327223#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 327224#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 326952#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 326953#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 327591#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 326997#L513 assume !(1 == ~t5_pc~0); 326998#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 327228#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 327798#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 326949#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 326950#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 326906#L532 assume !(1 == ~t6_pc~0); 326907#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 327055#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 327246#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 327247#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 327150#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 327151#L551 assume !(1 == ~t7_pc~0); 327652#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 327594#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 327595#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 327997#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 328002#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 327351#L570 assume 1 == ~t8_pc~0; 327352#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 327479#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 327730#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 327476#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 326935#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 326936#L952 assume !(1 == ~M_E~0); 327790#L952-2 assume !(1 == ~T1_E~0); 327743#L957-1 assume !(1 == ~T2_E~0); 327744#L962-1 assume !(1 == ~T3_E~0); 327496#L967-1 assume !(1 == ~T4_E~0); 327497#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 336254#L977-1 assume !(1 == ~T6_E~0); 336253#L982-1 assume !(1 == ~T7_E~0); 336252#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 336251#L992-1 assume !(1 == ~E_M~0); 336250#L997-1 assume !(1 == ~E_1~0); 336249#L1002-1 assume !(1 == ~E_2~0); 336248#L1007-1 assume !(1 == ~E_3~0); 336246#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 336247#L1017-1 assume !(1 == ~E_5~0); 336580#L1022-1 assume !(1 == ~E_6~0); 336579#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 336578#L1032-1 assume !(1 == ~E_8~0); 336576#L1037-1 assume { :end_inline_reset_delta_events } true; 336577#L1303-2 [2022-12-13 19:42:23,640 INFO L750 eck$LassoCheckResult]: Loop: 336577#L1303-2 assume !false; 359821#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 359819#L829 assume !false; 359817#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 359818#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 408540#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 408539#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 408537#L712 assume !(0 != eval_~tmp~0#1); 408538#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 408824#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 408823#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 408822#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 408821#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 408820#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 408819#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 408818#L874-3 assume !(0 == ~T5_E~0); 408817#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 408816#L884-3 assume !(0 == ~T7_E~0); 408815#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 408814#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 408813#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 408812#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 408811#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 408810#L914-3 assume !(0 == ~E_4~0); 408809#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 408808#L924-3 assume !(0 == ~E_6~0); 408807#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 408806#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 408805#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 408804#L418-30 assume !(1 == ~m_pc~0); 408803#L418-32 is_master_triggered_~__retres1~0#1 := 0; 408802#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 408801#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 408800#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 408799#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 408798#L437-30 assume !(1 == ~t1_pc~0); 408797#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 408796#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 408795#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 408794#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 408793#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 408792#L456-30 assume 1 == ~t2_pc~0; 408790#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 408789#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 408788#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 408787#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 408786#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 408785#L475-30 assume !(1 == ~t3_pc~0); 408784#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 408783#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 408782#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 408781#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 408780#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 408779#L494-30 assume !(1 == ~t4_pc~0); 408778#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 408776#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 408775#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 408774#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 408773#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 408772#L513-30 assume !(1 == ~t5_pc~0); 408771#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 408770#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 408769#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 408768#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 408767#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 408766#L532-30 assume !(1 == ~t6_pc~0); 408764#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 408763#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 408762#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 408761#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 408760#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 408759#L551-30 assume !(1 == ~t7_pc~0); 408758#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 408757#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 408756#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 408755#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 408754#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 408753#L570-30 assume 1 == ~t8_pc~0; 408752#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 408750#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 408749#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 408748#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 408747#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 408746#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 360348#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 408745#L957-3 assume !(1 == ~T2_E~0); 408744#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 408743#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 408742#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 361177#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 408741#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 408740#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 408739#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 408738#L997-3 assume !(1 == ~E_1~0); 408737#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 408736#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 408735#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 360331#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 408734#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 408733#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 408732#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 360322#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 360323#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 408572#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 408571#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 408570#L1322 assume !(0 == start_simulation_~tmp~3#1); 408569#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 359974#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 359966#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 359965#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 359964#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 359963#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 359962#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 359961#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 336577#L1303-2 [2022-12-13 19:42:23,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:23,640 INFO L85 PathProgramCache]: Analyzing trace with hash -952811832, now seen corresponding path program 1 times [2022-12-13 19:42:23,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:23,641 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102974850] [2022-12-13 19:42:23,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:23,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:23,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:23,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:23,677 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:23,678 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [102974850] [2022-12-13 19:42:23,678 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [102974850] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:23,678 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:23,678 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 19:42:23,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1594155285] [2022-12-13 19:42:23,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:23,678 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:23,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:23,679 INFO L85 PathProgramCache]: Analyzing trace with hash -752291558, now seen corresponding path program 1 times [2022-12-13 19:42:23,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:23,679 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429899045] [2022-12-13 19:42:23,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:23,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:23,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:23,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:23,705 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:23,705 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [429899045] [2022-12-13 19:42:23,705 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [429899045] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:23,705 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:23,705 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:23,706 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639436160] [2022-12-13 19:42:23,706 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:23,706 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:23,706 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:23,706 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:23,706 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:23,707 INFO L87 Difference]: Start difference. First operand 123549 states and 175220 transitions. cyclomatic complexity: 51735 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:24,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:24,484 INFO L93 Difference]: Finished difference Result 231925 states and 328130 transitions. [2022-12-13 19:42:24,484 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 231925 states and 328130 transitions. [2022-12-13 19:42:25,382 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 230356 [2022-12-13 19:42:25,733 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 231925 states to 231925 states and 328130 transitions. [2022-12-13 19:42:25,733 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 231925 [2022-12-13 19:42:25,809 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 231925 [2022-12-13 19:42:25,809 INFO L73 IsDeterministic]: Start isDeterministic. Operand 231925 states and 328130 transitions. [2022-12-13 19:42:25,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:25,878 INFO L218 hiAutomatonCegarLoop]: Abstraction has 231925 states and 328130 transitions. [2022-12-13 19:42:25,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231925 states and 328130 transitions. [2022-12-13 19:42:27,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231925 to 231493. [2022-12-13 19:42:27,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 231493 states, 231493 states have (on average 1.4155849204943562) internal successors, (327698), 231492 states have internal predecessors, (327698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:28,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231493 states to 231493 states and 327698 transitions. [2022-12-13 19:42:28,253 INFO L240 hiAutomatonCegarLoop]: Abstraction has 231493 states and 327698 transitions. [2022-12-13 19:42:28,253 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:28,254 INFO L428 stractBuchiCegarLoop]: Abstraction has 231493 states and 327698 transitions. [2022-12-13 19:42:28,254 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 19:42:28,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 231493 states and 327698 transitions. [2022-12-13 19:42:28,909 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 229924 [2022-12-13 19:42:28,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:28,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:28,910 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:28,910 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:28,910 INFO L748 eck$LassoCheckResult]: Stem: 682592#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 682593#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 683313#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 683314#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 683386#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 683032#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 683033#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 682614#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 682615#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 682544#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 682545#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 682811#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 682784#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 682785#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 683099#L854 assume !(0 == ~M_E~0); 682881#L854-2 assume !(0 == ~T1_E~0); 682882#L859-1 assume !(0 == ~T2_E~0); 682422#L864-1 assume !(0 == ~T3_E~0); 682423#L869-1 assume !(0 == ~T4_E~0); 682533#L874-1 assume !(0 == ~T5_E~0); 683363#L879-1 assume !(0 == ~T6_E~0); 682865#L884-1 assume !(0 == ~T7_E~0); 682293#L889-1 assume !(0 == ~T8_E~0); 682294#L894-1 assume !(0 == ~E_M~0); 682626#L899-1 assume !(0 == ~E_1~0); 683105#L904-1 assume !(0 == ~E_2~0); 682805#L909-1 assume !(0 == ~E_3~0); 682806#L914-1 assume !(0 == ~E_4~0); 683023#L919-1 assume !(0 == ~E_5~0); 682705#L924-1 assume !(0 == ~E_6~0); 682519#L929-1 assume !(0 == ~E_7~0); 682520#L934-1 assume !(0 == ~E_8~0); 682781#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 682310#L418 assume !(1 == ~m_pc~0); 682311#L418-2 is_master_triggered_~__retres1~0#1 := 0; 683299#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 683242#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 683223#L1061 assume !(0 != activate_threads_~tmp~1#1); 683132#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 683133#L437 assume !(1 == ~t1_pc~0); 683345#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 683233#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 682334#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 682335#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 682652#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 683216#L456 assume !(1 == ~t2_pc~0); 682573#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 682572#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 682738#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 682739#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 682915#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 682417#L475 assume !(1 == ~t3_pc~0); 682418#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 682482#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 682301#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 682302#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 682655#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 682656#L494 assume !(1 == ~t4_pc~0); 682699#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 682700#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 682432#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 682433#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 683048#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 682478#L513 assume !(1 == ~t5_pc~0); 682479#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 682704#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 683244#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 682429#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 682430#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 682386#L532 assume !(1 == ~t6_pc~0); 682387#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 682534#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 682721#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 682722#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 682628#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 682629#L551 assume !(1 == ~t7_pc~0); 683106#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 683050#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 683051#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 683417#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 683421#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 682822#L570 assume !(1 == ~t8_pc~0); 682823#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 683319#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 683181#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 682942#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 682415#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 682416#L952 assume !(1 == ~M_E~0); 683238#L952-2 assume !(1 == ~T1_E~0); 683192#L957-1 assume !(1 == ~T2_E~0); 683193#L962-1 assume !(1 == ~T3_E~0); 682960#L967-1 assume !(1 == ~T4_E~0); 682961#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 708012#L977-1 assume !(1 == ~T6_E~0); 708011#L982-1 assume !(1 == ~T7_E~0); 708010#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 708009#L992-1 assume !(1 == ~E_M~0); 708008#L997-1 assume !(1 == ~E_1~0); 708007#L1002-1 assume !(1 == ~E_2~0); 708006#L1007-1 assume !(1 == ~E_3~0); 708005#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 682296#L1017-1 assume !(1 == ~E_5~0); 683160#L1022-1 assume !(1 == ~E_6~0); 682928#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 682929#L1032-1 assume !(1 == ~E_8~0); 683087#L1037-1 assume { :end_inline_reset_delta_events } true; 683088#L1303-2 [2022-12-13 19:42:28,910 INFO L750 eck$LassoCheckResult]: Loop: 683088#L1303-2 assume !false; 766398#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 766397#L829 assume !false; 766396#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 766391#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 766386#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 766385#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 766383#L712 assume !(0 != eval_~tmp~0#1); 766384#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 766659#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 766658#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 766657#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 766656#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 766655#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 766654#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 766653#L874-3 assume !(0 == ~T5_E~0); 766652#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 766651#L884-3 assume !(0 == ~T7_E~0); 766650#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 766649#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 766648#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 766647#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 766646#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 766645#L914-3 assume !(0 == ~E_4~0); 766644#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 766643#L924-3 assume !(0 == ~E_6~0); 766642#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 766641#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 766640#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 766639#L418-30 assume !(1 == ~m_pc~0); 766638#L418-32 is_master_triggered_~__retres1~0#1 := 0; 766637#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 766636#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 766635#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 766634#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 766633#L437-30 assume !(1 == ~t1_pc~0); 766632#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 766631#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 766630#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 766629#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 766628#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 766627#L456-30 assume !(1 == ~t2_pc~0); 766626#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 766624#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 766623#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 766622#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 766621#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 766620#L475-30 assume !(1 == ~t3_pc~0); 766619#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 766618#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 766617#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 766616#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 766615#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 766614#L494-30 assume !(1 == ~t4_pc~0); 766613#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 766611#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 766610#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 766609#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 766608#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 766607#L513-30 assume !(1 == ~t5_pc~0); 766606#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 766605#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 766604#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 766603#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 766602#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 766601#L532-30 assume 1 == ~t6_pc~0; 766600#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 766598#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 766597#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 766596#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 766595#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 766594#L551-30 assume !(1 == ~t7_pc~0); 766593#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 766592#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 766591#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 766590#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 766589#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 766588#L570-30 assume !(1 == ~t8_pc~0); 766587#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 766586#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 766585#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 766584#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 766583#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 766582#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 734173#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 766581#L957-3 assume !(1 == ~T2_E~0); 766580#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 766579#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 766578#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 756298#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 766577#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 766576#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 766575#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 766574#L997-3 assume !(1 == ~E_1~0); 766573#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 766572#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 766571#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 750646#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 766570#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 766569#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 766568#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 766567#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 766558#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 766557#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 766556#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 766555#L1322 assume !(0 == start_simulation_~tmp~3#1); 766553#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 766551#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 766543#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 766542#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 766541#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 766540#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 766539#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 766538#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 683088#L1303-2 [2022-12-13 19:42:28,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:28,910 INFO L85 PathProgramCache]: Analyzing trace with hash 1284551433, now seen corresponding path program 1 times [2022-12-13 19:42:28,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:28,911 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [95063522] [2022-12-13 19:42:28,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:28,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:28,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:28,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:28,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:28,946 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [95063522] [2022-12-13 19:42:28,946 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [95063522] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:28,947 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:28,947 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:28,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [836317478] [2022-12-13 19:42:28,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:28,947 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:28,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:28,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1036753115, now seen corresponding path program 1 times [2022-12-13 19:42:28,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:28,948 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793086257] [2022-12-13 19:42:28,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:28,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:28,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:28,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:28,971 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:28,971 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793086257] [2022-12-13 19:42:28,971 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [793086257] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:28,971 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:28,971 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:28,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1748656084] [2022-12-13 19:42:28,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:28,972 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:28,972 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:28,972 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:42:28,972 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:42:28,972 INFO L87 Difference]: Start difference. First operand 231493 states and 327698 transitions. cyclomatic complexity: 96333 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:29,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:29,366 INFO L93 Difference]: Finished difference Result 176932 states and 249822 transitions. [2022-12-13 19:42:29,367 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176932 states and 249822 transitions. [2022-12-13 19:42:30,076 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 175750 [2022-12-13 19:42:30,402 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176932 states to 176932 states and 249822 transitions. [2022-12-13 19:42:30,402 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176932 [2022-12-13 19:42:30,612 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176932 [2022-12-13 19:42:30,612 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176932 states and 249822 transitions. [2022-12-13 19:42:30,654 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:30,654 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176932 states and 249822 transitions. [2022-12-13 19:42:30,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176932 states and 249822 transitions. [2022-12-13 19:42:31,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176932 to 122397. [2022-12-13 19:42:31,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122397 states, 122397 states have (on average 1.4123140273045909) internal successors, (172863), 122396 states have internal predecessors, (172863), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:32,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122397 states to 122397 states and 172863 transitions. [2022-12-13 19:42:32,010 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122397 states and 172863 transitions. [2022-12-13 19:42:32,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:42:32,011 INFO L428 stractBuchiCegarLoop]: Abstraction has 122397 states and 172863 transitions. [2022-12-13 19:42:32,011 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 19:42:32,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122397 states and 172863 transitions. [2022-12-13 19:42:32,427 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 121576 [2022-12-13 19:42:32,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:32,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:32,428 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:32,428 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:32,428 INFO L748 eck$LassoCheckResult]: Stem: 1091028#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1091029#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1091761#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1091762#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1091839#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1091480#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1091481#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1091049#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1091050#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1090980#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1090981#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1091253#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1091224#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1091225#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1091543#L854 assume !(0 == ~M_E~0); 1091324#L854-2 assume !(0 == ~T1_E~0); 1091325#L859-1 assume !(0 == ~T2_E~0); 1090857#L864-1 assume !(0 == ~T3_E~0); 1090858#L869-1 assume !(0 == ~T4_E~0); 1090968#L874-1 assume !(0 == ~T5_E~0); 1091813#L879-1 assume !(0 == ~T6_E~0); 1091308#L884-1 assume !(0 == ~T7_E~0); 1090728#L889-1 assume !(0 == ~T8_E~0); 1090729#L894-1 assume !(0 == ~E_M~0); 1091065#L899-1 assume !(0 == ~E_1~0); 1091549#L904-1 assume !(0 == ~E_2~0); 1091246#L909-1 assume !(0 == ~E_3~0); 1091247#L914-1 assume !(0 == ~E_4~0); 1091467#L919-1 assume !(0 == ~E_5~0); 1091144#L924-1 assume !(0 == ~E_6~0); 1090954#L929-1 assume !(0 == ~E_7~0); 1090955#L934-1 assume !(0 == ~E_8~0); 1091223#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1090745#L418 assume !(1 == ~m_pc~0); 1090746#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1091743#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1091684#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1091670#L1061 assume !(0 != activate_threads_~tmp~1#1); 1091577#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1091578#L437 assume !(1 == ~t1_pc~0); 1091797#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1091677#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1090769#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1090770#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1091092#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1091662#L456 assume !(1 == ~t2_pc~0); 1091008#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1091007#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1091178#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1091179#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1091356#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1090852#L475 assume !(1 == ~t3_pc~0); 1090853#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1090917#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1090736#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1090737#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1091095#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1091096#L494 assume !(1 == ~t4_pc~0); 1091139#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1091140#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1090867#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1090868#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1091496#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1090910#L513 assume !(1 == ~t5_pc~0); 1090911#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1091143#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1091686#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1090864#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1090865#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1090821#L532 assume !(1 == ~t6_pc~0); 1090822#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1090969#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1091161#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1091162#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1091068#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1091069#L551 assume !(1 == ~t7_pc~0); 1091550#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1091498#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1091499#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1091860#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1091863#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1091266#L570 assume !(1 == ~t8_pc~0); 1091267#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1091765#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1091627#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1091382#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1090850#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1090851#L952 assume !(1 == ~M_E~0); 1090791#L952-2 assume !(1 == ~T1_E~0); 1090792#L957-1 assume !(1 == ~T2_E~0); 1091638#L962-1 assume !(1 == ~T3_E~0); 1091401#L967-1 assume !(1 == ~T4_E~0); 1091402#L972-1 assume !(1 == ~T5_E~0); 1091705#L977-1 assume !(1 == ~T6_E~0); 1091706#L982-1 assume !(1 == ~T7_E~0); 1090972#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1090973#L992-1 assume !(1 == ~E_M~0); 1090982#L997-1 assume !(1 == ~E_1~0); 1091354#L1002-1 assume !(1 == ~E_2~0); 1091339#L1007-1 assume !(1 == ~E_3~0); 1090730#L1012-1 assume !(1 == ~E_4~0); 1090731#L1017-1 assume !(1 == ~E_5~0); 1091342#L1022-1 assume !(1 == ~E_6~0); 1091343#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1091369#L1032-1 assume !(1 == ~E_8~0); 1091529#L1037-1 assume { :end_inline_reset_delta_events } true; 1091530#L1303-2 [2022-12-13 19:42:32,428 INFO L750 eck$LassoCheckResult]: Loop: 1091530#L1303-2 assume !false; 1137873#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1137871#L829 assume !false; 1137544#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1137040#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1137034#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1137032#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1137030#L712 assume !(0 != eval_~tmp~0#1); 1109059#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1109056#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1109057#L854-3 assume !(0 == ~M_E~0); 1142475#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1142474#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1142473#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1142472#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1142471#L874-3 assume !(0 == ~T5_E~0); 1142470#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1142469#L884-3 assume !(0 == ~T7_E~0); 1142468#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1142467#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1142466#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1142465#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1142464#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1142463#L914-3 assume !(0 == ~E_4~0); 1142462#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1142461#L924-3 assume !(0 == ~E_6~0); 1142460#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1142459#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1142458#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1142457#L418-30 assume !(1 == ~m_pc~0); 1142456#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1142455#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1142454#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1142453#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1142452#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1142451#L437-30 assume !(1 == ~t1_pc~0); 1142450#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1142449#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1142448#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1142447#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1142446#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1142445#L456-30 assume 1 == ~t2_pc~0; 1142443#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1142442#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1142441#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1142440#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1142439#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1142438#L475-30 assume !(1 == ~t3_pc~0); 1142437#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1142436#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1142434#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1142432#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1142430#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1142428#L494-30 assume 1 == ~t4_pc~0; 1142425#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1142423#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1142421#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1142419#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1142417#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1142415#L513-30 assume !(1 == ~t5_pc~0); 1142413#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1142411#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1142409#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1142406#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1142404#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1142402#L532-30 assume 1 == ~t6_pc~0; 1142400#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1142397#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1142396#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1142388#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1142336#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1142331#L551-30 assume !(1 == ~t7_pc~0); 1142326#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1142321#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1142316#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1142311#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1142306#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1142300#L570-30 assume !(1 == ~t8_pc~0); 1142295#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1142290#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1142285#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1142280#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1142275#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1142271#L952-3 assume !(1 == ~M_E~0); 1142266#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1142261#L957-3 assume !(1 == ~T2_E~0); 1142256#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1142251#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1142246#L972-3 assume !(1 == ~T5_E~0); 1142240#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1142236#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1142233#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1142230#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1142219#L997-3 assume !(1 == ~E_1~0); 1142216#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1108863#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1108861#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1108859#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1108857#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1108855#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1108852#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1108853#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1141281#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1141279#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1107330#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1107152#L1322 assume !(0 == start_simulation_~tmp~3#1); 1107153#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1110112#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1139051#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1138273#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1138271#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1138269#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1138268#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1138267#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1091530#L1303-2 [2022-12-13 19:42:32,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:32,428 INFO L85 PathProgramCache]: Analyzing trace with hash 330692485, now seen corresponding path program 1 times [2022-12-13 19:42:32,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:32,429 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000803828] [2022-12-13 19:42:32,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:32,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:32,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:32,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:32,464 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:32,464 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1000803828] [2022-12-13 19:42:32,464 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1000803828] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:32,464 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:32,464 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:32,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1660820380] [2022-12-13 19:42:32,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:32,464 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:32,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:32,465 INFO L85 PathProgramCache]: Analyzing trace with hash 29166423, now seen corresponding path program 1 times [2022-12-13 19:42:32,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:32,465 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359400184] [2022-12-13 19:42:32,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:32,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:32,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:32,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:32,486 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:32,486 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359400184] [2022-12-13 19:42:32,486 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1359400184] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:32,486 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:32,486 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:32,486 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1410863512] [2022-12-13 19:42:32,486 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:32,486 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:32,486 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:32,487 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:42:32,487 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:42:32,487 INFO L87 Difference]: Start difference. First operand 122397 states and 172863 transitions. cyclomatic complexity: 50530 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:32,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:32,905 INFO L93 Difference]: Finished difference Result 196401 states and 277064 transitions. [2022-12-13 19:42:32,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 196401 states and 277064 transitions. [2022-12-13 19:42:33,550 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 195138 [2022-12-13 19:42:33,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 196401 states to 196401 states and 277064 transitions. [2022-12-13 19:42:33,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 196401 [2022-12-13 19:42:33,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 196401 [2022-12-13 19:42:33,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196401 states and 277064 transitions. [2022-12-13 19:42:34,019 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:34,019 INFO L218 hiAutomatonCegarLoop]: Abstraction has 196401 states and 277064 transitions. [2022-12-13 19:42:34,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196401 states and 277064 transitions. [2022-12-13 19:42:35,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196401 to 139577. [2022-12-13 19:42:35,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139577 states, 139577 states have (on average 1.4126611117877588) internal successors, (197175), 139576 states have internal predecessors, (197175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:35,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139577 states to 139577 states and 197175 transitions. [2022-12-13 19:42:35,380 INFO L240 hiAutomatonCegarLoop]: Abstraction has 139577 states and 197175 transitions. [2022-12-13 19:42:35,380 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:42:35,381 INFO L428 stractBuchiCegarLoop]: Abstraction has 139577 states and 197175 transitions. [2022-12-13 19:42:35,381 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 19:42:35,381 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 139577 states and 197175 transitions. [2022-12-13 19:42:35,937 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 138680 [2022-12-13 19:42:35,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:35,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:35,938 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:35,938 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:35,938 INFO L748 eck$LassoCheckResult]: Stem: 1409842#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1409843#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1410609#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1410610#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1410696#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1410303#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1410304#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1409866#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1409867#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1409794#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1409795#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1410066#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1410039#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1410040#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1410371#L854 assume !(0 == ~M_E~0); 1410137#L854-2 assume !(0 == ~T1_E~0); 1410138#L859-1 assume !(0 == ~T2_E~0); 1409667#L864-1 assume !(0 == ~T3_E~0); 1409668#L869-1 assume !(0 == ~T4_E~0); 1409781#L874-1 assume !(0 == ~T5_E~0); 1410666#L879-1 assume !(0 == ~T6_E~0); 1410121#L884-1 assume !(0 == ~T7_E~0); 1409537#L889-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1409538#L894-1 assume !(0 == ~E_M~0); 1410749#L899-1 assume !(0 == ~E_1~0); 1410750#L904-1 assume !(0 == ~E_2~0); 1410060#L909-1 assume !(0 == ~E_3~0); 1410061#L914-1 assume !(0 == ~E_4~0); 1410323#L919-1 assume !(0 == ~E_5~0); 1410324#L924-1 assume !(0 == ~E_6~0); 1409766#L929-1 assume !(0 == ~E_7~0); 1409767#L934-1 assume !(0 == ~E_8~0); 1410037#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1410038#L418 assume !(1 == ~m_pc~0); 1410715#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1410716#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1410521#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1410522#L1061 assume !(0 != activate_threads_~tmp~1#1); 1410408#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1410409#L437 assume !(1 == ~t1_pc~0); 1410645#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1410646#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1409579#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1409580#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1410670#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1410671#L456 assume !(1 == ~t2_pc~0); 1409822#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1409821#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1409992#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1409993#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1410171#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1410172#L475 assume !(1 == ~t3_pc~0); 1410249#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1410250#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1409546#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1409547#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1409909#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1409910#L494 assume !(1 == ~t4_pc~0); 1409952#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1409953#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1409677#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1409678#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1410319#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1410320#L513 assume !(1 == ~t5_pc~0); 1409957#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1409958#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1410524#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1410525#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1410710#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1410711#L532 assume !(1 == ~t6_pc~0); 1409784#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1409783#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1409974#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1409975#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1409879#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1409880#L551 assume !(1 == ~t7_pc~0); 1410381#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1410382#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1410731#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1410732#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1410738#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1410739#L570 assume !(1 == ~t8_pc~0); 1410656#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1410657#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1410453#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1410454#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1409660#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1409661#L952 assume !(1 == ~M_E~0); 1409601#L952-2 assume !(1 == ~T1_E~0); 1409602#L957-1 assume !(1 == ~T2_E~0); 1410712#L962-1 assume !(1 == ~T3_E~0); 1410713#L967-1 assume !(1 == ~T4_E~0); 1410697#L972-1 assume !(1 == ~T5_E~0); 1410698#L977-1 assume !(1 == ~T6_E~0); 1410740#L982-1 assume !(1 == ~T7_E~0); 1410741#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1409787#L992-1 assume !(1 == ~E_M~0); 1409796#L997-1 assume !(1 == ~E_1~0); 1410169#L1002-1 assume !(1 == ~E_2~0); 1410154#L1007-1 assume !(1 == ~E_3~0); 1409540#L1012-1 assume !(1 == ~E_4~0); 1409541#L1017-1 assume !(1 == ~E_5~0); 1410160#L1022-1 assume !(1 == ~E_6~0); 1410161#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1410186#L1032-1 assume !(1 == ~E_8~0); 1410359#L1037-1 assume { :end_inline_reset_delta_events } true; 1410360#L1303-2 [2022-12-13 19:42:35,939 INFO L750 eck$LassoCheckResult]: Loop: 1410360#L1303-2 assume !false; 1469923#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1469744#L829 assume !false; 1469920#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1469906#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1469900#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1469898#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1469896#L712 assume !(0 != eval_~tmp~0#1); 1469897#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1535408#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1535407#L854-3 assume !(0 == ~M_E~0); 1535406#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1535405#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1535404#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1535403#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1535402#L874-3 assume !(0 == ~T5_E~0); 1535401#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1535400#L884-3 assume !(0 == ~T7_E~0); 1535399#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1535398#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1535396#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1535394#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1535392#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1535390#L914-3 assume !(0 == ~E_4~0); 1535388#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1535386#L924-3 assume !(0 == ~E_6~0); 1535384#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1535382#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1535380#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1535378#L418-30 assume !(1 == ~m_pc~0); 1535376#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1535374#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1535372#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1535370#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1535368#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1535366#L437-30 assume !(1 == ~t1_pc~0); 1535364#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1535362#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1535360#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1535358#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1535356#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1535354#L456-30 assume 1 == ~t2_pc~0; 1535351#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1535348#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1535346#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1535344#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1535342#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1535340#L475-30 assume !(1 == ~t3_pc~0); 1535338#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1535336#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1535334#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1535332#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1535330#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1535328#L494-30 assume !(1 == ~t4_pc~0); 1535326#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1535322#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1535320#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1535318#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1535316#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1535314#L513-30 assume !(1 == ~t5_pc~0); 1535312#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1535310#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1535308#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1535306#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1535304#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1535302#L532-30 assume 1 == ~t6_pc~0; 1535300#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1535296#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1535294#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1535292#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1535290#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1535288#L551-30 assume !(1 == ~t7_pc~0); 1535286#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1535284#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1535282#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1535280#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1535278#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1535276#L570-30 assume !(1 == ~t8_pc~0); 1535274#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1535272#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1535270#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1535268#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1535266#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1535264#L952-3 assume !(1 == ~M_E~0); 1535262#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1535260#L957-3 assume !(1 == ~T2_E~0); 1535258#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1535256#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1535254#L972-3 assume !(1 == ~T5_E~0); 1535252#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1535250#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1535247#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1535246#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1535242#L997-3 assume !(1 == ~E_1~0); 1535240#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1535238#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1535237#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1535236#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1535235#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1535234#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1535233#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1535232#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1535214#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1535212#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1535162#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1451829#L1322 assume !(0 == start_simulation_~tmp~3#1); 1451830#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1469945#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1469936#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1469934#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1469932#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1469930#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1469928#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1469926#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1410360#L1303-2 [2022-12-13 19:42:35,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:35,940 INFO L85 PathProgramCache]: Analyzing trace with hash -2085143865, now seen corresponding path program 1 times [2022-12-13 19:42:35,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:35,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [142574853] [2022-12-13 19:42:35,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:35,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:35,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:35,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:35,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:35,975 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [142574853] [2022-12-13 19:42:35,975 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [142574853] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:35,975 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:35,975 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:35,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047335219] [2022-12-13 19:42:35,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:35,976 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:35,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:35,976 INFO L85 PathProgramCache]: Analyzing trace with hash 1057698584, now seen corresponding path program 1 times [2022-12-13 19:42:35,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:35,976 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776931526] [2022-12-13 19:42:35,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:35,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:35,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:36,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:36,000 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:36,000 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776931526] [2022-12-13 19:42:36,000 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776931526] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:36,000 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:36,000 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:36,001 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240068389] [2022-12-13 19:42:36,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:36,001 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:36,001 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:36,001 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:42:36,001 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:42:36,002 INFO L87 Difference]: Start difference. First operand 139577 states and 197175 transitions. cyclomatic complexity: 57662 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:36,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:36,317 INFO L93 Difference]: Finished difference Result 122397 states and 172321 transitions. [2022-12-13 19:42:36,317 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122397 states and 172321 transitions. [2022-12-13 19:42:36,698 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 121576 [2022-12-13 19:42:37,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122397 states to 122397 states and 172321 transitions. [2022-12-13 19:42:37,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122397 [2022-12-13 19:42:37,145 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122397 [2022-12-13 19:42:37,145 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122397 states and 172321 transitions. [2022-12-13 19:42:37,189 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:37,189 INFO L218 hiAutomatonCegarLoop]: Abstraction has 122397 states and 172321 transitions. [2022-12-13 19:42:37,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122397 states and 172321 transitions. [2022-12-13 19:42:37,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122397 to 122397. [2022-12-13 19:42:38,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122397 states, 122397 states have (on average 1.4078858141947923) internal successors, (172321), 122396 states have internal predecessors, (172321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:38,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122397 states to 122397 states and 172321 transitions. [2022-12-13 19:42:38,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122397 states and 172321 transitions. [2022-12-13 19:42:38,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:42:38,204 INFO L428 stractBuchiCegarLoop]: Abstraction has 122397 states and 172321 transitions. [2022-12-13 19:42:38,204 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 19:42:38,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122397 states and 172321 transitions. [2022-12-13 19:42:38,489 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 121576 [2022-12-13 19:42:38,489 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:38,489 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:38,491 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:38,491 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:38,491 INFO L748 eck$LassoCheckResult]: Stem: 1671819#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1671820#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1672555#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1672556#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1672630#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1672264#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1672265#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1671841#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1671842#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1671771#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1671772#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1672037#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1672009#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1672010#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1672328#L854 assume !(0 == ~M_E~0); 1672107#L854-2 assume !(0 == ~T1_E~0); 1672108#L859-1 assume !(0 == ~T2_E~0); 1671649#L864-1 assume !(0 == ~T3_E~0); 1671650#L869-1 assume !(0 == ~T4_E~0); 1671760#L874-1 assume !(0 == ~T5_E~0); 1672606#L879-1 assume !(0 == ~T6_E~0); 1672093#L884-1 assume !(0 == ~T7_E~0); 1671520#L889-1 assume !(0 == ~T8_E~0); 1671521#L894-1 assume !(0 == ~E_M~0); 1671852#L899-1 assume !(0 == ~E_1~0); 1672334#L904-1 assume !(0 == ~E_2~0); 1672031#L909-1 assume !(0 == ~E_3~0); 1672032#L914-1 assume !(0 == ~E_4~0); 1672254#L919-1 assume !(0 == ~E_5~0); 1671931#L924-1 assume !(0 == ~E_6~0); 1671746#L929-1 assume !(0 == ~E_7~0); 1671747#L934-1 assume !(0 == ~E_8~0); 1672008#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1671537#L418 assume !(1 == ~m_pc~0); 1671538#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1672538#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1672482#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1672463#L1061 assume !(0 != activate_threads_~tmp~1#1); 1672363#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1672364#L437 assume !(1 == ~t1_pc~0); 1672591#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1672471#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1671561#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1671562#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1671880#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1672454#L456 assume !(1 == ~t2_pc~0); 1671800#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1671799#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1671964#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1671965#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1672139#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1671644#L475 assume !(1 == ~t3_pc~0); 1671645#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1671709#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1671528#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1671529#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1671883#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1671884#L494 assume !(1 == ~t4_pc~0); 1671926#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1671927#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1671659#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1671660#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1672279#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1671705#L513 assume !(1 == ~t5_pc~0); 1671706#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1671930#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1672484#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1671656#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1671657#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1671613#L532 assume !(1 == ~t6_pc~0); 1671614#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1671761#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1671946#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1671947#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1671856#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1671857#L551 assume !(1 == ~t7_pc~0); 1672335#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1672281#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1672282#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1672650#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1672656#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1672050#L570 assume !(1 == ~t8_pc~0); 1672051#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1672563#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1672413#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1672165#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1671642#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1671643#L952 assume !(1 == ~M_E~0); 1671583#L952-2 assume !(1 == ~T1_E~0); 1671584#L957-1 assume !(1 == ~T2_E~0); 1672427#L962-1 assume !(1 == ~T3_E~0); 1672184#L967-1 assume !(1 == ~T4_E~0); 1672185#L972-1 assume !(1 == ~T5_E~0); 1672500#L977-1 assume !(1 == ~T6_E~0); 1672501#L982-1 assume !(1 == ~T7_E~0); 1671763#L987-1 assume !(1 == ~T8_E~0); 1671764#L992-1 assume !(1 == ~E_M~0); 1671773#L997-1 assume !(1 == ~E_1~0); 1672137#L1002-1 assume !(1 == ~E_2~0); 1672122#L1007-1 assume !(1 == ~E_3~0); 1671522#L1012-1 assume !(1 == ~E_4~0); 1671523#L1017-1 assume !(1 == ~E_5~0); 1672128#L1022-1 assume !(1 == ~E_6~0); 1672129#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1672152#L1032-1 assume !(1 == ~E_8~0); 1672317#L1037-1 assume { :end_inline_reset_delta_events } true; 1672318#L1303-2 [2022-12-13 19:42:38,492 INFO L750 eck$LassoCheckResult]: Loop: 1672318#L1303-2 assume !false; 1709874#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1695555#L829 assume !false; 1695552#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1695197#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1695192#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1695190#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1695187#L712 assume !(0 != eval_~tmp~0#1); 1695188#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1717364#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1717358#L854-3 assume !(0 == ~M_E~0); 1717352#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1717347#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1717342#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1717337#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1717333#L874-3 assume !(0 == ~T5_E~0); 1717329#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1717325#L884-3 assume !(0 == ~T7_E~0); 1717320#L889-3 assume !(0 == ~T8_E~0); 1717315#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1717310#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1717305#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1717299#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1717293#L914-3 assume !(0 == ~E_4~0); 1717288#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1717283#L924-3 assume !(0 == ~E_6~0); 1717279#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1717273#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1717267#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1717261#L418-30 assume !(1 == ~m_pc~0); 1717257#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1717252#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1717248#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1717242#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1717236#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1717230#L437-30 assume !(1 == ~t1_pc~0); 1717225#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1717220#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1717215#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1717208#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1717201#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1717195#L456-30 assume !(1 == ~t2_pc~0); 1717192#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1717186#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1717181#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1717175#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1717169#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1717163#L475-30 assume !(1 == ~t3_pc~0); 1717157#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1717152#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1717147#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1717141#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1717134#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1717129#L494-30 assume 1 == ~t4_pc~0; 1717122#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1717116#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1717114#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1717112#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1717109#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1717106#L513-30 assume !(1 == ~t5_pc~0); 1717102#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1717099#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1717096#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1717093#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1717090#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1717089#L532-30 assume !(1 == ~t6_pc~0); 1717086#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1717082#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1717080#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1717078#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1717075#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1717071#L551-30 assume !(1 == ~t7_pc~0); 1717068#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1717065#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1717062#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1717059#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1717056#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1717054#L570-30 assume !(1 == ~t8_pc~0); 1717051#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1717048#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1717045#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1717042#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1717039#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1717034#L952-3 assume !(1 == ~M_E~0); 1717031#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1717028#L957-3 assume !(1 == ~T2_E~0); 1717025#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1717022#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1717019#L972-3 assume !(1 == ~T5_E~0); 1717017#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1717015#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1717012#L987-3 assume !(1 == ~T8_E~0); 1717009#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1717007#L997-3 assume !(1 == ~E_1~0); 1717005#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1717004#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1717003#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1717001#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1716999#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1716997#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1716995#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1716993#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1716981#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1716978#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1716975#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1716971#L1322 assume !(0 == start_simulation_~tmp~3#1); 1716972#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1717796#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1717787#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1717785#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1717783#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1717781#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1717779#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1717777#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1672318#L1303-2 [2022-12-13 19:42:38,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:38,492 INFO L85 PathProgramCache]: Analyzing trace with hash 1031757063, now seen corresponding path program 1 times [2022-12-13 19:42:38,492 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:38,492 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [952395609] [2022-12-13 19:42:38,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:38,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:38,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:38,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:38,534 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:38,534 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [952395609] [2022-12-13 19:42:38,534 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [952395609] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:38,535 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:38,535 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:38,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [30951651] [2022-12-13 19:42:38,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:38,535 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:38,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:38,536 INFO L85 PathProgramCache]: Analyzing trace with hash 767188249, now seen corresponding path program 1 times [2022-12-13 19:42:38,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:38,536 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728777404] [2022-12-13 19:42:38,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:38,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:38,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:38,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:38,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:38,556 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1728777404] [2022-12-13 19:42:38,556 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1728777404] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:38,556 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:38,556 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:38,556 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [403921015] [2022-12-13 19:42:38,556 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:38,557 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:38,557 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:38,557 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:42:38,557 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:42:38,557 INFO L87 Difference]: Start difference. First operand 122397 states and 172321 transitions. cyclomatic complexity: 49988 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:39,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:39,330 INFO L93 Difference]: Finished difference Result 190541 states and 267918 transitions. [2022-12-13 19:42:39,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 190541 states and 267918 transitions. [2022-12-13 19:42:40,026 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 189178 [2022-12-13 19:42:40,517 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 190541 states to 190541 states and 267918 transitions. [2022-12-13 19:42:40,517 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 190541 [2022-12-13 19:42:40,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 190541 [2022-12-13 19:42:40,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 190541 states and 267918 transitions. [2022-12-13 19:42:40,639 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:40,639 INFO L218 hiAutomatonCegarLoop]: Abstraction has 190541 states and 267918 transitions. [2022-12-13 19:42:40,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190541 states and 267918 transitions. [2022-12-13 19:42:41,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190541 to 139505. [2022-12-13 19:42:41,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139505 states, 139505 states have (on average 1.405576861044407) internal successors, (196085), 139504 states have internal predecessors, (196085), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:41,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139505 states to 139505 states and 196085 transitions. [2022-12-13 19:42:41,898 INFO L240 hiAutomatonCegarLoop]: Abstraction has 139505 states and 196085 transitions. [2022-12-13 19:42:41,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:42:41,899 INFO L428 stractBuchiCegarLoop]: Abstraction has 139505 states and 196085 transitions. [2022-12-13 19:42:41,900 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 19:42:41,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 139505 states and 196085 transitions. [2022-12-13 19:42:42,346 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 138608 [2022-12-13 19:42:42,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:42,346 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:42,347 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:42,347 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:42,347 INFO L748 eck$LassoCheckResult]: Stem: 1984769#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1984770#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1985556#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1985557#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1985642#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1985221#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1985222#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1984790#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1984791#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1984720#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1984721#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1984994#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1984966#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1984967#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1985288#L854 assume !(0 == ~M_E~0); 1985061#L854-2 assume !(0 == ~T1_E~0); 1985062#L859-1 assume !(0 == ~T2_E~0); 1984594#L864-1 assume !(0 == ~T3_E~0); 1984595#L869-1 assume !(0 == ~T4_E~0); 1984707#L874-1 assume !(0 == ~T5_E~0); 1985613#L879-1 assume !(0 == ~T6_E~0); 1985046#L884-1 assume !(0 == ~T7_E~0); 1984468#L889-1 assume !(0 == ~T8_E~0); 1984469#L894-1 assume !(0 == ~E_M~0); 1984801#L899-1 assume !(0 == ~E_1~0); 1985294#L904-1 assume !(0 == ~E_2~0); 1984987#L909-1 assume !(0 == ~E_3~0); 1984988#L914-1 assume !(0 == ~E_4~0); 1985209#L919-1 assume !(0 == ~E_5~0); 1984884#L924-1 assume !(0 == ~E_6~0); 1984692#L929-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1984693#L934-1 assume !(0 == ~E_8~0); 1984965#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1984484#L418 assume !(1 == ~m_pc~0); 1984485#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1985534#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1985535#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1985434#L1061 assume !(0 != activate_threads_~tmp~1#1); 1985435#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1985653#L437 assume !(1 == ~t1_pc~0); 1985654#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1985443#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1985444#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1984829#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1984830#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1985424#L456 assume !(1 == ~t2_pc~0); 1985425#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1985649#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1985650#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1985475#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1985476#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1985706#L475 assume !(1 == ~t3_pc~0); 1985168#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1985169#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1984476#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1984477#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1984833#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1984834#L494 assume !(1 == ~t4_pc~0); 1984878#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1984879#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1984604#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1984605#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1985239#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1985240#L513 assume !(1 == ~t5_pc~0); 1984882#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1984883#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1985457#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1985458#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1985656#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1985657#L532 assume !(1 == ~t6_pc~0); 1984710#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1984709#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1984900#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1984901#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1984803#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1984804#L551 assume !(1 == ~t7_pc~0); 1985705#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1985243#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1985244#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1985704#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1985703#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1985005#L570 assume !(1 == ~t8_pc~0); 1985006#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1985564#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1985565#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1985121#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1984587#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1984588#L952 assume !(1 == ~M_E~0); 1984529#L952-2 assume !(1 == ~T1_E~0); 1984530#L957-1 assume !(1 == ~T2_E~0); 1985658#L962-1 assume !(1 == ~T3_E~0); 1985140#L967-1 assume !(1 == ~T4_E~0); 1985141#L972-1 assume !(1 == ~T5_E~0); 1985643#L977-1 assume !(1 == ~T6_E~0); 1985699#L982-1 assume !(1 == ~T7_E~0); 1985698#L987-1 assume !(1 == ~T8_E~0); 1985697#L992-1 assume !(1 == ~E_M~0); 1985696#L997-1 assume !(1 == ~E_1~0); 1985695#L1002-1 assume !(1 == ~E_2~0); 1985077#L1007-1 assume !(1 == ~E_3~0); 1984470#L1012-1 assume !(1 == ~E_4~0); 1984471#L1017-1 assume !(1 == ~E_5~0); 1985083#L1022-1 assume !(1 == ~E_6~0); 1985084#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1985109#L1032-1 assume !(1 == ~E_8~0); 1985275#L1037-1 assume { :end_inline_reset_delta_events } true; 1985276#L1303-2 [2022-12-13 19:42:42,347 INFO L750 eck$LassoCheckResult]: Loop: 1985276#L1303-2 assume !false; 2035536#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2035534#L829 assume !false; 2035532#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2035518#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2035512#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2035510#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2035507#L712 assume !(0 != eval_~tmp~0#1); 2035505#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2035503#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2035501#L854-3 assume !(0 == ~M_E~0); 2035499#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2035497#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2035495#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2035493#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2035491#L874-3 assume !(0 == ~T5_E~0); 2035489#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2035487#L884-3 assume !(0 == ~T7_E~0); 2035485#L889-3 assume !(0 == ~T8_E~0); 2035483#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2035481#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2035479#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2035477#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2035475#L914-3 assume !(0 == ~E_4~0); 2035473#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2035471#L924-3 assume !(0 == ~E_6~0); 2035468#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2035469#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2072053#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2072050#L418-30 assume !(1 == ~m_pc~0); 2072048#L418-32 is_master_triggered_~__retres1~0#1 := 0; 2072046#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2072044#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2072042#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 2072039#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2072037#L437-30 assume !(1 == ~t1_pc~0); 2072035#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2072033#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2072031#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2072029#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2072027#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2072026#L456-30 assume !(1 == ~t2_pc~0); 2067011#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2067008#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2067006#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2067004#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2067002#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2067000#L475-30 assume !(1 == ~t3_pc~0); 2066997#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2066995#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2066993#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2066991#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2066988#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2066986#L494-30 assume !(1 == ~t4_pc~0); 2066984#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2035558#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2035553#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2035549#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 2035544#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2035540#L513-30 assume !(1 == ~t5_pc~0); 2035535#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2035533#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2035531#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2035530#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2035529#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2035528#L532-30 assume 1 == ~t6_pc~0; 2035527#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2035525#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2035524#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2035523#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2035513#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2035511#L551-30 assume !(1 == ~t7_pc~0); 2035509#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2035506#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2035504#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2035502#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2035500#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2035498#L570-30 assume !(1 == ~t8_pc~0); 2035496#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2035494#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2035492#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2035490#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2035488#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2035486#L952-3 assume !(1 == ~M_E~0); 2035484#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2035482#L957-3 assume !(1 == ~T2_E~0); 2035480#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2035478#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2035476#L972-3 assume !(1 == ~T5_E~0); 2035474#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2035472#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2035470#L987-3 assume !(1 == ~T8_E~0); 2035467#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2035465#L997-3 assume !(1 == ~E_1~0); 2035463#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2035461#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2035459#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2035457#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2035455#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2035319#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2035317#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2035315#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2035295#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2035292#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2035290#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2018554#L1322 assume !(0 == start_simulation_~tmp~3#1); 2018555#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2105096#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2105087#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2105085#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2105083#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2105081#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2105078#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2105007#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1985276#L1303-2 [2022-12-13 19:42:42,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:42,347 INFO L85 PathProgramCache]: Analyzing trace with hash -1185873335, now seen corresponding path program 1 times [2022-12-13 19:42:42,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:42,348 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1389958659] [2022-12-13 19:42:42,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:42,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:42,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:42,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:42,376 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:42,376 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1389958659] [2022-12-13 19:42:42,376 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1389958659] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:42,376 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:42,376 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:42,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1398041199] [2022-12-13 19:42:42,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:42,376 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:42,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:42,377 INFO L85 PathProgramCache]: Analyzing trace with hash 327517081, now seen corresponding path program 1 times [2022-12-13 19:42:42,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:42,377 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123254158] [2022-12-13 19:42:42,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:42,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:42,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:42,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:42,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:42,397 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123254158] [2022-12-13 19:42:42,397 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123254158] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:42,397 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:42,397 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:42,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [977104170] [2022-12-13 19:42:42,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:42,397 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:42,397 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:42,397 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:42:42,397 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:42:42,398 INFO L87 Difference]: Start difference. First operand 139505 states and 196085 transitions. cyclomatic complexity: 56644 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:42,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:42,806 INFO L93 Difference]: Finished difference Result 172603 states and 241981 transitions. [2022-12-13 19:42:42,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 172603 states and 241981 transitions. [2022-12-13 19:42:43,481 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 171318 [2022-12-13 19:42:43,770 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 172603 states to 172603 states and 241981 transitions. [2022-12-13 19:42:43,770 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 172603 [2022-12-13 19:42:43,829 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 172603 [2022-12-13 19:42:43,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 172603 states and 241981 transitions. [2022-12-13 19:42:43,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:43,895 INFO L218 hiAutomatonCegarLoop]: Abstraction has 172603 states and 241981 transitions. [2022-12-13 19:42:43,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172603 states and 241981 transitions. [2022-12-13 19:42:44,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172603 to 122397. [2022-12-13 19:42:45,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122397 states, 122397 states have (on average 1.3995686168778647) internal successors, (171303), 122396 states have internal predecessors, (171303), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:45,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122397 states to 122397 states and 171303 transitions. [2022-12-13 19:42:45,186 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122397 states and 171303 transitions. [2022-12-13 19:42:45,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:42:45,187 INFO L428 stractBuchiCegarLoop]: Abstraction has 122397 states and 171303 transitions. [2022-12-13 19:42:45,188 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 19:42:45,188 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122397 states and 171303 transitions. [2022-12-13 19:42:45,474 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 121576 [2022-12-13 19:42:45,475 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:45,475 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:45,475 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:45,476 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:45,476 INFO L748 eck$LassoCheckResult]: Stem: 2296883#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2296884#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2297616#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2297617#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2297700#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 2297325#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2297326#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2296900#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2296901#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2296833#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2296834#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2297103#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2297076#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2297077#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2297390#L854 assume !(0 == ~M_E~0); 2297166#L854-2 assume !(0 == ~T1_E~0); 2297167#L859-1 assume !(0 == ~T2_E~0); 2296713#L864-1 assume !(0 == ~T3_E~0); 2296714#L869-1 assume !(0 == ~T4_E~0); 2296824#L874-1 assume !(0 == ~T5_E~0); 2297671#L879-1 assume !(0 == ~T6_E~0); 2297155#L884-1 assume !(0 == ~T7_E~0); 2296586#L889-1 assume !(0 == ~T8_E~0); 2296587#L894-1 assume !(0 == ~E_M~0); 2296914#L899-1 assume !(0 == ~E_1~0); 2297397#L904-1 assume !(0 == ~E_2~0); 2297092#L909-1 assume !(0 == ~E_3~0); 2297093#L914-1 assume !(0 == ~E_4~0); 2297312#L919-1 assume !(0 == ~E_5~0); 2296995#L924-1 assume !(0 == ~E_6~0); 2296806#L929-1 assume !(0 == ~E_7~0); 2296807#L934-1 assume !(0 == ~E_8~0); 2297073#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2296602#L418 assume !(1 == ~m_pc~0); 2296603#L418-2 is_master_triggered_~__retres1~0#1 := 0; 2297598#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2297538#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2297521#L1061 assume !(0 != activate_threads_~tmp~1#1); 2297426#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2297427#L437 assume !(1 == ~t1_pc~0); 2297657#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2297528#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2296623#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2296624#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 2296941#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2297511#L456 assume !(1 == ~t2_pc~0); 2296861#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2296860#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2297029#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2297030#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 2297202#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2296708#L475 assume !(1 == ~t3_pc~0); 2296709#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2296771#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2296594#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2296595#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 2296944#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2296945#L494 assume !(1 == ~t4_pc~0); 2296989#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2296990#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2296723#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2296724#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 2297342#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2296766#L513 assume !(1 == ~t5_pc~0); 2296767#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2296991#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2297541#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2296720#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 2296721#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2296676#L532 assume !(1 == ~t6_pc~0); 2296677#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2296825#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2297010#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2297011#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 2296918#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2296919#L551 assume !(1 == ~t7_pc~0); 2297399#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2297344#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2297345#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2297724#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 2297729#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2297114#L570 assume !(1 == ~t8_pc~0); 2297115#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2297621#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2297476#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2297225#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 2296702#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2296703#L952 assume !(1 == ~M_E~0); 2296648#L952-2 assume !(1 == ~T1_E~0); 2296649#L957-1 assume !(1 == ~T2_E~0); 2297488#L962-1 assume !(1 == ~T3_E~0); 2297246#L967-1 assume !(1 == ~T4_E~0); 2297247#L972-1 assume !(1 == ~T5_E~0); 2297561#L977-1 assume !(1 == ~T6_E~0); 2297562#L982-1 assume !(1 == ~T7_E~0); 2296827#L987-1 assume !(1 == ~T8_E~0); 2296828#L992-1 assume !(1 == ~E_M~0); 2296835#L997-1 assume !(1 == ~E_1~0); 2297200#L1002-1 assume !(1 == ~E_2~0); 2297185#L1007-1 assume !(1 == ~E_3~0); 2296588#L1012-1 assume !(1 == ~E_4~0); 2296589#L1017-1 assume !(1 == ~E_5~0); 2297188#L1022-1 assume !(1 == ~E_6~0); 2297189#L1027-1 assume !(1 == ~E_7~0); 2297215#L1032-1 assume !(1 == ~E_8~0); 2297377#L1037-1 assume { :end_inline_reset_delta_events } true; 2297378#L1303-2 [2022-12-13 19:42:45,476 INFO L750 eck$LassoCheckResult]: Loop: 2297378#L1303-2 assume !false; 2357645#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2357455#L829 assume !false; 2357644#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2357639#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2357634#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2357633#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2357631#L712 assume !(0 != eval_~tmp~0#1); 2357632#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2369738#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2369737#L854-3 assume !(0 == ~M_E~0); 2369736#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2369735#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2369734#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2369733#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2369732#L874-3 assume !(0 == ~T5_E~0); 2369731#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2369730#L884-3 assume !(0 == ~T7_E~0); 2369729#L889-3 assume !(0 == ~T8_E~0); 2369727#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2369725#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2369723#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2369721#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2369719#L914-3 assume !(0 == ~E_4~0); 2369717#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2369715#L924-3 assume !(0 == ~E_6~0); 2369713#L929-3 assume !(0 == ~E_7~0); 2369711#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2369708#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2369706#L418-30 assume !(1 == ~m_pc~0); 2369704#L418-32 is_master_triggered_~__retres1~0#1 := 0; 2369702#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2369700#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2369698#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 2369695#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2369693#L437-30 assume !(1 == ~t1_pc~0); 2369691#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2369689#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2369687#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2369685#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2369683#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2369681#L456-30 assume 1 == ~t2_pc~0; 2369678#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2369676#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2369674#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2369672#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2369669#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2369667#L475-30 assume !(1 == ~t3_pc~0); 2369665#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2369663#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2369661#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2369659#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2369656#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2369654#L494-30 assume !(1 == ~t4_pc~0); 2369652#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2369649#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2369647#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2369645#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 2369642#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2369640#L513-30 assume !(1 == ~t5_pc~0); 2369638#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2369636#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2369634#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2369631#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2369629#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2369627#L532-30 assume !(1 == ~t6_pc~0); 2369624#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2369622#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2369620#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2369618#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2369616#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2369613#L551-30 assume !(1 == ~t7_pc~0); 2369611#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2369609#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2369607#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2369605#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2369604#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2369603#L570-30 assume !(1 == ~t8_pc~0); 2368725#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2368724#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2368723#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2368722#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2368721#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2368720#L952-3 assume !(1 == ~M_E~0); 2368719#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2368718#L957-3 assume !(1 == ~T2_E~0); 2368717#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2368713#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2368711#L972-3 assume !(1 == ~T5_E~0); 2368709#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2368708#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2368706#L987-3 assume !(1 == ~T8_E~0); 2368705#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2368704#L997-3 assume !(1 == ~E_1~0); 2368703#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2368702#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2368701#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2368700#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2368699#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2368697#L1027-3 assume !(1 == ~E_7~0); 2368694#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2368691#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2368649#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2368647#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2368644#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2337101#L1322 assume !(0 == start_simulation_~tmp~3#1); 2337102#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2357665#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2357656#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2357655#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2357654#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2357650#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2357648#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2357646#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 2297378#L1303-2 [2022-12-13 19:42:45,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:45,476 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 1 times [2022-12-13 19:42:45,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:45,477 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531905841] [2022-12-13 19:42:45,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:45,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:45,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:45,490 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:42:45,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:45,551 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:42:45,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:45,552 INFO L85 PathProgramCache]: Analyzing trace with hash 1684142297, now seen corresponding path program 1 times [2022-12-13 19:42:45,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:45,552 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [769271962] [2022-12-13 19:42:45,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:45,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:45,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:45,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:45,574 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:45,574 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [769271962] [2022-12-13 19:42:45,574 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [769271962] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:45,574 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:45,574 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:45,574 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [680223880] [2022-12-13 19:42:45,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:45,575 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:45,575 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:45,575 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:45,575 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:45,575 INFO L87 Difference]: Start difference. First operand 122397 states and 171303 transitions. cyclomatic complexity: 48970 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:46,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:46,060 INFO L93 Difference]: Finished difference Result 139577 states and 195217 transitions. [2022-12-13 19:42:46,060 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 139577 states and 195217 transitions. [2022-12-13 19:42:46,495 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 138680 [2022-12-13 19:42:46,777 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 139577 states to 139577 states and 195217 transitions. [2022-12-13 19:42:46,778 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 139577 [2022-12-13 19:42:46,842 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 139577 [2022-12-13 19:42:46,842 INFO L73 IsDeterministic]: Start isDeterministic. Operand 139577 states and 195217 transitions. [2022-12-13 19:42:47,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:47,082 INFO L218 hiAutomatonCegarLoop]: Abstraction has 139577 states and 195217 transitions. [2022-12-13 19:42:47,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139577 states and 195217 transitions. [2022-12-13 19:42:48,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139577 to 139577. [2022-12-13 19:42:48,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139577 states, 139577 states have (on average 1.398633012602363) internal successors, (195217), 139576 states have internal predecessors, (195217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:48,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139577 states to 139577 states and 195217 transitions. [2022-12-13 19:42:48,337 INFO L240 hiAutomatonCegarLoop]: Abstraction has 139577 states and 195217 transitions. [2022-12-13 19:42:48,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:48,338 INFO L428 stractBuchiCegarLoop]: Abstraction has 139577 states and 195217 transitions. [2022-12-13 19:42:48,338 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 19:42:48,338 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 139577 states and 195217 transitions. [2022-12-13 19:42:48,727 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 138680 [2022-12-13 19:42:48,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:48,728 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:48,729 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:48,729 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:48,729 INFO L748 eck$LassoCheckResult]: Stem: 2558866#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2558867#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2559672#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2559673#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2559766#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 2559337#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2559338#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2558883#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2558884#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2558816#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2558817#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2559091#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2559064#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2559065#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2559413#L854 assume !(0 == ~M_E~0); 2559157#L854-2 assume !(0 == ~T1_E~0); 2559158#L859-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2558691#L864-1 assume !(0 == ~T3_E~0); 2558692#L869-1 assume !(0 == ~T4_E~0); 2559771#L874-1 assume !(0 == ~T5_E~0); 2559772#L879-1 assume !(0 == ~T6_E~0); 2559146#L884-1 assume !(0 == ~T7_E~0); 2558565#L889-1 assume !(0 == ~T8_E~0); 2558566#L894-1 assume !(0 == ~E_M~0); 2559831#L899-1 assume !(0 == ~E_1~0); 2559419#L904-1 assume !(0 == ~E_2~0); 2559420#L909-1 assume !(0 == ~E_3~0); 2559322#L914-1 assume !(0 == ~E_4~0); 2559323#L919-1 assume !(0 == ~E_5~0); 2558981#L924-1 assume !(0 == ~E_6~0); 2558982#L929-1 assume !(0 == ~E_7~0); 2559744#L934-1 assume !(0 == ~E_8~0); 2559061#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2558581#L418 assume !(1 == ~m_pc~0); 2558582#L418-2 is_master_triggered_~__retres1~0#1 := 0; 2559648#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2559649#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2559548#L1061 assume !(0 != activate_threads_~tmp~1#1); 2559549#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2559780#L437 assume !(1 == ~t1_pc~0); 2559781#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2559558#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2559559#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2558926#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 2558927#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2559535#L456 assume !(1 == ~t2_pc~0); 2559536#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2559775#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2559776#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2559588#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 2559589#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2559854#L475 assume !(1 == ~t3_pc~0); 2559279#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2559280#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2558573#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2558574#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 2558930#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2558931#L494 assume !(1 == ~t4_pc~0); 2558974#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2558975#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2558701#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2558702#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 2559354#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2559355#L513 assume !(1 == ~t5_pc~0); 2558976#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2558977#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2559572#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2559573#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 2559783#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2559784#L532 assume !(1 == ~t6_pc~0); 2558808#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2558807#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2558996#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2558997#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 2558902#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2558903#L551 assume !(1 == ~t7_pc~0); 2559853#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2559359#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2559360#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2559852#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 2559815#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2559816#L570 assume !(1 == ~t8_pc~0); 2559718#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2559719#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2559499#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2559500#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 2558680#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2558681#L952 assume !(1 == ~M_E~0); 2558626#L952-2 assume !(1 == ~T1_E~0); 2558627#L957-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2559511#L962-1 assume !(1 == ~T3_E~0); 2559245#L967-1 assume !(1 == ~T4_E~0); 2559246#L972-1 assume !(1 == ~T5_E~0); 2559596#L977-1 assume !(1 == ~T6_E~0); 2559597#L982-1 assume !(1 == ~T7_E~0); 2558810#L987-1 assume !(1 == ~T8_E~0); 2558811#L992-1 assume !(1 == ~E_M~0); 2558818#L997-1 assume !(1 == ~E_1~0); 2559192#L1002-1 assume !(1 == ~E_2~0); 2559177#L1007-1 assume !(1 == ~E_3~0); 2558567#L1012-1 assume !(1 == ~E_4~0); 2558568#L1017-1 assume !(1 == ~E_5~0); 2559183#L1022-1 assume !(1 == ~E_6~0); 2559184#L1027-1 assume !(1 == ~E_7~0); 2559211#L1032-1 assume !(1 == ~E_8~0); 2559396#L1037-1 assume { :end_inline_reset_delta_events } true; 2559397#L1303-2 [2022-12-13 19:42:48,730 INFO L750 eck$LassoCheckResult]: Loop: 2559397#L1303-2 assume !false; 2633516#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2633514#L829 assume !false; 2633513#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2621210#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2621204#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2621205#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2621368#L712 assume !(0 != eval_~tmp~0#1); 2621369#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2625882#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2625880#L854-3 assume !(0 == ~M_E~0); 2625878#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2625875#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2625873#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2625871#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2625869#L874-3 assume !(0 == ~T5_E~0); 2625867#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2625865#L884-3 assume !(0 == ~T7_E~0); 2625863#L889-3 assume !(0 == ~T8_E~0); 2625861#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2625859#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2625857#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2625855#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2625853#L914-3 assume !(0 == ~E_4~0); 2625851#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2625849#L924-3 assume !(0 == ~E_6~0); 2625847#L929-3 assume !(0 == ~E_7~0); 2625845#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2625843#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2625841#L418-30 assume !(1 == ~m_pc~0); 2625839#L418-32 is_master_triggered_~__retres1~0#1 := 0; 2625837#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2625835#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2625833#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 2625831#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2625829#L437-30 assume !(1 == ~t1_pc~0); 2625827#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2625825#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2625823#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2625820#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2625818#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2625814#L456-30 assume !(1 == ~t2_pc~0); 2625816#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2662063#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2662062#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2662061#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2662060#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2662059#L475-30 assume !(1 == ~t3_pc~0); 2662058#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2662057#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2662056#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2662055#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2662054#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2662053#L494-30 assume 1 == ~t4_pc~0; 2662051#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2662050#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2662049#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2662048#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 2662047#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2662046#L513-30 assume !(1 == ~t5_pc~0); 2662045#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2662044#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2662043#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2662042#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2662041#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2662040#L532-30 assume !(1 == ~t6_pc~0); 2662038#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2662037#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2662036#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2662035#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2662034#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2662033#L551-30 assume !(1 == ~t7_pc~0); 2662032#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2662031#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2662030#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2662029#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2662028#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2662027#L570-30 assume !(1 == ~t8_pc~0); 2662026#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2662025#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2662024#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2662023#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2662022#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2662021#L952-3 assume !(1 == ~M_E~0); 2662020#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2662019#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2662017#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2662016#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2662015#L972-3 assume !(1 == ~T5_E~0); 2662014#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2662013#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2662012#L987-3 assume !(1 == ~T8_E~0); 2662011#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2662010#L997-3 assume !(1 == ~E_1~0); 2662009#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2662008#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2662007#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2662006#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2662005#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2662004#L1027-3 assume !(1 == ~E_7~0); 2662003#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2662002#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2633487#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2633486#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2633485#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2633483#L1322 assume !(0 == start_simulation_~tmp~3#1); 2633484#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2633545#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2633535#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2633533#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2633531#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2633529#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2633527#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2633525#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 2559397#L1303-2 [2022-12-13 19:42:48,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:48,730 INFO L85 PathProgramCache]: Analyzing trace with hash 743043657, now seen corresponding path program 1 times [2022-12-13 19:42:48,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:48,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31700779] [2022-12-13 19:42:48,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:48,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:48,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:48,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:48,773 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:48,773 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [31700779] [2022-12-13 19:42:48,774 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [31700779] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:48,774 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:48,774 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:48,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [110990593] [2022-12-13 19:42:48,774 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:48,774 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:48,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:48,775 INFO L85 PathProgramCache]: Analyzing trace with hash 1401394775, now seen corresponding path program 1 times [2022-12-13 19:42:48,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:48,775 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323600120] [2022-12-13 19:42:48,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:48,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:48,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:48,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:48,803 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:48,803 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323600120] [2022-12-13 19:42:48,803 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1323600120] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:48,803 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:48,803 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:48,804 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [35875017] [2022-12-13 19:42:48,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:48,804 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:48,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:48,804 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:42:48,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:42:48,805 INFO L87 Difference]: Start difference. First operand 139577 states and 195217 transitions. cyclomatic complexity: 55704 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:49,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:49,456 INFO L93 Difference]: Finished difference Result 179227 states and 250332 transitions. [2022-12-13 19:42:49,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179227 states and 250332 transitions. [2022-12-13 19:42:49,934 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 178034 [2022-12-13 19:42:50,226 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179227 states to 179227 states and 250332 transitions. [2022-12-13 19:42:50,226 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179227 [2022-12-13 19:42:50,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179227 [2022-12-13 19:42:50,293 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179227 states and 250332 transitions. [2022-12-13 19:42:50,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:50,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179227 states and 250332 transitions. [2022-12-13 19:42:50,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179227 states and 250332 transitions. [2022-12-13 19:42:51,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179227 to 122397. [2022-12-13 19:42:51,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122397 states, 122397 states have (on average 1.3977956976069674) internal successors, (171086), 122396 states have internal predecessors, (171086), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:51,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122397 states to 122397 states and 171086 transitions. [2022-12-13 19:42:51,771 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122397 states and 171086 transitions. [2022-12-13 19:42:51,772 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:42:51,773 INFO L428 stractBuchiCegarLoop]: Abstraction has 122397 states and 171086 transitions. [2022-12-13 19:42:51,773 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 19:42:51,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122397 states and 171086 transitions. [2022-12-13 19:42:52,004 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 121576 [2022-12-13 19:42:52,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:52,004 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:52,005 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:52,005 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:52,005 INFO L748 eck$LassoCheckResult]: Stem: 2877676#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2877677#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2878408#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2878409#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2878469#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 2878112#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2878113#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2877693#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2877694#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2877627#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2877628#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2877891#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2877865#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2877866#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2878177#L854 assume !(0 == ~M_E~0); 2877955#L854-2 assume !(0 == ~T1_E~0); 2877956#L859-1 assume !(0 == ~T2_E~0); 2877507#L864-1 assume !(0 == ~T3_E~0); 2877508#L869-1 assume !(0 == ~T4_E~0); 2877618#L874-1 assume !(0 == ~T5_E~0); 2878450#L879-1 assume !(0 == ~T6_E~0); 2877943#L884-1 assume !(0 == ~T7_E~0); 2877381#L889-1 assume !(0 == ~T8_E~0); 2877382#L894-1 assume !(0 == ~E_M~0); 2877707#L899-1 assume !(0 == ~E_1~0); 2878184#L904-1 assume !(0 == ~E_2~0); 2877880#L909-1 assume !(0 == ~E_3~0); 2877881#L914-1 assume !(0 == ~E_4~0); 2878099#L919-1 assume !(0 == ~E_5~0); 2877788#L924-1 assume !(0 == ~E_6~0); 2877600#L929-1 assume !(0 == ~E_7~0); 2877601#L934-1 assume !(0 == ~E_8~0); 2877862#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2877397#L418 assume !(1 == ~m_pc~0); 2877398#L418-2 is_master_triggered_~__retres1~0#1 := 0; 2878392#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2878329#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2878312#L1061 assume !(0 != activate_threads_~tmp~1#1); 2878213#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2878214#L437 assume !(1 == ~t1_pc~0); 2878438#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2878320#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2877417#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2877418#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 2877736#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2878301#L456 assume !(1 == ~t2_pc~0); 2877655#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2877654#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2877819#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2877820#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 2877992#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2877502#L475 assume !(1 == ~t3_pc~0); 2877503#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2877565#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2877389#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2877390#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 2877739#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2877740#L494 assume !(1 == ~t4_pc~0); 2877782#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2877783#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2877517#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2877518#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 2878129#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2877560#L513 assume !(1 == ~t5_pc~0); 2877561#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2877784#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2878332#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2877514#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 2877515#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2877470#L532 assume !(1 == ~t6_pc~0); 2877471#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2877619#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2877801#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2877802#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 2877711#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2877712#L551 assume !(1 == ~t7_pc~0); 2878185#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2878132#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2878133#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2878488#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 2878497#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2877901#L570 assume !(1 == ~t8_pc~0); 2877902#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2878414#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2878263#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2878015#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 2877496#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2877497#L952 assume !(1 == ~M_E~0); 2877442#L952-2 assume !(1 == ~T1_E~0); 2877443#L957-1 assume !(1 == ~T2_E~0); 2878276#L962-1 assume !(1 == ~T3_E~0); 2878038#L967-1 assume !(1 == ~T4_E~0); 2878039#L972-1 assume !(1 == ~T5_E~0); 2878353#L977-1 assume !(1 == ~T6_E~0); 2878354#L982-1 assume !(1 == ~T7_E~0); 2877621#L987-1 assume !(1 == ~T8_E~0); 2877622#L992-1 assume !(1 == ~E_M~0); 2877629#L997-1 assume !(1 == ~E_1~0); 2877989#L1002-1 assume !(1 == ~E_2~0); 2877974#L1007-1 assume !(1 == ~E_3~0); 2877383#L1012-1 assume !(1 == ~E_4~0); 2877384#L1017-1 assume !(1 == ~E_5~0); 2877977#L1022-1 assume !(1 == ~E_6~0); 2877978#L1027-1 assume !(1 == ~E_7~0); 2878005#L1032-1 assume !(1 == ~E_8~0); 2878164#L1037-1 assume { :end_inline_reset_delta_events } true; 2878165#L1303-2 [2022-12-13 19:42:52,006 INFO L750 eck$LassoCheckResult]: Loop: 2878165#L1303-2 assume !false; 2898401#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2898400#L829 assume !false; 2898399#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2898392#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2898384#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2898379#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2898373#L712 assume !(0 != eval_~tmp~0#1); 2898372#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2898371#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2898370#L854-3 assume !(0 == ~M_E~0); 2898369#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2898368#L859-3 assume !(0 == ~T2_E~0); 2898367#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2898366#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2898365#L874-3 assume !(0 == ~T5_E~0); 2898364#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2898362#L884-3 assume !(0 == ~T7_E~0); 2898360#L889-3 assume !(0 == ~T8_E~0); 2898358#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2898356#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2898354#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2898352#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2898350#L914-3 assume !(0 == ~E_4~0); 2898348#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2898346#L924-3 assume !(0 == ~E_6~0); 2898344#L929-3 assume !(0 == ~E_7~0); 2898342#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2898340#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2898338#L418-30 assume !(1 == ~m_pc~0); 2898335#L418-32 is_master_triggered_~__retres1~0#1 := 0; 2898333#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2898331#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2898329#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 2898327#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2898324#L437-30 assume !(1 == ~t1_pc~0); 2898323#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2898320#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2898318#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2898316#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2898314#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2898312#L456-30 assume 1 == ~t2_pc~0; 2898309#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2898306#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2898304#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2898302#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2898300#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2898298#L475-30 assume !(1 == ~t3_pc~0); 2898296#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2898294#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2898292#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2898290#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2898288#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2898286#L494-30 assume !(1 == ~t4_pc~0); 2898284#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2898280#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2898278#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2898276#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 2898274#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2898272#L513-30 assume !(1 == ~t5_pc~0); 2898269#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2898267#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2898265#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2898263#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2898261#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2898259#L532-30 assume !(1 == ~t6_pc~0); 2898256#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2898254#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2898252#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2898250#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2898248#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2898246#L551-30 assume !(1 == ~t7_pc~0); 2898244#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2898243#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2898239#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2898237#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2898235#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2898234#L570-30 assume !(1 == ~t8_pc~0); 2898229#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2898225#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2898220#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2898215#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2898210#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2898208#L952-3 assume !(1 == ~M_E~0); 2898206#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2898205#L957-3 assume !(1 == ~T2_E~0); 2898204#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2898203#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2898202#L972-3 assume !(1 == ~T5_E~0); 2898201#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2898200#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2898190#L987-3 assume !(1 == ~T8_E~0); 2898188#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2898186#L997-3 assume !(1 == ~E_1~0); 2898183#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2898181#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2898179#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2898177#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2898175#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2898173#L1027-3 assume !(1 == ~E_7~0); 2898171#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2898169#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2898151#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2898149#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2898147#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2897078#L1322 assume !(0 == start_simulation_~tmp~3#1); 2897079#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2898576#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2898567#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2898565#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2898563#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2898561#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2898560#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2898556#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 2878165#L1303-2 [2022-12-13 19:42:52,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:52,006 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 2 times [2022-12-13 19:42:52,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:52,006 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [605175184] [2022-12-13 19:42:52,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:52,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:52,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:52,014 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:42:52,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:42:52,041 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:42:52,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:52,041 INFO L85 PathProgramCache]: Analyzing trace with hash -182566377, now seen corresponding path program 1 times [2022-12-13 19:42:52,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:52,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215377] [2022-12-13 19:42:52,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:52,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:52,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:52,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:52,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:52,062 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215377] [2022-12-13 19:42:52,062 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215377] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:52,062 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:52,062 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:52,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1808704597] [2022-12-13 19:42:52,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:52,063 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:52,063 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:52,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:42:52,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:42:52,064 INFO L87 Difference]: Start difference. First operand 122397 states and 171086 transitions. cyclomatic complexity: 48753 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:52,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:52,559 INFO L93 Difference]: Finished difference Result 199781 states and 277344 transitions. [2022-12-13 19:42:52,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 199781 states and 277344 transitions. [2022-12-13 19:42:53,465 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 198404 [2022-12-13 19:42:53,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 199781 states to 199781 states and 277344 transitions. [2022-12-13 19:42:53,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 199781 [2022-12-13 19:42:53,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 199781 [2022-12-13 19:42:53,990 INFO L73 IsDeterministic]: Start isDeterministic. Operand 199781 states and 277344 transitions. [2022-12-13 19:42:54,077 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:54,077 INFO L218 hiAutomatonCegarLoop]: Abstraction has 199781 states and 277344 transitions. [2022-12-13 19:42:54,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199781 states and 277344 transitions. [2022-12-13 19:42:55,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199781 to 199269. [2022-12-13 19:42:55,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 199269 states, 199269 states have (on average 1.3883544354616122) internal successors, (276656), 199268 states have internal predecessors, (276656), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:55,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199269 states to 199269 states and 276656 transitions. [2022-12-13 19:42:55,894 INFO L240 hiAutomatonCegarLoop]: Abstraction has 199269 states and 276656 transitions. [2022-12-13 19:42:55,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:42:55,895 INFO L428 stractBuchiCegarLoop]: Abstraction has 199269 states and 276656 transitions. [2022-12-13 19:42:55,895 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 19:42:55,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 199269 states and 276656 transitions. [2022-12-13 19:42:56,389 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 198084 [2022-12-13 19:42:56,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:42:56,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:42:56,390 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:56,390 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:42:56,390 INFO L748 eck$LassoCheckResult]: Stem: 3199860#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 3199861#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3200664#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3200665#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3200763#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 3200325#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3200326#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3199881#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3199882#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3199813#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3199814#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3200086#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3200057#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3200058#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3200399#L854 assume !(0 == ~M_E~0); 3200157#L854-2 assume !(0 == ~T1_E~0); 3200158#L859-1 assume !(0 == ~T2_E~0); 3199690#L864-1 assume !(0 == ~T3_E~0); 3199691#L869-1 assume !(0 == ~T4_E~0); 3199800#L874-1 assume !(0 == ~T5_E~0); 3200728#L879-1 assume !(0 == ~T6_E~0); 3200142#L884-1 assume !(0 == ~T7_E~0); 3199564#L889-1 assume !(0 == ~T8_E~0); 3199565#L894-1 assume !(0 == ~E_M~0); 3199892#L899-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3200405#L904-1 assume !(0 == ~E_2~0); 3200406#L909-1 assume !(0 == ~E_3~0); 3200311#L914-1 assume !(0 == ~E_4~0); 3200312#L919-1 assume !(0 == ~E_5~0); 3199975#L924-1 assume !(0 == ~E_6~0); 3199976#L929-1 assume !(0 == ~E_7~0); 3200741#L934-1 assume !(0 == ~E_8~0); 3200054#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3199580#L418 assume !(1 == ~m_pc~0); 3199581#L418-2 is_master_triggered_~__retres1~0#1 := 0; 3200641#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3200642#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3200548#L1061 assume !(0 != activate_threads_~tmp~1#1); 3200549#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3200777#L437 assume !(1 == ~t1_pc~0); 3200778#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3200558#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3200559#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3199920#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 3199921#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3200537#L456 assume !(1 == ~t2_pc~0); 3200538#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3200772#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3200773#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3200589#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 3200590#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3199685#L475 assume !(1 == ~t3_pc~0); 3199686#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3199749#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3199750#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3200710#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 3200711#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3200631#L494 assume !(1 == ~t4_pc~0); 3200632#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3200275#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3200276#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3200815#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 3200816#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3199745#L513 assume !(1 == ~t5_pc~0); 3199746#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3200789#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3200790#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3199697#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 3199698#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3199655#L532 assume !(1 == ~t6_pc~0); 3199656#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3200117#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3200118#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3200752#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 3200753#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3200595#L551 assume !(1 == ~t7_pc~0); 3200407#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3200408#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3200802#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3200803#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 3200841#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3200097#L570 assume !(1 == ~t8_pc~0); 3200098#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3200675#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3200676#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3200219#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 3199683#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3199684#L952 assume !(1 == ~M_E~0); 3199625#L952-2 assume !(1 == ~T1_E~0); 3199626#L957-1 assume !(1 == ~T2_E~0); 3200782#L962-1 assume !(1 == ~T3_E~0); 3200783#L967-1 assume !(1 == ~T4_E~0); 3200764#L972-1 assume !(1 == ~T5_E~0); 3200765#L977-1 assume !(1 == ~T6_E~0); 3200814#L982-1 assume !(1 == ~T7_E~0); 3199805#L987-1 assume !(1 == ~T8_E~0); 3199806#L992-1 assume !(1 == ~E_M~0); 3199815#L997-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3200188#L1002-1 assume !(1 == ~E_2~0); 3200172#L1007-1 assume !(1 == ~E_3~0); 3199566#L1012-1 assume !(1 == ~E_4~0); 3199567#L1017-1 assume !(1 == ~E_5~0); 3200178#L1022-1 assume !(1 == ~E_6~0); 3200179#L1027-1 assume !(1 == ~E_7~0); 3200207#L1032-1 assume !(1 == ~E_8~0); 3200384#L1037-1 assume { :end_inline_reset_delta_events } true; 3200385#L1303-2 [2022-12-13 19:42:56,390 INFO L750 eck$LassoCheckResult]: Loop: 3200385#L1303-2 assume !false; 3255770#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3255768#L829 assume !false; 3254767#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3243532#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3243523#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3243521#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3243518#L712 assume !(0 != eval_~tmp~0#1); 3243519#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3256025#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3256023#L854-3 assume !(0 == ~M_E~0); 3256021#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3256019#L859-3 assume !(0 == ~T2_E~0); 3256017#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3256015#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3256013#L874-3 assume !(0 == ~T5_E~0); 3256011#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3256009#L884-3 assume !(0 == ~T7_E~0); 3256007#L889-3 assume !(0 == ~T8_E~0); 3256005#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3256002#L899-3 assume !(0 == ~E_1~0); 3256003#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3256034#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3256033#L914-3 assume !(0 == ~E_4~0); 3256032#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3256031#L924-3 assume !(0 == ~E_6~0); 3256030#L929-3 assume !(0 == ~E_7~0); 3256029#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3256028#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3256027#L418-30 assume !(1 == ~m_pc~0); 3256026#L418-32 is_master_triggered_~__retres1~0#1 := 0; 3256024#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3256022#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3256020#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 3256018#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3256016#L437-30 assume !(1 == ~t1_pc~0); 3256014#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 3256012#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3256010#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3256008#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3256006#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3256004#L456-30 assume !(1 == ~t2_pc~0); 3256001#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 3255998#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3255996#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3255994#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3255992#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3255990#L475-30 assume !(1 == ~t3_pc~0); 3255988#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 3255986#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3255984#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3255982#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3255980#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3255978#L494-30 assume 1 == ~t4_pc~0; 3255975#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3255973#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3255971#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3255969#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 3255967#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3255965#L513-30 assume !(1 == ~t5_pc~0); 3255963#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 3255961#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3255959#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3255957#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3255954#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3255952#L532-30 assume !(1 == ~t6_pc~0); 3255949#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 3255947#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3255945#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3255943#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3255941#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3255939#L551-30 assume !(1 == ~t7_pc~0); 3255937#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 3255935#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3255933#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3255931#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3255928#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3255926#L570-30 assume !(1 == ~t8_pc~0); 3255924#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 3255922#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3255920#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3255918#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3255916#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3255914#L952-3 assume !(1 == ~M_E~0); 3255912#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3255910#L957-3 assume !(1 == ~T2_E~0); 3255908#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3255906#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3255903#L972-3 assume !(1 == ~T5_E~0); 3255901#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3255899#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3255897#L987-3 assume !(1 == ~T8_E~0); 3255895#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3255851#L997-3 assume !(1 == ~E_1~0); 3255849#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3255846#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3255843#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3255841#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3255839#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3255837#L1027-3 assume !(1 == ~E_7~0); 3255835#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3255833#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3255812#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3255810#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3255808#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 3255804#L1322 assume !(0 == start_simulation_~tmp~3#1); 3255802#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3255796#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3255788#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3255786#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 3255784#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3255782#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3255780#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 3255778#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 3200385#L1303-2 [2022-12-13 19:42:56,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:56,391 INFO L85 PathProgramCache]: Analyzing trace with hash -1215057335, now seen corresponding path program 1 times [2022-12-13 19:42:56,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:56,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166856851] [2022-12-13 19:42:56,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:56,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:56,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:56,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:56,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:56,424 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166856851] [2022-12-13 19:42:56,424 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [166856851] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:56,424 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:56,424 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:42:56,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1214417151] [2022-12-13 19:42:56,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:56,424 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 19:42:56,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:42:56,425 INFO L85 PathProgramCache]: Analyzing trace with hash -698085419, now seen corresponding path program 1 times [2022-12-13 19:42:56,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:42:56,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830395817] [2022-12-13 19:42:56,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:42:56,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:42:56,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:42:56,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:42:56,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:42:56,457 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1830395817] [2022-12-13 19:42:56,457 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1830395817] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:42:56,457 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:42:56,457 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:42:56,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1342616839] [2022-12-13 19:42:56,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:42:56,458 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:42:56,458 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:42:56,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 19:42:56,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 19:42:56,458 INFO L87 Difference]: Start difference. First operand 199269 states and 276656 transitions. cyclomatic complexity: 77451 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:42:57,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:42:57,346 INFO L93 Difference]: Finished difference Result 282807 states and 392209 transitions. [2022-12-13 19:42:57,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 282807 states and 392209 transitions. [2022-12-13 19:42:58,467 INFO L131 ngComponentsAnalysis]: Automaton has 112 accepting balls. 274402 [2022-12-13 19:42:59,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 282807 states to 282807 states and 392209 transitions. [2022-12-13 19:42:59,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 282807 [2022-12-13 19:42:59,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 282807 [2022-12-13 19:42:59,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 282807 states and 392209 transitions. [2022-12-13 19:42:59,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:42:59,360 INFO L218 hiAutomatonCegarLoop]: Abstraction has 282807 states and 392209 transitions. [2022-12-13 19:42:59,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282807 states and 392209 transitions. [2022-12-13 19:43:01,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282807 to 193601. [2022-12-13 19:43:01,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 193601 states, 193601 states have (on average 1.3874979984607518) internal successors, (268621), 193600 states have internal predecessors, (268621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:43:01,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193601 states to 193601 states and 268621 transitions. [2022-12-13 19:43:01,392 INFO L240 hiAutomatonCegarLoop]: Abstraction has 193601 states and 268621 transitions. [2022-12-13 19:43:01,393 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 19:43:01,393 INFO L428 stractBuchiCegarLoop]: Abstraction has 193601 states and 268621 transitions. [2022-12-13 19:43:01,393 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 19:43:01,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 193601 states and 268621 transitions. [2022-12-13 19:43:01,833 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 192492 [2022-12-13 19:43:01,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:43:01,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:43:01,835 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:43:01,835 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:43:01,835 INFO L748 eck$LassoCheckResult]: Stem: 3681949#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 3681950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3682699#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3682700#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3682771#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 3682399#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3682400#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3681970#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3681971#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3681902#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3681903#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3682173#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3682145#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3682146#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3682466#L854 assume !(0 == ~M_E~0); 3682238#L854-2 assume !(0 == ~T1_E~0); 3682239#L859-1 assume !(0 == ~T2_E~0); 3681780#L864-1 assume !(0 == ~T3_E~0); 3681781#L869-1 assume !(0 == ~T4_E~0); 3681892#L874-1 assume !(0 == ~T5_E~0); 3682744#L879-1 assume !(0 == ~T6_E~0); 3682224#L884-1 assume !(0 == ~T7_E~0); 3681653#L889-1 assume !(0 == ~T8_E~0); 3681654#L894-1 assume !(0 == ~E_M~0); 3681979#L899-1 assume !(0 == ~E_1~0); 3682472#L904-1 assume !(0 == ~E_2~0); 3682162#L909-1 assume !(0 == ~E_3~0); 3682163#L914-1 assume !(0 == ~E_4~0); 3682387#L919-1 assume !(0 == ~E_5~0); 3682064#L924-1 assume !(0 == ~E_6~0); 3681876#L929-1 assume !(0 == ~E_7~0); 3681877#L934-1 assume !(0 == ~E_8~0); 3682142#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3681670#L418 assume !(1 == ~m_pc~0); 3681671#L418-2 is_master_triggered_~__retres1~0#1 := 0; 3682681#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3682620#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3682604#L1061 assume !(0 != activate_threads_~tmp~1#1); 3682503#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3682504#L437 assume !(1 == ~t1_pc~0); 3682731#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3682611#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3681693#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3681694#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 3682011#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3682594#L456 assume !(1 == ~t2_pc~0); 3681931#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3681930#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3682099#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3682100#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 3682273#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3681775#L475 assume !(1 == ~t3_pc~0); 3681776#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3681841#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3681662#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3681663#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 3682014#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3682015#L494 assume !(1 == ~t4_pc~0); 3682058#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3682059#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3681791#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3681792#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 3682415#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3681837#L513 assume !(1 == ~t5_pc~0); 3681838#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3682063#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3682622#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3681787#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 3681788#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3681743#L532 assume !(1 == ~t6_pc~0); 3681744#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3681891#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3682080#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3682081#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 3681983#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3681984#L551 assume !(1 == ~t7_pc~0); 3682473#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3682418#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3682419#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3682794#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 3682804#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3682184#L570 assume !(1 == ~t8_pc~0); 3682185#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3682704#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3682558#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3682298#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 3681773#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3681774#L952 assume !(1 == ~M_E~0); 3681715#L952-2 assume !(1 == ~T1_E~0); 3681716#L957-1 assume !(1 == ~T2_E~0); 3682567#L962-1 assume !(1 == ~T3_E~0); 3682316#L967-1 assume !(1 == ~T4_E~0); 3682317#L972-1 assume !(1 == ~T5_E~0); 3682641#L977-1 assume !(1 == ~T6_E~0); 3682642#L982-1 assume !(1 == ~T7_E~0); 3681894#L987-1 assume !(1 == ~T8_E~0); 3681895#L992-1 assume !(1 == ~E_M~0); 3681904#L997-1 assume !(1 == ~E_1~0); 3682271#L1002-1 assume !(1 == ~E_2~0); 3682255#L1007-1 assume !(1 == ~E_3~0); 3681655#L1012-1 assume !(1 == ~E_4~0); 3681656#L1017-1 assume !(1 == ~E_5~0); 3682261#L1022-1 assume !(1 == ~E_6~0); 3682262#L1027-1 assume !(1 == ~E_7~0); 3682287#L1032-1 assume !(1 == ~E_8~0); 3682448#L1037-1 assume { :end_inline_reset_delta_events } true; 3682449#L1303-2 [2022-12-13 19:43:01,835 INFO L750 eck$LassoCheckResult]: Loop: 3682449#L1303-2 assume !false; 3806604#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3806484#L829 assume !false; 3806601#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3806580#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3806575#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3806574#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3806572#L712 assume !(0 != eval_~tmp~0#1); 3806573#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3840696#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3840694#L854-3 assume !(0 == ~M_E~0); 3840692#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3840690#L859-3 assume !(0 == ~T2_E~0); 3839580#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3839579#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3839569#L874-3 assume !(0 == ~T5_E~0); 3839567#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3839565#L884-3 assume !(0 == ~T7_E~0); 3839562#L889-3 assume !(0 == ~T8_E~0); 3839560#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3839558#L899-3 assume !(0 == ~E_1~0); 3839556#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3839554#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3839552#L914-3 assume !(0 == ~E_4~0); 3839550#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3839548#L924-3 assume !(0 == ~E_6~0); 3839546#L929-3 assume !(0 == ~E_7~0); 3839544#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3839542#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3839540#L418-30 assume !(1 == ~m_pc~0); 3839538#L418-32 is_master_triggered_~__retres1~0#1 := 0; 3839536#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3839534#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3839532#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 3839530#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3839528#L437-30 assume !(1 == ~t1_pc~0); 3839526#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 3839524#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3839522#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3839520#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3839518#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3839516#L456-30 assume !(1 == ~t2_pc~0); 3839514#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 3741396#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3741395#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3741394#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3741393#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3741392#L475-30 assume !(1 == ~t3_pc~0); 3741391#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 3741390#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3741389#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3741388#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3741387#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3741386#L494-30 assume !(1 == ~t4_pc~0); 3741385#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 3741383#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3741382#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3741380#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 3741378#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3741376#L513-30 assume !(1 == ~t5_pc~0); 3741374#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 3741372#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3741370#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3741368#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3741366#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3741364#L532-30 assume !(1 == ~t6_pc~0); 3741361#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 3741359#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3741357#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3741355#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3741353#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3741351#L551-30 assume !(1 == ~t7_pc~0); 3741348#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 3741346#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3741344#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3741342#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3741340#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3741338#L570-30 assume !(1 == ~t8_pc~0); 3741337#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 3741335#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3741333#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3741331#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3741329#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3741327#L952-3 assume !(1 == ~M_E~0); 3741324#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3741322#L957-3 assume !(1 == ~T2_E~0); 3741320#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3741318#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3741316#L972-3 assume !(1 == ~T5_E~0); 3741314#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3741311#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3741309#L987-3 assume !(1 == ~T8_E~0); 3741307#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3741305#L997-3 assume !(1 == ~E_1~0); 3741303#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3741301#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3741298#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3741296#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3741294#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3741292#L1027-3 assume !(1 == ~E_7~0); 3741290#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3741288#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3741268#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3741257#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3741258#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 3710842#L1322 assume !(0 == start_simulation_~tmp~3#1); 3710843#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3806627#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3806618#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3806616#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 3806614#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3806612#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3806610#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 3806608#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 3682449#L1303-2 [2022-12-13 19:43:01,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:43:01,835 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 3 times [2022-12-13 19:43:01,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:43:01,836 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543739746] [2022-12-13 19:43:01,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:43:01,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:43:01,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:43:01,844 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:43:01,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:43:01,882 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:43:01,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:43:01,883 INFO L85 PathProgramCache]: Analyzing trace with hash 330446742, now seen corresponding path program 1 times [2022-12-13 19:43:01,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:43:01,883 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [408272124] [2022-12-13 19:43:01,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:43:01,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:43:01,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:43:01,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:43:01,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:43:01,912 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [408272124] [2022-12-13 19:43:01,912 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [408272124] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:43:01,912 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:43:01,912 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 19:43:01,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928703840] [2022-12-13 19:43:01,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:43:01,913 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:43:01,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:43:01,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 19:43:01,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 19:43:01,913 INFO L87 Difference]: Start difference. First operand 193601 states and 268621 transitions. cyclomatic complexity: 75084 Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:43:02,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:43:02,911 INFO L93 Difference]: Finished difference Result 350125 states and 480805 transitions. [2022-12-13 19:43:02,911 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 350125 states and 480805 transitions. [2022-12-13 19:43:04,382 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 348016 [2022-12-13 19:43:04,998 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 350125 states to 350125 states and 480805 transitions. [2022-12-13 19:43:04,998 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350125 [2022-12-13 19:43:05,337 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 350125 [2022-12-13 19:43:05,337 INFO L73 IsDeterministic]: Start isDeterministic. Operand 350125 states and 480805 transitions. [2022-12-13 19:43:05,424 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:43:05,424 INFO L218 hiAutomatonCegarLoop]: Abstraction has 350125 states and 480805 transitions. [2022-12-13 19:43:05,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350125 states and 480805 transitions. [2022-12-13 19:43:07,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350125 to 194681. [2022-12-13 19:43:07,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 194681 states, 194681 states have (on average 1.3853483390777734) internal successors, (269701), 194680 states have internal predecessors, (269701), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:43:07,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194681 states to 194681 states and 269701 transitions. [2022-12-13 19:43:07,404 INFO L240 hiAutomatonCegarLoop]: Abstraction has 194681 states and 269701 transitions. [2022-12-13 19:43:07,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 19:43:07,405 INFO L428 stractBuchiCegarLoop]: Abstraction has 194681 states and 269701 transitions. [2022-12-13 19:43:07,405 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-12-13 19:43:07,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 194681 states and 269701 transitions. [2022-12-13 19:43:07,996 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 193572 [2022-12-13 19:43:07,996 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:43:07,996 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:43:07,997 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:43:07,997 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:43:07,997 INFO L748 eck$LassoCheckResult]: Stem: 4225692#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4225693#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4226483#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4226484#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4226576#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 4226161#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4226162#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4225714#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4225715#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4225645#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4225646#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4225927#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4225897#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4225898#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4226234#L854 assume !(0 == ~M_E~0); 4225996#L854-2 assume !(0 == ~T1_E~0); 4225997#L859-1 assume !(0 == ~T2_E~0); 4225520#L864-1 assume !(0 == ~T3_E~0); 4225521#L869-1 assume !(0 == ~T4_E~0); 4225635#L874-1 assume !(0 == ~T5_E~0); 4226548#L879-1 assume !(0 == ~T6_E~0); 4225981#L884-1 assume !(0 == ~T7_E~0); 4225394#L889-1 assume !(0 == ~T8_E~0); 4225395#L894-1 assume !(0 == ~E_M~0); 4225726#L899-1 assume !(0 == ~E_1~0); 4226240#L904-1 assume !(0 == ~E_2~0); 4225918#L909-1 assume !(0 == ~E_3~0); 4225919#L914-1 assume !(0 == ~E_4~0); 4226148#L919-1 assume !(0 == ~E_5~0); 4225815#L924-1 assume !(0 == ~E_6~0); 4225620#L929-1 assume !(0 == ~E_7~0); 4225621#L934-1 assume !(0 == ~E_8~0); 4225894#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4225410#L418 assume !(1 == ~m_pc~0); 4225411#L418-2 is_master_triggered_~__retres1~0#1 := 0; 4226459#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4226388#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4226372#L1061 assume !(0 != activate_threads_~tmp~1#1); 4226269#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4226270#L437 assume !(1 == ~t1_pc~0); 4226532#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4226380#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4225433#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4225434#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 4225760#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4226363#L456 assume !(1 == ~t2_pc~0); 4225674#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4225673#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4225848#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4225849#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 4226031#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4225515#L475 assume !(1 == ~t3_pc~0); 4225516#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4225582#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4225402#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4225403#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 4225763#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4225764#L494 assume !(1 == ~t4_pc~0); 4225809#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4225810#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4225531#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4225532#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 4226180#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4225578#L513 assume !(1 == ~t5_pc~0); 4225579#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4225814#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4226390#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4225527#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 4225528#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4225485#L532 assume !(1 == ~t6_pc~0); 4225486#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4225634#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4225830#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4225831#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 4225732#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4225733#L551 assume !(1 == ~t7_pc~0); 4226241#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4226184#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4226185#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4226608#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 4226616#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4225940#L570 assume !(1 == ~t8_pc~0); 4225941#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4226492#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4226320#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4226058#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 4225513#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4225514#L952 assume !(1 == ~M_E~0); 4225455#L952-2 assume !(1 == ~T1_E~0); 4225456#L957-1 assume !(1 == ~T2_E~0); 4226331#L962-1 assume !(1 == ~T3_E~0); 4226080#L967-1 assume !(1 == ~T4_E~0); 4226081#L972-1 assume !(1 == ~T5_E~0); 4226410#L977-1 assume !(1 == ~T6_E~0); 4226411#L982-1 assume !(1 == ~T7_E~0); 4225637#L987-1 assume !(1 == ~T8_E~0); 4225638#L992-1 assume !(1 == ~E_M~0); 4225647#L997-1 assume !(1 == ~E_1~0); 4226028#L1002-1 assume !(1 == ~E_2~0); 4226013#L1007-1 assume !(1 == ~E_3~0); 4225396#L1012-1 assume !(1 == ~E_4~0); 4225397#L1017-1 assume !(1 == ~E_5~0); 4226019#L1022-1 assume !(1 == ~E_6~0); 4226020#L1027-1 assume !(1 == ~E_7~0); 4226046#L1032-1 assume !(1 == ~E_8~0); 4226218#L1037-1 assume { :end_inline_reset_delta_events } true; 4226219#L1303-2 [2022-12-13 19:43:07,997 INFO L750 eck$LassoCheckResult]: Loop: 4226219#L1303-2 assume !false; 4282736#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4280918#L829 assume !false; 4279267#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4275730#L650 assume !(0 == ~m_st~0); 4275731#L654 assume !(0 == ~t1_st~0); 4275734#L658 assume !(0 == ~t2_st~0); 4275728#L662 assume !(0 == ~t3_st~0); 4275729#L666 assume !(0 == ~t4_st~0); 4275733#L670 assume !(0 == ~t5_st~0); 4275725#L674 assume !(0 == ~t6_st~0); 4275727#L678 assume !(0 == ~t7_st~0); 4275732#L682 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 4275671#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4275635#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4275636#L712 assume !(0 != eval_~tmp~0#1); 4282915#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4282914#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4282913#L854-3 assume !(0 == ~M_E~0); 4282912#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4282911#L859-3 assume !(0 == ~T2_E~0); 4282910#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4282909#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4282908#L874-3 assume !(0 == ~T5_E~0); 4282907#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4282906#L884-3 assume !(0 == ~T7_E~0); 4282905#L889-3 assume !(0 == ~T8_E~0); 4282904#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4282903#L899-3 assume !(0 == ~E_1~0); 4282902#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4282901#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4282900#L914-3 assume !(0 == ~E_4~0); 4282899#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4282898#L924-3 assume !(0 == ~E_6~0); 4282897#L929-3 assume !(0 == ~E_7~0); 4282896#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4282895#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4282894#L418-30 assume !(1 == ~m_pc~0); 4282893#L418-32 is_master_triggered_~__retres1~0#1 := 0; 4282892#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4282891#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4282890#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 4282889#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4282888#L437-30 assume !(1 == ~t1_pc~0); 4282887#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 4282886#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4282885#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4282884#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4282883#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4282882#L456-30 assume !(1 == ~t2_pc~0); 4282881#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 4282879#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4282878#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4282877#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4282876#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4282875#L475-30 assume !(1 == ~t3_pc~0); 4282874#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 4282873#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4282872#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4282871#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4282870#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4282869#L494-30 assume 1 == ~t4_pc~0; 4282867#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4282866#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4282865#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4282864#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 4282863#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4282862#L513-30 assume !(1 == ~t5_pc~0); 4282861#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 4282860#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4282859#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4282858#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4282857#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4282856#L532-30 assume 1 == ~t6_pc~0; 4282855#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4282853#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4282852#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4282851#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4282850#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4282849#L551-30 assume !(1 == ~t7_pc~0); 4282848#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 4282847#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4282846#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4282845#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4282844#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4282843#L570-30 assume !(1 == ~t8_pc~0); 4282842#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4282841#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4282840#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4282839#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4282838#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4282837#L952-3 assume !(1 == ~M_E~0); 4282836#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4282835#L957-3 assume !(1 == ~T2_E~0); 4282834#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4282833#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4282832#L972-3 assume !(1 == ~T5_E~0); 4282831#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4282830#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4282829#L987-3 assume !(1 == ~T8_E~0); 4282828#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4282827#L997-3 assume !(1 == ~E_1~0); 4282826#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4282825#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4282824#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4282823#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4282822#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4282821#L1027-3 assume !(1 == ~E_7~0); 4282820#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4282819#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4282810#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4282808#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4282806#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4282803#L1322 assume !(0 == start_simulation_~tmp~3#1); 4282802#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4282800#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4282789#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4282786#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 4282784#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4282782#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4282777#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4282755#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 4226219#L1303-2 [2022-12-13 19:43:07,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:43:07,998 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 4 times [2022-12-13 19:43:07,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:43:07,998 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1940258012] [2022-12-13 19:43:07,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:43:07,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:43:08,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:43:08,005 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:43:08,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:43:08,028 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:43:08,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:43:08,029 INFO L85 PathProgramCache]: Analyzing trace with hash -51909314, now seen corresponding path program 1 times [2022-12-13 19:43:08,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:43:08,029 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2010141147] [2022-12-13 19:43:08,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:43:08,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:43:08,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:43:08,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:43:08,051 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:43:08,051 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2010141147] [2022-12-13 19:43:08,051 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2010141147] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:43:08,051 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:43:08,051 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:43:08,051 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1052499086] [2022-12-13 19:43:08,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:43:08,051 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 19:43:08,051 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:43:08,052 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:43:08,052 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:43:08,052 INFO L87 Difference]: Start difference. First operand 194681 states and 269701 transitions. cyclomatic complexity: 75084 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:43:08,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:43:08,683 INFO L93 Difference]: Finished difference Result 304569 states and 417653 transitions. [2022-12-13 19:43:08,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 304569 states and 417653 transitions. [2022-12-13 19:43:09,954 INFO L131 ngComponentsAnalysis]: Automaton has 104 accepting balls. 303110 [2022-12-13 19:43:10,498 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 304569 states to 304569 states and 417653 transitions. [2022-12-13 19:43:10,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 304569 [2022-12-13 19:43:10,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 304569 [2022-12-13 19:43:10,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 304569 states and 417653 transitions. [2022-12-13 19:43:10,875 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:43:10,875 INFO L218 hiAutomatonCegarLoop]: Abstraction has 304569 states and 417653 transitions. [2022-12-13 19:43:10,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304569 states and 417653 transitions. [2022-12-13 19:43:12,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304569 to 301049. [2022-12-13 19:43:12,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 301049 states, 301049 states have (on average 1.371806582981508) internal successors, (412981), 301048 states have internal predecessors, (412981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:43:13,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 301049 states to 301049 states and 412981 transitions. [2022-12-13 19:43:13,396 INFO L240 hiAutomatonCegarLoop]: Abstraction has 301049 states and 412981 transitions. [2022-12-13 19:43:13,397 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 19:43:13,397 INFO L428 stractBuchiCegarLoop]: Abstraction has 301049 states and 412981 transitions. [2022-12-13 19:43:13,397 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-12-13 19:43:13,397 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 301049 states and 412981 transitions. [2022-12-13 19:43:14,313 INFO L131 ngComponentsAnalysis]: Automaton has 104 accepting balls. 299590 [2022-12-13 19:43:14,313 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 19:43:14,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 19:43:14,314 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:43:14,314 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 19:43:14,314 INFO L748 eck$LassoCheckResult]: Stem: 4724943#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4724944#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4725714#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4725715#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4725796#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 4725404#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4725405#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4724964#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4724965#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4724898#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4724899#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4725168#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4725139#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4725140#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4725473#L854 assume !(0 == ~M_E~0); 4725237#L854-2 assume !(0 == ~T1_E~0); 4725238#L859-1 assume !(0 == ~T2_E~0); 4724775#L864-1 assume !(0 == ~T3_E~0); 4724776#L869-1 assume !(0 == ~T4_E~0); 4724887#L874-1 assume !(0 == ~T5_E~0); 4725767#L879-1 assume !(0 == ~T6_E~0); 4725224#L884-1 assume !(0 == ~T7_E~0); 4724650#L889-1 assume !(0 == ~T8_E~0); 4724651#L894-1 assume !(0 == ~E_M~0); 4724974#L899-1 assume !(0 == ~E_1~0); 4725479#L904-1 assume !(0 == ~E_2~0); 4725157#L909-1 assume !(0 == ~E_3~0); 4725158#L914-1 assume !(0 == ~E_4~0); 4725392#L919-1 assume !(0 == ~E_5~0); 4725057#L924-1 assume !(0 == ~E_6~0); 4724870#L929-1 assume !(0 == ~E_7~0); 4724871#L934-1 assume !(0 == ~E_8~0); 4725136#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4724666#L418 assume !(1 == ~m_pc~0); 4724667#L418-2 is_master_triggered_~__retres1~0#1 := 0; 4725693#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4725631#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4725606#L1061 assume !(0 != activate_threads_~tmp~1#1); 4725509#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4725510#L437 assume !(1 == ~t1_pc~0); 4725751#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4725616#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4724686#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4724687#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 4725004#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4725596#L456 assume !(1 == ~t2_pc~0); 4724925#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4724924#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4725091#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4725092#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 4725274#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4724770#L475 assume !(1 == ~t3_pc~0); 4724771#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4724835#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4724658#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4724659#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 4725007#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4725008#L494 assume !(1 == ~t4_pc~0); 4725052#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4725053#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4724785#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4724786#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 4725421#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4724833#L513 assume !(1 == ~t5_pc~0); 4724834#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4725056#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4725633#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4724782#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 4724783#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4724739#L532 assume !(1 == ~t6_pc~0); 4724740#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4724888#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4725073#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4725074#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 4724978#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4724979#L551 assume !(1 == ~t7_pc~0); 4725480#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4725423#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4725424#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4725824#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 4725830#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4725180#L570 assume !(1 == ~t8_pc~0); 4725181#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4725718#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4725560#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4725300#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 4724766#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4724767#L952 assume !(1 == ~M_E~0); 4724711#L952-2 assume !(1 == ~T1_E~0); 4724712#L957-1 assume !(1 == ~T2_E~0); 4725572#L962-1 assume !(1 == ~T3_E~0); 4725319#L967-1 assume !(1 == ~T4_E~0); 4725320#L972-1 assume !(1 == ~T5_E~0); 4725649#L977-1 assume !(1 == ~T6_E~0); 4725650#L982-1 assume !(1 == ~T7_E~0); 4724890#L987-1 assume !(1 == ~T8_E~0); 4724891#L992-1 assume !(1 == ~E_M~0); 4724900#L997-1 assume !(1 == ~E_1~0); 4725272#L1002-1 assume !(1 == ~E_2~0); 4725257#L1007-1 assume !(1 == ~E_3~0); 4724652#L1012-1 assume !(1 == ~E_4~0); 4724653#L1017-1 assume !(1 == ~E_5~0); 4725263#L1022-1 assume !(1 == ~E_6~0); 4725264#L1027-1 assume !(1 == ~E_7~0); 4725287#L1032-1 assume !(1 == ~E_8~0); 4725455#L1037-1 assume { :end_inline_reset_delta_events } true; 4725456#L1303-2 assume !false; 4791130#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4789843#L829 [2022-12-13 19:43:14,314 INFO L750 eck$LassoCheckResult]: Loop: 4789843#L829 assume !false; 4791129#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4791126#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4791124#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4791122#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4791120#L712 assume 0 != eval_~tmp~0#1; 4791117#L712-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 4791115#L720 assume !(0 != eval_~tmp_ndt_1~0#1); 4791113#L717 assume !(0 == ~t1_st~0); 4778754#L731 assume !(0 == ~t2_st~0); 4791108#L745 assume !(0 == ~t3_st~0); 4790989#L759 assume !(0 == ~t4_st~0); 4790987#L773 assume !(0 == ~t5_st~0); 4789853#L787 assume !(0 == ~t6_st~0); 4789848#L801 assume !(0 == ~t7_st~0); 4789845#L815 assume !(0 == ~t8_st~0); 4789843#L829 [2022-12-13 19:43:14,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:43:14,315 INFO L85 PathProgramCache]: Analyzing trace with hash -617044821, now seen corresponding path program 1 times [2022-12-13 19:43:14,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:43:14,315 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141341319] [2022-12-13 19:43:14,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:43:14,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:43:14,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:43:14,328 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:43:14,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:43:14,353 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:43:14,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:43:14,353 INFO L85 PathProgramCache]: Analyzing trace with hash 1725870294, now seen corresponding path program 1 times [2022-12-13 19:43:14,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:43:14,354 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121742981] [2022-12-13 19:43:14,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:43:14,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:43:14,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:43:14,357 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 19:43:14,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 19:43:14,361 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 19:43:14,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 19:43:14,361 INFO L85 PathProgramCache]: Analyzing trace with hash 891076992, now seen corresponding path program 1 times [2022-12-13 19:43:14,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 19:43:14,361 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052741988] [2022-12-13 19:43:14,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 19:43:14,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 19:43:14,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 19:43:14,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 19:43:14,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 19:43:14,394 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1052741988] [2022-12-13 19:43:14,394 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1052741988] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 19:43:14,394 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 19:43:14,394 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 19:43:14,395 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832525038] [2022-12-13 19:43:14,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 19:43:14,465 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 19:43:14,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 19:43:14,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 19:43:14,465 INFO L87 Difference]: Start difference. First operand 301049 states and 412981 transitions. cyclomatic complexity: 112036 Second operand has 3 states, 3 states have (on average 41.333333333333336) internal successors, (124), 3 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 19:43:15,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 19:43:15,891 INFO L93 Difference]: Finished difference Result 576984 states and 785871 transitions. [2022-12-13 19:43:15,891 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 576984 states and 785871 transitions. [2022-12-13 19:43:17,844 INFO L131 ngComponentsAnalysis]: Automaton has 152 accepting balls. 565288 [2022-12-13 19:43:18,900 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 576984 states to 576984 states and 785871 transitions. [2022-12-13 19:43:18,900 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 576984 [2022-12-13 19:43:19,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 576984 [2022-12-13 19:43:19,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 576984 states and 785871 transitions. [2022-12-13 19:43:19,223 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 19:43:19,223 INFO L218 hiAutomatonCegarLoop]: Abstraction has 576984 states and 785871 transitions. [2022-12-13 19:43:19,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 576984 states and 785871 transitions.