./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 20:32:11,285 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 20:32:11,286 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 20:32:11,299 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 20:32:11,299 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 20:32:11,300 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 20:32:11,300 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 20:32:11,302 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 20:32:11,303 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 20:32:11,303 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 20:32:11,304 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 20:32:11,305 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 20:32:11,305 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 20:32:11,305 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 20:32:11,306 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 20:32:11,307 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 20:32:11,308 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 20:32:11,308 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 20:32:11,309 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 20:32:11,310 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 20:32:11,311 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 20:32:11,312 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 20:32:11,313 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 20:32:11,313 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 20:32:11,316 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 20:32:11,316 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 20:32:11,316 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 20:32:11,317 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 20:32:11,317 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 20:32:11,318 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 20:32:11,318 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 20:32:11,318 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 20:32:11,319 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 20:32:11,319 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 20:32:11,320 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 20:32:11,320 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 20:32:11,321 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 20:32:11,321 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 20:32:11,321 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 20:32:11,322 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 20:32:11,322 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 20:32:11,323 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 20:32:11,337 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 20:32:11,337 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 20:32:11,337 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 20:32:11,337 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 20:32:11,338 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 20:32:11,338 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 20:32:11,338 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 20:32:11,339 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 20:32:11,339 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 20:32:11,339 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 20:32:11,339 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 20:32:11,339 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 20:32:11,339 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 20:32:11,339 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 20:32:11,339 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 20:32:11,339 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 20:32:11,340 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 20:32:11,340 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 20:32:11,340 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 20:32:11,340 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 20:32:11,340 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 20:32:11,340 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 20:32:11,340 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 20:32:11,340 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 20:32:11,340 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 20:32:11,341 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 20:32:11,341 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 20:32:11,341 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 20:32:11,341 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 20:32:11,341 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 20:32:11,341 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 20:32:11,342 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 20:32:11,342 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9 [2022-12-13 20:32:11,517 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 20:32:11,534 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 20:32:11,536 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 20:32:11,537 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 20:32:11,538 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 20:32:11,538 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c [2022-12-13 20:32:14,223 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 20:32:14,394 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 20:32:14,395 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/sv-benchmarks/c/systemc/token_ring.09.cil-2.c [2022-12-13 20:32:14,403 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8/data/73575acbd/7acbbd2bd7a54d798d3f15bac6a6bc05/FLAG2a0ef65a1 [2022-12-13 20:32:14,413 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8/data/73575acbd/7acbbd2bd7a54d798d3f15bac6a6bc05 [2022-12-13 20:32:14,415 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 20:32:14,416 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 20:32:14,417 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 20:32:14,417 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 20:32:14,419 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 20:32:14,420 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 08:32:14" (1/1) ... [2022-12-13 20:32:14,420 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7b6f67aa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14, skipping insertion in model container [2022-12-13 20:32:14,421 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 08:32:14" (1/1) ... [2022-12-13 20:32:14,426 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 20:32:14,456 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 20:32:14,554 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/sv-benchmarks/c/systemc/token_ring.09.cil-2.c[671,684] [2022-12-13 20:32:14,620 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 20:32:14,630 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 20:32:14,639 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/sv-benchmarks/c/systemc/token_ring.09.cil-2.c[671,684] [2022-12-13 20:32:14,677 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 20:32:14,690 INFO L208 MainTranslator]: Completed translation [2022-12-13 20:32:14,690 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14 WrapperNode [2022-12-13 20:32:14,690 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 20:32:14,691 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 20:32:14,691 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 20:32:14,691 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 20:32:14,696 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14" (1/1) ... [2022-12-13 20:32:14,707 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14" (1/1) ... [2022-12-13 20:32:14,772 INFO L138 Inliner]: procedures = 46, calls = 59, calls flagged for inlining = 54, calls inlined = 183, statements flattened = 2769 [2022-12-13 20:32:14,773 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 20:32:14,773 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 20:32:14,774 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 20:32:14,774 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 20:32:14,783 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14" (1/1) ... [2022-12-13 20:32:14,783 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14" (1/1) ... [2022-12-13 20:32:14,793 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14" (1/1) ... [2022-12-13 20:32:14,793 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14" (1/1) ... [2022-12-13 20:32:14,820 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14" (1/1) ... [2022-12-13 20:32:14,842 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14" (1/1) ... [2022-12-13 20:32:14,846 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14" (1/1) ... [2022-12-13 20:32:14,851 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14" (1/1) ... [2022-12-13 20:32:14,859 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 20:32:14,859 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 20:32:14,860 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 20:32:14,860 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 20:32:14,860 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14" (1/1) ... [2022-12-13 20:32:14,865 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 20:32:14,874 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 20:32:14,884 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 20:32:14,886 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6a65a298-5e9a-4334-9346-d5d964272476/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 20:32:14,920 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 20:32:14,920 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 20:32:14,921 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 20:32:14,921 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 20:32:15,002 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 20:32:15,003 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 20:32:16,186 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 20:32:16,198 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 20:32:16,198 INFO L300 CfgBuilder]: Removed 12 assume(true) statements. [2022-12-13 20:32:16,201 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 08:32:16 BoogieIcfgContainer [2022-12-13 20:32:16,201 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 20:32:16,201 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 20:32:16,201 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 20:32:16,204 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 20:32:16,205 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:32:16,205 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 08:32:14" (1/3) ... [2022-12-13 20:32:16,206 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1cb1b872 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 08:32:16, skipping insertion in model container [2022-12-13 20:32:16,206 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:32:16,206 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:32:14" (2/3) ... [2022-12-13 20:32:16,206 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1cb1b872 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 08:32:16, skipping insertion in model container [2022-12-13 20:32:16,206 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:32:16,206 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 08:32:16" (3/3) ... [2022-12-13 20:32:16,207 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-2.c [2022-12-13 20:32:16,265 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 20:32:16,265 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 20:32:16,265 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 20:32:16,266 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 20:32:16,266 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 20:32:16,266 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 20:32:16,266 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 20:32:16,266 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 20:32:16,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1183 states, 1182 states have (on average 1.5109983079526226) internal successors, (1786), 1182 states have internal predecessors, (1786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:16,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1052 [2022-12-13 20:32:16,309 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:16,309 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:16,319 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:16,319 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:16,319 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 20:32:16,321 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1183 states, 1182 states have (on average 1.5109983079526226) internal successors, (1786), 1182 states have internal predecessors, (1786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:16,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1052 [2022-12-13 20:32:16,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:16,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:16,333 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:16,333 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:16,339 INFO L748 eck$LassoCheckResult]: Stem: 178#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1086#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 874#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1084#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 516#L670true assume !(1 == ~m_i~0);~m_st~0 := 2; 300#L670-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 833#L675-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 918#L680-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1025#L685-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 898#L690-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1171#L695-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 392#L700-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 381#L705-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 533#L710-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 251#L715-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 772#L951true assume !(0 == ~M_E~0); 111#L951-2true assume !(0 == ~T1_E~0); 191#L956-1true assume !(0 == ~T2_E~0); 1140#L961-1true assume !(0 == ~T3_E~0); 532#L966-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 650#L971-1true assume !(0 == ~T5_E~0); 1075#L976-1true assume !(0 == ~T6_E~0); 625#L981-1true assume !(0 == ~T7_E~0); 417#L986-1true assume !(0 == ~T8_E~0); 220#L991-1true assume !(0 == ~T9_E~0); 1115#L996-1true assume !(0 == ~E_M~0); 997#L1001-1true assume !(0 == ~E_1~0); 580#L1006-1true assume 0 == ~E_2~0;~E_2~0 := 1; 919#L1011-1true assume !(0 == ~E_3~0); 954#L1016-1true assume !(0 == ~E_4~0); 1088#L1021-1true assume !(0 == ~E_5~0); 17#L1026-1true assume !(0 == ~E_6~0); 1150#L1031-1true assume !(0 == ~E_7~0); 540#L1036-1true assume !(0 == ~E_8~0); 537#L1041-1true assume !(0 == ~E_9~0); 845#L1046-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1077#L472true assume 1 == ~m_pc~0; 1033#L473true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 563#L483true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 747#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 573#L1179true assume !(0 != activate_threads_~tmp~1#1); 21#L1179-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 890#L491true assume 1 == ~t1_pc~0; 579#L492true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 637#L502true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9#L1187true assume !(0 != activate_threads_~tmp___0~0#1); 18#L1187-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 827#L510true assume !(1 == ~t2_pc~0); 4#L510-2true is_transmit2_triggered_~__retres1~2#1 := 0; 994#L521true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1149#L1195true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 136#L1195-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 423#L529true assume 1 == ~t3_pc~0; 356#L530true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 762#L540true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1067#L1203true assume !(0 != activate_threads_~tmp___2~0#1); 99#L1203-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1116#L548true assume !(1 == ~t4_pc~0); 310#L548-2true is_transmit4_triggered_~__retres1~4#1 := 0; 197#L559true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66#L1211true assume !(0 != activate_threads_~tmp___3~0#1); 635#L1211-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43#L567true assume 1 == ~t5_pc~0; 886#L568true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1091#L578true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 749#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1023#L1219true assume !(0 != activate_threads_~tmp___4~0#1); 824#L1219-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 104#L586true assume !(1 == ~t6_pc~0); 137#L586-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1020#L597true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 285#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1175#L1227true assume !(0 != activate_threads_~tmp___5~0#1); 817#L1227-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1113#L605true assume 1 == ~t7_pc~0; 754#L606true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 565#L616true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1106#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1098#L1235true assume !(0 != activate_threads_~tmp___6~0#1); 1087#L1235-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 509#L624true assume !(1 == ~t8_pc~0); 1052#L624-2true is_transmit8_triggered_~__retres1~8#1 := 0; 612#L635true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 675#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 783#L1243true assume !(0 != activate_threads_~tmp___7~0#1); 1158#L1243-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28#L643true assume 1 == ~t9_pc~0; 853#L644true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 708#L654true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 331#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 223#L1251true assume !(0 != activate_threads_~tmp___8~0#1); 1112#L1251-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126#L1059true assume !(1 == ~M_E~0); 1178#L1059-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 208#L1064-1true assume !(1 == ~T2_E~0); 717#L1069-1true assume !(1 == ~T3_E~0); 1074#L1074-1true assume !(1 == ~T4_E~0); 779#L1079-1true assume !(1 == ~T5_E~0); 753#L1084-1true assume !(1 == ~T6_E~0); 927#L1089-1true assume !(1 == ~T7_E~0); 808#L1094-1true assume !(1 == ~T8_E~0); 445#L1099-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 943#L1104-1true assume !(1 == ~E_M~0); 616#L1109-1true assume !(1 == ~E_1~0); 294#L1114-1true assume !(1 == ~E_2~0); 1120#L1119-1true assume !(1 == ~E_3~0); 339#L1124-1true assume !(1 == ~E_4~0); 26#L1129-1true assume !(1 == ~E_5~0); 519#L1134-1true assume !(1 == ~E_6~0); 189#L1139-1true assume 1 == ~E_7~0;~E_7~0 := 2; 306#L1144-1true assume !(1 == ~E_8~0); 1162#L1149-1true assume !(1 == ~E_9~0); 107#L1154-1true assume { :end_inline_reset_delta_events } true; 171#L1440-2true [2022-12-13 20:32:16,341 INFO L750 eck$LassoCheckResult]: Loop: 171#L1440-2true assume !false; 979#L1441true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 846#L926true assume false; 681#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 452#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 242#L951-3true assume !(0 == ~M_E~0); 1151#L951-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 664#L956-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 511#L961-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 327#L966-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 938#L971-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 557#L976-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 37#L981-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 233#L986-3true assume !(0 == ~T8_E~0); 27#L991-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 644#L996-3true assume 0 == ~E_M~0;~E_M~0 := 1; 776#L1001-3true assume 0 == ~E_1~0;~E_1~0 := 1; 305#L1006-3true assume 0 == ~E_2~0;~E_2~0 := 1; 672#L1011-3true assume 0 == ~E_3~0;~E_3~0 := 1; 915#L1016-3true assume 0 == ~E_4~0;~E_4~0 := 1; 726#L1021-3true assume 0 == ~E_5~0;~E_5~0 := 1; 456#L1026-3true assume !(0 == ~E_6~0); 1069#L1031-3true assume 0 == ~E_7~0;~E_7~0 := 1; 641#L1036-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1126#L1041-3true assume 0 == ~E_9~0;~E_9~0 := 1; 712#L1046-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 662#L472-33true assume 1 == ~m_pc~0; 786#L473-11true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 924#L483-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 697#is_master_triggered_returnLabel#12true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 669#L1179-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 334#L1179-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1055#L491-33true assume !(1 == ~t1_pc~0); 51#L491-35true is_transmit1_triggered_~__retres1~1#1 := 0; 974#L502-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1070#is_transmit1_triggered_returnLabel#12true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1013#L1187-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1073#L1187-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 620#L510-33true assume 1 == ~t2_pc~0; 673#L511-11true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 999#L521-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 653#is_transmit2_triggered_returnLabel#12true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 732#L1195-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2#L1195-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 150#L529-33true assume 1 == ~t3_pc~0; 13#L530-11true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 141#L540-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85#is_transmit3_triggered_returnLabel#12true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1021#L1203-33true assume !(0 != activate_threads_~tmp___2~0#1); 58#L1203-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 180#L548-33true assume 1 == ~t4_pc~0; 252#L549-11true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 587#L559-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 932#is_transmit4_triggered_returnLabel#12true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 277#L1211-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 146#L1211-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 929#L567-33true assume !(1 == ~t5_pc~0); 206#L567-35true is_transmit5_triggered_~__retres1~5#1 := 0; 362#L578-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1019#is_transmit5_triggered_returnLabel#12true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1040#L1219-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1127#L1219-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 531#L586-33true assume !(1 == ~t6_pc~0); 214#L586-35true is_transmit6_triggered_~__retres1~6#1 := 0; 567#L597-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 374#is_transmit6_triggered_returnLabel#12true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1146#L1227-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 156#L1227-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 257#L605-33true assume 1 == ~t7_pc~0; 1179#L606-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 122#L616-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 768#is_transmit7_triggered_returnLabel#12true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1117#L1235-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 63#L1235-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 140#L624-33true assume 1 == ~t8_pc~0; 581#L625-11true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1049#L635-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 510#is_transmit8_triggered_returnLabel#12true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 266#L1243-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1163#L1243-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 123#L643-33true assume 1 == ~t9_pc~0; 534#L644-11true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 478#L654-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 656#is_transmit9_triggered_returnLabel#12true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 443#L1251-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 802#L1251-35true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59#L1059-3true assume 1 == ~M_E~0;~M_E~0 := 2; 347#L1059-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1173#L1064-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 389#L1069-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 626#L1074-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 878#L1079-3true assume !(1 == ~T5_E~0); 541#L1084-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 477#L1089-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 590#L1094-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 410#L1099-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 646#L1104-3true assume 1 == ~E_M~0;~E_M~0 := 2; 950#L1109-3true assume 1 == ~E_1~0;~E_1~0 := 2; 634#L1114-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1041#L1119-3true assume !(1 == ~E_3~0); 1172#L1124-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1071#L1129-3true assume 1 == ~E_5~0;~E_5~0 := 2; 212#L1134-3true assume 1 == ~E_6~0;~E_6~0 := 2; 494#L1139-3true assume 1 == ~E_7~0;~E_7~0 := 2; 323#L1144-3true assume 1 == ~E_8~0;~E_8~0 := 2; 446#L1149-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1166#L1154-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1104#L728-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 744#L780-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 264#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 12#L1459true assume !(0 == start_simulation_~tmp~3#1); 728#L1459-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 911#L728-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 547#L780-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 29#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 239#L1414true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 350#L1421true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 467#stop_simulation_returnLabel#1true start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 724#L1472true assume !(0 != start_simulation_~tmp___0~1#1); 171#L1440-2true [2022-12-13 20:32:16,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:16,345 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times [2022-12-13 20:32:16,352 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:16,352 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868415964] [2022-12-13 20:32:16,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:16,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:16,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:16,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:16,533 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:16,533 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868415964] [2022-12-13 20:32:16,534 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [868415964] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:16,534 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:16,534 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:16,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141677831] [2022-12-13 20:32:16,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:16,540 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:16,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:16,542 INFO L85 PathProgramCache]: Analyzing trace with hash -710473320, now seen corresponding path program 1 times [2022-12-13 20:32:16,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:16,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742934260] [2022-12-13 20:32:16,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:16,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:16,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:16,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:16,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:16,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [742934260] [2022-12-13 20:32:16,580 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [742934260] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:16,580 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:16,581 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:32:16,581 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047710362] [2022-12-13 20:32:16,581 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:16,582 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:16,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:16,606 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:16,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:16,610 INFO L87 Difference]: Start difference. First operand has 1183 states, 1182 states have (on average 1.5109983079526226) internal successors, (1786), 1182 states have internal predecessors, (1786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:16,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:16,670 INFO L93 Difference]: Finished difference Result 1181 states and 1757 transitions. [2022-12-13 20:32:16,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1181 states and 1757 transitions. [2022-12-13 20:32:16,677 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:16,685 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1181 states to 1175 states and 1751 transitions. [2022-12-13 20:32:16,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-12-13 20:32:16,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-12-13 20:32:16,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1751 transitions. [2022-12-13 20:32:16,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:16,707 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1751 transitions. [2022-12-13 20:32:16,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1751 transitions. [2022-12-13 20:32:16,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-12-13 20:32:16,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.490212765957447) internal successors, (1751), 1174 states have internal predecessors, (1751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:16,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1751 transitions. [2022-12-13 20:32:16,755 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1751 transitions. [2022-12-13 20:32:16,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:16,759 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1751 transitions. [2022-12-13 20:32:16,759 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 20:32:16,759 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1751 transitions. [2022-12-13 20:32:16,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:16,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:16,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:16,765 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:16,765 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:16,766 INFO L748 eck$LassoCheckResult]: Stem: 2743#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2744#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3486#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3487#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3210#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 2935#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2936#L675-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3465#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3499#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3492#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3493#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3064#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3051#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3052#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2862#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2863#L951 assume !(0 == ~M_E~0); 2613#L951-2 assume !(0 == ~T1_E~0); 2614#L956-1 assume !(0 == ~T2_E~0); 2762#L961-1 assume !(0 == ~T3_E~0); 3229#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3230#L971-1 assume !(0 == ~T5_E~0); 3352#L976-1 assume !(0 == ~T6_E~0); 3327#L981-1 assume !(0 == ~T7_E~0); 3100#L986-1 assume !(0 == ~T8_E~0); 2812#L991-1 assume !(0 == ~T9_E~0); 2813#L996-1 assume !(0 == ~E_M~0); 3520#L1001-1 assume !(0 == ~E_1~0); 3280#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3281#L1011-1 assume !(0 == ~E_3~0); 3500#L1016-1 assume !(0 == ~E_4~0); 3509#L1021-1 assume !(0 == ~E_5~0); 2409#L1026-1 assume !(0 == ~E_6~0); 2410#L1031-1 assume !(0 == ~E_7~0); 3236#L1036-1 assume !(0 == ~E_8~0); 3232#L1041-1 assume !(0 == ~E_9~0); 3233#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3472#L472 assume 1 == ~m_pc~0; 3537#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3261#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3262#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3270#L1179 assume !(0 != activate_threads_~tmp~1#1); 2417#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2418#L491 assume 1 == ~t1_pc~0; 3279#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2907#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2440#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2389#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 2390#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2413#L510 assume !(1 == ~t2_pc~0); 2378#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2379#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2927#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2928#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2666#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2667#L529 assume 1 == ~t3_pc~0; 3013#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3014#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2387#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2388#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 2589#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2590#L548 assume !(1 == ~t4_pc~0); 2479#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2478#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2554#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2525#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 2526#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2466#L567 assume 1 == ~t5_pc~0; 2467#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2527#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3420#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3421#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 3460#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2600#L586 assume !(1 == ~t6_pc~0); 2601#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2668#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2912#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2913#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 3454#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3455#L605 assume 1 == ~t7_pc~0; 3428#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3084#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3263#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3546#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 3545#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3204#L624 assume !(1 == ~t8_pc~0); 2661#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2660#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3312#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3371#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 3438#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2432#L643 assume 1 == ~t9_pc~0; 2433#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3392#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2978#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2819#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 2820#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2645#L1059 assume !(1 == ~M_E~0); 2646#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2790#L1064-1 assume !(1 == ~T2_E~0); 2791#L1069-1 assume !(1 == ~T3_E~0); 3399#L1074-1 assume !(1 == ~T4_E~0); 3436#L1079-1 assume !(1 == ~T5_E~0); 3426#L1084-1 assume !(1 == ~T6_E~0); 3427#L1089-1 assume !(1 == ~T7_E~0); 3450#L1094-1 assume !(1 == ~T8_E~0); 3138#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3139#L1104-1 assume !(1 == ~E_M~0); 3314#L1109-1 assume !(1 == ~E_1~0); 2929#L1114-1 assume !(1 == ~E_2~0); 2930#L1119-1 assume !(1 == ~E_3~0); 2988#L1124-1 assume !(1 == ~E_4~0); 2428#L1129-1 assume !(1 == ~E_5~0); 2429#L1134-1 assume !(1 == ~E_6~0); 2758#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2759#L1144-1 assume !(1 == ~E_8~0); 2945#L1149-1 assume !(1 == ~E_9~0); 2606#L1154-1 assume { :end_inline_reset_delta_events } true; 2607#L1440-2 [2022-12-13 20:32:16,766 INFO L750 eck$LassoCheckResult]: Loop: 2607#L1440-2 assume !false; 2728#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2831#L926 assume !false; 2990#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2991#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2689#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2690#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2697#L795 assume !(0 != eval_~tmp~0#1); 2698#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3147#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2846#L951-3 assume !(0 == ~M_E~0); 2847#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3362#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3206#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2973#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2974#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3255#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2452#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2453#L986-3 assume !(0 == ~T8_E~0); 2430#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2431#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3349#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2941#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2942#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3370#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3406#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3150#L1026-3 assume !(0 == ~E_6~0); 3151#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3343#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3344#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3397#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3360#L472-33 assume 1 == ~m_pc~0; 3361#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2552#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3388#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3367#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2981#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2982#L491-33 assume 1 == ~t1_pc~0; 3271#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2488#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3515#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3529#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3530#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3321#L510-33 assume !(1 == ~t2_pc~0); 3315#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 3316#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3354#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3355#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2373#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2374#L529-33 assume !(1 == ~t3_pc~0); 2400#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2399#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2564#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2565#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 2504#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2505#L548-33 assume 1 == ~t4_pc~0; 2746#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2864#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3287#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2901#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2684#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2685#L567-33 assume 1 == ~t5_pc~0; 3120#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2786#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3024#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3534#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3540#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3228#L586-33 assume !(1 == ~t6_pc~0); 2802#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2803#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3040#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3041#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2701#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2702#L605-33 assume !(1 == ~t7_pc~0); 2868#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2630#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2631#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3431#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2516#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2517#L624-33 assume !(1 == ~t8_pc~0); 2672#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 2678#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3205#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2883#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2884#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2632#L643-33 assume 1 == ~t9_pc~0; 2633#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2715#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3177#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3134#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3135#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2506#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2507#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3002#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3060#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3061#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3328#L1079-3 assume !(1 == ~T5_E~0); 3237#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3175#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3176#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3093#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3094#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3350#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3334#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3335#L1119-3 assume !(1 == ~E_3~0); 3539#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3544#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2797#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2798#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2959#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2960#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3140#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3547#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2509#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2879#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2395#L1459 assume !(0 == start_simulation_~tmp~3#1); 2397#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3407#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2687#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2435#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2436#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2843#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3003#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3162#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 2607#L1440-2 [2022-12-13 20:32:16,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:16,767 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times [2022-12-13 20:32:16,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:16,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971956821] [2022-12-13 20:32:16,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:16,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:16,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:16,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:16,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:16,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [971956821] [2022-12-13 20:32:16,823 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [971956821] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:16,823 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:16,823 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:16,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [603502026] [2022-12-13 20:32:16,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:16,824 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:16,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:16,824 INFO L85 PathProgramCache]: Analyzing trace with hash 1730550151, now seen corresponding path program 1 times [2022-12-13 20:32:16,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:16,825 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [518776997] [2022-12-13 20:32:16,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:16,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:16,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:16,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:16,892 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:16,893 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [518776997] [2022-12-13 20:32:16,893 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [518776997] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:16,893 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:16,893 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:16,893 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [826698609] [2022-12-13 20:32:16,893 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:16,894 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:16,894 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:16,894 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:16,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:16,895 INFO L87 Difference]: Start difference. First operand 1175 states and 1751 transitions. cyclomatic complexity: 577 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:16,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:16,916 INFO L93 Difference]: Finished difference Result 1175 states and 1750 transitions. [2022-12-13 20:32:16,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1750 transitions. [2022-12-13 20:32:16,920 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:16,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1750 transitions. [2022-12-13 20:32:16,924 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-12-13 20:32:16,924 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-12-13 20:32:16,924 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1750 transitions. [2022-12-13 20:32:16,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:16,926 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1750 transitions. [2022-12-13 20:32:16,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1750 transitions. [2022-12-13 20:32:16,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-12-13 20:32:16,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4893617021276595) internal successors, (1750), 1174 states have internal predecessors, (1750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:16,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1750 transitions. [2022-12-13 20:32:16,941 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1750 transitions. [2022-12-13 20:32:16,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:16,942 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1750 transitions. [2022-12-13 20:32:16,942 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 20:32:16,942 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1750 transitions. [2022-12-13 20:32:16,946 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:16,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:16,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:16,948 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:16,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:16,948 INFO L748 eck$LassoCheckResult]: Stem: 5102#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5103#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5843#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5844#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5567#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 5292#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5293#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5822#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5856#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5849#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5850#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5421#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5408#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5409#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5220#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5221#L951 assume !(0 == ~M_E~0); 4970#L951-2 assume !(0 == ~T1_E~0); 4971#L956-1 assume !(0 == ~T2_E~0); 5119#L961-1 assume !(0 == ~T3_E~0); 5586#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5587#L971-1 assume !(0 == ~T5_E~0); 5709#L976-1 assume !(0 == ~T6_E~0); 5684#L981-1 assume !(0 == ~T7_E~0); 5460#L986-1 assume !(0 == ~T8_E~0); 5169#L991-1 assume !(0 == ~T9_E~0); 5170#L996-1 assume !(0 == ~E_M~0); 5878#L1001-1 assume !(0 == ~E_1~0); 5637#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5638#L1011-1 assume !(0 == ~E_3~0); 5857#L1016-1 assume !(0 == ~E_4~0); 5866#L1021-1 assume !(0 == ~E_5~0); 4766#L1026-1 assume !(0 == ~E_6~0); 4767#L1031-1 assume !(0 == ~E_7~0); 5593#L1036-1 assume !(0 == ~E_8~0); 5591#L1041-1 assume !(0 == ~E_9~0); 5592#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5829#L472 assume 1 == ~m_pc~0; 5894#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5618#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5619#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5627#L1179 assume !(0 != activate_threads_~tmp~1#1); 4774#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4775#L491 assume 1 == ~t1_pc~0; 5636#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5264#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4797#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4746#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 4747#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4770#L510 assume !(1 == ~t2_pc~0); 4735#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4736#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5284#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5285#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5023#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5024#L529 assume 1 == ~t3_pc~0; 5370#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5371#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4744#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4745#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 4946#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4947#L548 assume !(1 == ~t4_pc~0); 4836#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4835#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4911#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4882#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 4883#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4825#L567 assume 1 == ~t5_pc~0; 4826#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4884#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5777#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5778#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 5817#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4957#L586 assume !(1 == ~t6_pc~0); 4958#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5027#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5272#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5273#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 5811#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5812#L605 assume 1 == ~t7_pc~0; 5785#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5443#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5621#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5903#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 5902#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5561#L624 assume !(1 == ~t8_pc~0); 5018#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5017#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5669#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5728#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 5795#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4789#L643 assume 1 == ~t9_pc~0; 4790#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5749#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5335#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5176#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 5177#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5002#L1059 assume !(1 == ~M_E~0); 5003#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5147#L1064-1 assume !(1 == ~T2_E~0); 5148#L1069-1 assume !(1 == ~T3_E~0); 5756#L1074-1 assume !(1 == ~T4_E~0); 5794#L1079-1 assume !(1 == ~T5_E~0); 5783#L1084-1 assume !(1 == ~T6_E~0); 5784#L1089-1 assume !(1 == ~T7_E~0); 5807#L1094-1 assume !(1 == ~T8_E~0); 5495#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5496#L1104-1 assume !(1 == ~E_M~0); 5673#L1109-1 assume !(1 == ~E_1~0); 5286#L1114-1 assume !(1 == ~E_2~0); 5287#L1119-1 assume !(1 == ~E_3~0); 5345#L1124-1 assume !(1 == ~E_4~0); 4785#L1129-1 assume !(1 == ~E_5~0); 4786#L1134-1 assume !(1 == ~E_6~0); 5115#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5116#L1144-1 assume !(1 == ~E_8~0); 5302#L1149-1 assume !(1 == ~E_9~0); 4963#L1154-1 assume { :end_inline_reset_delta_events } true; 4964#L1440-2 [2022-12-13 20:32:16,949 INFO L750 eck$LassoCheckResult]: Loop: 4964#L1440-2 assume !false; 5087#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5190#L926 assume !false; 5347#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5348#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5046#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5047#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5054#L795 assume !(0 != eval_~tmp~0#1); 5055#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5504#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5203#L951-3 assume !(0 == ~M_E~0); 5204#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5719#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5563#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5331#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5332#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5612#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4809#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4810#L986-3 assume !(0 == ~T8_E~0); 4787#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4788#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5706#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5298#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5299#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5727#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5763#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5508#L1026-3 assume !(0 == ~E_6~0); 5509#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5700#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5701#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5754#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5717#L472-33 assume 1 == ~m_pc~0; 5718#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4909#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5745#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5724#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5338#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5339#L491-33 assume 1 == ~t1_pc~0; 5628#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4845#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5872#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5886#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5887#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5674#L510-33 assume !(1 == ~t2_pc~0); 5671#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 5672#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5711#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5712#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4730#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4731#L529-33 assume 1 == ~t3_pc~0; 4755#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4756#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4919#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4920#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 4861#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4862#L548-33 assume 1 == ~t4_pc~0; 5098#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5219#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5644#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5258#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5041#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5042#L567-33 assume 1 == ~t5_pc~0; 5476#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5143#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5380#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5891#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5896#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5585#L586-33 assume !(1 == ~t6_pc~0); 5160#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5161#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5397#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5398#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5060#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5061#L605-33 assume !(1 == ~t7_pc~0); 5228#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 4987#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4988#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5788#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4873#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4874#L624-33 assume 1 == ~t8_pc~0; 5030#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5038#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5562#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5240#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5241#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4989#L643-33 assume 1 == ~t9_pc~0; 4990#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5072#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5534#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5491#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5492#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4863#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4864#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5359#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5417#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5418#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5685#L1079-3 assume !(1 == ~T5_E~0); 5594#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5532#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5533#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5450#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5451#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5707#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5691#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5692#L1119-3 assume !(1 == ~E_3~0); 5897#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5901#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5154#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5155#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5319#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5320#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5497#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5904#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4866#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5238#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 4752#L1459 assume !(0 == start_simulation_~tmp~3#1); 4754#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5764#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5044#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4792#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 4793#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5200#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5361#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5519#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 4964#L1440-2 [2022-12-13 20:32:16,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:16,949 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times [2022-12-13 20:32:16,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:16,950 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021093207] [2022-12-13 20:32:16,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:16,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:16,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:16,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:16,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:16,985 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021093207] [2022-12-13 20:32:16,985 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021093207] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:16,986 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:16,986 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:16,986 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784725663] [2022-12-13 20:32:16,986 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:16,986 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:16,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:16,987 INFO L85 PathProgramCache]: Analyzing trace with hash -1832038971, now seen corresponding path program 1 times [2022-12-13 20:32:16,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:16,987 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875744765] [2022-12-13 20:32:16,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:16,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:16,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:17,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:17,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:17,047 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1875744765] [2022-12-13 20:32:17,047 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1875744765] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:17,047 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:17,048 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:17,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [374009042] [2022-12-13 20:32:17,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:17,048 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:17,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:17,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:17,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:17,049 INFO L87 Difference]: Start difference. First operand 1175 states and 1750 transitions. cyclomatic complexity: 576 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:17,070 INFO L93 Difference]: Finished difference Result 1175 states and 1749 transitions. [2022-12-13 20:32:17,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1749 transitions. [2022-12-13 20:32:17,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:17,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1749 transitions. [2022-12-13 20:32:17,077 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-12-13 20:32:17,078 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-12-13 20:32:17,078 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1749 transitions. [2022-12-13 20:32:17,079 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:17,079 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1749 transitions. [2022-12-13 20:32:17,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1749 transitions. [2022-12-13 20:32:17,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-12-13 20:32:17,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4885106382978723) internal successors, (1749), 1174 states have internal predecessors, (1749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1749 transitions. [2022-12-13 20:32:17,093 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1749 transitions. [2022-12-13 20:32:17,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:17,094 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1749 transitions. [2022-12-13 20:32:17,094 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 20:32:17,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1749 transitions. [2022-12-13 20:32:17,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:17,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:17,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:17,098 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:17,098 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:17,099 INFO L748 eck$LassoCheckResult]: Stem: 7460#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7461#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 8200#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8201#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7924#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 7651#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7652#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8179#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8213#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8206#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8207#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7778#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7765#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7766#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7577#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7578#L951 assume !(0 == ~M_E~0); 7329#L951-2 assume !(0 == ~T1_E~0); 7330#L956-1 assume !(0 == ~T2_E~0); 7476#L961-1 assume !(0 == ~T3_E~0); 7943#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7944#L971-1 assume !(0 == ~T5_E~0); 8066#L976-1 assume !(0 == ~T6_E~0); 8041#L981-1 assume !(0 == ~T7_E~0); 7817#L986-1 assume !(0 == ~T8_E~0); 7526#L991-1 assume !(0 == ~T9_E~0); 7527#L996-1 assume !(0 == ~E_M~0); 8235#L1001-1 assume !(0 == ~E_1~0); 7994#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7995#L1011-1 assume !(0 == ~E_3~0); 8215#L1016-1 assume !(0 == ~E_4~0); 8223#L1021-1 assume !(0 == ~E_5~0); 7123#L1026-1 assume !(0 == ~E_6~0); 7124#L1031-1 assume !(0 == ~E_7~0); 7950#L1036-1 assume !(0 == ~E_8~0); 7948#L1041-1 assume !(0 == ~E_9~0); 7949#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8186#L472 assume 1 == ~m_pc~0; 8251#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7975#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7976#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7984#L1179 assume !(0 != activate_threads_~tmp~1#1); 7131#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7132#L491 assume 1 == ~t1_pc~0; 7993#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7623#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7154#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7103#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 7104#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7127#L510 assume !(1 == ~t2_pc~0); 7092#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7093#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7641#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7642#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7380#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7381#L529 assume 1 == ~t3_pc~0; 7727#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7728#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7101#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7102#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 7303#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7304#L548 assume !(1 == ~t4_pc~0); 7195#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7194#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7268#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7239#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 7240#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7185#L567 assume 1 == ~t5_pc~0; 7186#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7241#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8134#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8135#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 8174#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7314#L586 assume !(1 == ~t6_pc~0); 7315#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7384#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7629#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7630#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 8168#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8169#L605 assume 1 == ~t7_pc~0; 8142#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7803#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7978#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8260#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 8259#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7918#L624 assume !(1 == ~t8_pc~0); 7375#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7374#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8026#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8086#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 8152#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7146#L643 assume 1 == ~t9_pc~0; 7147#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8106#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7692#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7533#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 7534#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7359#L1059 assume !(1 == ~M_E~0); 7360#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7504#L1064-1 assume !(1 == ~T2_E~0); 7505#L1069-1 assume !(1 == ~T3_E~0); 8113#L1074-1 assume !(1 == ~T4_E~0); 8151#L1079-1 assume !(1 == ~T5_E~0); 8140#L1084-1 assume !(1 == ~T6_E~0); 8141#L1089-1 assume !(1 == ~T7_E~0); 8164#L1094-1 assume !(1 == ~T8_E~0); 7852#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7853#L1104-1 assume !(1 == ~E_M~0); 8030#L1109-1 assume !(1 == ~E_1~0); 7643#L1114-1 assume !(1 == ~E_2~0); 7644#L1119-1 assume !(1 == ~E_3~0); 7703#L1124-1 assume !(1 == ~E_4~0); 7144#L1129-1 assume !(1 == ~E_5~0); 7145#L1134-1 assume !(1 == ~E_6~0); 7474#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7475#L1144-1 assume !(1 == ~E_8~0); 7659#L1149-1 assume !(1 == ~E_9~0); 7320#L1154-1 assume { :end_inline_reset_delta_events } true; 7321#L1440-2 [2022-12-13 20:32:17,099 INFO L750 eck$LassoCheckResult]: Loop: 7321#L1440-2 assume !false; 7444#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7545#L926 assume !false; 7704#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7705#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7403#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7404#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7411#L795 assume !(0 != eval_~tmp~0#1); 7412#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7861#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7562#L951-3 assume !(0 == ~M_E~0); 7563#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8077#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7921#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7688#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7689#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7969#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7172#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7173#L986-3 assume !(0 == ~T8_E~0); 7142#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7143#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8063#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7655#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7656#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8084#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8120#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7864#L1026-3 assume !(0 == ~E_6~0); 7865#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8057#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8058#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8111#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8073#L472-33 assume 1 == ~m_pc~0; 8074#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7263#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8102#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8081#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7695#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7696#L491-33 assume 1 == ~t1_pc~0; 7985#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7202#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8229#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8243#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8244#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8034#L510-33 assume 1 == ~t2_pc~0; 8035#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8029#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8068#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8069#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7087#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7088#L529-33 assume 1 == ~t3_pc~0; 7112#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7113#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7278#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7279#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 7218#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7219#L548-33 assume 1 == ~t4_pc~0; 7456#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7576#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8001#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7615#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7398#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7399#L567-33 assume 1 == ~t5_pc~0; 7834#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7500#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7737#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8248#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8253#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7942#L586-33 assume 1 == ~t6_pc~0; 7908#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7518#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7755#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7756#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7417#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7418#L605-33 assume !(1 == ~t7_pc~0); 7585#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 7351#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7352#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8145#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7230#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7231#L624-33 assume 1 == ~t8_pc~0; 7387#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7395#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7919#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7597#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7598#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7353#L643-33 assume 1 == ~t9_pc~0; 7354#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7429#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7891#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7848#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7849#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7220#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7221#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7716#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7774#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7775#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8042#L1079-3 assume !(1 == ~T5_E~0); 7951#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7889#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7890#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7807#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7808#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8064#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8050#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8051#L1119-3 assume !(1 == ~E_3~0); 8254#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8258#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7511#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7512#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7678#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7679#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7854#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8261#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7223#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7595#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7109#L1459 assume !(0 == start_simulation_~tmp~3#1); 7111#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8121#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7401#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7149#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 7150#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7557#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7718#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 7876#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 7321#L1440-2 [2022-12-13 20:32:17,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:17,100 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times [2022-12-13 20:32:17,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:17,100 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854329193] [2022-12-13 20:32:17,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:17,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:17,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:17,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:17,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:17,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854329193] [2022-12-13 20:32:17,135 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [854329193] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:17,135 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:17,135 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:17,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [130525545] [2022-12-13 20:32:17,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:17,136 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:17,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:17,137 INFO L85 PathProgramCache]: Analyzing trace with hash 762667075, now seen corresponding path program 1 times [2022-12-13 20:32:17,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:17,137 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970372892] [2022-12-13 20:32:17,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:17,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:17,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:17,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:17,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:17,177 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970372892] [2022-12-13 20:32:17,177 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1970372892] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:17,177 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:17,177 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:17,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406804009] [2022-12-13 20:32:17,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:17,178 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:17,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:17,178 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:17,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:17,179 INFO L87 Difference]: Start difference. First operand 1175 states and 1749 transitions. cyclomatic complexity: 575 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:17,195 INFO L93 Difference]: Finished difference Result 1175 states and 1748 transitions. [2022-12-13 20:32:17,195 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1748 transitions. [2022-12-13 20:32:17,199 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:17,203 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1748 transitions. [2022-12-13 20:32:17,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-12-13 20:32:17,203 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-12-13 20:32:17,203 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1748 transitions. [2022-12-13 20:32:17,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:17,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1748 transitions. [2022-12-13 20:32:17,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1748 transitions. [2022-12-13 20:32:17,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-12-13 20:32:17,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4876595744680852) internal successors, (1748), 1174 states have internal predecessors, (1748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1748 transitions. [2022-12-13 20:32:17,218 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1748 transitions. [2022-12-13 20:32:17,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:17,219 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1748 transitions. [2022-12-13 20:32:17,219 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 20:32:17,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1748 transitions. [2022-12-13 20:32:17,222 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:17,222 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:17,222 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:17,223 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:17,223 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:17,224 INFO L748 eck$LassoCheckResult]: Stem: 9812#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 9813#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10555#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10556#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10281#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 10006#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10007#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10536#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10570#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10563#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10564#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10135#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10122#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10123#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9933#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9934#L951 assume !(0 == ~M_E~0); 9684#L951-2 assume !(0 == ~T1_E~0); 9685#L956-1 assume !(0 == ~T2_E~0); 9833#L961-1 assume !(0 == ~T3_E~0); 10300#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10301#L971-1 assume !(0 == ~T5_E~0); 10423#L976-1 assume !(0 == ~T6_E~0); 10398#L981-1 assume !(0 == ~T7_E~0); 10171#L986-1 assume !(0 == ~T8_E~0); 9883#L991-1 assume !(0 == ~T9_E~0); 9884#L996-1 assume !(0 == ~E_M~0); 10591#L1001-1 assume !(0 == ~E_1~0); 10351#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 10352#L1011-1 assume !(0 == ~E_3~0); 10571#L1016-1 assume !(0 == ~E_4~0); 10580#L1021-1 assume !(0 == ~E_5~0); 9480#L1026-1 assume !(0 == ~E_6~0); 9481#L1031-1 assume !(0 == ~E_7~0); 10307#L1036-1 assume !(0 == ~E_8~0); 10303#L1041-1 assume !(0 == ~E_9~0); 10304#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10543#L472 assume 1 == ~m_pc~0; 10608#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10332#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10333#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10341#L1179 assume !(0 != activate_threads_~tmp~1#1); 9488#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9489#L491 assume 1 == ~t1_pc~0; 10350#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9978#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9511#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9460#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 9461#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9482#L510 assume !(1 == ~t2_pc~0); 9449#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9450#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9998#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9999#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9737#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9738#L529 assume 1 == ~t3_pc~0; 10084#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10085#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9458#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9459#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 9660#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9661#L548 assume !(1 == ~t4_pc~0); 9550#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9549#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9625#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9594#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 9595#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9537#L567 assume 1 == ~t5_pc~0; 9538#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9596#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10491#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10492#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 10531#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9671#L586 assume !(1 == ~t6_pc~0); 9672#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9739#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9983#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9984#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 10525#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10526#L605 assume 1 == ~t7_pc~0; 10499#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10153#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10334#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10617#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 10616#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10275#L624 assume !(1 == ~t8_pc~0); 9732#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9731#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10383#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10442#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 10509#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9503#L643 assume 1 == ~t9_pc~0; 9504#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10463#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10047#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9888#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 9889#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9716#L1059 assume !(1 == ~M_E~0); 9717#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9861#L1064-1 assume !(1 == ~T2_E~0); 9862#L1069-1 assume !(1 == ~T3_E~0); 10470#L1074-1 assume !(1 == ~T4_E~0); 10507#L1079-1 assume !(1 == ~T5_E~0); 10497#L1084-1 assume !(1 == ~T6_E~0); 10498#L1089-1 assume !(1 == ~T7_E~0); 10521#L1094-1 assume !(1 == ~T8_E~0); 10209#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10210#L1104-1 assume !(1 == ~E_M~0); 10385#L1109-1 assume !(1 == ~E_1~0); 10000#L1114-1 assume !(1 == ~E_2~0); 10001#L1119-1 assume !(1 == ~E_3~0); 10059#L1124-1 assume !(1 == ~E_4~0); 9499#L1129-1 assume !(1 == ~E_5~0); 9500#L1134-1 assume !(1 == ~E_6~0); 9829#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9830#L1144-1 assume !(1 == ~E_8~0); 10014#L1149-1 assume !(1 == ~E_9~0); 9677#L1154-1 assume { :end_inline_reset_delta_events } true; 9678#L1440-2 [2022-12-13 20:32:17,224 INFO L750 eck$LassoCheckResult]: Loop: 9678#L1440-2 assume !false; 9799#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9902#L926 assume !false; 10061#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10062#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9757#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9758#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9767#L795 assume !(0 != eval_~tmp~0#1); 9768#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10218#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9917#L951-3 assume !(0 == ~M_E~0); 9918#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10433#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10277#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10041#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10042#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10326#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9520#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9521#L986-3 assume !(0 == ~T8_E~0); 9501#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9502#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10420#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10012#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10013#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10441#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10477#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10221#L1026-3 assume !(0 == ~E_6~0); 10222#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10414#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10415#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10468#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10431#L472-33 assume 1 == ~m_pc~0; 10432#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9623#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10459#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10438#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10052#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10053#L491-33 assume 1 == ~t1_pc~0; 10342#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9559#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10586#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10600#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10601#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10391#L510-33 assume !(1 == ~t2_pc~0); 10386#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 10387#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10425#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10426#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9444#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9445#L529-33 assume 1 == ~t3_pc~0; 9469#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9470#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9635#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9636#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 9575#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9576#L548-33 assume 1 == ~t4_pc~0; 9815#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9935#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10358#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9972#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9755#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9756#L567-33 assume !(1 == ~t5_pc~0); 9856#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 9857#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10094#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10605#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10610#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10299#L586-33 assume !(1 == ~t6_pc~0); 9874#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 9875#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10112#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10113#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9774#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9775#L605-33 assume !(1 == ~t7_pc~0); 9942#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 9708#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9709#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10502#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9587#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9588#L624-33 assume 1 == ~t8_pc~0; 9744#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9752#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10276#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9954#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9955#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9710#L643-33 assume !(1 == ~t9_pc~0); 9712#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 9786#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10248#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10205#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10206#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9577#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9578#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10073#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10132#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10133#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10399#L1079-3 assume !(1 == ~T5_E~0); 10308#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10246#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10247#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10164#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10165#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10421#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10407#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10408#L1119-3 assume !(1 == ~E_3~0); 10611#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10615#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9868#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9869#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10035#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10036#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10211#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10618#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9582#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9952#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 9466#L1459 assume !(0 == start_simulation_~tmp~3#1); 9468#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10478#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9760#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9506#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 9507#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9914#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10077#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 10236#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 9678#L1440-2 [2022-12-13 20:32:17,224 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:17,225 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times [2022-12-13 20:32:17,225 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:17,225 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901348298] [2022-12-13 20:32:17,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:17,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:17,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:17,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:17,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:17,269 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901348298] [2022-12-13 20:32:17,270 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [901348298] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:17,270 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:17,270 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:17,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55367436] [2022-12-13 20:32:17,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:17,271 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:17,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:17,271 INFO L85 PathProgramCache]: Analyzing trace with hash 2082928583, now seen corresponding path program 1 times [2022-12-13 20:32:17,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:17,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902055290] [2022-12-13 20:32:17,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:17,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:17,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:17,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:17,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:17,318 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902055290] [2022-12-13 20:32:17,318 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [902055290] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:17,318 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:17,318 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:17,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721375059] [2022-12-13 20:32:17,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:17,319 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:17,319 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:17,319 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:17,319 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:17,320 INFO L87 Difference]: Start difference. First operand 1175 states and 1748 transitions. cyclomatic complexity: 574 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:17,339 INFO L93 Difference]: Finished difference Result 1175 states and 1747 transitions. [2022-12-13 20:32:17,339 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1747 transitions. [2022-12-13 20:32:17,344 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:17,348 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1747 transitions. [2022-12-13 20:32:17,348 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-12-13 20:32:17,349 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-12-13 20:32:17,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1747 transitions. [2022-12-13 20:32:17,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:17,350 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1747 transitions. [2022-12-13 20:32:17,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1747 transitions. [2022-12-13 20:32:17,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-12-13 20:32:17,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4868085106382978) internal successors, (1747), 1174 states have internal predecessors, (1747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1747 transitions. [2022-12-13 20:32:17,366 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1747 transitions. [2022-12-13 20:32:17,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:17,366 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1747 transitions. [2022-12-13 20:32:17,367 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 20:32:17,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1747 transitions. [2022-12-13 20:32:17,370 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:17,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:17,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:17,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:17,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:17,371 INFO L748 eck$LassoCheckResult]: Stem: 12169#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12170#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12912#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12913#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12638#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 12363#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12364#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12893#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12927#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12920#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12921#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12492#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12479#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12480#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12290#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12291#L951 assume !(0 == ~M_E~0); 12041#L951-2 assume !(0 == ~T1_E~0); 12042#L956-1 assume !(0 == ~T2_E~0); 12190#L961-1 assume !(0 == ~T3_E~0); 12657#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12658#L971-1 assume !(0 == ~T5_E~0); 12780#L976-1 assume !(0 == ~T6_E~0); 12755#L981-1 assume !(0 == ~T7_E~0); 12528#L986-1 assume !(0 == ~T8_E~0); 12240#L991-1 assume !(0 == ~T9_E~0); 12241#L996-1 assume !(0 == ~E_M~0); 12948#L1001-1 assume !(0 == ~E_1~0); 12708#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12709#L1011-1 assume !(0 == ~E_3~0); 12928#L1016-1 assume !(0 == ~E_4~0); 12937#L1021-1 assume !(0 == ~E_5~0); 11837#L1026-1 assume !(0 == ~E_6~0); 11838#L1031-1 assume !(0 == ~E_7~0); 12664#L1036-1 assume !(0 == ~E_8~0); 12660#L1041-1 assume !(0 == ~E_9~0); 12661#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12900#L472 assume 1 == ~m_pc~0; 12965#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12689#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12690#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12698#L1179 assume !(0 != activate_threads_~tmp~1#1); 11845#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11846#L491 assume 1 == ~t1_pc~0; 12707#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12335#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11868#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11817#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 11818#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11839#L510 assume !(1 == ~t2_pc~0); 11806#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11807#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12355#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12356#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12094#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12095#L529 assume 1 == ~t3_pc~0; 12441#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12442#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11815#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11816#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 12017#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12018#L548 assume !(1 == ~t4_pc~0); 11907#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11906#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11982#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11951#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 11952#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11894#L567 assume 1 == ~t5_pc~0; 11895#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11953#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12848#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12849#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 12888#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12028#L586 assume !(1 == ~t6_pc~0); 12029#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12096#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12340#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12341#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 12882#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12883#L605 assume 1 == ~t7_pc~0; 12856#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12510#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12691#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12974#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 12973#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12632#L624 assume !(1 == ~t8_pc~0); 12089#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12088#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12740#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12799#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 12866#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11860#L643 assume 1 == ~t9_pc~0; 11861#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12820#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12404#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12245#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 12246#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12073#L1059 assume !(1 == ~M_E~0); 12074#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12218#L1064-1 assume !(1 == ~T2_E~0); 12219#L1069-1 assume !(1 == ~T3_E~0); 12827#L1074-1 assume !(1 == ~T4_E~0); 12864#L1079-1 assume !(1 == ~T5_E~0); 12854#L1084-1 assume !(1 == ~T6_E~0); 12855#L1089-1 assume !(1 == ~T7_E~0); 12878#L1094-1 assume !(1 == ~T8_E~0); 12566#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12567#L1104-1 assume !(1 == ~E_M~0); 12742#L1109-1 assume !(1 == ~E_1~0); 12357#L1114-1 assume !(1 == ~E_2~0); 12358#L1119-1 assume !(1 == ~E_3~0); 12416#L1124-1 assume !(1 == ~E_4~0); 11856#L1129-1 assume !(1 == ~E_5~0); 11857#L1134-1 assume !(1 == ~E_6~0); 12186#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12187#L1144-1 assume !(1 == ~E_8~0); 12371#L1149-1 assume !(1 == ~E_9~0); 12034#L1154-1 assume { :end_inline_reset_delta_events } true; 12035#L1440-2 [2022-12-13 20:32:17,372 INFO L750 eck$LassoCheckResult]: Loop: 12035#L1440-2 assume !false; 12156#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12259#L926 assume !false; 12418#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12419#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12114#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12115#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12124#L795 assume !(0 != eval_~tmp~0#1); 12125#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12575#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12274#L951-3 assume !(0 == ~M_E~0); 12275#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12790#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12634#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12398#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12399#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12683#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11877#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11878#L986-3 assume !(0 == ~T8_E~0); 11858#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11859#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12777#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12369#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12370#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12798#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12834#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12578#L1026-3 assume !(0 == ~E_6~0); 12579#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12771#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12772#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12825#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12788#L472-33 assume 1 == ~m_pc~0; 12789#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11980#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12816#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12795#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12409#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12410#L491-33 assume 1 == ~t1_pc~0; 12699#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11916#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12943#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12957#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12958#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12748#L510-33 assume !(1 == ~t2_pc~0); 12743#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 12744#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12782#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12783#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11801#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11802#L529-33 assume 1 == ~t3_pc~0; 11826#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11827#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11992#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11993#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 11932#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11933#L548-33 assume 1 == ~t4_pc~0; 12172#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12292#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12715#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12329#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12112#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12113#L567-33 assume 1 == ~t5_pc~0; 12548#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12214#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12451#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12962#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12967#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12656#L586-33 assume !(1 == ~t6_pc~0); 12231#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 12232#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12469#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12470#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12131#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12132#L605-33 assume !(1 == ~t7_pc~0); 12299#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 12065#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12066#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12859#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11944#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11945#L624-33 assume 1 == ~t8_pc~0; 12101#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12109#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12633#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12311#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12312#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12067#L643-33 assume 1 == ~t9_pc~0; 12068#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12143#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12605#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12562#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12563#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11934#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11935#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12430#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12489#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12490#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12756#L1079-3 assume !(1 == ~T5_E~0); 12665#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12603#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12604#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12521#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12522#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12778#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12764#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12765#L1119-3 assume !(1 == ~E_3~0); 12968#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12972#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12225#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12226#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12392#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12393#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12568#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12975#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11939#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12309#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 11823#L1459 assume !(0 == start_simulation_~tmp~3#1); 11825#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12835#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12117#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11863#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 11864#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12271#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12434#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 12593#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 12035#L1440-2 [2022-12-13 20:32:17,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:17,372 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times [2022-12-13 20:32:17,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:17,372 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544696103] [2022-12-13 20:32:17,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:17,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:17,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:17,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:17,400 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:17,400 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [544696103] [2022-12-13 20:32:17,400 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [544696103] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:17,400 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:17,400 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:17,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [894688875] [2022-12-13 20:32:17,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:17,401 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:17,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:17,401 INFO L85 PathProgramCache]: Analyzing trace with hash -1832038971, now seen corresponding path program 2 times [2022-12-13 20:32:17,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:17,402 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [460321481] [2022-12-13 20:32:17,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:17,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:17,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:17,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:17,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:17,436 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [460321481] [2022-12-13 20:32:17,436 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [460321481] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:17,436 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:17,436 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:17,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1994298484] [2022-12-13 20:32:17,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:17,437 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:17,437 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:17,437 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:17,438 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:17,438 INFO L87 Difference]: Start difference. First operand 1175 states and 1747 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:17,452 INFO L93 Difference]: Finished difference Result 1175 states and 1746 transitions. [2022-12-13 20:32:17,452 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1746 transitions. [2022-12-13 20:32:17,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:17,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1746 transitions. [2022-12-13 20:32:17,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-12-13 20:32:17,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-12-13 20:32:17,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1746 transitions. [2022-12-13 20:32:17,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:17,461 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1746 transitions. [2022-12-13 20:32:17,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1746 transitions. [2022-12-13 20:32:17,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-12-13 20:32:17,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4859574468085106) internal successors, (1746), 1174 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1746 transitions. [2022-12-13 20:32:17,473 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1746 transitions. [2022-12-13 20:32:17,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:17,474 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1746 transitions. [2022-12-13 20:32:17,474 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 20:32:17,474 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1746 transitions. [2022-12-13 20:32:17,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:17,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:17,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:17,478 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:17,478 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:17,478 INFO L748 eck$LassoCheckResult]: Stem: 14526#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 14527#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15269#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15270#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14995#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 14720#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14721#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15250#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15284#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15277#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15278#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14849#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14836#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14837#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14647#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14648#L951 assume !(0 == ~M_E~0); 14398#L951-2 assume !(0 == ~T1_E~0); 14399#L956-1 assume !(0 == ~T2_E~0); 14547#L961-1 assume !(0 == ~T3_E~0); 15014#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15015#L971-1 assume !(0 == ~T5_E~0); 15137#L976-1 assume !(0 == ~T6_E~0); 15112#L981-1 assume !(0 == ~T7_E~0); 14885#L986-1 assume !(0 == ~T8_E~0); 14597#L991-1 assume !(0 == ~T9_E~0); 14598#L996-1 assume !(0 == ~E_M~0); 15305#L1001-1 assume !(0 == ~E_1~0); 15065#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 15066#L1011-1 assume !(0 == ~E_3~0); 15285#L1016-1 assume !(0 == ~E_4~0); 15294#L1021-1 assume !(0 == ~E_5~0); 14194#L1026-1 assume !(0 == ~E_6~0); 14195#L1031-1 assume !(0 == ~E_7~0); 15021#L1036-1 assume !(0 == ~E_8~0); 15017#L1041-1 assume !(0 == ~E_9~0); 15018#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15257#L472 assume 1 == ~m_pc~0; 15322#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15046#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15047#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15055#L1179 assume !(0 != activate_threads_~tmp~1#1); 14202#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14203#L491 assume 1 == ~t1_pc~0; 15064#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14692#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14225#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14174#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 14175#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14196#L510 assume !(1 == ~t2_pc~0); 14163#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14164#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14712#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14713#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14451#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14452#L529 assume 1 == ~t3_pc~0; 14798#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14799#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14172#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14173#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 14374#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14375#L548 assume !(1 == ~t4_pc~0); 14264#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14263#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14339#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14308#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 14309#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14251#L567 assume 1 == ~t5_pc~0; 14252#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14310#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15205#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15206#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 15245#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14385#L586 assume !(1 == ~t6_pc~0); 14386#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14453#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14697#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14698#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 15239#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15240#L605 assume 1 == ~t7_pc~0; 15213#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14867#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15048#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15331#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 15330#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14989#L624 assume !(1 == ~t8_pc~0); 14446#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14445#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15097#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15156#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 15223#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14217#L643 assume 1 == ~t9_pc~0; 14218#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15177#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14761#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14602#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 14603#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14430#L1059 assume !(1 == ~M_E~0); 14431#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14575#L1064-1 assume !(1 == ~T2_E~0); 14576#L1069-1 assume !(1 == ~T3_E~0); 15184#L1074-1 assume !(1 == ~T4_E~0); 15221#L1079-1 assume !(1 == ~T5_E~0); 15211#L1084-1 assume !(1 == ~T6_E~0); 15212#L1089-1 assume !(1 == ~T7_E~0); 15235#L1094-1 assume !(1 == ~T8_E~0); 14923#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14924#L1104-1 assume !(1 == ~E_M~0); 15099#L1109-1 assume !(1 == ~E_1~0); 14714#L1114-1 assume !(1 == ~E_2~0); 14715#L1119-1 assume !(1 == ~E_3~0); 14773#L1124-1 assume !(1 == ~E_4~0); 14213#L1129-1 assume !(1 == ~E_5~0); 14214#L1134-1 assume !(1 == ~E_6~0); 14543#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14544#L1144-1 assume !(1 == ~E_8~0); 14728#L1149-1 assume !(1 == ~E_9~0); 14391#L1154-1 assume { :end_inline_reset_delta_events } true; 14392#L1440-2 [2022-12-13 20:32:17,478 INFO L750 eck$LassoCheckResult]: Loop: 14392#L1440-2 assume !false; 14513#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14616#L926 assume !false; 14775#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14776#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14471#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14472#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14481#L795 assume !(0 != eval_~tmp~0#1); 14482#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14932#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14631#L951-3 assume !(0 == ~M_E~0); 14632#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15147#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14991#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14755#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14756#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15040#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14234#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14235#L986-3 assume !(0 == ~T8_E~0); 14215#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14216#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15134#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14726#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14727#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15155#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15191#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14935#L1026-3 assume !(0 == ~E_6~0); 14936#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15128#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15129#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15182#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15145#L472-33 assume !(1 == ~m_pc~0); 14336#L472-35 is_master_triggered_~__retres1~0#1 := 0; 14337#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15173#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15152#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14766#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14767#L491-33 assume 1 == ~t1_pc~0; 15056#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14273#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15300#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15314#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15315#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15105#L510-33 assume 1 == ~t2_pc~0; 15106#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15101#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15139#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15140#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14158#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14159#L529-33 assume 1 == ~t3_pc~0; 14183#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14184#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14349#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14350#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 14289#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14290#L548-33 assume 1 == ~t4_pc~0; 14529#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14649#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15072#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14686#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14469#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14470#L567-33 assume 1 == ~t5_pc~0; 14905#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14571#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14808#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15319#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15324#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15013#L586-33 assume 1 == ~t6_pc~0; 14979#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14589#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14826#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14827#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14488#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14489#L605-33 assume !(1 == ~t7_pc~0); 14656#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 14422#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14423#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15216#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14301#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14302#L624-33 assume 1 == ~t8_pc~0; 14458#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14466#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14990#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14668#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14669#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14424#L643-33 assume 1 == ~t9_pc~0; 14425#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14500#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14962#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14919#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14920#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14291#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14292#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14787#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14846#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14847#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15113#L1079-3 assume !(1 == ~T5_E~0); 15022#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14960#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14961#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14878#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14879#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15135#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15121#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15122#L1119-3 assume !(1 == ~E_3~0); 15325#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15329#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14582#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14583#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14749#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14750#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14925#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15332#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14296#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14666#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 14180#L1459 assume !(0 == start_simulation_~tmp~3#1); 14182#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15192#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14474#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14220#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 14221#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14628#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14791#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 14950#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 14392#L1440-2 [2022-12-13 20:32:17,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:17,479 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times [2022-12-13 20:32:17,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:17,479 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [165689264] [2022-12-13 20:32:17,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:17,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:17,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:17,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:17,505 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:17,505 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [165689264] [2022-12-13 20:32:17,505 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [165689264] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:17,505 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:17,505 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:17,505 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1606811654] [2022-12-13 20:32:17,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:17,506 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:17,506 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:17,506 INFO L85 PathProgramCache]: Analyzing trace with hash 1879852036, now seen corresponding path program 1 times [2022-12-13 20:32:17,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:17,506 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1536278761] [2022-12-13 20:32:17,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:17,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:17,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:17,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:17,540 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:17,540 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1536278761] [2022-12-13 20:32:17,540 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1536278761] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:17,540 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:17,540 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:17,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1908247412] [2022-12-13 20:32:17,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:17,541 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:17,541 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:17,541 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:17,541 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:17,542 INFO L87 Difference]: Start difference. First operand 1175 states and 1746 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:17,556 INFO L93 Difference]: Finished difference Result 1175 states and 1745 transitions. [2022-12-13 20:32:17,557 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1745 transitions. [2022-12-13 20:32:17,574 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:17,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1745 transitions. [2022-12-13 20:32:17,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-12-13 20:32:17,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-12-13 20:32:17,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1745 transitions. [2022-12-13 20:32:17,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:17,582 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1745 transitions. [2022-12-13 20:32:17,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1745 transitions. [2022-12-13 20:32:17,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-12-13 20:32:17,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4851063829787234) internal successors, (1745), 1174 states have internal predecessors, (1745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1745 transitions. [2022-12-13 20:32:17,602 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1745 transitions. [2022-12-13 20:32:17,602 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:17,603 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1745 transitions. [2022-12-13 20:32:17,603 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 20:32:17,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1745 transitions. [2022-12-13 20:32:17,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:17,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:17,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:17,610 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:17,610 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:17,610 INFO L748 eck$LassoCheckResult]: Stem: 16885#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 16886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17628#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17629#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17352#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 17077#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17078#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17607#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17641#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17634#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17635#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17206#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17193#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17194#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17004#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17005#L951 assume !(0 == ~M_E~0); 16755#L951-2 assume !(0 == ~T1_E~0); 16756#L956-1 assume !(0 == ~T2_E~0); 16904#L961-1 assume !(0 == ~T3_E~0); 17371#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17372#L971-1 assume !(0 == ~T5_E~0); 17494#L976-1 assume !(0 == ~T6_E~0); 17469#L981-1 assume !(0 == ~T7_E~0); 17242#L986-1 assume !(0 == ~T8_E~0); 16954#L991-1 assume !(0 == ~T9_E~0); 16955#L996-1 assume !(0 == ~E_M~0); 17662#L1001-1 assume !(0 == ~E_1~0); 17422#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17423#L1011-1 assume !(0 == ~E_3~0); 17642#L1016-1 assume !(0 == ~E_4~0); 17651#L1021-1 assume !(0 == ~E_5~0); 16551#L1026-1 assume !(0 == ~E_6~0); 16552#L1031-1 assume !(0 == ~E_7~0); 17378#L1036-1 assume !(0 == ~E_8~0); 17374#L1041-1 assume !(0 == ~E_9~0); 17375#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17614#L472 assume 1 == ~m_pc~0; 17679#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17403#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17404#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17412#L1179 assume !(0 != activate_threads_~tmp~1#1); 16559#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16560#L491 assume 1 == ~t1_pc~0; 17421#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17049#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16582#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16531#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 16532#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16553#L510 assume !(1 == ~t2_pc~0); 16520#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16521#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17069#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17070#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16808#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16809#L529 assume 1 == ~t3_pc~0; 17155#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17156#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16529#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16530#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 16731#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16732#L548 assume !(1 == ~t4_pc~0); 16621#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16620#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16696#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16665#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 16666#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16608#L567 assume 1 == ~t5_pc~0; 16609#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16667#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17562#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17563#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 17602#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16742#L586 assume !(1 == ~t6_pc~0); 16743#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16810#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17054#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17055#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 17596#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17597#L605 assume 1 == ~t7_pc~0; 17570#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17224#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17405#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17688#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 17687#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17346#L624 assume !(1 == ~t8_pc~0); 16803#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16802#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17454#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17513#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 17580#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16574#L643 assume 1 == ~t9_pc~0; 16575#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17534#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17118#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16961#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 16962#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16787#L1059 assume !(1 == ~M_E~0); 16788#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16932#L1064-1 assume !(1 == ~T2_E~0); 16933#L1069-1 assume !(1 == ~T3_E~0); 17541#L1074-1 assume !(1 == ~T4_E~0); 17578#L1079-1 assume !(1 == ~T5_E~0); 17568#L1084-1 assume !(1 == ~T6_E~0); 17569#L1089-1 assume !(1 == ~T7_E~0); 17592#L1094-1 assume !(1 == ~T8_E~0); 17280#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17281#L1104-1 assume !(1 == ~E_M~0); 17456#L1109-1 assume !(1 == ~E_1~0); 17071#L1114-1 assume !(1 == ~E_2~0); 17072#L1119-1 assume !(1 == ~E_3~0); 17130#L1124-1 assume !(1 == ~E_4~0); 16570#L1129-1 assume !(1 == ~E_5~0); 16571#L1134-1 assume !(1 == ~E_6~0); 16900#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16901#L1144-1 assume !(1 == ~E_8~0); 17087#L1149-1 assume !(1 == ~E_9~0); 16748#L1154-1 assume { :end_inline_reset_delta_events } true; 16749#L1440-2 [2022-12-13 20:32:17,610 INFO L750 eck$LassoCheckResult]: Loop: 16749#L1440-2 assume !false; 16870#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16973#L926 assume !false; 17132#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17133#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16831#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16832#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16839#L795 assume !(0 != eval_~tmp~0#1); 16840#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17289#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16988#L951-3 assume !(0 == ~M_E~0); 16989#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17504#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17348#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17113#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17114#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17397#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16594#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16595#L986-3 assume !(0 == ~T8_E~0); 16572#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16573#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17491#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17083#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17084#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17512#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17548#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17292#L1026-3 assume !(0 == ~E_6~0); 17293#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17485#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17486#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17539#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17502#L472-33 assume !(1 == ~m_pc~0); 16693#L472-35 is_master_triggered_~__retres1~0#1 := 0; 16694#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17530#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17509#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17123#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17124#L491-33 assume 1 == ~t1_pc~0; 17413#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16630#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17657#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17671#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17672#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17462#L510-33 assume !(1 == ~t2_pc~0); 17457#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 17458#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17496#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17497#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16515#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16516#L529-33 assume 1 == ~t3_pc~0; 16540#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16541#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16706#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16707#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 16646#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16647#L548-33 assume 1 == ~t4_pc~0; 16888#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17006#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17429#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17043#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16826#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16827#L567-33 assume 1 == ~t5_pc~0; 17262#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16928#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17166#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17676#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17682#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17370#L586-33 assume !(1 == ~t6_pc~0); 16945#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 16946#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17183#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17184#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16845#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16846#L605-33 assume !(1 == ~t7_pc~0); 17013#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 16779#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16780#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17573#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16658#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16659#L624-33 assume !(1 == ~t8_pc~0); 16816#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 16823#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17347#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17025#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17026#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16781#L643-33 assume 1 == ~t9_pc~0; 16782#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16857#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17319#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17276#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17277#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16648#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16649#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17144#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17203#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17204#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17470#L1079-3 assume !(1 == ~T5_E~0); 17379#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17317#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17318#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17235#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17236#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17492#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17476#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17477#L1119-3 assume !(1 == ~E_3~0); 17681#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17686#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16939#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16940#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17101#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17102#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17282#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17689#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16651#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17021#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 16537#L1459 assume !(0 == start_simulation_~tmp~3#1); 16539#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17549#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16829#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16577#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 16578#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16985#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17145#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 17304#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 16749#L1440-2 [2022-12-13 20:32:17,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:17,611 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times [2022-12-13 20:32:17,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:17,611 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [661822859] [2022-12-13 20:32:17,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:17,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:17,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:17,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:17,637 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:17,637 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [661822859] [2022-12-13 20:32:17,637 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [661822859] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:17,637 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:17,637 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:17,637 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [376108131] [2022-12-13 20:32:17,638 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:17,638 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:17,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:17,638 INFO L85 PathProgramCache]: Analyzing trace with hash -1588331705, now seen corresponding path program 1 times [2022-12-13 20:32:17,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:17,639 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1866814645] [2022-12-13 20:32:17,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:17,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:17,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:17,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:17,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:17,672 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1866814645] [2022-12-13 20:32:17,672 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1866814645] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:17,672 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:17,672 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:17,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [31165620] [2022-12-13 20:32:17,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:17,672 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:17,673 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:17,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:17,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:17,673 INFO L87 Difference]: Start difference. First operand 1175 states and 1745 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:17,689 INFO L93 Difference]: Finished difference Result 1175 states and 1744 transitions. [2022-12-13 20:32:17,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1744 transitions. [2022-12-13 20:32:17,693 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:17,695 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1744 transitions. [2022-12-13 20:32:17,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2022-12-13 20:32:17,696 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2022-12-13 20:32:17,696 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1744 transitions. [2022-12-13 20:32:17,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:17,697 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1744 transitions. [2022-12-13 20:32:17,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1744 transitions. [2022-12-13 20:32:17,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2022-12-13 20:32:17,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4842553191489363) internal successors, (1744), 1174 states have internal predecessors, (1744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1744 transitions. [2022-12-13 20:32:17,710 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1744 transitions. [2022-12-13 20:32:17,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:17,711 INFO L428 stractBuchiCegarLoop]: Abstraction has 1175 states and 1744 transitions. [2022-12-13 20:32:17,711 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 20:32:17,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1744 transitions. [2022-12-13 20:32:17,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048 [2022-12-13 20:32:17,714 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:17,714 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:17,715 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:17,715 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:17,715 INFO L748 eck$LassoCheckResult]: Stem: 19242#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 19985#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19986#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19709#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 19434#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19435#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19964#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19998#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19991#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19992#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19563#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19550#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19551#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19361#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19362#L951 assume !(0 == ~M_E~0); 19112#L951-2 assume !(0 == ~T1_E~0); 19113#L956-1 assume !(0 == ~T2_E~0); 19261#L961-1 assume !(0 == ~T3_E~0); 19728#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19729#L971-1 assume !(0 == ~T5_E~0); 19851#L976-1 assume !(0 == ~T6_E~0); 19826#L981-1 assume !(0 == ~T7_E~0); 19599#L986-1 assume !(0 == ~T8_E~0); 19311#L991-1 assume !(0 == ~T9_E~0); 19312#L996-1 assume !(0 == ~E_M~0); 20020#L1001-1 assume !(0 == ~E_1~0); 19779#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 19780#L1011-1 assume !(0 == ~E_3~0); 19999#L1016-1 assume !(0 == ~E_4~0); 20008#L1021-1 assume !(0 == ~E_5~0); 18908#L1026-1 assume !(0 == ~E_6~0); 18909#L1031-1 assume !(0 == ~E_7~0); 19735#L1036-1 assume !(0 == ~E_8~0); 19731#L1041-1 assume !(0 == ~E_9~0); 19732#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19971#L472 assume 1 == ~m_pc~0; 20036#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19760#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19761#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19769#L1179 assume !(0 != activate_threads_~tmp~1#1); 18916#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18917#L491 assume 1 == ~t1_pc~0; 19778#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19406#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18939#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18888#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 18889#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18912#L510 assume !(1 == ~t2_pc~0); 18877#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18878#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19426#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19427#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19165#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19166#L529 assume 1 == ~t3_pc~0; 19512#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19513#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18886#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18887#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 19088#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19089#L548 assume !(1 == ~t4_pc~0); 18978#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18977#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19053#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19024#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 19025#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18965#L567 assume 1 == ~t5_pc~0; 18966#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19026#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19919#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19920#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 19959#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19099#L586 assume !(1 == ~t6_pc~0); 19100#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19167#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19414#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19415#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 19953#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19954#L605 assume 1 == ~t7_pc~0; 19927#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19584#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19762#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20045#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 20044#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19703#L624 assume !(1 == ~t8_pc~0); 19160#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19159#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19811#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19870#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 19937#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18931#L643 assume 1 == ~t9_pc~0; 18932#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19891#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19477#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19318#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 19319#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19144#L1059 assume !(1 == ~M_E~0); 19145#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19289#L1064-1 assume !(1 == ~T2_E~0); 19290#L1069-1 assume !(1 == ~T3_E~0); 19898#L1074-1 assume !(1 == ~T4_E~0); 19935#L1079-1 assume !(1 == ~T5_E~0); 19925#L1084-1 assume !(1 == ~T6_E~0); 19926#L1089-1 assume !(1 == ~T7_E~0); 19949#L1094-1 assume !(1 == ~T8_E~0); 19637#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19638#L1104-1 assume !(1 == ~E_M~0); 19813#L1109-1 assume !(1 == ~E_1~0); 19428#L1114-1 assume !(1 == ~E_2~0); 19429#L1119-1 assume !(1 == ~E_3~0); 19487#L1124-1 assume !(1 == ~E_4~0); 18927#L1129-1 assume !(1 == ~E_5~0); 18928#L1134-1 assume !(1 == ~E_6~0); 19257#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19258#L1144-1 assume !(1 == ~E_8~0); 19444#L1149-1 assume !(1 == ~E_9~0); 19105#L1154-1 assume { :end_inline_reset_delta_events } true; 19106#L1440-2 [2022-12-13 20:32:17,715 INFO L750 eck$LassoCheckResult]: Loop: 19106#L1440-2 assume !false; 19227#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19330#L926 assume !false; 19489#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19490#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19188#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19189#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19196#L795 assume !(0 != eval_~tmp~0#1); 19197#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19646#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19345#L951-3 assume !(0 == ~M_E~0); 19346#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19861#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19705#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19473#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19474#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19754#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18951#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18952#L986-3 assume !(0 == ~T8_E~0); 18929#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18930#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19848#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19440#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19441#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19869#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19905#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19650#L1026-3 assume !(0 == ~E_6~0); 19651#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19842#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19843#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19896#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19859#L472-33 assume 1 == ~m_pc~0; 19860#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19051#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19887#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19866#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19480#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19481#L491-33 assume 1 == ~t1_pc~0; 19770#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18987#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20014#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20028#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20029#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19820#L510-33 assume !(1 == ~t2_pc~0); 19814#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 19815#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19853#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19854#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18872#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18873#L529-33 assume 1 == ~t3_pc~0; 18897#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18898#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19063#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19064#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 19003#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19004#L548-33 assume 1 == ~t4_pc~0; 19245#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19363#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19786#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19398#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19183#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19184#L567-33 assume !(1 == ~t5_pc~0); 19281#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 19282#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19522#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20033#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20038#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19727#L586-33 assume !(1 == ~t6_pc~0); 19301#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 19302#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19539#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19540#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19202#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19203#L605-33 assume !(1 == ~t7_pc~0); 19370#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 19129#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19130#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19930#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19015#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19016#L624-33 assume 1 == ~t8_pc~0; 19172#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19180#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19704#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19382#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19383#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19131#L643-33 assume 1 == ~t9_pc~0; 19132#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19214#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19676#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19633#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19634#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19005#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19006#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19501#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19559#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19560#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19827#L1079-3 assume !(1 == ~T5_E~0); 19736#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19674#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19675#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19592#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19593#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19849#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19833#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19834#L1119-3 assume !(1 == ~E_3~0); 20039#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20043#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19296#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19297#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19458#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19459#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19639#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20046#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19008#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19380#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 18894#L1459 assume !(0 == start_simulation_~tmp~3#1); 18896#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19906#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19186#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18934#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 18935#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19342#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19502#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 19661#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 19106#L1440-2 [2022-12-13 20:32:17,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:17,716 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times [2022-12-13 20:32:17,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:17,716 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590462989] [2022-12-13 20:32:17,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:17,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:17,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:17,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:17,767 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:17,767 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [590462989] [2022-12-13 20:32:17,767 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [590462989] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:17,767 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:17,767 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:17,768 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [666808350] [2022-12-13 20:32:17,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:17,768 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:17,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:17,768 INFO L85 PathProgramCache]: Analyzing trace with hash -1255110330, now seen corresponding path program 1 times [2022-12-13 20:32:17,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:17,768 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005541474] [2022-12-13 20:32:17,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:17,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:17,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:17,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:17,800 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:17,800 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2005541474] [2022-12-13 20:32:17,800 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2005541474] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:17,800 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:17,800 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:17,800 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [477790411] [2022-12-13 20:32:17,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:17,801 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:17,801 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:17,801 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:32:17,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:32:17,801 INFO L87 Difference]: Start difference. First operand 1175 states and 1744 transitions. cyclomatic complexity: 570 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:17,922 INFO L93 Difference]: Finished difference Result 2151 states and 3181 transitions. [2022-12-13 20:32:17,922 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2151 states and 3181 transitions. [2022-12-13 20:32:17,929 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2004 [2022-12-13 20:32:17,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2151 states to 2151 states and 3181 transitions. [2022-12-13 20:32:17,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2151 [2022-12-13 20:32:17,947 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2151 [2022-12-13 20:32:17,947 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2151 states and 3181 transitions. [2022-12-13 20:32:17,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:17,950 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2151 states and 3181 transitions. [2022-12-13 20:32:17,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2151 states and 3181 transitions. [2022-12-13 20:32:17,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2151 to 2151. [2022-12-13 20:32:17,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2151 states, 2151 states have (on average 1.478847047884705) internal successors, (3181), 2150 states have internal predecessors, (3181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:17,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2151 states to 2151 states and 3181 transitions. [2022-12-13 20:32:17,992 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2151 states and 3181 transitions. [2022-12-13 20:32:17,993 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:32:17,993 INFO L428 stractBuchiCegarLoop]: Abstraction has 2151 states and 3181 transitions. [2022-12-13 20:32:17,993 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 20:32:17,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2151 states and 3181 transitions. [2022-12-13 20:32:17,998 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2004 [2022-12-13 20:32:17,999 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:17,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:18,000 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:18,000 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:18,000 INFO L748 eck$LassoCheckResult]: Stem: 22584#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 22585#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 23356#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23357#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23062#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 22779#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22780#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23332#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23372#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23362#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23363#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22910#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22896#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22897#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22703#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22704#L951 assume !(0 == ~M_E~0); 22450#L951-2 assume !(0 == ~T1_E~0); 22451#L956-1 assume !(0 == ~T2_E~0); 22600#L961-1 assume !(0 == ~T3_E~0); 23081#L966-1 assume !(0 == ~T4_E~0); 23082#L971-1 assume !(0 == ~T5_E~0); 23207#L976-1 assume !(0 == ~T6_E~0); 23182#L981-1 assume !(0 == ~T7_E~0); 22950#L986-1 assume !(0 == ~T8_E~0); 22651#L991-1 assume !(0 == ~T9_E~0); 22652#L996-1 assume !(0 == ~E_M~0); 23398#L1001-1 assume !(0 == ~E_1~0); 23134#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 23135#L1011-1 assume !(0 == ~E_3~0); 23374#L1016-1 assume !(0 == ~E_4~0); 23383#L1021-1 assume !(0 == ~E_5~0); 22244#L1026-1 assume !(0 == ~E_6~0); 22245#L1031-1 assume !(0 == ~E_7~0); 23090#L1036-1 assume !(0 == ~E_8~0); 23088#L1041-1 assume !(0 == ~E_9~0); 23089#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23339#L472 assume 1 == ~m_pc~0; 23415#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23115#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23116#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23124#L1179 assume !(0 != activate_threads_~tmp~1#1); 22252#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22253#L491 assume 1 == ~t1_pc~0; 23133#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22751#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22275#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22224#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 22225#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22248#L510 assume !(1 == ~t2_pc~0); 22213#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22214#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22769#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22770#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22502#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22503#L529 assume 1 == ~t3_pc~0; 22858#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22859#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22222#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22223#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 22424#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22425#L548 assume !(1 == ~t4_pc~0); 22314#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22313#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22389#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22360#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 22361#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22306#L567 assume 1 == ~t5_pc~0; 22307#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22362#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23286#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23287#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 23327#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22435#L586 assume !(1 == ~t6_pc~0); 22436#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22506#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22757#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22758#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 23321#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23322#L605 assume 1 == ~t7_pc~0; 23294#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22936#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23118#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23424#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 23423#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23056#L624 assume !(1 == ~t8_pc~0); 22497#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22496#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23167#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23228#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 23305#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22267#L643 assume 1 == ~t9_pc~0; 22268#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23251#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22823#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22658#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 22659#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22480#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 22481#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22628#L1064-1 assume !(1 == ~T2_E~0); 22629#L1069-1 assume !(1 == ~T3_E~0); 23259#L1074-1 assume !(1 == ~T4_E~0); 23304#L1079-1 assume !(1 == ~T5_E~0); 23292#L1084-1 assume !(1 == ~T6_E~0); 23293#L1089-1 assume !(1 == ~T7_E~0); 23317#L1094-1 assume !(1 == ~T8_E~0); 22985#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22986#L1104-1 assume !(1 == ~E_M~0); 23171#L1109-1 assume !(1 == ~E_1~0); 22771#L1114-1 assume !(1 == ~E_2~0); 22772#L1119-1 assume !(1 == ~E_3~0); 22834#L1124-1 assume !(1 == ~E_4~0); 22263#L1129-1 assume !(1 == ~E_5~0); 22264#L1134-1 assume !(1 == ~E_6~0); 22598#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 22599#L1144-1 assume !(1 == ~E_8~0); 23465#L1149-1 assume !(1 == ~E_9~0); 23442#L1154-1 assume { :end_inline_reset_delta_events } true; 22566#L1440-2 [2022-12-13 20:32:18,000 INFO L750 eck$LassoCheckResult]: Loop: 22566#L1440-2 assume !false; 22567#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23340#L926 assume !false; 23341#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23213#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22569#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22793#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22794#L795 assume !(0 != eval_~tmp~0#1); 23230#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23231#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23428#L951-3 assume !(0 == ~M_E~0); 23426#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23219#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23059#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22819#L966-3 assume !(0 == ~T4_E~0); 22820#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23109#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22290#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22291#L986-3 assume !(0 == ~T8_E~0); 22265#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22266#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23202#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22783#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22784#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23226#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23267#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22997#L1026-3 assume !(0 == ~E_6~0); 22998#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23198#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23199#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23256#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23215#L472-33 assume 1 == ~m_pc~0; 23216#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22384#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23247#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23223#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22826#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22827#L491-33 assume !(1 == ~t1_pc~0); 22322#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 22323#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23390#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23406#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23407#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23175#L510-33 assume !(1 == ~t2_pc~0); 23169#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 23170#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23209#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23210#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22208#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22209#L529-33 assume 1 == ~t3_pc~0; 22233#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22234#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22399#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22400#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 22339#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22340#L548-33 assume 1 == ~t4_pc~0; 22580#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22702#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23141#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22743#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22520#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22521#L567-33 assume 1 == ~t5_pc~0; 22967#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22624#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22868#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23411#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23417#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23080#L586-33 assume !(1 == ~t6_pc~0); 22641#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 22642#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22886#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22887#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22539#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22540#L605-33 assume !(1 == ~t7_pc~0); 22711#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 22472#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22473#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23298#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22351#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22352#L624-33 assume 1 == ~t8_pc~0; 22509#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22517#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23057#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22724#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22725#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22474#L643-33 assume 1 == ~t9_pc~0; 22475#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22551#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23024#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22981#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22982#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22341#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22342#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22847#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22906#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22907#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23183#L1079-3 assume !(1 == ~T5_E~0); 23091#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23022#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23023#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22940#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22941#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23205#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23191#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23192#L1119-3 assume !(1 == ~E_3~0); 23418#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23422#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22635#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22636#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22809#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22810#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22987#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23425#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22344#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22722#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 22230#L1459 assume !(0 == start_simulation_~tmp~3#1); 22232#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23367#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22523#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22270#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 22271#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22683#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22849#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 23009#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 22566#L1440-2 [2022-12-13 20:32:18,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:18,001 INFO L85 PathProgramCache]: Analyzing trace with hash 99525123, now seen corresponding path program 1 times [2022-12-13 20:32:18,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:18,001 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [16416330] [2022-12-13 20:32:18,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:18,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:18,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:18,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:18,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:18,036 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [16416330] [2022-12-13 20:32:18,036 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [16416330] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:18,036 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:18,036 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:32:18,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [685676240] [2022-12-13 20:32:18,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:18,037 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:18,037 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:18,037 INFO L85 PathProgramCache]: Analyzing trace with hash -1153662588, now seen corresponding path program 1 times [2022-12-13 20:32:18,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:18,037 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803295011] [2022-12-13 20:32:18,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:18,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:18,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:18,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:18,068 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:18,068 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803295011] [2022-12-13 20:32:18,068 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [803295011] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:18,068 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:18,068 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:18,068 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094267163] [2022-12-13 20:32:18,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:18,069 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:18,069 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:18,069 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:18,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:18,069 INFO L87 Difference]: Start difference. First operand 2151 states and 3181 transitions. cyclomatic complexity: 1032 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:18,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:18,126 INFO L93 Difference]: Finished difference Result 2151 states and 3151 transitions. [2022-12-13 20:32:18,126 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2151 states and 3151 transitions. [2022-12-13 20:32:18,133 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2004 [2022-12-13 20:32:18,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2151 states to 2151 states and 3151 transitions. [2022-12-13 20:32:18,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2151 [2022-12-13 20:32:18,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2151 [2022-12-13 20:32:18,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2151 states and 3151 transitions. [2022-12-13 20:32:18,142 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:18,142 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2151 states and 3151 transitions. [2022-12-13 20:32:18,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2151 states and 3151 transitions. [2022-12-13 20:32:18,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2151 to 2151. [2022-12-13 20:32:18,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2151 states, 2151 states have (on average 1.4649000464900046) internal successors, (3151), 2150 states have internal predecessors, (3151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:18,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2151 states to 2151 states and 3151 transitions. [2022-12-13 20:32:18,169 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2151 states and 3151 transitions. [2022-12-13 20:32:18,170 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:18,170 INFO L428 stractBuchiCegarLoop]: Abstraction has 2151 states and 3151 transitions. [2022-12-13 20:32:18,170 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 20:32:18,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2151 states and 3151 transitions. [2022-12-13 20:32:18,175 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2004 [2022-12-13 20:32:18,175 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:18,175 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:18,176 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:18,176 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:18,177 INFO L748 eck$LassoCheckResult]: Stem: 26892#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 26893#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 27673#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27674#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27378#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 27089#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27090#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27649#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27687#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27680#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27681#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27222#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27208#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27209#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27012#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27013#L951 assume !(0 == ~M_E~0); 26758#L951-2 assume !(0 == ~T1_E~0); 26759#L956-1 assume !(0 == ~T2_E~0); 26908#L961-1 assume !(0 == ~T3_E~0); 27399#L966-1 assume !(0 == ~T4_E~0); 27400#L971-1 assume !(0 == ~T5_E~0); 27524#L976-1 assume !(0 == ~T6_E~0); 27499#L981-1 assume !(0 == ~T7_E~0); 27262#L986-1 assume !(0 == ~T8_E~0); 26958#L991-1 assume !(0 == ~T9_E~0); 26959#L996-1 assume !(0 == ~E_M~0); 27714#L1001-1 assume !(0 == ~E_1~0); 27451#L1006-1 assume !(0 == ~E_2~0); 27452#L1011-1 assume !(0 == ~E_3~0); 27689#L1016-1 assume !(0 == ~E_4~0); 27698#L1021-1 assume !(0 == ~E_5~0); 26552#L1026-1 assume !(0 == ~E_6~0); 26553#L1031-1 assume !(0 == ~E_7~0); 27406#L1036-1 assume !(0 == ~E_8~0); 27404#L1041-1 assume !(0 == ~E_9~0); 27405#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27656#L472 assume 1 == ~m_pc~0; 27731#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 27432#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27433#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27441#L1179 assume !(0 != activate_threads_~tmp~1#1); 26560#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26561#L491 assume 1 == ~t1_pc~0; 27450#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27061#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26584#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26533#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 26534#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26556#L510 assume !(1 == ~t2_pc~0); 26522#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26523#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27079#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27080#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26810#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26811#L529 assume 1 == ~t3_pc~0; 27170#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27171#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26531#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26532#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 26732#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26733#L548 assume !(1 == ~t4_pc~0); 26625#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26624#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26698#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26669#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 26670#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26615#L567 assume 1 == ~t5_pc~0; 26616#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26671#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27603#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27604#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 27644#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26743#L586 assume !(1 == ~t6_pc~0); 26744#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 26814#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27067#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27068#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 27638#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27639#L605 assume 1 == ~t7_pc~0; 27611#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27247#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27435#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27744#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 27743#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27372#L624 assume !(1 == ~t8_pc~0); 26805#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26804#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27483#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27547#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 27622#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26575#L643 assume 1 == ~t9_pc~0; 26576#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27570#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27134#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26965#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 26966#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26788#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 26789#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27800#L1064-1 assume !(1 == ~T2_E~0); 27799#L1069-1 assume !(1 == ~T3_E~0); 27798#L1074-1 assume !(1 == ~T4_E~0); 27741#L1079-1 assume !(1 == ~T5_E~0); 27797#L1084-1 assume !(1 == ~T6_E~0); 27796#L1089-1 assume !(1 == ~T7_E~0); 27795#L1094-1 assume !(1 == ~T8_E~0); 27794#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27793#L1104-1 assume !(1 == ~E_M~0); 27792#L1109-1 assume !(1 == ~E_1~0); 27789#L1114-1 assume !(1 == ~E_2~0); 27788#L1119-1 assume !(1 == ~E_3~0); 27786#L1124-1 assume !(1 == ~E_4~0); 27785#L1129-1 assume !(1 == ~E_5~0); 27784#L1134-1 assume !(1 == ~E_6~0); 27783#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27782#L1144-1 assume !(1 == ~E_8~0); 27781#L1149-1 assume !(1 == ~E_9~0); 27767#L1154-1 assume { :end_inline_reset_delta_events } true; 26874#L1440-2 [2022-12-13 20:32:18,177 INFO L750 eck$LassoCheckResult]: Loop: 26874#L1440-2 assume !false; 26875#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27657#L926 assume !false; 27658#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27530#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26877#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27103#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 27104#L795 assume !(0 != eval_~tmp~0#1); 27549#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27550#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27750#L951-3 assume !(0 == ~M_E~0); 27751#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28177#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28176#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28175#L966-3 assume !(0 == ~T4_E~0); 28174#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28173#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28172#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28171#L986-3 assume !(0 == ~T8_E~0); 28170#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28169#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28168#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28167#L1006-3 assume !(0 == ~E_2~0); 28166#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28165#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28164#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28163#L1026-3 assume !(0 == ~E_6~0); 28162#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28161#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28160#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28159#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28158#L472-33 assume !(1 == ~m_pc~0); 28156#L472-35 is_master_triggered_~__retres1~0#1 := 0; 28155#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28154#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28153#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28152#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28151#L491-33 assume 1 == ~t1_pc~0; 27442#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26632#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27706#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27722#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27723#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27491#L510-33 assume !(1 == ~t2_pc~0); 27485#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 27486#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27526#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27527#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26517#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26518#L529-33 assume !(1 == ~t3_pc~0); 26544#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 26543#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26708#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26709#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 26648#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26649#L548-33 assume 1 == ~t4_pc~0; 26888#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27011#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27458#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27052#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26828#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26829#L567-33 assume !(1 == ~t5_pc~0); 26931#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 26932#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27180#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27727#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27733#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27398#L586-33 assume !(1 == ~t6_pc~0); 26949#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 26950#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27198#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27199#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26847#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26848#L605-33 assume !(1 == ~t7_pc~0); 27020#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 26779#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26780#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27615#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26660#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26661#L624-33 assume 1 == ~t8_pc~0; 26817#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26825#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27373#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27034#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27035#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26781#L643-33 assume 1 == ~t9_pc~0; 26782#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26859#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27339#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27292#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27293#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26650#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26651#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27158#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27219#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27220#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27500#L1079-3 assume !(1 == ~T5_E~0); 27407#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27337#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27338#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27251#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27252#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27522#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27508#L1114-3 assume !(1 == ~E_2~0); 27509#L1119-3 assume !(1 == ~E_3~0); 27734#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27740#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26943#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26944#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27119#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27120#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27298#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27745#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26655#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27032#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 26539#L1459 assume !(0 == start_simulation_~tmp~3#1); 26541#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27588#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26831#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26578#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 26579#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27787#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27325#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 27326#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 26874#L1440-2 [2022-12-13 20:32:18,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:18,177 INFO L85 PathProgramCache]: Analyzing trace with hash 1976588353, now seen corresponding path program 1 times [2022-12-13 20:32:18,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:18,177 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457153036] [2022-12-13 20:32:18,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:18,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:18,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:18,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:18,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:18,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [457153036] [2022-12-13 20:32:18,214 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [457153036] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:18,214 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:18,214 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:32:18,214 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1122016440] [2022-12-13 20:32:18,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:18,215 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:18,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:18,215 INFO L85 PathProgramCache]: Analyzing trace with hash 722783878, now seen corresponding path program 1 times [2022-12-13 20:32:18,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:18,215 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225142110] [2022-12-13 20:32:18,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:18,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:18,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:18,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:18,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:18,248 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225142110] [2022-12-13 20:32:18,248 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1225142110] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:18,248 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:18,248 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:18,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2026020396] [2022-12-13 20:32:18,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:18,248 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:18,249 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:18,249 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:18,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:18,249 INFO L87 Difference]: Start difference. First operand 2151 states and 3151 transitions. cyclomatic complexity: 1002 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:18,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:18,332 INFO L93 Difference]: Finished difference Result 4115 states and 5970 transitions. [2022-12-13 20:32:18,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4115 states and 5970 transitions. [2022-12-13 20:32:18,345 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3967 [2022-12-13 20:32:18,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4115 states to 4115 states and 5970 transitions. [2022-12-13 20:32:18,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4115 [2022-12-13 20:32:18,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4115 [2022-12-13 20:32:18,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4115 states and 5970 transitions. [2022-12-13 20:32:18,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:18,362 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4115 states and 5970 transitions. [2022-12-13 20:32:18,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4115 states and 5970 transitions. [2022-12-13 20:32:18,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4115 to 3977. [2022-12-13 20:32:18,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3977 states, 3977 states have (on average 1.4528539099823987) internal successors, (5778), 3976 states have internal predecessors, (5778), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:18,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3977 states to 3977 states and 5778 transitions. [2022-12-13 20:32:18,414 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3977 states and 5778 transitions. [2022-12-13 20:32:18,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:18,415 INFO L428 stractBuchiCegarLoop]: Abstraction has 3977 states and 5778 transitions. [2022-12-13 20:32:18,415 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 20:32:18,415 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3977 states and 5778 transitions. [2022-12-13 20:32:18,424 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3829 [2022-12-13 20:32:18,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:18,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:18,425 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:18,425 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:18,426 INFO L748 eck$LassoCheckResult]: Stem: 33161#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 33162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 33956#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33957#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33649#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 33363#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33364#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33931#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33980#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33967#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33968#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33500#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33486#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33487#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33286#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33287#L951 assume !(0 == ~M_E~0); 33030#L951-2 assume !(0 == ~T1_E~0); 33031#L956-1 assume !(0 == ~T2_E~0); 33184#L961-1 assume !(0 == ~T3_E~0); 33668#L966-1 assume !(0 == ~T4_E~0); 33669#L971-1 assume !(0 == ~T5_E~0); 33797#L976-1 assume !(0 == ~T6_E~0); 33771#L981-1 assume !(0 == ~T7_E~0); 33539#L986-1 assume !(0 == ~T8_E~0); 33234#L991-1 assume !(0 == ~T9_E~0); 33235#L996-1 assume !(0 == ~E_M~0); 34012#L1001-1 assume !(0 == ~E_1~0); 33722#L1006-1 assume !(0 == ~E_2~0); 33723#L1011-1 assume !(0 == ~E_3~0); 33981#L1016-1 assume !(0 == ~E_4~0); 33996#L1021-1 assume !(0 == ~E_5~0); 32825#L1026-1 assume !(0 == ~E_6~0); 32826#L1031-1 assume !(0 == ~E_7~0); 33675#L1036-1 assume !(0 == ~E_8~0); 33671#L1041-1 assume !(0 == ~E_9~0); 33672#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33940#L472 assume !(1 == ~m_pc~0); 33893#L472-2 is_master_triggered_~__retres1~0#1 := 0; 33702#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33703#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33712#L1179 assume !(0 != activate_threads_~tmp~1#1); 32833#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32834#L491 assume 1 == ~t1_pc~0; 33721#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33334#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32857#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32806#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 32807#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32827#L510 assume !(1 == ~t2_pc~0); 32795#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32796#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33354#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33355#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33083#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33084#L529 assume 1 == ~t3_pc~0; 33445#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33446#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32804#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32805#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 33006#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33007#L548 assume !(1 == ~t4_pc~0); 32895#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 32894#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32972#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32940#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 32941#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32882#L567 assume 1 == ~t5_pc~0; 32883#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32942#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33876#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33877#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 33926#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33017#L586 assume !(1 == ~t6_pc~0); 33018#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33085#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33339#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33340#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 33919#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33920#L605 assume 1 == ~t7_pc~0; 33884#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33519#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33705#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34056#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 34054#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33642#L624 assume !(1 == ~t8_pc~0); 33078#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33077#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33754#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33822#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 33899#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32848#L643 assume 1 == ~t9_pc~0; 32849#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33844#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33406#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33239#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 33240#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33062#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 33063#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33212#L1064-1 assume !(1 == ~T2_E~0); 33213#L1069-1 assume !(1 == ~T3_E~0); 33853#L1074-1 assume !(1 == ~T4_E~0); 33897#L1079-1 assume !(1 == ~T5_E~0); 33882#L1084-1 assume !(1 == ~T6_E~0); 33883#L1089-1 assume !(1 == ~T7_E~0); 33915#L1094-1 assume !(1 == ~T8_E~0); 33577#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33578#L1104-1 assume !(1 == ~E_M~0); 33757#L1109-1 assume !(1 == ~E_1~0); 33356#L1114-1 assume !(1 == ~E_2~0); 33357#L1119-1 assume !(1 == ~E_3~0); 33418#L1124-1 assume !(1 == ~E_4~0); 32844#L1129-1 assume !(1 == ~E_5~0); 32845#L1134-1 assume !(1 == ~E_6~0); 33180#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 33181#L1144-1 assume !(1 == ~E_8~0); 33371#L1149-1 assume !(1 == ~E_9~0); 33023#L1154-1 assume { :end_inline_reset_delta_events } true; 33024#L1440-2 [2022-12-13 20:32:18,426 INFO L750 eck$LassoCheckResult]: Loop: 33024#L1440-2 assume !false; 33148#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33253#L926 assume !false; 33422#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33423#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 35041#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 35040#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 35039#L795 assume !(0 != eval_~tmp~0#1); 35038#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35037#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35026#L951-3 assume !(0 == ~M_E~0); 35018#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35019#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36706#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33400#L966-3 assume !(0 == ~T4_E~0); 33401#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36705#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32866#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32867#L986-3 assume !(0 == ~T8_E~0); 32846#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32847#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33894#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33895#L1006-3 assume !(0 == ~E_2~0); 33819#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33820#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33860#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33589#L1026-3 assume !(0 == ~E_6~0); 33590#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33788#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33789#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34069#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36702#L472-33 assume !(1 == ~m_pc~0); 32966#L472-35 is_master_triggered_~__retres1~0#1 := 0; 32967#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33839#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33816#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33411#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33412#L491-33 assume 1 == ~t1_pc~0; 36698#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36697#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34050#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34024#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34025#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33763#L510-33 assume !(1 == ~t2_pc~0); 33765#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 34014#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34015#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33865#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32790#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32791#L529-33 assume !(1 == ~t3_pc~0); 32817#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 32816#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36673#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36672#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 36671#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36670#L548-33 assume 1 == ~t4_pc~0; 36668#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36667#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36666#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36665#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36664#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36663#L567-33 assume !(1 == ~t5_pc~0); 36661#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 36660#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36659#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36658#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36657#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36656#L586-33 assume 1 == ~t6_pc~0; 36654#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36653#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36652#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36651#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36650#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36649#L605-33 assume !(1 == ~t7_pc~0); 36647#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 36646#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36645#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36644#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36643#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36642#L624-33 assume 1 == ~t8_pc~0; 36640#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36639#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36638#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36637#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36636#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36635#L643-33 assume !(1 == ~t9_pc~0); 36633#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 36632#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36631#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36630#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36629#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36628#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32923#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36627#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36626#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36625#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33772#L1079-3 assume !(1 == ~T5_E~0); 36624#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36623#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36622#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36621#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36620#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36619#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36618#L1114-3 assume !(1 == ~E_2~0); 36617#L1119-3 assume !(1 == ~E_3~0); 36616#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36615#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36614#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36613#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36612#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36611#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36610#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 36608#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 36599#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 36598#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 36597#L1459 assume !(0 == start_simulation_~tmp~3#1); 33943#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33973#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 33107#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 32851#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 32852#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33267#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33438#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 33603#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 33024#L1440-2 [2022-12-13 20:32:18,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:18,426 INFO L85 PathProgramCache]: Analyzing trace with hash -858385022, now seen corresponding path program 1 times [2022-12-13 20:32:18,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:18,426 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144453108] [2022-12-13 20:32:18,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:18,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:18,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:18,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:18,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:18,469 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144453108] [2022-12-13 20:32:18,469 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144453108] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:18,469 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:18,469 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:18,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [899208550] [2022-12-13 20:32:18,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:18,469 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:18,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:18,470 INFO L85 PathProgramCache]: Analyzing trace with hash -474411834, now seen corresponding path program 1 times [2022-12-13 20:32:18,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:18,470 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141245583] [2022-12-13 20:32:18,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:18,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:18,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:18,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:18,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:18,509 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1141245583] [2022-12-13 20:32:18,509 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1141245583] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:18,509 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:18,509 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:18,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1797460862] [2022-12-13 20:32:18,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:18,510 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:18,510 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:18,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:32:18,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:32:18,511 INFO L87 Difference]: Start difference. First operand 3977 states and 5778 transitions. cyclomatic complexity: 1805 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:18,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:18,699 INFO L93 Difference]: Finished difference Result 9525 states and 13699 transitions. [2022-12-13 20:32:18,699 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9525 states and 13699 transitions. [2022-12-13 20:32:18,733 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9224 [2022-12-13 20:32:18,762 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9525 states to 9525 states and 13699 transitions. [2022-12-13 20:32:18,762 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9525 [2022-12-13 20:32:18,768 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9525 [2022-12-13 20:32:18,768 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9525 states and 13699 transitions. [2022-12-13 20:32:18,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:18,777 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9525 states and 13699 transitions. [2022-12-13 20:32:18,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9525 states and 13699 transitions. [2022-12-13 20:32:18,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9525 to 7469. [2022-12-13 20:32:18,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7469 states, 7469 states have (on average 1.4441022894631141) internal successors, (10786), 7468 states have internal predecessors, (10786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:18,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7469 states to 7469 states and 10786 transitions. [2022-12-13 20:32:18,872 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7469 states and 10786 transitions. [2022-12-13 20:32:18,873 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:32:18,873 INFO L428 stractBuchiCegarLoop]: Abstraction has 7469 states and 10786 transitions. [2022-12-13 20:32:18,873 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 20:32:18,873 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7469 states and 10786 transitions. [2022-12-13 20:32:18,890 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7320 [2022-12-13 20:32:18,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:18,890 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:18,891 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:18,891 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:18,891 INFO L748 eck$LassoCheckResult]: Stem: 46671#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 46672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 47475#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47476#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47159#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 46874#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46875#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47452#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47501#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47489#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47490#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47008#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46994#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46995#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46796#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46797#L951 assume !(0 == ~M_E~0); 46541#L951-2 assume !(0 == ~T1_E~0); 46542#L956-1 assume !(0 == ~T2_E~0); 46694#L961-1 assume !(0 == ~T3_E~0); 47181#L966-1 assume !(0 == ~T4_E~0); 47182#L971-1 assume !(0 == ~T5_E~0); 47309#L976-1 assume !(0 == ~T6_E~0); 47282#L981-1 assume !(0 == ~T7_E~0); 47046#L986-1 assume !(0 == ~T8_E~0); 46744#L991-1 assume !(0 == ~T9_E~0); 46745#L996-1 assume !(0 == ~E_M~0); 47534#L1001-1 assume !(0 == ~E_1~0); 47233#L1006-1 assume !(0 == ~E_2~0); 47234#L1011-1 assume !(0 == ~E_3~0); 47502#L1016-1 assume !(0 == ~E_4~0); 47519#L1021-1 assume !(0 == ~E_5~0); 46337#L1026-1 assume !(0 == ~E_6~0); 46338#L1031-1 assume !(0 == ~E_7~0); 47188#L1036-1 assume !(0 == ~E_8~0); 47184#L1041-1 assume !(0 == ~E_9~0); 47185#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47461#L472 assume !(1 == ~m_pc~0); 47407#L472-2 is_master_triggered_~__retres1~0#1 := 0; 47213#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47214#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47222#L1179 assume !(0 != activate_threads_~tmp~1#1); 46345#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46346#L491 assume !(1 == ~t1_pc~0); 46842#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46843#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46369#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46318#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 46319#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46339#L510 assume !(1 == ~t2_pc~0); 46307#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46308#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46863#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46864#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46594#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46595#L529 assume 1 == ~t3_pc~0; 46956#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46957#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46316#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46317#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 46517#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46518#L548 assume !(1 == ~t4_pc~0); 46407#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46406#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46482#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46452#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 46453#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46394#L567 assume 1 == ~t5_pc~0; 46395#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46454#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47390#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47391#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 47447#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46528#L586 assume !(1 == ~t6_pc~0); 46529#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46596#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46848#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46849#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 47438#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47439#L605 assume 1 == ~t7_pc~0; 47398#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47026#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47215#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47567#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 47566#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47153#L624 assume !(1 == ~t8_pc~0); 46589#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46588#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47266#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47330#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 47413#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46360#L643 assume 1 == ~t9_pc~0; 46361#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47355#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46917#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46749#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 46750#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46573#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 46574#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47578#L1064-1 assume !(1 == ~T2_E~0); 47364#L1069-1 assume !(1 == ~T3_E~0); 47365#L1074-1 assume !(1 == ~T4_E~0); 47410#L1079-1 assume !(1 == ~T5_E~0); 47411#L1084-1 assume !(1 == ~T6_E~0); 47506#L1089-1 assume !(1 == ~T7_E~0); 47507#L1094-1 assume !(1 == ~T8_E~0); 47084#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47085#L1104-1 assume !(1 == ~E_M~0); 47268#L1109-1 assume !(1 == ~E_1~0); 47269#L1114-1 assume !(1 == ~E_2~0); 47571#L1119-1 assume !(1 == ~E_3~0); 47572#L1124-1 assume !(1 == ~E_4~0); 46356#L1129-1 assume !(1 == ~E_5~0); 46357#L1134-1 assume !(1 == ~E_6~0); 46690#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46691#L1144-1 assume !(1 == ~E_8~0); 47575#L1149-1 assume !(1 == ~E_9~0); 47576#L1154-1 assume { :end_inline_reset_delta_events } true; 51238#L1440-2 [2022-12-13 20:32:18,892 INFO L750 eck$LassoCheckResult]: Loop: 51238#L1440-2 assume !false; 51230#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51225#L926 assume !false; 51223#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 51220#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 51210#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 51208#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 51204#L795 assume !(0 != eval_~tmp~0#1); 51205#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53770#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53769#L951-3 assume !(0 == ~M_E~0); 53768#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53767#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53766#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53765#L966-3 assume !(0 == ~T4_E~0); 53764#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53763#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53762#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53761#L986-3 assume !(0 == ~T8_E~0); 53760#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53759#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53758#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53757#L1006-3 assume !(0 == ~E_2~0); 53756#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53755#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53754#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53753#L1026-3 assume !(0 == ~E_6~0); 53752#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53751#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47573#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47361#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47319#L472-33 assume !(1 == ~m_pc~0); 46476#L472-35 is_master_triggered_~__retres1~0#1 := 0; 46477#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53747#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53746#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53745#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53744#L491-33 assume !(1 == ~t1_pc~0); 49327#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 53743#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53742#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53741#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53740#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53739#L510-33 assume !(1 == ~t2_pc~0); 53737#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 53736#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53735#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53734#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53733#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53732#L529-33 assume 1 == ~t3_pc~0; 53730#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53729#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53728#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53727#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 53726#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53725#L548-33 assume 1 == ~t4_pc~0; 53723#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53722#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53721#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53720#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53719#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53718#L567-33 assume !(1 == ~t5_pc~0); 53716#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 53715#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53714#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53713#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53712#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53711#L586-33 assume 1 == ~t6_pc~0; 53709#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53708#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53707#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53706#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53705#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53704#L605-33 assume !(1 == ~t7_pc~0); 53702#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 53701#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53700#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53699#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53698#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53697#L624-33 assume !(1 == ~t8_pc~0); 53696#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 53694#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53693#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53692#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53691#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53690#L643-33 assume !(1 == ~t9_pc~0); 53688#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 53687#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53686#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53685#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53684#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53683#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46435#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46944#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47005#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47006#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47283#L1079-3 assume !(1 == ~T5_E~0); 47189#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47121#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47122#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47037#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47038#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47306#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47293#L1114-3 assume !(1 == ~E_2~0); 47294#L1119-3 assume !(1 == ~E_3~0); 47555#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47561#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46729#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46730#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53513#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53512#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53510#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 53389#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 53344#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 51561#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 51559#L1459 assume !(0 == start_simulation_~tmp~3#1); 47465#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 51288#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 51277#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 51275#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 51273#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51255#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51247#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 51246#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 51238#L1440-2 [2022-12-13 20:32:18,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:18,892 INFO L85 PathProgramCache]: Analyzing trace with hash -717285501, now seen corresponding path program 1 times [2022-12-13 20:32:18,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:18,892 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680363150] [2022-12-13 20:32:18,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:18,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:18,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:18,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:18,932 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:18,932 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1680363150] [2022-12-13 20:32:18,932 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1680363150] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:18,932 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:18,933 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:32:18,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [665530631] [2022-12-13 20:32:18,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:18,933 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:18,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:18,933 INFO L85 PathProgramCache]: Analyzing trace with hash 1320738055, now seen corresponding path program 1 times [2022-12-13 20:32:18,933 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:18,933 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577191805] [2022-12-13 20:32:18,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:18,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:18,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:18,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:18,961 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:18,961 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577191805] [2022-12-13 20:32:18,961 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [577191805] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:18,962 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:18,962 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:18,962 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1914532050] [2022-12-13 20:32:18,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:18,962 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:18,962 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:18,963 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 20:32:18,963 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 20:32:18,963 INFO L87 Difference]: Start difference. First operand 7469 states and 10786 transitions. cyclomatic complexity: 3321 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:19,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:19,127 INFO L93 Difference]: Finished difference Result 9597 states and 13807 transitions. [2022-12-13 20:32:19,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9597 states and 13807 transitions. [2022-12-13 20:32:19,154 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9444 [2022-12-13 20:32:19,173 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9597 states to 9597 states and 13807 transitions. [2022-12-13 20:32:19,173 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9597 [2022-12-13 20:32:19,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9597 [2022-12-13 20:32:19,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9597 states and 13807 transitions. [2022-12-13 20:32:19,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:19,184 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9597 states and 13807 transitions. [2022-12-13 20:32:19,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9597 states and 13807 transitions. [2022-12-13 20:32:19,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9597 to 7481. [2022-12-13 20:32:19,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7481 states, 7481 states have (on average 1.432562491645502) internal successors, (10717), 7480 states have internal predecessors, (10717), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:19,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7481 states to 7481 states and 10717 transitions. [2022-12-13 20:32:19,283 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7481 states and 10717 transitions. [2022-12-13 20:32:19,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 20:32:19,284 INFO L428 stractBuchiCegarLoop]: Abstraction has 7481 states and 10717 transitions. [2022-12-13 20:32:19,284 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 20:32:19,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7481 states and 10717 transitions. [2022-12-13 20:32:19,301 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7332 [2022-12-13 20:32:19,301 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:19,301 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:19,302 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:19,302 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:19,302 INFO L748 eck$LassoCheckResult]: Stem: 63767#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 63768#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 64907#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64908#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64377#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 63998#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63999#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64855#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64966#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64937#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64938#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64176#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64154#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64155#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 63904#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63905#L951 assume !(0 == ~M_E~0); 63624#L951-2 assume !(0 == ~T1_E~0); 63625#L956-1 assume !(0 == ~T2_E~0); 63789#L961-1 assume !(0 == ~T3_E~0); 64403#L966-1 assume !(0 == ~T4_E~0); 64404#L971-1 assume !(0 == ~T5_E~0); 64588#L976-1 assume !(0 == ~T6_E~0); 64553#L981-1 assume !(0 == ~T7_E~0); 64225#L986-1 assume !(0 == ~T8_E~0); 63846#L991-1 assume !(0 == ~T9_E~0); 63847#L996-1 assume !(0 == ~E_M~0); 65051#L1001-1 assume !(0 == ~E_1~0); 64484#L1006-1 assume !(0 == ~E_2~0); 64485#L1011-1 assume !(0 == ~E_3~0); 64967#L1016-1 assume !(0 == ~E_4~0); 65004#L1021-1 assume !(0 == ~E_5~0); 63416#L1026-1 assume !(0 == ~E_6~0); 63417#L1031-1 assume !(0 == ~E_7~0); 64415#L1036-1 assume !(0 == ~E_8~0); 64410#L1041-1 assume !(0 == ~E_9~0); 64411#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64870#L472 assume !(1 == ~m_pc~0); 64766#L472-2 is_master_triggered_~__retres1~0#1 := 0; 64461#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64462#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 64474#L1179 assume !(0 != activate_threads_~tmp~1#1); 63424#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63425#L491 assume !(1 == ~t1_pc~0); 63963#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63964#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63448#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63397#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 63398#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63418#L510 assume !(1 == ~t2_pc~0); 63386#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63387#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63985#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63986#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 63679#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63680#L529 assume 1 == ~t3_pc~0; 64101#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64102#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63395#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63396#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 63600#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63601#L548 assume !(1 == ~t4_pc~0); 63486#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63485#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63564#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63531#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 63532#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63473#L567 assume 1 == ~t5_pc~0; 63474#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63533#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64732#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64733#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 64843#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63611#L586 assume !(1 == ~t6_pc~0); 63612#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 63681#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63969#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63970#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 64830#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64831#L605 assume 1 == ~t7_pc~0; 64743#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64196#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64463#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65170#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 65163#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64369#L624 assume !(1 == ~t8_pc~0); 63673#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 63672#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64533#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64620#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 64779#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63439#L643 assume 1 == ~t9_pc~0; 63440#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64670#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64054#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63852#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 63853#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63656#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 63657#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63821#L1064-1 assume !(1 == ~T2_E~0); 63822#L1069-1 assume !(1 == ~T3_E~0); 64682#L1074-1 assume !(1 == ~T4_E~0); 64774#L1079-1 assume !(1 == ~T5_E~0); 64741#L1084-1 assume !(1 == ~T6_E~0); 64742#L1089-1 assume !(1 == ~T7_E~0); 64815#L1094-1 assume !(1 == ~T8_E~0); 64268#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64269#L1104-1 assume !(1 == ~E_M~0); 64536#L1109-1 assume !(1 == ~E_1~0); 63987#L1114-1 assume !(1 == ~E_2~0); 63988#L1119-1 assume !(1 == ~E_3~0); 64068#L1124-1 assume !(1 == ~E_4~0); 63435#L1129-1 assume !(1 == ~E_5~0); 63436#L1134-1 assume !(1 == ~E_6~0); 63785#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 63786#L1144-1 assume !(1 == ~E_8~0); 64011#L1149-1 assume !(1 == ~E_9~0); 65239#L1154-1 assume { :end_inline_reset_delta_events } true; 67530#L1440-2 [2022-12-13 20:32:19,303 INFO L750 eck$LassoCheckResult]: Loop: 67530#L1440-2 assume !false; 65588#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65585#L926 assume !false; 65579#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 65580#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 65553#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 65554#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 65544#L795 assume !(0 != eval_~tmp~0#1); 65545#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67514#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67511#L951-3 assume !(0 == ~M_E~0); 67512#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 67506#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67507#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67502#L966-3 assume !(0 == ~T4_E~0); 67503#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67498#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67499#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 67494#L986-3 assume !(0 == ~T8_E~0); 67495#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 67490#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 67491#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 67486#L1006-3 assume !(0 == ~E_2~0); 67487#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67482#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 67483#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67478#L1026-3 assume !(0 == ~E_6~0); 67479#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 67474#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 67475#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 67470#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67471#L472-33 assume !(1 == ~m_pc~0); 67466#L472-35 is_master_triggered_~__retres1~0#1 := 0; 67467#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67462#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 67463#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67458#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67459#L491-33 assume !(1 == ~t1_pc~0); 67198#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 67199#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67188#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 67189#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65471#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65472#L510-33 assume !(1 == ~t2_pc~0); 65466#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 65467#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65462#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65463#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 65458#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65459#L529-33 assume 1 == ~t3_pc~0; 65452#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 65453#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65448#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65449#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 65444#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65445#L548-33 assume !(1 == ~t4_pc~0); 65440#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 65439#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65434#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65435#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65430#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65431#L567-33 assume !(1 == ~t5_pc~0); 65424#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 65425#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65420#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65421#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65416#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65417#L586-33 assume 1 == ~t6_pc~0; 65410#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65411#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65406#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65407#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 65402#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65403#L605-33 assume !(1 == ~t7_pc~0); 65396#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 65397#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65392#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65393#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65388#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65389#L624-33 assume 1 == ~t8_pc~0; 65382#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 65383#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65378#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65379#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 65374#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65375#L643-33 assume !(1 == ~t9_pc~0); 65368#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 65369#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65364#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65365#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 65360#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65361#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 65356#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65357#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65352#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65353#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65348#L1079-3 assume !(1 == ~T5_E~0); 65349#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65344#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65345#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65340#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65341#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65336#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65337#L1114-3 assume !(1 == ~E_2~0); 65332#L1119-3 assume !(1 == ~E_3~0); 65333#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65328#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65329#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 65324#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65325#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65320#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65321#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 65316#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 65308#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 65290#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 65291#L1459 assume !(0 == start_simulation_~tmp~3#1); 66052#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 66053#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 67625#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 67624#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 67623#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65619#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65613#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 65614#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 67530#L1440-2 [2022-12-13 20:32:19,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:19,303 INFO L85 PathProgramCache]: Analyzing trace with hash 1891501957, now seen corresponding path program 1 times [2022-12-13 20:32:19,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:19,303 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945590104] [2022-12-13 20:32:19,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:19,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:19,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:19,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:19,350 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:19,350 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1945590104] [2022-12-13 20:32:19,350 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1945590104] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:19,350 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:19,351 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:19,351 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1976075674] [2022-12-13 20:32:19,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:19,351 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:19,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:19,351 INFO L85 PathProgramCache]: Analyzing trace with hash -936057079, now seen corresponding path program 1 times [2022-12-13 20:32:19,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:19,351 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318994760] [2022-12-13 20:32:19,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:19,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:19,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:19,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:19,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:19,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [318994760] [2022-12-13 20:32:19,378 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [318994760] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:19,379 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:19,379 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:19,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [354604818] [2022-12-13 20:32:19,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:19,379 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:19,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:19,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:32:19,379 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:32:19,380 INFO L87 Difference]: Start difference. First operand 7481 states and 10717 transitions. cyclomatic complexity: 3240 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:19,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:19,589 INFO L93 Difference]: Finished difference Result 17989 states and 25551 transitions. [2022-12-13 20:32:19,590 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17989 states and 25551 transitions. [2022-12-13 20:32:19,659 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 17535 [2022-12-13 20:32:19,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17989 states to 17989 states and 25551 transitions. [2022-12-13 20:32:19,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17989 [2022-12-13 20:32:19,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17989 [2022-12-13 20:32:19,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17989 states and 25551 transitions. [2022-12-13 20:32:19,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:19,717 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17989 states and 25551 transitions. [2022-12-13 20:32:19,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17989 states and 25551 transitions. [2022-12-13 20:32:19,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17989 to 14148. [2022-12-13 20:32:19,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14148 states, 14148 states have (on average 1.4256432004523607) internal successors, (20170), 14147 states have internal predecessors, (20170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:19,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14148 states to 14148 states and 20170 transitions. [2022-12-13 20:32:19,908 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14148 states and 20170 transitions. [2022-12-13 20:32:19,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:32:19,909 INFO L428 stractBuchiCegarLoop]: Abstraction has 14148 states and 20170 transitions. [2022-12-13 20:32:19,909 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 20:32:19,909 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14148 states and 20170 transitions. [2022-12-13 20:32:19,971 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13996 [2022-12-13 20:32:19,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:19,972 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:19,973 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:19,973 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:19,973 INFO L748 eck$LassoCheckResult]: Stem: 89231#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 89232#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 90061#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 90062#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89737#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 89442#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89443#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 90034#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 90088#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 90073#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 90074#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 89582#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 89566#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 89567#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 89359#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89360#L951 assume !(0 == ~M_E~0); 89100#L951-2 assume !(0 == ~T1_E~0); 89101#L956-1 assume !(0 == ~T2_E~0); 89254#L961-1 assume !(0 == ~T3_E~0); 89759#L966-1 assume !(0 == ~T4_E~0); 89760#L971-1 assume !(0 == ~T5_E~0); 89888#L976-1 assume !(0 == ~T6_E~0); 89862#L981-1 assume !(0 == ~T7_E~0); 89622#L986-1 assume !(0 == ~T8_E~0); 89308#L991-1 assume !(0 == ~T9_E~0); 89309#L996-1 assume !(0 == ~E_M~0); 90123#L1001-1 assume !(0 == ~E_1~0); 89810#L1006-1 assume !(0 == ~E_2~0); 89811#L1011-1 assume !(0 == ~E_3~0); 90089#L1016-1 assume !(0 == ~E_4~0); 90107#L1021-1 assume !(0 == ~E_5~0); 88896#L1026-1 assume !(0 == ~E_6~0); 88897#L1031-1 assume !(0 == ~E_7~0); 89766#L1036-1 assume !(0 == ~E_8~0); 89762#L1041-1 assume !(0 == ~E_9~0); 89763#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90044#L472 assume !(1 == ~m_pc~0); 89990#L472-2 is_master_triggered_~__retres1~0#1 := 0; 89790#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89791#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 89799#L1179 assume !(0 != activate_threads_~tmp~1#1); 88904#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88905#L491 assume !(1 == ~t1_pc~0); 89407#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 89408#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88928#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 88877#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 88878#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88898#L510 assume !(1 == ~t2_pc~0); 88866#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 88867#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89429#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 89430#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 89153#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89154#L529 assume !(1 == ~t3_pc~0); 89631#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 89914#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88875#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88876#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 89075#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89076#L548 assume !(1 == ~t4_pc~0); 88966#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88965#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89040#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89010#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 89011#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88953#L567 assume 1 == ~t5_pc~0; 88954#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 89012#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89973#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 89974#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 90029#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 89086#L586 assume !(1 == ~t6_pc~0); 89087#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 89155#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 89413#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89414#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 90020#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 90021#L605 assume 1 == ~t7_pc~0; 89980#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 89600#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 89792#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 90168#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 90167#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89729#L624 assume !(1 == ~t8_pc~0); 89148#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 89147#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89844#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 89910#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 89995#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88919#L643 assume 1 == ~t9_pc~0; 88920#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 89939#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89488#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 89313#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 89314#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89132#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 89133#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89284#L1064-1 assume !(1 == ~T2_E~0); 89285#L1069-1 assume !(1 == ~T3_E~0); 90161#L1074-1 assume !(1 == ~T4_E~0); 90162#L1079-1 assume !(1 == ~T5_E~0); 89978#L1084-1 assume !(1 == ~T6_E~0); 89979#L1089-1 assume !(1 == ~T7_E~0); 90013#L1094-1 assume !(1 == ~T8_E~0); 90014#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 90101#L1104-1 assume !(1 == ~E_M~0); 90102#L1109-1 assume !(1 == ~E_1~0); 89431#L1114-1 assume !(1 == ~E_2~0); 89432#L1119-1 assume !(1 == ~E_3~0); 89502#L1124-1 assume !(1 == ~E_4~0); 89503#L1129-1 assume !(1 == ~E_5~0); 89741#L1134-1 assume !(1 == ~E_6~0); 89742#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 89453#L1144-1 assume !(1 == ~E_8~0); 89454#L1149-1 assume !(1 == ~E_9~0); 89092#L1154-1 assume { :end_inline_reset_delta_events } true; 89093#L1440-2 [2022-12-13 20:32:19,974 INFO L750 eck$LassoCheckResult]: Loop: 89093#L1440-2 assume !false; 101866#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 101850#L926 assume !false; 101849#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 97474#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 97464#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 97462#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 97442#L795 assume !(0 != eval_~tmp~0#1); 97443#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 102708#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 102707#L951-3 assume !(0 == ~M_E~0); 90176#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 89900#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 89731#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 89482#L966-3 assume !(0 == ~T4_E~0); 89483#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 89785#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 88937#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 88938#L986-3 assume !(0 == ~T8_E~0); 88917#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 88918#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 89885#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 89451#L1006-3 assume !(0 == ~E_2~0); 89452#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 89909#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 89957#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 89672#L1026-3 assume !(0 == ~E_6~0); 89673#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 89880#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 89881#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 89945#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89896#L472-33 assume !(1 == ~m_pc~0); 89034#L472-35 is_master_triggered_~__retres1~0#1 := 0; 89035#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89933#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 89906#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 89493#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89494#L491-33 assume !(1 == ~t1_pc~0); 88971#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 88972#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90114#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 90159#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 102883#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102882#L510-33 assume !(1 == ~t2_pc~0); 102880#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 102717#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102716#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 102715#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 102706#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102705#L529-33 assume !(1 == ~t3_pc~0); 96074#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 102652#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102651#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 102650#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 102649#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102648#L548-33 assume !(1 == ~t4_pc~0); 102647#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 102645#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102644#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 102643#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 102642#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102641#L567-33 assume 1 == ~t5_pc~0; 102640#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 102636#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 102633#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 102630#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 102627#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 102624#L586-33 assume !(1 == ~t6_pc~0); 102621#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 102618#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 102615#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 102613#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 102611#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 102609#L605-33 assume 1 == ~t7_pc~0; 102607#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 102603#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102601#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 102599#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 102597#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 102595#L624-33 assume 1 == ~t8_pc~0; 102593#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 102591#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 102590#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 102588#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 102583#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 102581#L643-33 assume !(1 == ~t9_pc~0); 102577#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 102575#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 102571#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 102569#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 102565#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102562#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 101545#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 102558#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 102555#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 102552#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101537#L1079-3 assume !(1 == ~T5_E~0); 102547#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 102545#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 102543#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 102540#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 102537#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 102533#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 102530#L1114-3 assume !(1 == ~E_2~0); 102527#L1119-3 assume !(1 == ~E_3~0); 102524#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 90160#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 89292#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 89293#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 89475#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 89476#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 89662#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 90169#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 88999#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 89381#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 88883#L1459 assume !(0 == start_simulation_~tmp~3#1); 88885#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 101890#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 101880#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 101878#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 101876#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 101874#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 101873#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 101870#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 89093#L1440-2 [2022-12-13 20:32:19,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:19,974 INFO L85 PathProgramCache]: Analyzing trace with hash -1826536698, now seen corresponding path program 1 times [2022-12-13 20:32:19,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:19,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [732511855] [2022-12-13 20:32:19,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:19,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:19,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:20,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:20,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:20,023 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [732511855] [2022-12-13 20:32:20,023 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [732511855] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:20,023 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:20,024 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:32:20,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [831232818] [2022-12-13 20:32:20,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:20,024 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:20,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:20,025 INFO L85 PathProgramCache]: Analyzing trace with hash 969222345, now seen corresponding path program 1 times [2022-12-13 20:32:20,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:20,025 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658580122] [2022-12-13 20:32:20,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:20,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:20,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:20,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:20,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:20,077 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658580122] [2022-12-13 20:32:20,077 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1658580122] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:20,077 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:20,077 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:20,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1723213859] [2022-12-13 20:32:20,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:20,078 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:20,078 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:20,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:20,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:20,079 INFO L87 Difference]: Start difference. First operand 14148 states and 20170 transitions. cyclomatic complexity: 6026 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:20,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:20,226 INFO L93 Difference]: Finished difference Result 26863 states and 38123 transitions. [2022-12-13 20:32:20,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26863 states and 38123 transitions. [2022-12-13 20:32:20,349 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26672 [2022-12-13 20:32:20,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26863 states to 26863 states and 38123 transitions. [2022-12-13 20:32:20,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26863 [2022-12-13 20:32:20,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26863 [2022-12-13 20:32:20,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26863 states and 38123 transitions. [2022-12-13 20:32:20,426 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:20,426 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26863 states and 38123 transitions. [2022-12-13 20:32:20,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26863 states and 38123 transitions. [2022-12-13 20:32:20,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26863 to 26831. [2022-12-13 20:32:20,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26831 states, 26831 states have (on average 1.4196638216987814) internal successors, (38091), 26830 states have internal predecessors, (38091), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:20,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26831 states to 26831 states and 38091 transitions. [2022-12-13 20:32:20,701 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26831 states and 38091 transitions. [2022-12-13 20:32:20,702 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:20,702 INFO L428 stractBuchiCegarLoop]: Abstraction has 26831 states and 38091 transitions. [2022-12-13 20:32:20,702 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 20:32:20,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26831 states and 38091 transitions. [2022-12-13 20:32:20,791 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26640 [2022-12-13 20:32:20,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:20,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:20,793 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:20,793 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:20,794 INFO L748 eck$LassoCheckResult]: Stem: 130247#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 130248#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 131091#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131092#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 130749#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 130455#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 130456#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131059#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 131118#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131104#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131105#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 130594#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 130580#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 130581#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 130374#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 130375#L951 assume !(0 == ~M_E~0); 130115#L951-2 assume !(0 == ~T1_E~0); 130116#L956-1 assume !(0 == ~T2_E~0); 130270#L961-1 assume !(0 == ~T3_E~0); 130770#L966-1 assume !(0 == ~T4_E~0); 130771#L971-1 assume !(0 == ~T5_E~0); 130900#L976-1 assume !(0 == ~T6_E~0); 130873#L981-1 assume !(0 == ~T7_E~0); 130630#L986-1 assume !(0 == ~T8_E~0); 130321#L991-1 assume !(0 == ~T9_E~0); 130322#L996-1 assume !(0 == ~E_M~0); 131151#L1001-1 assume !(0 == ~E_1~0); 130825#L1006-1 assume !(0 == ~E_2~0); 130826#L1011-1 assume !(0 == ~E_3~0); 131119#L1016-1 assume !(0 == ~E_4~0); 131136#L1021-1 assume !(0 == ~E_5~0); 129914#L1026-1 assume !(0 == ~E_6~0); 129915#L1031-1 assume !(0 == ~E_7~0); 130777#L1036-1 assume !(0 == ~E_8~0); 130773#L1041-1 assume !(0 == ~E_9~0); 130774#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131075#L472 assume !(1 == ~m_pc~0); 131016#L472-2 is_master_triggered_~__retres1~0#1 := 0; 130804#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 130805#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 130814#L1179 assume !(0 != activate_threads_~tmp~1#1); 129922#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129923#L491 assume !(1 == ~t1_pc~0); 130423#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 130424#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 129945#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 129895#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 129896#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 129916#L510 assume !(1 == ~t2_pc~0); 129884#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 129885#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130444#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 130445#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 130170#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130171#L529 assume !(1 == ~t3_pc~0); 130639#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 130931#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 129893#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 129894#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 130091#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130092#L548 assume !(1 == ~t4_pc~0); 129981#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 129980#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130056#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 130024#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 130025#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 129969#L567 assume !(1 == ~t5_pc~0); 129970#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 130026#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130999#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 131000#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 131054#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 130102#L586 assume !(1 == ~t6_pc~0); 130103#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 130172#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 130429#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 130430#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 131047#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 131048#L605 assume 1 == ~t7_pc~0; 131006#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 130611#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 130806#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 131194#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 131193#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 130743#L624 assume !(1 == ~t8_pc~0); 130164#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 130163#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 130858#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 130927#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 131023#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 129936#L643 assume 1 == ~t9_pc~0; 129937#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 130966#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 130503#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 130327#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 130328#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130147#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 130148#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 143409#L1064-1 assume !(1 == ~T2_E~0); 143408#L1069-1 assume !(1 == ~T3_E~0); 143407#L1074-1 assume !(1 == ~T4_E~0); 131190#L1079-1 assume !(1 == ~T5_E~0); 143406#L1084-1 assume !(1 == ~T6_E~0); 143405#L1089-1 assume !(1 == ~T7_E~0); 143404#L1094-1 assume !(1 == ~T8_E~0); 143403#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 143402#L1104-1 assume !(1 == ~E_M~0); 143399#L1109-1 assume !(1 == ~E_1~0); 143397#L1114-1 assume !(1 == ~E_2~0); 131198#L1119-1 assume !(1 == ~E_3~0); 130516#L1124-1 assume !(1 == ~E_4~0); 130517#L1129-1 assume !(1 == ~E_5~0); 143389#L1134-1 assume !(1 == ~E_6~0); 143387#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 130467#L1144-1 assume !(1 == ~E_8~0); 130468#L1149-1 assume !(1 == ~E_9~0); 130108#L1154-1 assume { :end_inline_reset_delta_events } true; 130109#L1440-2 [2022-12-13 20:32:20,794 INFO L750 eck$LassoCheckResult]: Loop: 130109#L1440-2 assume !false; 151848#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 151843#L926 assume !false; 151841#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 151834#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 151824#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 151822#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 151818#L795 assume !(0 != eval_~tmp~0#1); 151819#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 130680#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 130358#L951-3 assume !(0 == ~M_E~0); 130359#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 130916#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 130745#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 130497#L966-3 assume !(0 == ~T4_E~0); 130498#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 130797#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 129954#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 129955#L986-3 assume !(0 == ~T8_E~0); 129934#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 129935#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 155648#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 155647#L1006-3 assume !(0 == ~E_2~0); 155646#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 155645#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 155644#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 155643#L1026-3 assume !(0 == ~E_6~0); 155642#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 155641#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 155640#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 155639#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 155586#L472-33 assume !(1 == ~m_pc~0); 155585#L472-35 is_master_triggered_~__retres1~0#1 := 0; 155584#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 155583#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 155582#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155581#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 155033#L491-33 assume !(1 == ~t1_pc~0); 155031#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 155029#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155027#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 155025#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 155022#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 155020#L510-33 assume !(1 == ~t2_pc~0); 155017#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 155015#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 155013#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 155011#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 154892#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152143#L529-33 assume !(1 == ~t3_pc~0); 152142#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 152141#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152140#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 152139#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 152138#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152137#L548-33 assume 1 == ~t4_pc~0; 152134#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 152132#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 152130#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 152128#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 152126#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 152124#L567-33 assume !(1 == ~t5_pc~0); 152122#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 152119#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 152117#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 152115#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 152113#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 152111#L586-33 assume 1 == ~t6_pc~0; 152108#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 152106#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 152104#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 152102#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 152100#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 152098#L605-33 assume 1 == ~t7_pc~0; 152096#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 152092#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 152090#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 152088#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 152086#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 152084#L624-33 assume !(1 == ~t8_pc~0); 152082#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 152078#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 152076#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 152074#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 152072#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 152070#L643-33 assume !(1 == ~t9_pc~0); 152067#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 152064#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 152062#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 152060#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 152058#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152056#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 143597#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 152052#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 152050#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 152048#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 143587#L1079-3 assume !(1 == ~T5_E~0); 152045#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 152043#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 152041#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 152039#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 152037#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 152035#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 152033#L1114-3 assume !(1 == ~E_2~0); 152031#L1119-3 assume !(1 == ~E_3~0); 152029#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 152027#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 152025#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 152023#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 152021#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 152019#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 152017#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 152011#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 152001#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 151999#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 151998#L1459 assume !(0 == start_simulation_~tmp~3#1); 151996#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 151992#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 151982#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 151980#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 151978#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 151976#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 151973#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 151971#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 130109#L1440-2 [2022-12-13 20:32:20,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:20,794 INFO L85 PathProgramCache]: Analyzing trace with hash 367589383, now seen corresponding path program 1 times [2022-12-13 20:32:20,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:20,795 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7989368] [2022-12-13 20:32:20,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:20,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:20,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:20,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:20,850 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:20,850 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [7989368] [2022-12-13 20:32:20,851 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [7989368] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:20,851 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:20,851 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:20,851 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1077919713] [2022-12-13 20:32:20,851 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:20,852 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:20,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:20,852 INFO L85 PathProgramCache]: Analyzing trace with hash -705222903, now seen corresponding path program 1 times [2022-12-13 20:32:20,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:20,852 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796833691] [2022-12-13 20:32:20,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:20,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:20,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:20,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:20,895 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:20,895 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796833691] [2022-12-13 20:32:20,896 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1796833691] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:20,896 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:20,896 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:20,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1708685150] [2022-12-13 20:32:20,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:20,897 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:20,897 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:20,897 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:32:20,897 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:32:20,897 INFO L87 Difference]: Start difference. First operand 26831 states and 38091 transitions. cyclomatic complexity: 11268 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:21,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:21,281 INFO L93 Difference]: Finished difference Result 64082 states and 90300 transitions. [2022-12-13 20:32:21,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64082 states and 90300 transitions. [2022-12-13 20:32:21,460 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 62636 [2022-12-13 20:32:21,614 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64082 states to 64082 states and 90300 transitions. [2022-12-13 20:32:21,614 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64082 [2022-12-13 20:32:21,638 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64082 [2022-12-13 20:32:21,638 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64082 states and 90300 transitions. [2022-12-13 20:32:21,671 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:21,672 INFO L218 hiAutomatonCegarLoop]: Abstraction has 64082 states and 90300 transitions. [2022-12-13 20:32:21,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64082 states and 90300 transitions. [2022-12-13 20:32:22,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64082 to 50910. [2022-12-13 20:32:22,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50910 states, 50910 states have (on average 1.41441759968572) internal successors, (72008), 50909 states have internal predecessors, (72008), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:22,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50910 states to 50910 states and 72008 transitions. [2022-12-13 20:32:22,173 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50910 states and 72008 transitions. [2022-12-13 20:32:22,173 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:32:22,174 INFO L428 stractBuchiCegarLoop]: Abstraction has 50910 states and 72008 transitions. [2022-12-13 20:32:22,174 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 20:32:22,174 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50910 states and 72008 transitions. [2022-12-13 20:32:22,314 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 50672 [2022-12-13 20:32:22,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:22,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:22,317 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:22,317 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:22,318 INFO L748 eck$LassoCheckResult]: Stem: 221170#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 221171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 222013#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 222014#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 221675#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 221376#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 221377#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 221985#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 222041#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 222030#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 222031#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 221515#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 221501#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 221502#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 221297#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 221298#L951 assume !(0 == ~M_E~0); 221037#L951-2 assume !(0 == ~T1_E~0); 221038#L956-1 assume !(0 == ~T2_E~0); 221195#L961-1 assume !(0 == ~T3_E~0); 221696#L966-1 assume !(0 == ~T4_E~0); 221697#L971-1 assume !(0 == ~T5_E~0); 221832#L976-1 assume !(0 == ~T6_E~0); 221804#L981-1 assume !(0 == ~T7_E~0); 221553#L986-1 assume !(0 == ~T8_E~0); 221247#L991-1 assume !(0 == ~T9_E~0); 221248#L996-1 assume !(0 == ~E_M~0); 222076#L1001-1 assume !(0 == ~E_1~0); 221750#L1006-1 assume !(0 == ~E_2~0); 221751#L1011-1 assume !(0 == ~E_3~0); 222042#L1016-1 assume !(0 == ~E_4~0); 222061#L1021-1 assume !(0 == ~E_5~0); 220837#L1026-1 assume !(0 == ~E_6~0); 220838#L1031-1 assume !(0 == ~E_7~0); 221703#L1036-1 assume !(0 == ~E_8~0); 221699#L1041-1 assume !(0 == ~E_9~0); 221700#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221996#L472 assume !(1 == ~m_pc~0); 221943#L472-2 is_master_triggered_~__retres1~0#1 := 0; 221730#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221731#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 221739#L1179 assume !(0 != activate_threads_~tmp~1#1); 220845#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 220846#L491 assume !(1 == ~t1_pc~0); 221341#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 221342#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 220869#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 220818#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 220819#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 220839#L510 assume !(1 == ~t2_pc~0); 220807#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 220808#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 221363#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 221364#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 221090#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221091#L529 assume !(1 == ~t3_pc~0); 221562#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 221859#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220816#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 220817#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 221012#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 221013#L548 assume !(1 == ~t4_pc~0); 220906#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 220905#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 220977#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 220948#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 220949#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220894#L567 assume !(1 == ~t5_pc~0); 220895#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 220950#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 221926#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 221927#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 221979#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 221023#L586 assume !(1 == ~t6_pc~0); 221024#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 221092#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 221347#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 221348#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 221973#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 221974#L605 assume !(1 == ~t7_pc~0); 221531#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 221532#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221732#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 222122#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 222121#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 221668#L624 assume !(1 == ~t8_pc~0); 221085#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 221084#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 221787#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 221854#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 221949#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 220860#L643 assume 1 == ~t9_pc~0; 220861#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 221886#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 221424#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 221252#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 221253#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221069#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 221070#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 221224#L1064-1 assume !(1 == ~T2_E~0); 221225#L1069-1 assume !(1 == ~T3_E~0); 222114#L1074-1 assume !(1 == ~T4_E~0); 222115#L1079-1 assume !(1 == ~T5_E~0); 221931#L1084-1 assume !(1 == ~T6_E~0); 221932#L1089-1 assume !(1 == ~T7_E~0); 221967#L1094-1 assume !(1 == ~T8_E~0); 221968#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 222056#L1104-1 assume !(1 == ~E_M~0); 222057#L1109-1 assume !(1 == ~E_1~0); 221365#L1114-1 assume !(1 == ~E_2~0); 221366#L1119-1 assume !(1 == ~E_3~0); 221436#L1124-1 assume !(1 == ~E_4~0); 221437#L1129-1 assume !(1 == ~E_5~0); 221679#L1134-1 assume !(1 == ~E_6~0); 221680#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 221387#L1144-1 assume !(1 == ~E_8~0); 221388#L1149-1 assume !(1 == ~E_9~0); 221029#L1154-1 assume { :end_inline_reset_delta_events } true; 221030#L1440-2 [2022-12-13 20:32:22,318 INFO L750 eck$LassoCheckResult]: Loop: 221030#L1440-2 assume !false; 265881#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 265876#L926 assume !false; 265874#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 265866#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 265856#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 265854#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 265852#L795 assume !(0 != eval_~tmp~0#1); 221860#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 221602#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 221603#L951-3 assume !(0 == ~M_E~0); 271633#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 221844#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 221670#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 221416#L966-3 assume !(0 == ~T4_E~0); 221417#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 221724#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 220878#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 220879#L986-3 assume !(0 == ~T8_E~0); 220858#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 220859#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 271546#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 221385#L1006-3 assume !(0 == ~E_2~0); 221386#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 221853#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 221905#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 221606#L1026-3 assume !(0 == ~E_6~0); 221607#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 221821#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 221822#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 221892#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221840#L472-33 assume !(1 == ~m_pc~0); 220971#L472-35 is_master_triggered_~__retres1~0#1 := 0; 220972#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221877#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 221850#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 221429#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 221430#L491-33 assume !(1 == ~t1_pc~0); 220911#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 220912#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 222068#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 222086#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 222087#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 221794#L510-33 assume !(1 == ~t2_pc~0); 221792#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 221793#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 221834#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 221835#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 220802#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 220803#L529-33 assume !(1 == ~t3_pc~0); 266109#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 266107#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 266105#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 266102#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 266100#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 266098#L548-33 assume !(1 == ~t4_pc~0); 266096#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 266093#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 266091#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 266090#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 266088#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 266086#L567-33 assume !(1 == ~t5_pc~0); 266084#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 266082#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 266080#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 266077#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 266075#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 266073#L586-33 assume 1 == ~t6_pc~0; 266070#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 266068#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 266066#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 266063#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 266061#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 266059#L605-33 assume !(1 == ~t7_pc~0); 243695#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 266056#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 266054#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 266052#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 266050#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 266048#L624-33 assume 1 == ~t8_pc~0; 266045#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 266043#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 266041#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 266039#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 266037#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 266035#L643-33 assume !(1 == ~t9_pc~0); 266032#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 266030#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 266028#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 266026#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 266024#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 266022#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 262574#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 266019#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 266017#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 266015#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 262564#L1079-3 assume !(1 == ~T5_E~0); 266014#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 266013#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 266012#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 266011#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 266010#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 266009#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 266008#L1114-3 assume !(1 == ~E_2~0); 266006#L1119-3 assume !(1 == ~E_3~0); 266004#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 266002#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 266000#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 265998#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 265996#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 265993#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 265991#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 265985#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 265975#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 265974#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 265972#L1459 assume !(0 == start_simulation_~tmp~3#1); 265969#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 265961#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 265951#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 265949#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 265947#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 265945#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 265943#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 265941#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 221030#L1440-2 [2022-12-13 20:32:22,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:22,319 INFO L85 PathProgramCache]: Analyzing trace with hash -589339000, now seen corresponding path program 1 times [2022-12-13 20:32:22,319 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:22,320 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516757956] [2022-12-13 20:32:22,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:22,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:22,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:22,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:22,380 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:22,381 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1516757956] [2022-12-13 20:32:22,381 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1516757956] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:22,381 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:22,381 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:22,381 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [607735705] [2022-12-13 20:32:22,381 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:22,381 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:22,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:22,382 INFO L85 PathProgramCache]: Analyzing trace with hash -794957558, now seen corresponding path program 1 times [2022-12-13 20:32:22,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:22,382 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137641001] [2022-12-13 20:32:22,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:22,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:22,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:22,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:22,416 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:22,416 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137641001] [2022-12-13 20:32:22,416 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1137641001] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:22,416 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:22,416 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:22,416 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41752944] [2022-12-13 20:32:22,416 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:22,417 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:22,417 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:22,417 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:32:22,417 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:32:22,417 INFO L87 Difference]: Start difference. First operand 50910 states and 72008 transitions. cyclomatic complexity: 21106 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:22,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:22,959 INFO L93 Difference]: Finished difference Result 120701 states and 169509 transitions. [2022-12-13 20:32:22,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120701 states and 169509 transitions. [2022-12-13 20:32:23,372 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 117968 [2022-12-13 20:32:23,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120701 states to 120701 states and 169509 transitions. [2022-12-13 20:32:23,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120701 [2022-12-13 20:32:23,614 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120701 [2022-12-13 20:32:23,614 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120701 states and 169509 transitions. [2022-12-13 20:32:23,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:23,700 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120701 states and 169509 transitions. [2022-12-13 20:32:23,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120701 states and 169509 transitions. [2022-12-13 20:32:24,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120701 to 96525. [2022-12-13 20:32:24,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 96525 states, 96525 states have (on average 1.40984200984201) internal successors, (136085), 96524 states have internal predecessors, (136085), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:24,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96525 states to 96525 states and 136085 transitions. [2022-12-13 20:32:24,653 INFO L240 hiAutomatonCegarLoop]: Abstraction has 96525 states and 136085 transitions. [2022-12-13 20:32:24,653 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:32:24,653 INFO L428 stractBuchiCegarLoop]: Abstraction has 96525 states and 136085 transitions. [2022-12-13 20:32:24,654 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 20:32:24,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 96525 states and 136085 transitions. [2022-12-13 20:32:24,940 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 96192 [2022-12-13 20:32:24,940 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:24,940 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:24,943 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:24,943 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:24,944 INFO L748 eck$LassoCheckResult]: Stem: 392789#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 392790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 393650#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 393651#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 393296#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 392999#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 393000#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 393614#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 393681#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 393666#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 393667#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 393136#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 393121#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 393122#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 392916#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 392917#L951 assume !(0 == ~M_E~0); 392658#L951-2 assume !(0 == ~T1_E~0); 392659#L956-1 assume !(0 == ~T2_E~0); 392814#L961-1 assume !(0 == ~T3_E~0); 393315#L966-1 assume !(0 == ~T4_E~0); 393316#L971-1 assume !(0 == ~T5_E~0); 393452#L976-1 assume !(0 == ~T6_E~0); 393427#L981-1 assume !(0 == ~T7_E~0); 393174#L986-1 assume !(0 == ~T8_E~0); 392866#L991-1 assume !(0 == ~T9_E~0); 392867#L996-1 assume !(0 == ~E_M~0); 393715#L1001-1 assume !(0 == ~E_1~0); 393374#L1006-1 assume !(0 == ~E_2~0); 393375#L1011-1 assume !(0 == ~E_3~0); 393682#L1016-1 assume !(0 == ~E_4~0); 393697#L1021-1 assume !(0 == ~E_5~0); 392458#L1026-1 assume !(0 == ~E_6~0); 392459#L1031-1 assume !(0 == ~E_7~0); 393325#L1036-1 assume !(0 == ~E_8~0); 393321#L1041-1 assume !(0 == ~E_9~0); 393322#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 393630#L472 assume !(1 == ~m_pc~0); 393572#L472-2 is_master_triggered_~__retres1~0#1 := 0; 393356#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 393357#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 393365#L1179 assume !(0 != activate_threads_~tmp~1#1); 392466#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 392467#L491 assume !(1 == ~t1_pc~0); 392964#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 392965#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 392489#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 392439#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 392440#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 392460#L510 assume !(1 == ~t2_pc~0); 392428#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 392429#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 392985#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 392986#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 392710#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 392711#L529 assume !(1 == ~t3_pc~0); 393183#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 393484#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 392437#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 392438#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 392633#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 392634#L548 assume !(1 == ~t4_pc~0); 392525#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 392524#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 392598#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 392567#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 392568#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 392513#L567 assume !(1 == ~t5_pc~0); 392514#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 392569#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 393554#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 393555#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 393608#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 392644#L586 assume !(1 == ~t6_pc~0); 392645#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 392712#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 392970#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 392971#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 393602#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 393603#L605 assume !(1 == ~t7_pc~0); 393152#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 393153#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 393358#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 393775#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 393771#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 393290#L624 assume !(1 == ~t8_pc~0); 392705#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 392704#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 393411#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 393480#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 393579#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 392481#L643 assume !(1 == ~t9_pc~0); 392482#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 393515#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 393045#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 392871#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 392872#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 392689#L1059 assume 1 == ~M_E~0;~M_E~0 := 2; 392690#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 473422#L1064-1 assume !(1 == ~T2_E~0); 473420#L1069-1 assume !(1 == ~T3_E~0); 473418#L1074-1 assume !(1 == ~T4_E~0); 393766#L1079-1 assume !(1 == ~T5_E~0); 473415#L1084-1 assume !(1 == ~T6_E~0); 473413#L1089-1 assume !(1 == ~T7_E~0); 473411#L1094-1 assume !(1 == ~T8_E~0); 473410#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 473408#L1104-1 assume !(1 == ~E_M~0); 473406#L1109-1 assume !(1 == ~E_1~0); 473404#L1114-1 assume !(1 == ~E_2~0); 473402#L1119-1 assume !(1 == ~E_3~0); 473399#L1124-1 assume !(1 == ~E_4~0); 473397#L1129-1 assume !(1 == ~E_5~0); 473395#L1134-1 assume !(1 == ~E_6~0); 473393#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 473391#L1144-1 assume !(1 == ~E_8~0); 473389#L1149-1 assume !(1 == ~E_9~0); 473387#L1154-1 assume { :end_inline_reset_delta_events } true; 473383#L1440-2 [2022-12-13 20:32:24,944 INFO L750 eck$LassoCheckResult]: Loop: 473383#L1440-2 assume !false; 473381#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 473377#L926 assume !false; 473375#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 473367#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 473344#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 473330#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 473314#L795 assume !(0 != eval_~tmp~0#1); 473315#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 486289#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 486281#L951-3 assume !(0 == ~M_E~0); 486275#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 486268#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 486263#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 486256#L966-3 assume !(0 == ~T4_E~0); 486255#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 486254#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 486253#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 486131#L986-3 assume !(0 == ~T8_E~0); 485834#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 485833#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 485832#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 485831#L1006-3 assume !(0 == ~E_2~0); 485830#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 485829#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 485828#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 485827#L1026-3 assume !(0 == ~E_6~0); 485826#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 485825#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 485824#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 485822#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 485820#L472-33 assume !(1 == ~m_pc~0); 485818#L472-35 is_master_triggered_~__retres1~0#1 := 0; 485816#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 485814#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 485812#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 485810#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 485809#L491-33 assume !(1 == ~t1_pc~0); 484230#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 485806#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 485804#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 485802#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 485799#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 485797#L510-33 assume !(1 == ~t2_pc~0); 485794#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 485792#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 485790#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 485788#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 485786#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 485785#L529-33 assume !(1 == ~t3_pc~0); 472877#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 485781#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 485779#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 485777#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 485775#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 485773#L548-33 assume !(1 == ~t4_pc~0); 485770#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 485767#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 485765#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 485763#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 485761#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 485759#L567-33 assume !(1 == ~t5_pc~0); 485756#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 485754#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 485752#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 485750#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 485748#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 485746#L586-33 assume !(1 == ~t6_pc~0); 485743#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 485740#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 485738#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 485736#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 485734#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 473553#L605-33 assume !(1 == ~t7_pc~0); 473551#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 473548#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 473546#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 473544#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 473542#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 473540#L624-33 assume !(1 == ~t8_pc~0); 473538#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 473536#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 473534#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 473532#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 473530#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 473528#L643-33 assume !(1 == ~t9_pc~0); 451910#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 473524#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 473522#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 473520#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 473518#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 473516#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 473510#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 473508#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 473506#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 473504#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 473500#L1079-3 assume !(1 == ~T5_E~0); 473498#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 473496#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 473494#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 473492#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 473490#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 473488#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 473486#L1114-3 assume !(1 == ~E_2~0); 473484#L1119-3 assume !(1 == ~E_3~0); 473482#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 473480#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 473478#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 473476#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 473474#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 473472#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 473470#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 473464#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 473454#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 473452#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 473450#L1459 assume !(0 == start_simulation_~tmp~3#1); 473448#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 473446#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 473434#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 473432#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 473430#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 473425#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 473424#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 473386#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 473383#L1440-2 [2022-12-13 20:32:24,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:24,945 INFO L85 PathProgramCache]: Analyzing trace with hash 2033110665, now seen corresponding path program 1 times [2022-12-13 20:32:24,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:24,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332419793] [2022-12-13 20:32:24,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:24,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:24,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:24,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:24,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:24,996 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1332419793] [2022-12-13 20:32:24,996 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1332419793] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:24,996 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:24,996 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:32:24,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73913612] [2022-12-13 20:32:24,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:24,997 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:24,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:24,997 INFO L85 PathProgramCache]: Analyzing trace with hash -1428167924, now seen corresponding path program 1 times [2022-12-13 20:32:24,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:24,997 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [47324188] [2022-12-13 20:32:24,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:24,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:25,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:25,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:25,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:25,206 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [47324188] [2022-12-13 20:32:25,206 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [47324188] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:25,206 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:25,206 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:25,206 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638342571] [2022-12-13 20:32:25,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:25,207 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:25,207 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:25,207 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:25,207 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:25,208 INFO L87 Difference]: Start difference. First operand 96525 states and 136085 transitions. cyclomatic complexity: 39568 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:25,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:25,620 INFO L93 Difference]: Finished difference Result 143145 states and 202124 transitions. [2022-12-13 20:32:25,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 143145 states and 202124 transitions. [2022-12-13 20:32:26,005 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 142720 [2022-12-13 20:32:26,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 143145 states to 143145 states and 202124 transitions. [2022-12-13 20:32:26,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 143145 [2022-12-13 20:32:26,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 143145 [2022-12-13 20:32:26,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 143145 states and 202124 transitions. [2022-12-13 20:32:26,305 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:26,305 INFO L218 hiAutomatonCegarLoop]: Abstraction has 143145 states and 202124 transitions. [2022-12-13 20:32:26,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143145 states and 202124 transitions. [2022-12-13 20:32:27,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143145 to 97785. [2022-12-13 20:32:27,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97785 states, 97785 states have (on average 1.4154931737996626) internal successors, (138414), 97784 states have internal predecessors, (138414), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:27,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97785 states to 97785 states and 138414 transitions. [2022-12-13 20:32:27,337 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97785 states and 138414 transitions. [2022-12-13 20:32:27,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:27,338 INFO L428 stractBuchiCegarLoop]: Abstraction has 97785 states and 138414 transitions. [2022-12-13 20:32:27,338 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 20:32:27,338 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97785 states and 138414 transitions. [2022-12-13 20:32:27,568 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97472 [2022-12-13 20:32:27,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:27,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:27,572 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:27,572 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:27,572 INFO L748 eck$LassoCheckResult]: Stem: 632468#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 632469#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 633342#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 633343#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 632976#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 632672#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 632673#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 633306#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 633377#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 633365#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 633366#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 632807#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 632793#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 632794#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 632590#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 632591#L951 assume !(0 == ~M_E~0); 632336#L951-2 assume !(0 == ~T1_E~0); 632337#L956-1 assume !(0 == ~T2_E~0); 632486#L961-1 assume !(0 == ~T3_E~0); 632995#L966-1 assume !(0 == ~T4_E~0); 632996#L971-1 assume !(0 == ~T5_E~0); 633136#L976-1 assume !(0 == ~T6_E~0); 633110#L981-1 assume !(0 == ~T7_E~0); 632850#L986-1 assume !(0 == ~T8_E~0); 632537#L991-1 assume !(0 == ~T9_E~0); 632538#L996-1 assume !(0 == ~E_M~0); 633415#L1001-1 assume !(0 == ~E_1~0); 633052#L1006-1 assume !(0 == ~E_2~0); 633053#L1011-1 assume !(0 == ~E_3~0); 633380#L1016-1 assume !(0 == ~E_4~0); 633395#L1021-1 assume !(0 == ~E_5~0); 632135#L1026-1 assume !(0 == ~E_6~0); 632136#L1031-1 assume !(0 == ~E_7~0); 633005#L1036-1 assume !(0 == ~E_8~0); 633003#L1041-1 assume !(0 == ~E_9~0); 633004#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 633319#L472 assume !(1 == ~m_pc~0); 633259#L472-2 is_master_triggered_~__retres1~0#1 := 0; 633033#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 633034#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 633043#L1179 assume !(0 != activate_threads_~tmp~1#1); 632143#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 632144#L491 assume !(1 == ~t1_pc~0); 632639#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 632640#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 632166#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 632116#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 632117#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 632139#L510 assume !(1 == ~t2_pc~0); 632105#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 632106#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 632658#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 632659#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 632385#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 632386#L529 assume !(1 == ~t3_pc~0); 632858#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 633169#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 632114#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 632115#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 632309#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 632310#L548 assume !(1 == ~t4_pc~0); 632205#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 632204#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 632274#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 632247#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 632248#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 632196#L567 assume !(1 == ~t5_pc~0); 632197#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 632249#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 633237#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 633238#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 633300#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 632320#L586 assume !(1 == ~t6_pc~0); 632321#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 632389#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 632646#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 632647#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 633292#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 633293#L605 assume !(1 == ~t7_pc~0); 632831#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 632832#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 633036#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 633469#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 633465#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 632968#L624 assume !(1 == ~t8_pc~0); 632380#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 632379#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 633093#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 633164#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 633266#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 632158#L643 assume !(1 == ~t9_pc~0); 632159#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 633195#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 632717#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 632544#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 632545#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 632365#L1059 assume !(1 == ~M_E~0); 632366#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 632514#L1064-1 assume !(1 == ~T2_E~0); 632515#L1069-1 assume !(1 == ~T3_E~0); 633206#L1074-1 assume !(1 == ~T4_E~0); 633263#L1079-1 assume !(1 == ~T5_E~0); 633242#L1084-1 assume !(1 == ~T6_E~0); 633243#L1089-1 assume !(1 == ~T7_E~0); 633287#L1094-1 assume !(1 == ~T8_E~0); 632890#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 632891#L1104-1 assume !(1 == ~E_M~0); 633099#L1109-1 assume !(1 == ~E_1~0); 632663#L1114-1 assume !(1 == ~E_2~0); 632664#L1119-1 assume !(1 == ~E_3~0); 632730#L1124-1 assume !(1 == ~E_4~0); 632156#L1129-1 assume !(1 == ~E_5~0); 632157#L1134-1 assume !(1 == ~E_6~0); 632484#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 632485#L1144-1 assume !(1 == ~E_8~0); 632682#L1149-1 assume !(1 == ~E_9~0); 632326#L1154-1 assume { :end_inline_reset_delta_events } true; 632327#L1440-2 [2022-12-13 20:32:27,573 INFO L750 eck$LassoCheckResult]: Loop: 632327#L1440-2 assume !false; 708287#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 708283#L926 assume !false; 708281#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 708256#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 708240#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 708234#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 708227#L795 assume !(0 != eval_~tmp~0#1); 708228#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 728360#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 728359#L951-3 assume !(0 == ~M_E~0); 728358#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 728357#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 728356#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 728355#L966-3 assume !(0 == ~T4_E~0); 728354#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 728353#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 728352#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 728351#L986-3 assume !(0 == ~T8_E~0); 728350#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 728349#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 728348#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 728347#L1006-3 assume !(0 == ~E_2~0); 728346#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 728345#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 728344#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 728343#L1026-3 assume !(0 == ~E_6~0); 728342#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 728341#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 728340#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 728339#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 728338#L472-33 assume !(1 == ~m_pc~0); 728337#L472-35 is_master_triggered_~__retres1~0#1 := 0; 728336#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 728335#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 728334#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 728333#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 728332#L491-33 assume !(1 == ~t1_pc~0); 723732#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 728331#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 727239#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 727237#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 727235#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 727233#L510-33 assume !(1 == ~t2_pc~0); 727231#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 727154#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 726989#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 726988#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 726970#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 695279#L529-33 assume !(1 == ~t3_pc~0); 695276#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 695274#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 695272#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 695270#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 695268#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 695266#L548-33 assume 1 == ~t4_pc~0; 695264#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 695262#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 695260#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 695258#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 695256#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 695255#L567-33 assume !(1 == ~t5_pc~0); 695254#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 695250#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 695248#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 695246#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 695243#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 695241#L586-33 assume 1 == ~t6_pc~0; 695238#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 695236#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 695234#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 695232#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 693907#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 682100#L605-33 assume !(1 == ~t7_pc~0); 682098#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 682096#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 682094#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 682092#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 682090#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 682089#L624-33 assume !(1 == ~t8_pc~0); 682088#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 682086#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 682085#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 682084#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 682083#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 681237#L643-33 assume !(1 == ~t9_pc~0); 681235#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 681233#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 681231#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 681229#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 681226#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 681224#L1059-3 assume !(1 == ~M_E~0); 666838#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 681221#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 681219#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 681217#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 681214#L1079-3 assume !(1 == ~T5_E~0); 681212#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 681210#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 681208#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 681206#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 681204#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 681201#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 681199#L1114-3 assume !(1 == ~E_2~0); 681197#L1119-3 assume !(1 == ~E_3~0); 681195#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 681193#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 681191#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 681188#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 681186#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 681184#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 681182#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 681144#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 681134#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 681132#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 666636#L1459 assume !(0 == start_simulation_~tmp~3#1); 666637#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 708368#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 708354#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 708347#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 708341#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 708334#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 708326#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 708320#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 632327#L1440-2 [2022-12-13 20:32:27,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:27,574 INFO L85 PathProgramCache]: Analyzing trace with hash -1839154805, now seen corresponding path program 1 times [2022-12-13 20:32:27,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:27,574 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432031684] [2022-12-13 20:32:27,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:27,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:27,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:27,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:27,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:27,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432031684] [2022-12-13 20:32:27,625 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [432031684] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:27,625 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:27,625 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:32:27,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1194395282] [2022-12-13 20:32:27,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:27,626 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:27,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:27,626 INFO L85 PathProgramCache]: Analyzing trace with hash 1416516620, now seen corresponding path program 1 times [2022-12-13 20:32:27,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:27,627 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417028647] [2022-12-13 20:32:27,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:27,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:27,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:27,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:27,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:27,674 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1417028647] [2022-12-13 20:32:27,674 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1417028647] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:27,674 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:27,674 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:27,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1826765000] [2022-12-13 20:32:27,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:27,675 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:27,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:27,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:27,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:27,676 INFO L87 Difference]: Start difference. First operand 97785 states and 138414 transitions. cyclomatic complexity: 40633 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:28,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:28,051 INFO L93 Difference]: Finished difference Result 97785 states and 138028 transitions. [2022-12-13 20:32:28,051 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97785 states and 138028 transitions. [2022-12-13 20:32:28,311 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97472 [2022-12-13 20:32:28,459 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97785 states to 97785 states and 138028 transitions. [2022-12-13 20:32:28,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97785 [2022-12-13 20:32:28,493 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97785 [2022-12-13 20:32:28,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97785 states and 138028 transitions. [2022-12-13 20:32:28,534 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:28,535 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97785 states and 138028 transitions. [2022-12-13 20:32:28,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97785 states and 138028 transitions. [2022-12-13 20:32:29,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97785 to 97785. [2022-12-13 20:32:29,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97785 states, 97785 states have (on average 1.4115457380988905) internal successors, (138028), 97784 states have internal predecessors, (138028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:29,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97785 states to 97785 states and 138028 transitions. [2022-12-13 20:32:29,379 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97785 states and 138028 transitions. [2022-12-13 20:32:29,380 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:29,380 INFO L428 stractBuchiCegarLoop]: Abstraction has 97785 states and 138028 transitions. [2022-12-13 20:32:29,381 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 20:32:29,381 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97785 states and 138028 transitions. [2022-12-13 20:32:29,601 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97472 [2022-12-13 20:32:29,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:29,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:29,604 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:29,604 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:29,605 INFO L748 eck$LassoCheckResult]: Stem: 828046#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 828047#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 828920#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 828921#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 828567#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 828253#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 828254#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 828892#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 828953#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 828939#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 828940#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 828392#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 828377#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 828378#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 828170#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 828171#L951 assume !(0 == ~M_E~0); 827912#L951-2 assume !(0 == ~T1_E~0); 827913#L956-1 assume !(0 == ~T2_E~0); 828066#L961-1 assume !(0 == ~T3_E~0); 828589#L966-1 assume !(0 == ~T4_E~0); 828590#L971-1 assume !(0 == ~T5_E~0); 828727#L976-1 assume !(0 == ~T6_E~0); 828700#L981-1 assume !(0 == ~T7_E~0); 828435#L986-1 assume !(0 == ~T8_E~0); 828119#L991-1 assume !(0 == ~T9_E~0); 828120#L996-1 assume !(0 == ~E_M~0); 828998#L1001-1 assume !(0 == ~E_1~0); 828643#L1006-1 assume !(0 == ~E_2~0); 828644#L1011-1 assume !(0 == ~E_3~0); 828955#L1016-1 assume !(0 == ~E_4~0); 828975#L1021-1 assume !(0 == ~E_5~0); 827712#L1026-1 assume !(0 == ~E_6~0); 827713#L1031-1 assume !(0 == ~E_7~0); 828597#L1036-1 assume !(0 == ~E_8~0); 828595#L1041-1 assume !(0 == ~E_9~0); 828596#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 828903#L472 assume !(1 == ~m_pc~0); 828846#L472-2 is_master_triggered_~__retres1~0#1 := 0; 828624#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 828625#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 828634#L1179 assume !(0 != activate_threads_~tmp~1#1); 827720#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 827721#L491 assume !(1 == ~t1_pc~0); 828217#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 828218#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 827742#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 827693#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 827694#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 827716#L510 assume !(1 == ~t2_pc~0); 827682#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 827683#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 828236#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 828237#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 827962#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 827963#L529 assume !(1 == ~t3_pc~0); 828442#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 828757#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 827691#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 827692#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 827885#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 827886#L548 assume !(1 == ~t4_pc~0); 827781#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 827780#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 827850#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 827824#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 827825#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 827772#L567 assume !(1 == ~t5_pc~0); 827773#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 827823#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 828828#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 828829#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 828886#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 827896#L586 assume !(1 == ~t6_pc~0); 827897#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 827966#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 828224#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 828225#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 828877#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 828878#L605 assume !(1 == ~t7_pc~0); 828415#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 828416#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 828627#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 829055#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 829052#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 828559#L624 assume !(1 == ~t8_pc~0); 827956#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 827955#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 828683#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 828754#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 828851#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 827734#L643 assume !(1 == ~t9_pc~0); 827735#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 828789#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 828301#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 828126#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 828127#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 827941#L1059 assume !(1 == ~M_E~0); 827942#L1059-2 assume !(1 == ~T1_E~0); 828096#L1064-1 assume !(1 == ~T2_E~0); 828097#L1069-1 assume !(1 == ~T3_E~0); 828801#L1074-1 assume !(1 == ~T4_E~0); 828849#L1079-1 assume !(1 == ~T5_E~0); 828833#L1084-1 assume !(1 == ~T6_E~0); 828834#L1089-1 assume !(1 == ~T7_E~0); 828871#L1094-1 assume !(1 == ~T8_E~0); 828476#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 828477#L1104-1 assume !(1 == ~E_M~0); 828689#L1109-1 assume !(1 == ~E_1~0); 828238#L1114-1 assume !(1 == ~E_2~0); 828239#L1119-1 assume !(1 == ~E_3~0); 828313#L1124-1 assume !(1 == ~E_4~0); 827732#L1129-1 assume !(1 == ~E_5~0); 827733#L1134-1 assume !(1 == ~E_6~0); 828064#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 828065#L1144-1 assume !(1 == ~E_8~0); 828264#L1149-1 assume !(1 == ~E_9~0); 827902#L1154-1 assume { :end_inline_reset_delta_events } true; 827903#L1440-2 [2022-12-13 20:32:29,605 INFO L750 eck$LassoCheckResult]: Loop: 827903#L1440-2 assume !false; 900280#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 900275#L926 assume !false; 900273#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 900267#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 900258#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 900256#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 900253#L795 assume !(0 != eval_~tmp~0#1); 900254#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 916991#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 916989#L951-3 assume !(0 == ~M_E~0); 916986#L951-5 assume !(0 == ~T1_E~0); 916984#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 916982#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 916980#L966-3 assume !(0 == ~T4_E~0); 916978#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 916975#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 916973#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 916971#L986-3 assume !(0 == ~T8_E~0); 916969#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 916967#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 916965#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 916962#L1006-3 assume !(0 == ~E_2~0); 916959#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 916957#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 916955#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 916953#L1026-3 assume !(0 == ~E_6~0); 916951#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 916949#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 916948#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 916945#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 916943#L472-33 assume !(1 == ~m_pc~0); 916941#L472-35 is_master_triggered_~__retres1~0#1 := 0; 916939#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 916937#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 916935#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 916933#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 916931#L491-33 assume !(1 == ~t1_pc~0); 905976#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 916928#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 916922#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 916906#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 916902#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 916898#L510-33 assume !(1 == ~t2_pc~0); 916787#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 916786#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 916785#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 916774#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 916772#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 916770#L529-33 assume !(1 == ~t3_pc~0); 907771#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 916746#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 916737#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 916728#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 916720#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 916715#L548-33 assume 1 == ~t4_pc~0; 916709#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 916707#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 916706#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 916704#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 916702#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 916700#L567-33 assume !(1 == ~t5_pc~0); 916698#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 916695#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 916693#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 916691#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 916686#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 916681#L586-33 assume !(1 == ~t6_pc~0); 916675#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 916669#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 916664#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 916660#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 916657#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 916654#L605-33 assume !(1 == ~t7_pc~0); 887966#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 916646#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 916643#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 916639#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 916634#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 916629#L624-33 assume 1 == ~t8_pc~0; 916623#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 916618#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 916614#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 909389#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 909388#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 909387#L643-33 assume !(1 == ~t9_pc~0); 860872#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 909386#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 909383#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 909382#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 909380#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 909379#L1059-3 assume !(1 == ~M_E~0); 891652#L1059-5 assume !(1 == ~T1_E~0); 909357#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 909350#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 909342#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 909243#L1079-3 assume !(1 == ~T5_E~0); 909233#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 909223#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 909214#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 909206#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 909205#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 909204#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 909203#L1114-3 assume !(1 == ~E_2~0); 909202#L1119-3 assume !(1 == ~E_3~0); 909201#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 909200#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 909199#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 909197#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 909195#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 909193#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 909191#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 909185#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 908857#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 908854#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 908845#L1459 assume !(0 == start_simulation_~tmp~3#1); 908842#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 900303#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 900293#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 900291#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 900287#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 900286#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 900285#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 900283#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 827903#L1440-2 [2022-12-13 20:32:29,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:29,605 INFO L85 PathProgramCache]: Analyzing trace with hash 1638164041, now seen corresponding path program 1 times [2022-12-13 20:32:29,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:29,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674545389] [2022-12-13 20:32:29,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:29,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:29,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:29,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:29,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:29,649 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [674545389] [2022-12-13 20:32:29,649 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [674545389] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:29,649 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:29,649 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:29,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [896087085] [2022-12-13 20:32:29,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:29,649 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:29,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:29,650 INFO L85 PathProgramCache]: Analyzing trace with hash 237198924, now seen corresponding path program 1 times [2022-12-13 20:32:29,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:29,650 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [846573416] [2022-12-13 20:32:29,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:29,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:29,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:29,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:29,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:29,681 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [846573416] [2022-12-13 20:32:29,681 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [846573416] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:29,682 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:29,682 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:29,682 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1986854210] [2022-12-13 20:32:29,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:29,682 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:29,682 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:29,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:32:29,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:32:29,683 INFO L87 Difference]: Start difference. First operand 97785 states and 138028 transitions. cyclomatic complexity: 40247 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:30,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:30,187 INFO L93 Difference]: Finished difference Result 154489 states and 217717 transitions. [2022-12-13 20:32:30,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154489 states and 217717 transitions. [2022-12-13 20:32:30,828 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 153984 [2022-12-13 20:32:31,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154489 states to 154489 states and 217717 transitions. [2022-12-13 20:32:31,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 154489 [2022-12-13 20:32:31,159 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 154489 [2022-12-13 20:32:31,159 INFO L73 IsDeterministic]: Start isDeterministic. Operand 154489 states and 217717 transitions. [2022-12-13 20:32:31,219 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:31,219 INFO L218 hiAutomatonCegarLoop]: Abstraction has 154489 states and 217717 transitions. [2022-12-13 20:32:31,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154489 states and 217717 transitions. [2022-12-13 20:32:32,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154489 to 109134. [2022-12-13 20:32:32,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 109134 states, 109134 states have (on average 1.4130243553796251) internal successors, (154209), 109133 states have internal predecessors, (154209), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:32,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109134 states to 109134 states and 154209 transitions. [2022-12-13 20:32:32,337 INFO L240 hiAutomatonCegarLoop]: Abstraction has 109134 states and 154209 transitions. [2022-12-13 20:32:32,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:32:32,338 INFO L428 stractBuchiCegarLoop]: Abstraction has 109134 states and 154209 transitions. [2022-12-13 20:32:32,338 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 20:32:32,338 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 109134 states and 154209 transitions. [2022-12-13 20:32:32,718 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108736 [2022-12-13 20:32:32,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:32,718 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:32,722 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:32,722 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:32,722 INFO L748 eck$LassoCheckResult]: Stem: 1080337#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1080338#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1081226#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1081227#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1080844#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1080537#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1080538#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1081195#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1081260#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1081246#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1081247#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1080673#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1080660#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1080661#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1080460#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1080461#L951 assume !(0 == ~M_E~0); 1080204#L951-2 assume !(0 == ~T1_E~0); 1080205#L956-1 assume !(0 == ~T2_E~0); 1080357#L961-1 assume !(0 == ~T3_E~0); 1080865#L966-1 assume !(0 == ~T4_E~0); 1080866#L971-1 assume !(0 == ~T5_E~0); 1081016#L976-1 assume !(0 == ~T6_E~0); 1080985#L981-1 assume !(0 == ~T7_E~0); 1080714#L986-1 assume !(0 == ~T8_E~0); 1080410#L991-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1080411#L996-1 assume !(0 == ~E_M~0); 1081424#L1001-1 assume !(0 == ~E_1~0); 1080930#L1006-1 assume !(0 == ~E_2~0); 1080931#L1011-1 assume !(0 == ~E_3~0); 1081283#L1016-1 assume !(0 == ~E_4~0); 1081284#L1021-1 assume !(0 == ~E_5~0); 1079996#L1026-1 assume !(0 == ~E_6~0); 1079997#L1031-1 assume !(0 == ~E_7~0); 1080875#L1036-1 assume !(0 == ~E_8~0); 1080876#L1041-1 assume !(0 == ~E_9~0); 1081206#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1081207#L472 assume !(1 == ~m_pc~0); 1081145#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1081146#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1081122#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1081123#L1179 assume !(0 != activate_threads_~tmp~1#1); 1080005#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1080006#L491 assume !(1 == ~t1_pc~0); 1080507#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1080508#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1081423#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1079977#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1079978#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1081189#L510 assume !(1 == ~t2_pc~0); 1081176#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1081421#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1080526#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1080527#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1080254#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1080255#L529 assume !(1 == ~t3_pc~0); 1081046#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1081047#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1079975#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1079976#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1080177#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1080178#L548 assume !(1 == ~t4_pc~0); 1080067#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1080066#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1080140#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1080141#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1080998#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1080999#L567 assume !(1 == ~t5_pc~0); 1080111#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1080112#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1081125#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1081126#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1081327#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1080188#L586 assume !(1 == ~t6_pc~0); 1080189#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1081419#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1080514#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1080515#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1081177#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1081178#L605 assume !(1 == ~t7_pc~0); 1080692#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1080693#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1081378#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1081379#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1081366#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1080835#L624 assume !(1 == ~t8_pc~0); 1080836#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1080968#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1080969#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1081153#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1081154#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1080020#L643 assume !(1 == ~t9_pc~0); 1080021#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1081321#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1080585#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1080586#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1081382#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1080233#L1059 assume !(1 == ~M_E~0); 1080234#L1059-2 assume !(1 == ~T1_E~0); 1080387#L1064-1 assume !(1 == ~T2_E~0); 1080388#L1069-1 assume !(1 == ~T3_E~0); 1081359#L1074-1 assume !(1 == ~T4_E~0); 1081360#L1079-1 assume !(1 == ~T5_E~0); 1081130#L1084-1 assume !(1 == ~T6_E~0); 1081131#L1089-1 assume !(1 == ~T7_E~0); 1081170#L1094-1 assume !(1 == ~T8_E~0); 1081171#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1080756#L1104-1 assume !(1 == ~E_M~0); 1080974#L1109-1 assume !(1 == ~E_1~0); 1080528#L1114-1 assume !(1 == ~E_2~0); 1080529#L1119-1 assume !(1 == ~E_3~0); 1080598#L1124-1 assume !(1 == ~E_4~0); 1080018#L1129-1 assume !(1 == ~E_5~0); 1080019#L1134-1 assume !(1 == ~E_6~0); 1080355#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1080356#L1144-1 assume !(1 == ~E_8~0); 1080548#L1149-1 assume !(1 == ~E_9~0); 1080194#L1154-1 assume { :end_inline_reset_delta_events } true; 1080195#L1440-2 [2022-12-13 20:32:32,723 INFO L750 eck$LassoCheckResult]: Loop: 1080195#L1440-2 assume !false; 1172113#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1172105#L926 assume !false; 1172102#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1172074#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1172060#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1172055#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1172049#L795 assume !(0 != eval_~tmp~0#1); 1172050#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1177380#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1177378#L951-3 assume !(0 == ~M_E~0); 1177376#L951-5 assume !(0 == ~T1_E~0); 1177374#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1177372#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1177370#L966-3 assume !(0 == ~T4_E~0); 1177367#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1177365#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1177363#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1177354#L986-3 assume !(0 == ~T8_E~0); 1177124#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1177125#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1177118#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1177119#L1006-3 assume !(0 == ~E_2~0); 1177111#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1177112#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1177106#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1177107#L1026-3 assume !(0 == ~E_6~0); 1177086#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1177087#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1177080#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1177081#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1177073#L472-33 assume !(1 == ~m_pc~0); 1177074#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1177067#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1177068#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1177061#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1177062#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1177035#L491-33 assume !(1 == ~t1_pc~0); 1177031#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1177028#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1177024#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1177020#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1177016#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1177011#L510-33 assume !(1 == ~t2_pc~0); 1177006#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1177002#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1176997#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1176992#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1176788#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1151161#L529-33 assume !(1 == ~t3_pc~0); 1151160#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1151158#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1151154#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1151150#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 1151147#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1151142#L548-33 assume 1 == ~t4_pc~0; 1151143#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1151133#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1151134#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1151127#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1151128#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1151119#L567-33 assume !(1 == ~t5_pc~0); 1151120#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1151111#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1151112#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1151102#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1151103#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1151093#L586-33 assume !(1 == ~t6_pc~0); 1151095#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1151084#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1151085#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1151076#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1151077#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1151067#L605-33 assume !(1 == ~t7_pc~0); 1134487#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1151061#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1151062#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1151057#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1151058#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1151042#L624-33 assume 1 == ~t8_pc~0; 1151043#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1151035#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1151036#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1151025#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1151026#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1145905#L643-33 assume !(1 == ~t9_pc~0); 1145903#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1145901#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1145899#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1145897#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1145896#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1145894#L1059-3 assume !(1 == ~M_E~0); 1115003#L1059-5 assume !(1 == ~T1_E~0); 1145891#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1127818#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1127817#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1127816#L1079-3 assume !(1 == ~T5_E~0); 1127815#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1127814#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1127813#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1127775#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1127772#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1127770#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1127325#L1114-3 assume !(1 == ~E_2~0); 1127323#L1119-3 assume !(1 == ~E_3~0); 1127321#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1127319#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1127317#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1127315#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1127313#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1127309#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1127307#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1127301#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1127291#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1127289#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1114521#L1459 assume !(0 == start_simulation_~tmp~3#1); 1114522#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1172194#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1172178#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1172172#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1172164#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1172155#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1172145#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1172134#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1080195#L1440-2 [2022-12-13 20:32:32,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:32,723 INFO L85 PathProgramCache]: Analyzing trace with hash -1773294265, now seen corresponding path program 1 times [2022-12-13 20:32:32,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:32,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250517299] [2022-12-13 20:32:32,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:32,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:32,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:32,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:32,763 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:32,763 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250517299] [2022-12-13 20:32:32,763 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [250517299] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:32,763 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:32,763 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:32,763 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537016688] [2022-12-13 20:32:32,763 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:32,764 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:32,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:32,764 INFO L85 PathProgramCache]: Analyzing trace with hash 237198924, now seen corresponding path program 2 times [2022-12-13 20:32:32,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:32,764 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474960551] [2022-12-13 20:32:32,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:32,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:32,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:32,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:32,788 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:32,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1474960551] [2022-12-13 20:32:32,788 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1474960551] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:32,788 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:32,788 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:32,788 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228018110] [2022-12-13 20:32:32,788 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:32,789 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:32,789 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:32,789 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:32:32,789 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:32:32,789 INFO L87 Difference]: Start difference. First operand 109134 states and 154209 transitions. cyclomatic complexity: 45079 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:33,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:33,097 INFO L93 Difference]: Finished difference Result 143129 states and 201066 transitions. [2022-12-13 20:32:33,097 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 143129 states and 201066 transitions. [2022-12-13 20:32:33,666 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 142720 [2022-12-13 20:32:33,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 143129 states to 143129 states and 201066 transitions. [2022-12-13 20:32:33,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 143129 [2022-12-13 20:32:33,947 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 143129 [2022-12-13 20:32:33,947 INFO L73 IsDeterministic]: Start isDeterministic. Operand 143129 states and 201066 transitions. [2022-12-13 20:32:33,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:33,993 INFO L218 hiAutomatonCegarLoop]: Abstraction has 143129 states and 201066 transitions. [2022-12-13 20:32:34,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143129 states and 201066 transitions. [2022-12-13 20:32:34,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143129 to 97785. [2022-12-13 20:32:34,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97785 states, 97785 states have (on average 1.4075983023981182) internal successors, (137642), 97784 states have internal predecessors, (137642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:35,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97785 states to 97785 states and 137642 transitions. [2022-12-13 20:32:35,128 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97785 states and 137642 transitions. [2022-12-13 20:32:35,128 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:32:35,129 INFO L428 stractBuchiCegarLoop]: Abstraction has 97785 states and 137642 transitions. [2022-12-13 20:32:35,129 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 20:32:35,129 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97785 states and 137642 transitions. [2022-12-13 20:32:35,469 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97472 [2022-12-13 20:32:35,469 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:35,469 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:35,473 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:35,473 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:35,473 INFO L748 eck$LassoCheckResult]: Stem: 1332602#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1332603#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1333458#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1333459#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1333105#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1332802#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1332803#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1333424#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1333488#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1333475#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1333476#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1332938#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1332924#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1332925#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1332726#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1332727#L951 assume !(0 == ~M_E~0); 1332472#L951-2 assume !(0 == ~T1_E~0); 1332473#L956-1 assume !(0 == ~T2_E~0); 1332624#L961-1 assume !(0 == ~T3_E~0); 1333126#L966-1 assume !(0 == ~T4_E~0); 1333127#L971-1 assume !(0 == ~T5_E~0); 1333265#L976-1 assume !(0 == ~T6_E~0); 1333238#L981-1 assume !(0 == ~T7_E~0); 1332981#L986-1 assume !(0 == ~T8_E~0); 1332675#L991-1 assume !(0 == ~T9_E~0); 1332676#L996-1 assume !(0 == ~E_M~0); 1333529#L1001-1 assume !(0 == ~E_1~0); 1333183#L1006-1 assume !(0 == ~E_2~0); 1333184#L1011-1 assume !(0 == ~E_3~0); 1333489#L1016-1 assume !(0 == ~E_4~0); 1333508#L1021-1 assume !(0 == ~E_5~0); 1332269#L1026-1 assume !(0 == ~E_6~0); 1332270#L1031-1 assume !(0 == ~E_7~0); 1333136#L1036-1 assume !(0 == ~E_8~0); 1333134#L1041-1 assume !(0 == ~E_9~0); 1333135#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1333439#L472 assume !(1 == ~m_pc~0); 1333378#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1333162#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1333163#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1333174#L1179 assume !(0 != activate_threads_~tmp~1#1); 1332277#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1332278#L491 assume !(1 == ~t1_pc~0); 1332772#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1332773#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1332300#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1332250#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1332251#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1332273#L510 assume !(1 == ~t2_pc~0); 1332239#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1332240#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1332791#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1332792#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1332522#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1332523#L529 assume !(1 == ~t3_pc~0); 1332987#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1333290#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1332248#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1332249#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1332445#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1332446#L548 assume !(1 == ~t4_pc~0); 1332336#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1332335#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1332410#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1332380#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1332381#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1332326#L567 assume !(1 == ~t5_pc~0); 1332327#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1332382#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1333359#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1333360#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1333417#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1332456#L586 assume !(1 == ~t6_pc~0); 1332457#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1332526#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1332776#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1332777#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1333411#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1333412#L605 assume !(1 == ~t7_pc~0); 1332958#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1332959#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1333165#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1333579#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1333574#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1333098#L624 assume !(1 == ~t8_pc~0); 1332517#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1332516#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1333222#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1333285#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1333385#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1332292#L643 assume !(1 == ~t9_pc~0); 1332293#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1333320#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1332849#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1332680#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1332681#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1332501#L1059 assume !(1 == ~M_E~0); 1332502#L1059-2 assume !(1 == ~T1_E~0); 1332653#L1064-1 assume !(1 == ~T2_E~0); 1332654#L1069-1 assume !(1 == ~T3_E~0); 1333330#L1074-1 assume !(1 == ~T4_E~0); 1333383#L1079-1 assume !(1 == ~T5_E~0); 1333364#L1084-1 assume !(1 == ~T6_E~0); 1333365#L1089-1 assume !(1 == ~T7_E~0); 1333406#L1094-1 assume !(1 == ~T8_E~0); 1333020#L1099-1 assume !(1 == ~T9_E~0); 1333021#L1104-1 assume !(1 == ~E_M~0); 1333227#L1109-1 assume !(1 == ~E_1~0); 1332793#L1114-1 assume !(1 == ~E_2~0); 1332794#L1119-1 assume !(1 == ~E_3~0); 1332863#L1124-1 assume !(1 == ~E_4~0); 1332288#L1129-1 assume !(1 == ~E_5~0); 1332289#L1134-1 assume !(1 == ~E_6~0); 1332620#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1332621#L1144-1 assume !(1 == ~E_8~0); 1332813#L1149-1 assume !(1 == ~E_9~0); 1332462#L1154-1 assume { :end_inline_reset_delta_events } true; 1332463#L1440-2 [2022-12-13 20:32:35,473 INFO L750 eck$LassoCheckResult]: Loop: 1332463#L1440-2 assume !false; 1332589#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1332695#L926 assume !false; 1332864#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1332865#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1332543#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1332544#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1332554#L795 assume !(0 != eval_~tmp~0#1); 1332555#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1429737#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1429736#L951-3 assume !(0 == ~M_E~0); 1429735#L951-5 assume !(0 == ~T1_E~0); 1429734#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1429733#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1429732#L966-3 assume !(0 == ~T4_E~0); 1429730#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1429729#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1429728#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1429727#L986-3 assume !(0 == ~T8_E~0); 1429725#L991-3 assume !(0 == ~T9_E~0); 1429723#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1429721#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1429719#L1006-3 assume !(0 == ~E_2~0); 1429717#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1429715#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1429713#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1429711#L1026-3 assume !(0 == ~E_6~0); 1429709#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1429707#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1429705#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1429703#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1429701#L472-33 assume !(1 == ~m_pc~0); 1429699#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1429697#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1429695#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1429693#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1429691#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1426249#L491-33 assume !(1 == ~t1_pc~0); 1426247#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1426245#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1426243#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1426241#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1426240#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1426239#L510-33 assume !(1 == ~t2_pc~0); 1426173#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1426172#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1426171#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1426170#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1425723#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1399957#L529-33 assume !(1 == ~t3_pc~0); 1399955#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1399953#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1399951#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1399949#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 1399947#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1399945#L548-33 assume !(1 == ~t4_pc~0); 1399943#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1399940#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1399938#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1399936#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1399934#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1399932#L567-33 assume !(1 == ~t5_pc~0); 1399930#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1399928#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1399926#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1399924#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1399922#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1399920#L586-33 assume 1 == ~t6_pc~0; 1399917#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1399915#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1399913#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1399911#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1399909#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1399907#L605-33 assume !(1 == ~t7_pc~0); 1399467#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1399903#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1399901#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1399899#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1399897#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1399895#L624-33 assume 1 == ~t8_pc~0; 1399893#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1399891#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1399889#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1399887#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1399885#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1376821#L643-33 assume !(1 == ~t9_pc~0); 1376819#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1376817#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1376815#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1376813#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1376811#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1376809#L1059-3 assume !(1 == ~M_E~0); 1376439#L1059-5 assume !(1 == ~T1_E~0); 1376805#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1376803#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1376801#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1376799#L1079-3 assume !(1 == ~T5_E~0); 1376797#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1376796#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1376795#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1376794#L1099-3 assume !(1 == ~T9_E~0); 1376793#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1376792#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1376791#L1114-3 assume !(1 == ~E_2~0); 1376790#L1119-3 assume !(1 == ~E_3~0); 1376789#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1376788#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1376787#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1376785#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1376783#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1376781#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1376779#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1376773#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1376763#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1376761#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1376759#L1459 assume !(0 == start_simulation_~tmp~3#1); 1333339#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1333340#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1332546#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1332294#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1332295#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1332705#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1332880#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1333048#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1332463#L1440-2 [2022-12-13 20:32:35,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:35,474 INFO L85 PathProgramCache]: Analyzing trace with hash 1896329479, now seen corresponding path program 1 times [2022-12-13 20:32:35,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:35,474 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438737123] [2022-12-13 20:32:35,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:35,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:35,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:35,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:35,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:35,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438737123] [2022-12-13 20:32:35,531 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1438737123] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:35,531 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:35,531 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:35,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [173987959] [2022-12-13 20:32:35,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:35,531 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:35,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:35,532 INFO L85 PathProgramCache]: Analyzing trace with hash 1118988428, now seen corresponding path program 1 times [2022-12-13 20:32:35,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:35,532 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [518304936] [2022-12-13 20:32:35,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:35,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:35,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:35,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:35,563 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:35,563 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [518304936] [2022-12-13 20:32:35,563 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [518304936] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:35,563 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:35,563 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:35,563 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [714396395] [2022-12-13 20:32:35,563 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:35,564 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:35,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:35,564 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:32:35,564 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:32:35,564 INFO L87 Difference]: Start difference. First operand 97785 states and 137642 transitions. cyclomatic complexity: 39861 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:35,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:35,960 INFO L93 Difference]: Finished difference Result 151249 states and 212051 transitions. [2022-12-13 20:32:35,961 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151249 states and 212051 transitions. [2022-12-13 20:32:36,574 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 150688 [2022-12-13 20:32:36,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151249 states to 151249 states and 212051 transitions. [2022-12-13 20:32:36,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 151249 [2022-12-13 20:32:36,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 151249 [2022-12-13 20:32:36,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 151249 states and 212051 transitions. [2022-12-13 20:32:36,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:36,878 INFO L218 hiAutomatonCegarLoop]: Abstraction has 151249 states and 212051 transitions. [2022-12-13 20:32:36,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151249 states and 212051 transitions. [2022-12-13 20:32:37,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151249 to 109070. [2022-12-13 20:32:37,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 109070 states, 109070 states have (on average 1.4038507380581278) internal successors, (153118), 109069 states have internal predecessors, (153118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:37,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109070 states to 109070 states and 153118 transitions. [2022-12-13 20:32:37,896 INFO L240 hiAutomatonCegarLoop]: Abstraction has 109070 states and 153118 transitions. [2022-12-13 20:32:37,897 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:32:37,897 INFO L428 stractBuchiCegarLoop]: Abstraction has 109070 states and 153118 transitions. [2022-12-13 20:32:37,897 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 20:32:37,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 109070 states and 153118 transitions. [2022-12-13 20:32:38,164 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108672 [2022-12-13 20:32:38,164 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:38,164 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:38,169 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:38,169 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:38,169 INFO L748 eck$LassoCheckResult]: Stem: 1581647#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1581648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1582497#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1582498#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1582143#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1581850#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1581851#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1582470#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1582530#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1582517#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1582518#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1581984#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1581970#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1581971#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1581772#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1581773#L951 assume !(0 == ~M_E~0); 1581516#L951-2 assume !(0 == ~T1_E~0); 1581517#L956-1 assume !(0 == ~T2_E~0); 1581667#L961-1 assume !(0 == ~T3_E~0); 1582163#L966-1 assume !(0 == ~T4_E~0); 1582164#L971-1 assume !(0 == ~T5_E~0); 1582308#L976-1 assume !(0 == ~T6_E~0); 1582281#L981-1 assume !(0 == ~T7_E~0); 1582024#L986-1 assume !(0 == ~T8_E~0); 1581719#L991-1 assume !(0 == ~T9_E~0); 1581720#L996-1 assume !(0 == ~E_M~0); 1582572#L1001-1 assume !(0 == ~E_1~0); 1582227#L1006-1 assume !(0 == ~E_2~0); 1582228#L1011-1 assume !(0 == ~E_3~0); 1582532#L1016-1 assume !(0 == ~E_4~0); 1582548#L1021-1 assume !(0 == ~E_5~0); 1581313#L1026-1 assume !(0 == ~E_6~0); 1581314#L1031-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1582653#L1036-1 assume !(0 == ~E_8~0); 1582171#L1041-1 assume !(0 == ~E_9~0); 1582172#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1582480#L472 assume !(1 == ~m_pc~0); 1582707#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1582204#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1582205#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1582215#L1179 assume !(0 != activate_threads_~tmp~1#1); 1582216#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1582706#L491 assume !(1 == ~t1_pc~0); 1581818#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1581819#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1582705#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1581294#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1581295#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1582704#L510 assume !(1 == ~t2_pc~0); 1582702#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1582701#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1581839#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1581840#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1581567#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1581568#L529 assume !(1 == ~t3_pc~0); 1582030#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1582338#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1581292#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1581293#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1582696#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1582635#L548 assume !(1 == ~t4_pc~0); 1581383#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1581382#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1581678#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1581429#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1581430#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1581371#L567 assume !(1 == ~t5_pc~0); 1581372#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1582626#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1582409#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1582410#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1582464#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1581502#L586 assume !(1 == ~t6_pc~0); 1581503#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1582686#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1581824#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1581825#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1582685#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1582634#L605 assume !(1 == ~t7_pc~0); 1582003#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1582004#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1582630#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1582631#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1582622#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1582135#L624 assume !(1 == ~t8_pc~0); 1582136#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1582263#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1582264#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1582334#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1582431#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1582680#L643 assume !(1 == ~t9_pc~0); 1582679#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1582678#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1582677#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1582676#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1582633#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1581547#L1059 assume !(1 == ~M_E~0); 1581548#L1059-2 assume !(1 == ~T1_E~0); 1582674#L1064-1 assume !(1 == ~T2_E~0); 1582673#L1069-1 assume !(1 == ~T3_E~0); 1582617#L1074-1 assume !(1 == ~T4_E~0); 1582429#L1079-1 assume !(1 == ~T5_E~0); 1582414#L1084-1 assume !(1 == ~T6_E~0); 1582415#L1089-1 assume !(1 == ~T7_E~0); 1582450#L1094-1 assume !(1 == ~T8_E~0); 1582059#L1099-1 assume !(1 == ~T9_E~0); 1582060#L1104-1 assume !(1 == ~E_M~0); 1582267#L1109-1 assume !(1 == ~E_1~0); 1582268#L1114-1 assume !(1 == ~E_2~0); 1582636#L1119-1 assume !(1 == ~E_3~0); 1581907#L1124-1 assume !(1 == ~E_4~0); 1581333#L1129-1 assume !(1 == ~E_5~0); 1581334#L1134-1 assume !(1 == ~E_6~0); 1582663#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1581664#L1144-1 assume !(1 == ~E_8~0); 1581860#L1149-1 assume !(1 == ~E_9~0); 1581508#L1154-1 assume { :end_inline_reset_delta_events } true; 1581509#L1440-2 [2022-12-13 20:32:38,169 INFO L750 eck$LassoCheckResult]: Loop: 1581509#L1440-2 assume !false; 1632249#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1632242#L926 assume !false; 1632240#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1632199#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1632185#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1632178#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1632169#L795 assume !(0 != eval_~tmp~0#1); 1632170#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1633906#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1633905#L951-3 assume !(0 == ~M_E~0); 1633904#L951-5 assume !(0 == ~T1_E~0); 1633903#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1633902#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1633901#L966-3 assume !(0 == ~T4_E~0); 1633900#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1633899#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1633898#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1633897#L986-3 assume !(0 == ~T8_E~0); 1633894#L991-3 assume !(0 == ~T9_E~0); 1633891#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1633888#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1633884#L1006-3 assume !(0 == ~E_2~0); 1633881#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1633878#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1633875#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1633872#L1026-3 assume !(0 == ~E_6~0); 1624950#L1031-3 assume !(0 == ~E_7~0); 1624952#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1633744#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1633742#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1633738#L472-33 assume !(1 == ~m_pc~0); 1633735#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1633732#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1633728#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1633725#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1633722#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1633720#L491-33 assume !(1 == ~t1_pc~0); 1632182#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1633717#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1633716#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1633715#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1633714#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1633713#L510-33 assume !(1 == ~t2_pc~0); 1633711#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1633709#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1633708#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1633707#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1633706#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1633705#L529-33 assume !(1 == ~t3_pc~0); 1631801#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1633704#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1633701#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1633699#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 1633697#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1633694#L548-33 assume 1 == ~t4_pc~0; 1633690#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1633687#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1633683#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1633680#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1633677#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1633674#L567-33 assume !(1 == ~t5_pc~0); 1633671#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1633667#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1633664#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1633661#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1633658#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1633655#L586-33 assume 1 == ~t6_pc~0; 1633651#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1633647#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1633642#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1633638#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1633634#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1621359#L605-33 assume !(1 == ~t7_pc~0); 1621357#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1621354#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1621352#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1621350#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1621348#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1621346#L624-33 assume 1 == ~t8_pc~0; 1621343#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1621341#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1621339#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1621337#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1621335#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1613524#L643-33 assume !(1 == ~t9_pc~0); 1613520#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1613518#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1613516#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1613510#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1613508#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1613506#L1059-3 assume !(1 == ~M_E~0); 1600409#L1059-5 assume !(1 == ~T1_E~0); 1613505#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1613504#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1613493#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1613491#L1079-3 assume !(1 == ~T5_E~0); 1613489#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1613486#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1613484#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1613482#L1099-3 assume !(1 == ~T9_E~0); 1613480#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1613478#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1613476#L1114-3 assume !(1 == ~E_2~0); 1613474#L1119-3 assume !(1 == ~E_3~0); 1613472#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1613470#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1613468#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1613466#L1139-3 assume !(1 == ~E_7~0); 1613463#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1613461#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1613459#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1613453#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1613443#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1606914#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1600313#L1459 assume !(0 == start_simulation_~tmp~3#1); 1600314#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1632300#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1632291#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1632290#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1632288#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1632285#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1632274#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1632265#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1581509#L1440-2 [2022-12-13 20:32:38,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:38,170 INFO L85 PathProgramCache]: Analyzing trace with hash 19846661, now seen corresponding path program 1 times [2022-12-13 20:32:38,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:38,170 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431524649] [2022-12-13 20:32:38,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:38,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:38,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:38,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:38,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:38,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431524649] [2022-12-13 20:32:38,207 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [431524649] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:38,207 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:38,207 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:38,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1313474153] [2022-12-13 20:32:38,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:38,208 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:38,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:38,208 INFO L85 PathProgramCache]: Analyzing trace with hash 561362315, now seen corresponding path program 1 times [2022-12-13 20:32:38,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:38,208 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131713737] [2022-12-13 20:32:38,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:38,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:38,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:38,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:38,233 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:38,233 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1131713737] [2022-12-13 20:32:38,233 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1131713737] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:38,233 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:38,233 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:38,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [275700233] [2022-12-13 20:32:38,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:38,234 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:38,234 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:38,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:32:38,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:32:38,234 INFO L87 Difference]: Start difference. First operand 109070 states and 153118 transitions. cyclomatic complexity: 44052 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:38,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:38,778 INFO L93 Difference]: Finished difference Result 138777 states and 194040 transitions. [2022-12-13 20:32:38,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 138777 states and 194040 transitions. [2022-12-13 20:32:39,271 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 138304 [2022-12-13 20:32:39,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 138777 states to 138777 states and 194040 transitions. [2022-12-13 20:32:39,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 138777 [2022-12-13 20:32:39,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 138777 [2022-12-13 20:32:39,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 138777 states and 194040 transitions. [2022-12-13 20:32:39,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:39,666 INFO L218 hiAutomatonCegarLoop]: Abstraction has 138777 states and 194040 transitions. [2022-12-13 20:32:39,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138777 states and 194040 transitions. [2022-12-13 20:32:40,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138777 to 97785. [2022-12-13 20:32:40,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97785 states, 97785 states have (on average 1.3984148898092754) internal successors, (136744), 97784 states have internal predecessors, (136744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:40,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97785 states to 97785 states and 136744 transitions. [2022-12-13 20:32:40,682 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97785 states and 136744 transitions. [2022-12-13 20:32:40,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:32:40,683 INFO L428 stractBuchiCegarLoop]: Abstraction has 97785 states and 136744 transitions. [2022-12-13 20:32:40,683 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 20:32:40,683 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97785 states and 136744 transitions. [2022-12-13 20:32:40,912 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97472 [2022-12-13 20:32:40,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:40,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:40,915 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:40,915 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:40,915 INFO L748 eck$LassoCheckResult]: Stem: 1829498#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1829499#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1830410#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1830411#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1830022#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1829704#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1829705#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1830369#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1830449#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1830430#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1830431#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1829845#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1829832#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1829833#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1829621#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1829622#L951 assume !(0 == ~M_E~0); 1829368#L951-2 assume !(0 == ~T1_E~0); 1829369#L956-1 assume !(0 == ~T2_E~0); 1829520#L961-1 assume !(0 == ~T3_E~0); 1830041#L966-1 assume !(0 == ~T4_E~0); 1830042#L971-1 assume !(0 == ~T5_E~0); 1830191#L976-1 assume !(0 == ~T6_E~0); 1830164#L981-1 assume !(0 == ~T7_E~0); 1829887#L986-1 assume !(0 == ~T8_E~0); 1829572#L991-1 assume !(0 == ~T9_E~0); 1829573#L996-1 assume !(0 == ~E_M~0); 1830495#L1001-1 assume !(0 == ~E_1~0); 1830102#L1006-1 assume !(0 == ~E_2~0); 1830103#L1011-1 assume !(0 == ~E_3~0); 1830450#L1016-1 assume !(0 == ~E_4~0); 1830473#L1021-1 assume !(0 == ~E_5~0); 1829170#L1026-1 assume !(0 == ~E_6~0); 1829171#L1031-1 assume !(0 == ~E_7~0); 1830055#L1036-1 assume !(0 == ~E_8~0); 1830051#L1041-1 assume !(0 == ~E_9~0); 1830052#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1830384#L472 assume !(1 == ~m_pc~0); 1830311#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1830082#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1830083#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1830091#L1179 assume !(0 != activate_threads_~tmp~1#1); 1829178#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1829179#L491 assume !(1 == ~t1_pc~0); 1829672#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1829673#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1829200#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1829151#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1829152#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1829172#L510 assume !(1 == ~t2_pc~0); 1829140#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1829141#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1829693#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1829694#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1829419#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1829420#L529 assume !(1 == ~t3_pc~0); 1829896#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1830222#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1829149#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1829150#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1829344#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1829345#L548 assume !(1 == ~t4_pc~0); 1829237#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1829236#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1829308#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1829279#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1829280#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1829225#L567 assume !(1 == ~t5_pc~0); 1829226#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1829281#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1830290#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1830291#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1830361#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1829355#L586 assume !(1 == ~t6_pc~0); 1829356#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1829421#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1829678#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1829679#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1830352#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1830353#L605 assume !(1 == ~t7_pc~0); 1829862#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1829863#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1830084#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1830557#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1830552#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1830014#L624 assume !(1 == ~t8_pc~0); 1829414#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1829413#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1830146#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1830218#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1830323#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1829192#L643 assume !(1 == ~t9_pc~0); 1829193#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1830252#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1829750#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1829577#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1829578#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1829399#L1059 assume !(1 == ~M_E~0); 1829400#L1059-2 assume !(1 == ~T1_E~0); 1829550#L1064-1 assume !(1 == ~T2_E~0); 1829551#L1069-1 assume !(1 == ~T3_E~0); 1830263#L1074-1 assume !(1 == ~T4_E~0); 1830317#L1079-1 assume !(1 == ~T5_E~0); 1830297#L1084-1 assume !(1 == ~T6_E~0); 1830298#L1089-1 assume !(1 == ~T7_E~0); 1830344#L1094-1 assume !(1 == ~T8_E~0); 1829931#L1099-1 assume !(1 == ~T9_E~0); 1829932#L1104-1 assume !(1 == ~E_M~0); 1830150#L1109-1 assume !(1 == ~E_1~0); 1829695#L1114-1 assume !(1 == ~E_2~0); 1829696#L1119-1 assume !(1 == ~E_3~0); 1829762#L1124-1 assume !(1 == ~E_4~0); 1829188#L1129-1 assume !(1 == ~E_5~0); 1829189#L1134-1 assume !(1 == ~E_6~0); 1829516#L1139-1 assume !(1 == ~E_7~0); 1829517#L1144-1 assume !(1 == ~E_8~0); 1829715#L1149-1 assume !(1 == ~E_9~0); 1829361#L1154-1 assume { :end_inline_reset_delta_events } true; 1829362#L1440-2 [2022-12-13 20:32:40,916 INFO L750 eck$LassoCheckResult]: Loop: 1829362#L1440-2 assume !false; 1901909#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1901905#L926 assume !false; 1901903#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1901685#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1901668#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1901659#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1901650#L795 assume !(0 != eval_~tmp~0#1); 1901651#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1925535#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1925534#L951-3 assume !(0 == ~M_E~0); 1925532#L951-5 assume !(0 == ~T1_E~0); 1925528#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1925525#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1925522#L966-3 assume !(0 == ~T4_E~0); 1925519#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1925515#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1925512#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1925508#L986-3 assume !(0 == ~T8_E~0); 1925505#L991-3 assume !(0 == ~T9_E~0); 1925502#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1925499#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1925493#L1006-3 assume !(0 == ~E_2~0); 1925489#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1925484#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1925480#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1925476#L1026-3 assume !(0 == ~E_6~0); 1925471#L1031-3 assume !(0 == ~E_7~0); 1925466#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1925462#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1925457#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1925453#L472-33 assume !(1 == ~m_pc~0); 1925449#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1925447#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1925445#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1924723#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1923466#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1919272#L491-33 assume !(1 == ~t1_pc~0); 1919269#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1919268#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1919265#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1919263#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1919261#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1919259#L510-33 assume !(1 == ~t2_pc~0); 1919256#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1919255#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1919254#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1919250#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1919248#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1919246#L529-33 assume !(1 == ~t3_pc~0); 1916836#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1919245#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1919241#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1919240#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 1919237#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1919236#L548-33 assume !(1 == ~t4_pc~0); 1919235#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1919233#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1919227#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1919225#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1919223#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1919222#L567-33 assume !(1 == ~t5_pc~0); 1919217#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1919216#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1919215#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1919214#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1919213#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1919211#L586-33 assume 1 == ~t6_pc~0; 1919205#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1919203#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1919201#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1919200#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1919198#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1919196#L605-33 assume !(1 == ~t7_pc~0); 1916995#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1919193#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1919191#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1918398#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1918397#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1918292#L624-33 assume !(1 == ~t8_pc~0); 1918279#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1917997#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1917990#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1917980#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1917363#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1880182#L643-33 assume !(1 == ~t9_pc~0); 1880176#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1880174#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1880172#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1880171#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1880170#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1880169#L1059-3 assume !(1 == ~M_E~0); 1855352#L1059-5 assume !(1 == ~T1_E~0); 1880157#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1880155#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1880152#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1880150#L1079-3 assume !(1 == ~T5_E~0); 1880148#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1880146#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1880144#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1880142#L1099-3 assume !(1 == ~T9_E~0); 1880140#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1880138#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1880136#L1114-3 assume !(1 == ~E_2~0); 1880134#L1119-3 assume !(1 == ~E_3~0); 1880132#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1880130#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1880128#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1880126#L1139-3 assume !(1 == ~E_7~0); 1880124#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1880122#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1880120#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1880114#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1880104#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1880103#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1855568#L1459 assume !(0 == start_simulation_~tmp~3#1); 1855569#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1901959#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1901949#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1901947#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1901945#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1901942#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1901940#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1901913#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1829362#L1440-2 [2022-12-13 20:32:40,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:40,916 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 1 times [2022-12-13 20:32:40,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:40,916 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [35444199] [2022-12-13 20:32:40,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:40,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:40,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:32:40,924 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:32:40,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:32:40,978 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:32:40,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:40,979 INFO L85 PathProgramCache]: Analyzing trace with hash 825513485, now seen corresponding path program 1 times [2022-12-13 20:32:40,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:40,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339659034] [2022-12-13 20:32:40,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:40,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:40,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:41,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:41,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:41,017 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339659034] [2022-12-13 20:32:41,017 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1339659034] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:41,017 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:41,017 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:41,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [478093060] [2022-12-13 20:32:41,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:41,018 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:41,018 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:41,018 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:41,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:41,018 INFO L87 Difference]: Start difference. First operand 97785 states and 136744 transitions. cyclomatic complexity: 38963 Second operand has 3 states, 3 states have (on average 41.333333333333336) internal successors, (124), 3 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:41,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:41,431 INFO L93 Difference]: Finished difference Result 109134 states and 152731 transitions. [2022-12-13 20:32:41,432 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109134 states and 152731 transitions. [2022-12-13 20:32:41,798 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108736 [2022-12-13 20:32:42,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109134 states to 109134 states and 152731 transitions. [2022-12-13 20:32:42,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 109134 [2022-12-13 20:32:42,074 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 109134 [2022-12-13 20:32:42,074 INFO L73 IsDeterministic]: Start isDeterministic. Operand 109134 states and 152731 transitions. [2022-12-13 20:32:42,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:42,117 INFO L218 hiAutomatonCegarLoop]: Abstraction has 109134 states and 152731 transitions. [2022-12-13 20:32:42,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109134 states and 152731 transitions. [2022-12-13 20:32:42,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109134 to 109134. [2022-12-13 20:32:42,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 109134 states, 109134 states have (on average 1.3994813715249144) internal successors, (152731), 109133 states have internal predecessors, (152731), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:43,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109134 states to 109134 states and 152731 transitions. [2022-12-13 20:32:43,128 INFO L240 hiAutomatonCegarLoop]: Abstraction has 109134 states and 152731 transitions. [2022-12-13 20:32:43,129 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:43,129 INFO L428 stractBuchiCegarLoop]: Abstraction has 109134 states and 152731 transitions. [2022-12-13 20:32:43,129 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 20:32:43,129 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 109134 states and 152731 transitions. [2022-12-13 20:32:43,562 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108736 [2022-12-13 20:32:43,562 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:43,562 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:43,568 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:43,568 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:43,568 INFO L748 eck$LassoCheckResult]: Stem: 2036430#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2036431#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2037330#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2037331#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2036942#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 2036634#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2036635#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2037291#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2037369#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2037348#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2037349#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2036776#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2036761#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2036762#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2036556#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2036557#L951 assume !(0 == ~M_E~0); 2036299#L951-2 assume !(0 == ~T1_E~0); 2036300#L956-1 assume !(0 == ~T2_E~0); 2036452#L961-1 assume !(0 == ~T3_E~0); 2036961#L966-1 assume !(0 == ~T4_E~0); 2036962#L971-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2037113#L976-1 assume !(0 == ~T6_E~0); 2037456#L981-1 assume !(0 == ~T7_E~0); 2036816#L986-1 assume !(0 == ~T8_E~0); 2036505#L991-1 assume !(0 == ~T9_E~0); 2036506#L996-1 assume !(0 == ~E_M~0); 2037563#L1001-1 assume !(0 == ~E_1~0); 2037026#L1006-1 assume !(0 == ~E_2~0); 2037027#L1011-1 assume !(0 == ~E_3~0); 2037370#L1016-1 assume !(0 == ~E_4~0); 2037391#L1021-1 assume !(0 == ~E_5~0); 2036095#L1026-1 assume !(0 == ~E_6~0); 2036096#L1031-1 assume !(0 == ~E_7~0); 2036971#L1036-1 assume !(0 == ~E_8~0); 2036972#L1041-1 assume !(0 == ~E_9~0); 2037560#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2037460#L472 assume !(1 == ~m_pc~0); 2037235#L472-2 is_master_triggered_~__retres1~0#1 := 0; 2037236#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2037558#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2037014#L1179 assume !(0 != activate_threads_~tmp~1#1); 2037015#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2037557#L491 assume !(1 == ~t1_pc~0); 2036601#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2036602#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2037556#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2037555#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 2036097#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2036098#L510 assume !(1 == ~t2_pc~0); 2036065#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2036066#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2037409#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2037499#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 2037500#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2037550#L529 assume !(1 == ~t3_pc~0); 2037549#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2037548#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2037547#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2037454#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 2036274#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2036275#L548 assume !(1 == ~t4_pc~0); 2037545#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2037543#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2036237#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2036238#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 2037542#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2037541#L567 assume !(1 == ~t5_pc~0); 2036208#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2036209#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2037540#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2037539#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 2037538#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2037537#L586 assume !(1 == ~t6_pc~0); 2036353#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2036354#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2036607#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2036608#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 2037274#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2037275#L605 assume !(1 == ~t7_pc~0); 2037532#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2037005#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2037006#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2037470#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 2037471#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2037529#L624 assume !(1 == ~t8_pc~0); 2036345#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2036344#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2037069#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2037141#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 2037243#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2036119#L643 assume !(1 == ~t9_pc~0); 2036120#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2037172#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2036681#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2036510#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 2036511#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2036330#L1059 assume !(1 == ~M_E~0); 2036331#L1059-2 assume !(1 == ~T1_E~0); 2036483#L1064-1 assume !(1 == ~T2_E~0); 2036484#L1069-1 assume !(1 == ~T3_E~0); 2037183#L1074-1 assume !(1 == ~T4_E~0); 2037239#L1079-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2037218#L1084-1 assume !(1 == ~T6_E~0); 2037219#L1089-1 assume !(1 == ~T7_E~0); 2037268#L1094-1 assume !(1 == ~T8_E~0); 2036855#L1099-1 assume !(1 == ~T9_E~0); 2036856#L1104-1 assume !(1 == ~E_M~0); 2037073#L1109-1 assume !(1 == ~E_1~0); 2036625#L1114-1 assume !(1 == ~E_2~0); 2036626#L1119-1 assume !(1 == ~E_3~0); 2036693#L1124-1 assume !(1 == ~E_4~0); 2036115#L1129-1 assume !(1 == ~E_5~0); 2036116#L1134-1 assume !(1 == ~E_6~0); 2036448#L1139-1 assume !(1 == ~E_7~0); 2036449#L1144-1 assume !(1 == ~E_8~0); 2036644#L1149-1 assume !(1 == ~E_9~0); 2036291#L1154-1 assume { :end_inline_reset_delta_events } true; 2036292#L1440-2 [2022-12-13 20:32:43,569 INFO L750 eck$LassoCheckResult]: Loop: 2036292#L1440-2 assume !false; 2099493#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2099482#L926 assume !false; 2099479#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2099444#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2099429#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2099423#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2099417#L795 assume !(0 != eval_~tmp~0#1); 2099418#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2135285#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2135284#L951-3 assume !(0 == ~M_E~0); 2135283#L951-5 assume !(0 == ~T1_E~0); 2135282#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2135281#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2135280#L966-3 assume !(0 == ~T4_E~0); 2135277#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2135278#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2142028#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2142027#L986-3 assume !(0 == ~T8_E~0); 2142026#L991-3 assume !(0 == ~T9_E~0); 2142025#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2142024#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2142023#L1006-3 assume !(0 == ~E_2~0); 2142022#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2142021#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2142020#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2142019#L1026-3 assume !(0 == ~E_6~0); 2142018#L1031-3 assume !(0 == ~E_7~0); 2142017#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2142016#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2142015#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2142014#L472-33 assume !(1 == ~m_pc~0); 2142013#L472-35 is_master_triggered_~__retres1~0#1 := 0; 2133748#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2133746#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2133744#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2133742#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2130997#L491-33 assume !(1 == ~t1_pc~0); 2130995#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2130993#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2130991#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2130989#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2130988#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2130987#L510-33 assume !(1 == ~t2_pc~0); 2130985#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 2130981#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2130979#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2130977#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 2130976#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2130975#L529-33 assume !(1 == ~t3_pc~0); 2105805#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2130974#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2130973#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2130972#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 2130970#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2130968#L548-33 assume 1 == ~t4_pc~0; 2130965#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2130963#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2130961#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2130959#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2130957#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2130954#L567-33 assume !(1 == ~t5_pc~0); 2130952#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2130950#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2130948#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2130946#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2130944#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2130943#L586-33 assume 1 == ~t6_pc~0; 2130940#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2130938#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2130936#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2130934#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2130933#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2130932#L605-33 assume !(1 == ~t7_pc~0); 2098308#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2130927#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2130925#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2130924#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2130923#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2130922#L624-33 assume 1 == ~t8_pc~0; 2130920#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2130919#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2130918#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2130917#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2130916#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2099937#L643-33 assume !(1 == ~t9_pc~0); 2099932#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2099927#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2099924#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2099919#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2099914#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2099909#L1059-3 assume !(1 == ~M_E~0); 2097491#L1059-5 assume !(1 == ~T1_E~0); 2099901#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2099898#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2099871#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2099866#L1079-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2099863#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2099861#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2099859#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2099857#L1099-3 assume !(1 == ~T9_E~0); 2099855#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2099853#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2099851#L1114-3 assume !(1 == ~E_2~0); 2099849#L1119-3 assume !(1 == ~E_3~0); 2099846#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2099844#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2099842#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2099840#L1139-3 assume !(1 == ~E_7~0); 2099838#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2099837#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2099820#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2099768#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2099754#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2099748#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2099742#L1459 assume !(0 == start_simulation_~tmp~3#1); 2099738#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2099530#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2099520#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2099518#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2099515#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2099514#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2099510#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 2099508#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 2036292#L1440-2 [2022-12-13 20:32:43,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:43,569 INFO L85 PathProgramCache]: Analyzing trace with hash 1316386309, now seen corresponding path program 1 times [2022-12-13 20:32:43,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:43,569 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583440491] [2022-12-13 20:32:43,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:43,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:43,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:43,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:43,617 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:43,617 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [583440491] [2022-12-13 20:32:43,617 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [583440491] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:43,617 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:43,618 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:43,618 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1102936106] [2022-12-13 20:32:43,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:43,618 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:43,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:43,619 INFO L85 PathProgramCache]: Analyzing trace with hash 1070835405, now seen corresponding path program 1 times [2022-12-13 20:32:43,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:43,619 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021783922] [2022-12-13 20:32:43,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:43,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:43,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:43,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:43,652 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:43,652 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021783922] [2022-12-13 20:32:43,652 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021783922] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:43,652 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:43,652 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:43,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1897248378] [2022-12-13 20:32:43,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:43,653 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:43,653 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:43,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:32:43,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:32:43,653 INFO L87 Difference]: Start difference. First operand 109134 states and 152731 transitions. cyclomatic complexity: 43601 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:44,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:44,069 INFO L93 Difference]: Finished difference Result 143144 states and 199633 transitions. [2022-12-13 20:32:44,069 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 143144 states and 199633 transitions. [2022-12-13 20:32:44,639 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 142720 [2022-12-13 20:32:45,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 143144 states to 143144 states and 199633 transitions. [2022-12-13 20:32:45,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 143144 [2022-12-13 20:32:45,066 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 143144 [2022-12-13 20:32:45,066 INFO L73 IsDeterministic]: Start isDeterministic. Operand 143144 states and 199633 transitions. [2022-12-13 20:32:45,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:45,111 INFO L218 hiAutomatonCegarLoop]: Abstraction has 143144 states and 199633 transitions. [2022-12-13 20:32:45,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143144 states and 199633 transitions. [2022-12-13 20:32:45,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143144 to 97785. [2022-12-13 20:32:45,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97785 states, 97785 states have (on average 1.3970956690698983) internal successors, (136615), 97784 states have internal predecessors, (136615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:46,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97785 states to 97785 states and 136615 transitions. [2022-12-13 20:32:46,037 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97785 states and 136615 transitions. [2022-12-13 20:32:46,037 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:32:46,037 INFO L428 stractBuchiCegarLoop]: Abstraction has 97785 states and 136615 transitions. [2022-12-13 20:32:46,037 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 20:32:46,038 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97785 states and 136615 transitions. [2022-12-13 20:32:46,261 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97472 [2022-12-13 20:32:46,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:46,261 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:46,264 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:46,264 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:46,264 INFO L748 eck$LassoCheckResult]: Stem: 2288711#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2288712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2289594#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2289595#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2289232#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 2288916#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2288917#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2289564#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2289629#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2289612#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2289613#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2289060#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2289042#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2289043#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2288837#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2288838#L951 assume !(0 == ~M_E~0); 2288582#L951-2 assume !(0 == ~T1_E~0); 2288583#L956-1 assume !(0 == ~T2_E~0); 2288733#L961-1 assume !(0 == ~T3_E~0); 2289251#L966-1 assume !(0 == ~T4_E~0); 2289252#L971-1 assume !(0 == ~T5_E~0); 2289398#L976-1 assume !(0 == ~T6_E~0); 2289370#L981-1 assume !(0 == ~T7_E~0); 2289098#L986-1 assume !(0 == ~T8_E~0); 2288784#L991-1 assume !(0 == ~T9_E~0); 2288785#L996-1 assume !(0 == ~E_M~0); 2289673#L1001-1 assume !(0 == ~E_1~0); 2289314#L1006-1 assume !(0 == ~E_2~0); 2289315#L1011-1 assume !(0 == ~E_3~0); 2289630#L1016-1 assume !(0 == ~E_4~0); 2289652#L1021-1 assume !(0 == ~E_5~0); 2288383#L1026-1 assume !(0 == ~E_6~0); 2288384#L1031-1 assume !(0 == ~E_7~0); 2289261#L1036-1 assume !(0 == ~E_8~0); 2289257#L1041-1 assume !(0 == ~E_9~0); 2289258#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2289573#L472 assume !(1 == ~m_pc~0); 2289516#L472-2 is_master_triggered_~__retres1~0#1 := 0; 2289293#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2289294#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2289303#L1179 assume !(0 != activate_threads_~tmp~1#1); 2288391#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2288392#L491 assume !(1 == ~t1_pc~0); 2288883#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2288884#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2288413#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2288364#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 2288365#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2288385#L510 assume !(1 == ~t2_pc~0); 2288353#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2288354#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2288905#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2288906#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 2288635#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2288636#L529 assume !(1 == ~t3_pc~0); 2289107#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2289426#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2288362#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2288363#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 2288557#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2288558#L548 assume !(1 == ~t4_pc~0); 2288449#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2288448#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2288521#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2288491#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 2288492#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2288437#L567 assume !(1 == ~t5_pc~0); 2288438#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2288493#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2289499#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2289500#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 2289558#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2288568#L586 assume !(1 == ~t6_pc~0); 2288569#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2288637#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2288889#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2288890#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 2289550#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2289551#L605 assume !(1 == ~t7_pc~0); 2289076#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2289077#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2289295#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2289740#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 2289736#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2289223#L624 assume !(1 == ~t8_pc~0); 2288630#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2288629#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2289355#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2289422#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 2289522#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2288405#L643 assume !(1 == ~t9_pc~0); 2288406#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2289459#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2288962#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2288789#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 2288790#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2288613#L1059 assume !(1 == ~M_E~0); 2288614#L1059-2 assume !(1 == ~T1_E~0); 2288762#L1064-1 assume !(1 == ~T2_E~0); 2288763#L1069-1 assume !(1 == ~T3_E~0); 2289469#L1074-1 assume !(1 == ~T4_E~0); 2289518#L1079-1 assume !(1 == ~T5_E~0); 2289504#L1084-1 assume !(1 == ~T6_E~0); 2289505#L1089-1 assume !(1 == ~T7_E~0); 2289543#L1094-1 assume !(1 == ~T8_E~0); 2289142#L1099-1 assume !(1 == ~T9_E~0); 2289143#L1104-1 assume !(1 == ~E_M~0); 2289357#L1109-1 assume !(1 == ~E_1~0); 2288907#L1114-1 assume !(1 == ~E_2~0); 2288908#L1119-1 assume !(1 == ~E_3~0); 2288974#L1124-1 assume !(1 == ~E_4~0); 2288401#L1129-1 assume !(1 == ~E_5~0); 2288402#L1134-1 assume !(1 == ~E_6~0); 2288729#L1139-1 assume !(1 == ~E_7~0); 2288730#L1144-1 assume !(1 == ~E_8~0); 2288927#L1149-1 assume !(1 == ~E_9~0); 2288574#L1154-1 assume { :end_inline_reset_delta_events } true; 2288575#L1440-2 [2022-12-13 20:32:46,265 INFO L750 eck$LassoCheckResult]: Loop: 2288575#L1440-2 assume !false; 2380635#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2380631#L926 assume !false; 2380628#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2380474#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2380458#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2380282#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2380215#L795 assume !(0 != eval_~tmp~0#1); 2380216#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2384299#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2384297#L951-3 assume !(0 == ~M_E~0); 2384295#L951-5 assume !(0 == ~T1_E~0); 2384293#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2384292#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2384290#L966-3 assume !(0 == ~T4_E~0); 2384288#L971-3 assume !(0 == ~T5_E~0); 2384286#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2384284#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2384281#L986-3 assume !(0 == ~T8_E~0); 2384279#L991-3 assume !(0 == ~T9_E~0); 2384277#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2384275#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2384273#L1006-3 assume !(0 == ~E_2~0); 2384271#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2384270#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2384269#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2384268#L1026-3 assume !(0 == ~E_6~0); 2384266#L1031-3 assume !(0 == ~E_7~0); 2384264#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2384262#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2384260#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2384258#L472-33 assume !(1 == ~m_pc~0); 2384255#L472-35 is_master_triggered_~__retres1~0#1 := 0; 2384253#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2384251#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2384249#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2384247#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2384245#L491-33 assume !(1 == ~t1_pc~0); 2380508#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2384242#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2384240#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2384238#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2384236#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2384234#L510-33 assume !(1 == ~t2_pc~0); 2384232#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 2384229#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2384227#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2384225#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 2384223#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2372154#L529-33 assume !(1 == ~t3_pc~0); 2372153#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2372152#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2372151#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2372140#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 2372138#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2372137#L548-33 assume 1 == ~t4_pc~0; 2372135#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2372134#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2372132#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2372131#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2372130#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2372129#L567-33 assume !(1 == ~t5_pc~0); 2372128#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2372127#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2372125#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2372123#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2372121#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2372119#L586-33 assume 1 == ~t6_pc~0; 2372116#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2372114#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2372112#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2372110#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2372108#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2372105#L605-33 assume !(1 == ~t7_pc~0); 2371147#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2372102#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2372100#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2372098#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2372097#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2372093#L624-33 assume 1 == ~t8_pc~0; 2372090#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2372088#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2372086#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2372083#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2372081#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2372080#L643-33 assume !(1 == ~t9_pc~0); 2322629#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2368545#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2368544#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2368543#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2368542#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2368541#L1059-3 assume !(1 == ~M_E~0); 2368301#L1059-5 assume !(1 == ~T1_E~0); 2368540#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2368539#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2368538#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2368536#L1079-3 assume !(1 == ~T5_E~0); 2368534#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2368532#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2368530#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2368528#L1099-3 assume !(1 == ~T9_E~0); 2368526#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2368524#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2368522#L1114-3 assume !(1 == ~E_2~0); 2368520#L1119-3 assume !(1 == ~E_3~0); 2368519#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2368517#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2368515#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2368513#L1139-3 assume !(1 == ~E_7~0); 2368511#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2368508#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2368506#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2368500#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2368491#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2368478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2339513#L1459 assume !(0 == start_simulation_~tmp~3#1); 2339514#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2380659#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2380649#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2380647#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2380645#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2380643#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2380640#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 2380638#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 2288575#L1440-2 [2022-12-13 20:32:46,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:46,265 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 2 times [2022-12-13 20:32:46,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:46,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691118467] [2022-12-13 20:32:46,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:46,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:46,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:32:46,274 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:32:46,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:32:46,305 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:32:46,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:46,305 INFO L85 PathProgramCache]: Analyzing trace with hash -477222259, now seen corresponding path program 1 times [2022-12-13 20:32:46,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:46,305 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1500034207] [2022-12-13 20:32:46,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:46,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:46,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:46,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:46,331 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:46,332 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1500034207] [2022-12-13 20:32:46,332 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1500034207] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:46,332 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:46,332 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:46,332 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449854639] [2022-12-13 20:32:46,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:46,332 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:46,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:46,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:32:46,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:32:46,333 INFO L87 Difference]: Start difference. First operand 97785 states and 136615 transitions. cyclomatic complexity: 38834 Second operand has 3 states, 3 states have (on average 41.333333333333336) internal successors, (124), 3 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:46,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:46,690 INFO L93 Difference]: Finished difference Result 176670 states and 245050 transitions. [2022-12-13 20:32:46,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176670 states and 245050 transitions. [2022-12-13 20:32:47,335 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 176080 [2022-12-13 20:32:47,603 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176670 states to 176670 states and 245050 transitions. [2022-12-13 20:32:47,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176670 [2022-12-13 20:32:47,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176670 [2022-12-13 20:32:47,661 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176670 states and 245050 transitions. [2022-12-13 20:32:47,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:47,717 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176670 states and 245050 transitions. [2022-12-13 20:32:47,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176670 states and 245050 transitions. [2022-12-13 20:32:49,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176670 to 176542. [2022-12-13 20:32:49,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 176542 states, 176542 states have (on average 1.3873299271561441) internal successors, (244922), 176541 states have internal predecessors, (244922), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:49,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176542 states to 176542 states and 244922 transitions. [2022-12-13 20:32:49,563 INFO L240 hiAutomatonCegarLoop]: Abstraction has 176542 states and 244922 transitions. [2022-12-13 20:32:49,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:32:49,564 INFO L428 stractBuchiCegarLoop]: Abstraction has 176542 states and 244922 transitions. [2022-12-13 20:32:49,564 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-12-13 20:32:49,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 176542 states and 244922 transitions. [2022-12-13 20:32:49,953 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 175952 [2022-12-13 20:32:49,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:49,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:49,958 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:49,959 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:49,959 INFO L748 eck$LassoCheckResult]: Stem: 2563176#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2563177#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2564060#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2564061#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2563685#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 2563382#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2563383#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2564027#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2564092#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2564074#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2564075#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2563519#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2563504#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2563505#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2563301#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2563302#L951 assume !(0 == ~M_E~0); 2563046#L951-2 assume !(0 == ~T1_E~0); 2563047#L956-1 assume !(0 == ~T2_E~0); 2563198#L961-1 assume !(0 == ~T3_E~0); 2563708#L966-1 assume !(0 == ~T4_E~0); 2563709#L971-1 assume !(0 == ~T5_E~0); 2563858#L976-1 assume !(0 == ~T6_E~0); 2563829#L981-1 assume !(0 == ~T7_E~0); 2563556#L986-1 assume !(0 == ~T8_E~0); 2563251#L991-1 assume !(0 == ~T9_E~0); 2563252#L996-1 assume !(0 == ~E_M~0); 2564139#L1001-1 assume !(0 == ~E_1~0); 2563772#L1006-1 assume !(0 == ~E_2~0); 2563773#L1011-1 assume 0 == ~E_3~0;~E_3~0 := 1; 2564093#L1016-1 assume !(0 == ~E_4~0); 2564188#L1021-1 assume !(0 == ~E_5~0); 2564189#L1026-1 assume !(0 == ~E_6~0); 2564228#L1031-1 assume !(0 == ~E_7~0); 2564229#L1036-1 assume !(0 == ~E_8~0); 2563712#L1041-1 assume !(0 == ~E_9~0); 2563713#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2564041#L472 assume !(1 == ~m_pc~0); 2564289#L472-2 is_master_triggered_~__retres1~0#1 := 0; 2563748#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2563749#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2563760#L1179 assume !(0 != activate_threads_~tmp~1#1); 2563761#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2564288#L491 assume !(1 == ~t1_pc~0); 2563352#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2563353#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2564287#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2564286#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 2562845#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2562846#L510 assume !(1 == ~t2_pc~0); 2562814#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2562815#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2564136#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2564226#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 2564227#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2564281#L529 assume !(1 == ~t3_pc~0); 2564280#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2564279#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2564278#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2564180#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 2563021#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2563022#L548 assume !(1 == ~t4_pc~0); 2564276#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2564274#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2562984#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2562985#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 2563842#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2562898#L567 assume !(1 == ~t5_pc~0); 2562899#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2564193#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2563959#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2563960#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 2564019#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2563032#L586 assume !(1 == ~t6_pc~0); 2563033#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2564268#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2563358#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2563359#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 2564267#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2564209#L605 assume !(1 == ~t7_pc~0); 2563536#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2563537#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2564201#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2564202#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 2564187#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2563676#L624 assume !(1 == ~t8_pc~0); 2563677#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2564264#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2564263#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2564262#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 2564233#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2562866#L643 assume !(1 == ~t9_pc~0); 2562867#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2563914#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2563426#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2563256#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 2563257#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2564256#L1059 assume !(1 == ~M_E~0); 2564255#L1059-2 assume !(1 == ~T1_E~0); 2564254#L1064-1 assume !(1 == ~T2_E~0); 2564253#L1069-1 assume !(1 == ~T3_E~0); 2564182#L1074-1 assume !(1 == ~T4_E~0); 2563978#L1079-1 assume !(1 == ~T5_E~0); 2563964#L1084-1 assume !(1 == ~T6_E~0); 2563965#L1089-1 assume !(1 == ~T7_E~0); 2564002#L1094-1 assume !(1 == ~T8_E~0); 2563596#L1099-1 assume !(1 == ~T9_E~0); 2563597#L1104-1 assume !(1 == ~E_M~0); 2563816#L1109-1 assume !(1 == ~E_1~0); 2563375#L1114-1 assume !(1 == ~E_2~0); 2563376#L1119-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2563438#L1124-1 assume !(1 == ~E_4~0); 2562862#L1129-1 assume !(1 == ~E_5~0); 2562863#L1134-1 assume !(1 == ~E_6~0); 2563194#L1139-1 assume !(1 == ~E_7~0); 2563195#L1144-1 assume !(1 == ~E_8~0); 2563392#L1149-1 assume !(1 == ~E_9~0); 2563038#L1154-1 assume { :end_inline_reset_delta_events } true; 2563039#L1440-2 [2022-12-13 20:32:49,959 INFO L750 eck$LassoCheckResult]: Loop: 2563039#L1440-2 assume !false; 2627998#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2627992#L926 assume !false; 2627989#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2627936#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2627926#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2627924#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2627921#L795 assume !(0 != eval_~tmp~0#1); 2627922#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2645936#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2645934#L951-3 assume !(0 == ~M_E~0); 2645932#L951-5 assume !(0 == ~T1_E~0); 2645930#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2645928#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2645926#L966-3 assume !(0 == ~T4_E~0); 2645924#L971-3 assume !(0 == ~T5_E~0); 2645922#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2645920#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2645918#L986-3 assume !(0 == ~T8_E~0); 2645916#L991-3 assume !(0 == ~T9_E~0); 2645914#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2645912#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2645910#L1006-3 assume !(0 == ~E_2~0); 2645907#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2645906#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2645905#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2645904#L1026-3 assume !(0 == ~E_6~0); 2645903#L1031-3 assume !(0 == ~E_7~0); 2645902#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2645901#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2645900#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2645899#L472-33 assume !(1 == ~m_pc~0); 2645898#L472-35 is_master_triggered_~__retres1~0#1 := 0; 2645897#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2645896#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2645895#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2645894#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2645893#L491-33 assume !(1 == ~t1_pc~0); 2587768#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2645892#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2645891#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2645890#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2645889#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2645888#L510-33 assume !(1 == ~t2_pc~0); 2645886#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 2645885#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2645884#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2645883#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 2645882#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2645881#L529-33 assume !(1 == ~t3_pc~0); 2635990#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2645880#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2645879#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2645878#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 2645877#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2645876#L548-33 assume 1 == ~t4_pc~0; 2645874#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2645873#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2645872#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2645871#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2645869#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2645867#L567-33 assume !(1 == ~t5_pc~0); 2645865#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2645863#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2645861#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2645859#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2645857#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2645856#L586-33 assume 1 == ~t6_pc~0; 2645853#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2645851#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2645849#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2645847#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2645844#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2645842#L605-33 assume !(1 == ~t7_pc~0); 2641526#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2645839#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2645837#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2645835#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2645833#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2645832#L624-33 assume 1 == ~t8_pc~0; 2645830#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2645828#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2645826#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2645824#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2645822#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2595397#L643-33 assume !(1 == ~t9_pc~0); 2595395#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2595393#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2595391#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2595389#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2595387#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2595385#L1059-3 assume !(1 == ~M_E~0); 2595058#L1059-5 assume !(1 == ~T1_E~0); 2595382#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2595380#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2595378#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2595376#L1079-3 assume !(1 == ~T5_E~0); 2595373#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2595371#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2595369#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2595367#L1099-3 assume !(1 == ~T9_E~0); 2595365#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2595363#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2595361#L1114-3 assume !(1 == ~E_2~0); 2595359#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2595356#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2595354#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2595352#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2595350#L1139-3 assume !(1 == ~E_7~0); 2595347#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2595345#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2595343#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2595335#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2595325#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2595323#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2595320#L1459 assume !(0 == start_simulation_~tmp~3#1); 2595321#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2628020#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2628010#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2628008#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2628006#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2628004#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2628003#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 2628001#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 2563039#L1440-2 [2022-12-13 20:32:49,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:49,959 INFO L85 PathProgramCache]: Analyzing trace with hash -818498043, now seen corresponding path program 1 times [2022-12-13 20:32:49,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:49,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1990298526] [2022-12-13 20:32:49,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:49,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:49,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:49,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:49,993 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:49,993 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1990298526] [2022-12-13 20:32:49,993 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1990298526] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:49,994 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:49,994 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:32:49,994 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [102794072] [2022-12-13 20:32:49,994 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:49,994 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:32:49,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:49,995 INFO L85 PathProgramCache]: Analyzing trace with hash 340426191, now seen corresponding path program 1 times [2022-12-13 20:32:49,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:49,995 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [758148662] [2022-12-13 20:32:49,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:49,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:50,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:50,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:50,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:50,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [758148662] [2022-12-13 20:32:50,038 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [758148662] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:50,038 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:50,038 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:32:50,038 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1480859433] [2022-12-13 20:32:50,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:50,038 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:50,039 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:50,039 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:32:50,039 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:32:50,039 INFO L87 Difference]: Start difference. First operand 176542 states and 244922 transitions. cyclomatic complexity: 68384 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:50,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:50,774 INFO L93 Difference]: Finished difference Result 255680 states and 354290 transitions. [2022-12-13 20:32:50,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 255680 states and 354290 transitions. [2022-12-13 20:32:51,769 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 248288 [2022-12-13 20:32:52,211 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 255680 states to 255680 states and 354290 transitions. [2022-12-13 20:32:52,211 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 255680 [2022-12-13 20:32:52,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 255680 [2022-12-13 20:32:52,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 255680 states and 354290 transitions. [2022-12-13 20:32:52,410 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:52,410 INFO L218 hiAutomatonCegarLoop]: Abstraction has 255680 states and 354290 transitions. [2022-12-13 20:32:52,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 255680 states and 354290 transitions. [2022-12-13 20:32:54,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 255680 to 176457. [2022-12-13 20:32:54,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 176457 states, 176457 states have (on average 1.386615436055243) internal successors, (244678), 176456 states have internal predecessors, (244678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:54,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176457 states to 176457 states and 244678 transitions. [2022-12-13 20:32:54,551 INFO L240 hiAutomatonCegarLoop]: Abstraction has 176457 states and 244678 transitions. [2022-12-13 20:32:54,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:32:54,552 INFO L428 stractBuchiCegarLoop]: Abstraction has 176457 states and 244678 transitions. [2022-12-13 20:32:54,552 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-12-13 20:32:54,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 176457 states and 244678 transitions. [2022-12-13 20:32:54,934 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 175952 [2022-12-13 20:32:54,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:32:54,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:32:54,939 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:54,939 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:32:54,940 INFO L748 eck$LassoCheckResult]: Stem: 2995405#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2995406#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2996275#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2996276#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2995911#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 2995607#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2995608#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2996238#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2996304#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2996290#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2996291#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2995750#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2995737#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2995738#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2995529#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2995530#L951 assume !(0 == ~M_E~0); 2995278#L951-2 assume !(0 == ~T1_E~0); 2995279#L956-1 assume !(0 == ~T2_E~0); 2995427#L961-1 assume !(0 == ~T3_E~0); 2995931#L966-1 assume !(0 == ~T4_E~0); 2995932#L971-1 assume !(0 == ~T5_E~0); 2996074#L976-1 assume !(0 == ~T6_E~0); 2996048#L981-1 assume !(0 == ~T7_E~0); 2995788#L986-1 assume !(0 == ~T8_E~0); 2995478#L991-1 assume !(0 == ~T9_E~0); 2995479#L996-1 assume !(0 == ~E_M~0); 2996348#L1001-1 assume !(0 == ~E_1~0); 2995992#L1006-1 assume !(0 == ~E_2~0); 2995993#L1011-1 assume !(0 == ~E_3~0); 2996305#L1016-1 assume !(0 == ~E_4~0); 2996323#L1021-1 assume !(0 == ~E_5~0); 2995077#L1026-1 assume !(0 == ~E_6~0); 2995078#L1031-1 assume !(0 == ~E_7~0); 2995941#L1036-1 assume !(0 == ~E_8~0); 2995937#L1041-1 assume !(0 == ~E_9~0); 2995938#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2996252#L472 assume !(1 == ~m_pc~0); 2996191#L472-2 is_master_triggered_~__retres1~0#1 := 0; 2995971#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2995972#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2995981#L1179 assume !(0 != activate_threads_~tmp~1#1); 2995085#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2995086#L491 assume !(1 == ~t1_pc~0); 2995576#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2995577#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2995108#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2995059#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 2995060#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2995079#L510 assume !(1 == ~t2_pc~0); 2995048#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2995049#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2995597#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2995598#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 2995330#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2995331#L529 assume !(1 == ~t3_pc~0); 2995797#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2996103#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2995057#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2995058#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 2995253#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2995254#L548 assume !(1 == ~t4_pc~0); 2995145#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2995144#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2995216#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2995188#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 2995189#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2995133#L567 assume !(1 == ~t5_pc~0); 2995134#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2995187#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2996174#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2996175#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 2996232#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2995264#L586 assume !(1 == ~t6_pc~0); 2995265#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2995332#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2995582#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2995583#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 2996225#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2996226#L605 assume !(1 == ~t7_pc~0); 2995767#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2995768#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2995973#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2996403#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 2996398#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2995903#L624 assume !(1 == ~t8_pc~0); 2995325#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2995324#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2996031#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2996099#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 2996196#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2995100#L643 assume !(1 == ~t9_pc~0); 2995101#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2996132#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2995657#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2995484#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 2995485#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2995309#L1059 assume !(1 == ~M_E~0); 2995310#L1059-2 assume !(1 == ~T1_E~0); 2995456#L1064-1 assume !(1 == ~T2_E~0); 2995457#L1069-1 assume !(1 == ~T3_E~0); 2996142#L1074-1 assume !(1 == ~T4_E~0); 2996193#L1079-1 assume !(1 == ~T5_E~0); 2996179#L1084-1 assume !(1 == ~T6_E~0); 2996180#L1089-1 assume !(1 == ~T7_E~0); 2996217#L1094-1 assume !(1 == ~T8_E~0); 2995828#L1099-1 assume !(1 == ~T9_E~0); 2995829#L1104-1 assume !(1 == ~E_M~0); 2996035#L1109-1 assume !(1 == ~E_1~0); 2995599#L1114-1 assume !(1 == ~E_2~0); 2995600#L1119-1 assume !(1 == ~E_3~0); 2995670#L1124-1 assume !(1 == ~E_4~0); 2995096#L1129-1 assume !(1 == ~E_5~0); 2995097#L1134-1 assume !(1 == ~E_6~0); 2995423#L1139-1 assume !(1 == ~E_7~0); 2995424#L1144-1 assume !(1 == ~E_8~0); 2995618#L1149-1 assume !(1 == ~E_9~0); 2995270#L1154-1 assume { :end_inline_reset_delta_events } true; 2995271#L1440-2 [2022-12-13 20:32:54,940 INFO L750 eck$LassoCheckResult]: Loop: 2995271#L1440-2 assume !false; 3069402#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3069399#L926 assume !false; 3069397#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3069389#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3069379#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3069377#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3069374#L795 assume !(0 != eval_~tmp~0#1); 3069375#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3075793#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3075789#L951-3 assume !(0 == ~M_E~0); 3075785#L951-5 assume !(0 == ~T1_E~0); 3075781#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3075777#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3075774#L966-3 assume !(0 == ~T4_E~0); 3075771#L971-3 assume !(0 == ~T5_E~0); 3075768#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3075765#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3075762#L986-3 assume !(0 == ~T8_E~0); 3075757#L991-3 assume !(0 == ~T9_E~0); 3075754#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3075751#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3075748#L1006-3 assume !(0 == ~E_2~0); 3075745#L1011-3 assume !(0 == ~E_3~0); 3075742#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3075732#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3075730#L1026-3 assume !(0 == ~E_6~0); 3075688#L1031-3 assume !(0 == ~E_7~0); 3075689#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3075683#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3075684#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3075675#L472-33 assume !(1 == ~m_pc~0); 3075676#L472-35 is_master_triggered_~__retres1~0#1 := 0; 3075667#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3075668#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3075530#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3075531#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3074863#L491-33 assume !(1 == ~t1_pc~0); 3074864#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3074855#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3074856#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3074849#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3074850#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3074843#L510-33 assume !(1 == ~t2_pc~0); 3074842#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 3074832#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3074833#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3074826#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 3074827#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3074032#L529-33 assume !(1 == ~t3_pc~0); 3074025#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3074020#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3073997#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3073947#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 3073944#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3073942#L548-33 assume !(1 == ~t4_pc~0); 3073940#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 3073937#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3073935#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3073933#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3073930#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3073928#L567-33 assume !(1 == ~t5_pc~0); 3073926#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3073924#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3073922#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3073920#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3073917#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3073905#L586-33 assume 1 == ~t6_pc~0; 3073894#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3073885#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3073878#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3073873#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3073869#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3053102#L605-33 assume !(1 == ~t7_pc~0); 3053100#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 3053098#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3053096#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3053094#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3053092#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3053090#L624-33 assume !(1 == ~t8_pc~0); 3053088#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 3053084#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3053082#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3053080#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3053078#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3053076#L643-33 assume !(1 == ~t9_pc~0); 3041900#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 3053072#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3053070#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3053068#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3053066#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3053064#L1059-3 assume !(1 == ~M_E~0); 3028711#L1059-5 assume !(1 == ~T1_E~0); 3053060#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3053058#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3053056#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3053054#L1079-3 assume !(1 == ~T5_E~0); 3053052#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3053049#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3053047#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3053045#L1099-3 assume !(1 == ~T9_E~0); 3053043#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3053041#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3053039#L1114-3 assume !(1 == ~E_2~0); 3052967#L1119-3 assume !(1 == ~E_3~0); 3052966#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3052965#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3052964#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3052963#L1139-3 assume !(1 == ~E_7~0); 3052962#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3052961#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3052960#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3033754#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3033744#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3033742#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3029191#L1459 assume !(0 == start_simulation_~tmp~3#1); 3029192#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3069426#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3069416#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3069414#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 3069411#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3069409#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3069407#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3069405#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 2995271#L1440-2 [2022-12-13 20:32:54,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:54,940 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 3 times [2022-12-13 20:32:54,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:54,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059218220] [2022-12-13 20:32:54,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:54,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:54,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:32:54,948 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:32:54,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:32:54,971 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:32:54,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:32:54,971 INFO L85 PathProgramCache]: Analyzing trace with hash -1520213487, now seen corresponding path program 1 times [2022-12-13 20:32:54,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:32:54,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381883372] [2022-12-13 20:32:54,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:32:54,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:32:54,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:32:55,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:32:55,002 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:32:55,002 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381883372] [2022-12-13 20:32:55,002 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [381883372] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:32:55,002 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:32:55,002 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:32:55,002 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047055290] [2022-12-13 20:32:55,002 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:32:55,002 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:32:55,002 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:32:55,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 20:32:55,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 20:32:55,003 INFO L87 Difference]: Start difference. First operand 176457 states and 244678 transitions. cyclomatic complexity: 68225 Second operand has 5 states, 5 states have (on average 24.8) internal successors, (124), 5 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:32:55,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:32:55,865 INFO L93 Difference]: Finished difference Result 324057 states and 445798 transitions. [2022-12-13 20:32:55,866 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 324057 states and 445798 transitions. [2022-12-13 20:32:57,024 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 323168 [2022-12-13 20:32:57,541 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 324057 states to 324057 states and 445798 transitions. [2022-12-13 20:32:57,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 324057 [2022-12-13 20:32:57,664 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 324057 [2022-12-13 20:32:57,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 324057 states and 445798 transitions. [2022-12-13 20:32:57,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:32:57,773 INFO L218 hiAutomatonCegarLoop]: Abstraction has 324057 states and 445798 transitions. [2022-12-13 20:32:57,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 324057 states and 445798 transitions. [2022-12-13 20:32:59,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 324057 to 177225. [2022-12-13 20:32:59,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 177225 states, 177225 states have (on average 1.3849400479616307) internal successors, (245446), 177224 states have internal predecessors, (245446), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:33:00,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177225 states to 177225 states and 245446 transitions. [2022-12-13 20:33:00,068 INFO L240 hiAutomatonCegarLoop]: Abstraction has 177225 states and 245446 transitions. [2022-12-13 20:33:00,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 20:33:00,069 INFO L428 stractBuchiCegarLoop]: Abstraction has 177225 states and 245446 transitions. [2022-12-13 20:33:00,069 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-12-13 20:33:00,069 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 177225 states and 245446 transitions. [2022-12-13 20:33:00,498 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 176720 [2022-12-13 20:33:00,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:33:00,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:33:00,504 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:33:00,504 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:33:00,504 INFO L748 eck$LassoCheckResult]: Stem: 3495936#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 3495937#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3496812#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3496813#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3496444#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 3496143#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3496144#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3496776#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3496840#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3496829#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3496830#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3496277#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3496264#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3496265#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3496063#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3496064#L951 assume !(0 == ~M_E~0); 3495808#L951-2 assume !(0 == ~T1_E~0); 3495809#L956-1 assume !(0 == ~T2_E~0); 3495959#L961-1 assume !(0 == ~T3_E~0); 3496466#L966-1 assume !(0 == ~T4_E~0); 3496467#L971-1 assume !(0 == ~T5_E~0); 3496617#L976-1 assume !(0 == ~T6_E~0); 3496586#L981-1 assume !(0 == ~T7_E~0); 3496315#L986-1 assume !(0 == ~T8_E~0); 3496012#L991-1 assume !(0 == ~T9_E~0); 3496013#L996-1 assume !(0 == ~E_M~0); 3496888#L1001-1 assume !(0 == ~E_1~0); 3496528#L1006-1 assume !(0 == ~E_2~0); 3496529#L1011-1 assume !(0 == ~E_3~0); 3496841#L1016-1 assume !(0 == ~E_4~0); 3496867#L1021-1 assume !(0 == ~E_5~0); 3495607#L1026-1 assume !(0 == ~E_6~0); 3495608#L1031-1 assume !(0 == ~E_7~0); 3496476#L1036-1 assume !(0 == ~E_8~0); 3496472#L1041-1 assume !(0 == ~E_9~0); 3496473#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3496786#L472 assume !(1 == ~m_pc~0); 3496733#L472-2 is_master_triggered_~__retres1~0#1 := 0; 3496506#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3496507#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3496517#L1179 assume !(0 != activate_threads_~tmp~1#1); 3495615#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3495616#L491 assume !(1 == ~t1_pc~0); 3496112#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3496113#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3495638#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3495589#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 3495590#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3495609#L510 assume !(1 == ~t2_pc~0); 3495578#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3495579#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3496133#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3496134#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 3495860#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3495861#L529 assume !(1 == ~t3_pc~0); 3496324#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3496646#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3495587#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3495588#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 3495783#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3495784#L548 assume !(1 == ~t4_pc~0); 3495674#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3495673#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3495747#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3495716#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 3495717#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3495662#L567 assume !(1 == ~t5_pc~0); 3495663#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3495718#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3496716#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3496717#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 3496770#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3495794#L586 assume !(1 == ~t6_pc~0); 3495795#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3495862#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3496118#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3496119#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 3496763#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3496764#L605 assume !(1 == ~t7_pc~0); 3496293#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3496294#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3496508#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3496943#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 3496939#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3496435#L624 assume !(1 == ~t8_pc~0); 3495855#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3495854#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3496570#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3496642#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 3496739#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3495630#L643 assume !(1 == ~t9_pc~0); 3495631#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3496676#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3496188#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3496017#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 3496018#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3495839#L1059 assume !(1 == ~M_E~0); 3495840#L1059-2 assume !(1 == ~T1_E~0); 3495990#L1064-1 assume !(1 == ~T2_E~0); 3495991#L1069-1 assume !(1 == ~T3_E~0); 3496686#L1074-1 assume !(1 == ~T4_E~0); 3496737#L1079-1 assume !(1 == ~T5_E~0); 3496722#L1084-1 assume !(1 == ~T6_E~0); 3496723#L1089-1 assume !(1 == ~T7_E~0); 3496756#L1094-1 assume !(1 == ~T8_E~0); 3496354#L1099-1 assume !(1 == ~T9_E~0); 3496355#L1104-1 assume !(1 == ~E_M~0); 3496572#L1109-1 assume !(1 == ~E_1~0); 3496135#L1114-1 assume !(1 == ~E_2~0); 3496136#L1119-1 assume !(1 == ~E_3~0); 3496200#L1124-1 assume !(1 == ~E_4~0); 3495626#L1129-1 assume !(1 == ~E_5~0); 3495627#L1134-1 assume !(1 == ~E_6~0); 3495955#L1139-1 assume !(1 == ~E_7~0); 3495956#L1144-1 assume !(1 == ~E_8~0); 3496153#L1149-1 assume !(1 == ~E_9~0); 3495800#L1154-1 assume { :end_inline_reset_delta_events } true; 3495801#L1440-2 [2022-12-13 20:33:00,504 INFO L750 eck$LassoCheckResult]: Loop: 3495801#L1440-2 assume !false; 3614357#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3612561#L926 assume !false; 3611496#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3611197#L728 assume !(0 == ~m_st~0); 3611198#L732 assume !(0 == ~t1_st~0); 3611192#L736 assume !(0 == ~t2_st~0); 3611193#L740 assume !(0 == ~t3_st~0); 3611196#L744 assume !(0 == ~t4_st~0); 3611190#L748 assume !(0 == ~t5_st~0); 3611191#L752 assume !(0 == ~t6_st~0); 3611195#L756 assume !(0 == ~t7_st~0); 3611188#L760 assume !(0 == ~t8_st~0); 3611189#L764 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 3611194#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3580076#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3580077#L795 assume !(0 != eval_~tmp~0#1); 3611183#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3611178#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3611179#L951-3 assume !(0 == ~M_E~0); 3611172#L951-5 assume !(0 == ~T1_E~0); 3611173#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3610996#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3610997#L966-3 assume !(0 == ~T4_E~0); 3610972#L971-3 assume !(0 == ~T5_E~0); 3610973#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3610940#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3610941#L986-3 assume !(0 == ~T8_E~0); 3610913#L991-3 assume !(0 == ~T9_E~0); 3610914#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3610891#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3610892#L1006-3 assume !(0 == ~E_2~0); 3610874#L1011-3 assume !(0 == ~E_3~0); 3610875#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3610836#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3610837#L1026-3 assume !(0 == ~E_6~0); 3610818#L1031-3 assume !(0 == ~E_7~0); 3610819#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3610801#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3610802#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3610783#L472-33 assume !(1 == ~m_pc~0); 3610784#L472-35 is_master_triggered_~__retres1~0#1 := 0; 3610764#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3610765#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3610743#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3610744#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3610726#L491-33 assume !(1 == ~t1_pc~0); 3610724#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3610722#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3610720#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3610718#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3610716#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3610713#L510-33 assume !(1 == ~t2_pc~0); 3610710#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 3610708#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3610706#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3610704#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 3610702#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3610700#L529-33 assume !(1 == ~t3_pc~0); 3573361#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3610698#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3610696#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3610694#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 3610692#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3610690#L548-33 assume !(1 == ~t4_pc~0); 3610687#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 3610684#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3610682#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3610680#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3610678#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3610676#L567-33 assume !(1 == ~t5_pc~0); 3610674#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3610672#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3610670#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3610668#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3610666#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3610664#L586-33 assume !(1 == ~t6_pc~0); 3610661#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3610658#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3610656#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3610654#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3610652#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3610650#L605-33 assume !(1 == ~t7_pc~0); 3609655#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 3610648#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3610646#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3610644#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3610642#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3610640#L624-33 assume !(1 == ~t8_pc~0); 3610637#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 3610634#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3610632#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3610630#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3610628#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3610626#L643-33 assume !(1 == ~t9_pc~0); 3571698#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 3610624#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3610622#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3610620#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3610618#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3610616#L1059-3 assume !(1 == ~M_E~0); 3608570#L1059-5 assume !(1 == ~T1_E~0); 3610614#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3610612#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3610610#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3610608#L1079-3 assume !(1 == ~T5_E~0); 3610606#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3610604#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3610602#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3610600#L1099-3 assume !(1 == ~T9_E~0); 3610598#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3610596#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3610594#L1114-3 assume !(1 == ~E_2~0); 3610592#L1119-3 assume !(1 == ~E_3~0); 3610591#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3610590#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3610589#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3610588#L1139-3 assume !(1 == ~E_7~0); 3610587#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3610586#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3610585#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3610583#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3610568#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3610561#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3610554#L1459 assume !(0 == start_simulation_~tmp~3#1); 3610555#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3614381#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3614371#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3614369#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 3614367#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3614365#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3614363#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3614360#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 3495801#L1440-2 [2022-12-13 20:33:00,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:33:00,505 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 4 times [2022-12-13 20:33:00,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:33:00,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [887107840] [2022-12-13 20:33:00,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:33:00,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:33:00,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:33:00,512 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:33:00,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:33:00,533 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:33:00,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:33:00,534 INFO L85 PathProgramCache]: Analyzing trace with hash 2147312103, now seen corresponding path program 1 times [2022-12-13 20:33:00,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:33:00,534 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [270101597] [2022-12-13 20:33:00,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:33:00,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:33:00,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:33:00,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:33:00,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:33:00,592 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [270101597] [2022-12-13 20:33:00,593 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [270101597] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:33:00,593 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:33:00,593 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:33:00,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [970262518] [2022-12-13 20:33:00,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:33:00,593 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:33:00,593 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:33:00,594 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 20:33:00,594 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 20:33:00,594 INFO L87 Difference]: Start difference. First operand 177225 states and 245446 transitions. cyclomatic complexity: 68225 Second operand has 5 states, 5 states have (on average 26.6) internal successors, (133), 5 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:33:01,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:33:01,578 INFO L93 Difference]: Finished difference Result 355897 states and 490501 transitions. [2022-12-13 20:33:01,578 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 355897 states and 490501 transitions. [2022-12-13 20:33:02,897 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 355136 [2022-12-13 20:33:03,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 355897 states to 355897 states and 490501 transitions. [2022-12-13 20:33:03,451 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 355897 [2022-12-13 20:33:03,593 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 355897 [2022-12-13 20:33:03,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 355897 states and 490501 transitions. [2022-12-13 20:33:03,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:33:03,899 INFO L218 hiAutomatonCegarLoop]: Abstraction has 355897 states and 490501 transitions. [2022-12-13 20:33:04,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 355897 states and 490501 transitions. [2022-12-13 20:33:05,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 355897 to 180393. [2022-12-13 20:33:05,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 180393 states, 180393 states have (on average 1.3730299956206726) internal successors, (247685), 180392 states have internal predecessors, (247685), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:33:05,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180393 states to 180393 states and 247685 transitions. [2022-12-13 20:33:05,894 INFO L240 hiAutomatonCegarLoop]: Abstraction has 180393 states and 247685 transitions. [2022-12-13 20:33:05,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 20:33:05,896 INFO L428 stractBuchiCegarLoop]: Abstraction has 180393 states and 247685 transitions. [2022-12-13 20:33:05,896 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-12-13 20:33:05,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 180393 states and 247685 transitions. [2022-12-13 20:33:06,336 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 179888 [2022-12-13 20:33:06,336 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:33:06,336 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:33:06,342 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:33:06,342 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:33:06,342 INFO L748 eck$LassoCheckResult]: Stem: 4029068#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 4029069#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 4029964#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4029965#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4029591#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 4029271#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4029272#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4029930#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4030003#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4029982#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4029983#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4029413#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4029398#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4029399#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4029192#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4029193#L951 assume !(0 == ~M_E~0); 4028941#L951-2 assume !(0 == ~T1_E~0); 4028942#L956-1 assume !(0 == ~T2_E~0); 4029091#L961-1 assume !(0 == ~T3_E~0); 4029615#L966-1 assume !(0 == ~T4_E~0); 4029616#L971-1 assume !(0 == ~T5_E~0); 4029753#L976-1 assume !(0 == ~T6_E~0); 4029725#L981-1 assume !(0 == ~T7_E~0); 4029453#L986-1 assume !(0 == ~T8_E~0); 4029141#L991-1 assume !(0 == ~T9_E~0); 4029142#L996-1 assume !(0 == ~E_M~0); 4030043#L1001-1 assume !(0 == ~E_1~0); 4029672#L1006-1 assume !(0 == ~E_2~0); 4029673#L1011-1 assume !(0 == ~E_3~0); 4030004#L1016-1 assume !(0 == ~E_4~0); 4030019#L1021-1 assume !(0 == ~E_5~0); 4028742#L1026-1 assume !(0 == ~E_6~0); 4028743#L1031-1 assume !(0 == ~E_7~0); 4029625#L1036-1 assume !(0 == ~E_8~0); 4029621#L1041-1 assume !(0 == ~E_9~0); 4029622#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4029944#L472 assume !(1 == ~m_pc~0); 4029877#L472-2 is_master_triggered_~__retres1~0#1 := 0; 4029652#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4029653#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4029661#L1179 assume !(0 != activate_threads_~tmp~1#1); 4028750#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4028751#L491 assume !(1 == ~t1_pc~0); 4029239#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4029240#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4028772#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4028724#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 4028725#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4028744#L510 assume !(1 == ~t2_pc~0); 4028713#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4028714#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4029260#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4029261#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 4028992#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4028993#L529 assume !(1 == ~t3_pc~0); 4029462#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4029785#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4028722#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4028723#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 4028916#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4028917#L548 assume !(1 == ~t4_pc~0); 4028808#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4028807#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4028881#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4028850#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 4028851#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4028796#L567 assume !(1 == ~t5_pc~0); 4028797#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4028852#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4029856#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4029857#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 4029923#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4028927#L586 assume !(1 == ~t6_pc~0); 4028928#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4028994#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4029245#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4029246#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 4029914#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4029915#L605 assume !(1 == ~t7_pc~0); 4029429#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4029430#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4029654#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4030097#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 4030092#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4029583#L624 assume !(1 == ~t8_pc~0); 4028987#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4028986#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4029710#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4029780#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 4029884#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4028764#L643 assume !(1 == ~t9_pc~0); 4028765#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4029817#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4029320#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4029146#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 4029147#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4028972#L1059 assume !(1 == ~M_E~0); 4028973#L1059-2 assume !(1 == ~T1_E~0); 4029120#L1064-1 assume !(1 == ~T2_E~0); 4029121#L1069-1 assume !(1 == ~T3_E~0); 4029827#L1074-1 assume !(1 == ~T4_E~0); 4029881#L1079-1 assume !(1 == ~T5_E~0); 4029861#L1084-1 assume !(1 == ~T6_E~0); 4029862#L1089-1 assume !(1 == ~T7_E~0); 4029906#L1094-1 assume !(1 == ~T8_E~0); 4029498#L1099-1 assume !(1 == ~T9_E~0); 4029499#L1104-1 assume !(1 == ~E_M~0); 4029712#L1109-1 assume !(1 == ~E_1~0); 4029262#L1114-1 assume !(1 == ~E_2~0); 4029263#L1119-1 assume !(1 == ~E_3~0); 4029334#L1124-1 assume !(1 == ~E_4~0); 4028760#L1129-1 assume !(1 == ~E_5~0); 4028761#L1134-1 assume !(1 == ~E_6~0); 4029087#L1139-1 assume !(1 == ~E_7~0); 4029088#L1144-1 assume !(1 == ~E_8~0); 4029281#L1149-1 assume !(1 == ~E_9~0); 4028933#L1154-1 assume { :end_inline_reset_delta_events } true; 4028934#L1440-2 [2022-12-13 20:33:06,342 INFO L750 eck$LassoCheckResult]: Loop: 4028934#L1440-2 assume !false; 4086190#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4085548#L926 assume !false; 4086189#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 4086187#L728 assume !(0 == ~m_st~0); 4086188#L732 assume !(0 == ~t1_st~0); 4086182#L736 assume !(0 == ~t2_st~0); 4086183#L740 assume !(0 == ~t3_st~0); 4086186#L744 assume !(0 == ~t4_st~0); 4086180#L748 assume !(0 == ~t5_st~0); 4086181#L752 assume !(0 == ~t6_st~0); 4086185#L756 assume !(0 == ~t7_st~0); 4086178#L760 assume !(0 == ~t8_st~0); 4086179#L764 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 4086184#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4094496#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4094485#L795 assume !(0 != eval_~tmp~0#1); 4094486#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4094477#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4094478#L951-3 assume !(0 == ~M_E~0); 4094469#L951-5 assume !(0 == ~T1_E~0); 4094470#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4094463#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4094464#L966-3 assume !(0 == ~T4_E~0); 4094457#L971-3 assume !(0 == ~T5_E~0); 4094458#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4094451#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4094452#L986-3 assume !(0 == ~T8_E~0); 4094446#L991-3 assume !(0 == ~T9_E~0); 4094447#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4094440#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4094441#L1006-3 assume !(0 == ~E_2~0); 4094434#L1011-3 assume !(0 == ~E_3~0); 4094435#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4094427#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4094428#L1026-3 assume !(0 == ~E_6~0); 4094421#L1031-3 assume !(0 == ~E_7~0); 4094422#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4094415#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4094416#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4094408#L472-33 assume !(1 == ~m_pc~0); 4094409#L472-35 is_master_triggered_~__retres1~0#1 := 0; 4094402#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4094403#is_master_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4094396#L1179-33 assume !(0 != activate_threads_~tmp~1#1); 4094397#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4088037#L491-33 assume !(1 == ~t1_pc~0); 4088038#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 4088033#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4088034#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4088029#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4088030#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4088023#L510-33 assume !(1 == ~t2_pc~0); 4088019#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 4088016#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4088013#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4088010#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 4088007#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4086468#L529-33 assume !(1 == ~t3_pc~0); 4086463#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 4086458#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4086453#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4086448#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 4086442#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4086438#L548-33 assume 1 == ~t4_pc~0; 4086432#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4086427#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4086423#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4086419#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4086415#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4086410#L567-33 assume !(1 == ~t5_pc~0); 4086406#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 4086402#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4086398#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4086394#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4086390#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4086386#L586-33 assume 1 == ~t6_pc~0; 4086380#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4086375#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4086371#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4086367#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4086363#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4086358#L605-33 assume !(1 == ~t7_pc~0); 4053567#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 4086353#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4086349#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4086345#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4086341#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4086338#L624-33 assume 1 == ~t8_pc~0; 4086332#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4086327#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4086323#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4086319#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4086315#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4086309#L643-33 assume !(1 == ~t9_pc~0); 4086003#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 4086302#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4086297#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4086292#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4086287#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4086282#L1059-3 assume !(1 == ~M_E~0); 4086277#L1059-5 assume !(1 == ~T1_E~0); 4086274#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4086271#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4086268#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4086264#L1079-3 assume !(1 == ~T5_E~0); 4086261#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4086258#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4086255#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4086252#L1099-3 assume !(1 == ~T9_E~0); 4086249#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4086246#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4086243#L1114-3 assume !(1 == ~E_2~0); 4086240#L1119-3 assume !(1 == ~E_3~0); 4086238#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4086236#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4086234#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4086232#L1139-3 assume !(1 == ~E_7~0); 4086230#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4086228#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4086226#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 4086223#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4086213#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4086211#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 4086209#L1459 assume !(0 == start_simulation_~tmp~3#1); 4086207#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 4086205#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4086196#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4086195#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 4086194#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4086193#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4086192#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 4086191#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 4028934#L1440-2 [2022-12-13 20:33:06,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:33:06,343 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 5 times [2022-12-13 20:33:06,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:33:06,343 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841529623] [2022-12-13 20:33:06,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:33:06,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:33:06,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:33:06,354 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:33:06,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:33:06,378 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:33:06,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:33:06,378 INFO L85 PathProgramCache]: Analyzing trace with hash 872160038, now seen corresponding path program 1 times [2022-12-13 20:33:06,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:33:06,378 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902005887] [2022-12-13 20:33:06,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:33:06,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:33:06,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:33:06,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:33:06,595 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:33:06,595 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1902005887] [2022-12-13 20:33:06,596 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1902005887] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:33:06,596 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:33:06,596 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:33:06,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [579970862] [2022-12-13 20:33:06,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:33:06,596 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:33:06,596 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:33:06,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:33:06,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:33:06,597 INFO L87 Difference]: Start difference. First operand 180393 states and 247685 transitions. cyclomatic complexity: 67296 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:33:07,185 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:33:07,185 INFO L93 Difference]: Finished difference Result 298179 states and 405655 transitions. [2022-12-13 20:33:07,185 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 298179 states and 405655 transitions. [2022-12-13 20:33:08,369 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 297544 [2022-12-13 20:33:08,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 298179 states to 298179 states and 405655 transitions. [2022-12-13 20:33:08,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 298179 [2022-12-13 20:33:08,976 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 298179 [2022-12-13 20:33:08,977 INFO L73 IsDeterministic]: Start isDeterministic. Operand 298179 states and 405655 transitions. [2022-12-13 20:33:09,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:33:09,081 INFO L218 hiAutomatonCegarLoop]: Abstraction has 298179 states and 405655 transitions. [2022-12-13 20:33:09,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298179 states and 405655 transitions. [2022-12-13 20:33:11,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298179 to 290211. [2022-12-13 20:33:11,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 290211 states, 290211 states have (on average 1.3618470698905278) internal successors, (395223), 290210 states have internal predecessors, (395223), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:33:11,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 290211 states to 290211 states and 395223 transitions. [2022-12-13 20:33:11,984 INFO L240 hiAutomatonCegarLoop]: Abstraction has 290211 states and 395223 transitions. [2022-12-13 20:33:11,985 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:33:11,985 INFO L428 stractBuchiCegarLoop]: Abstraction has 290211 states and 395223 transitions. [2022-12-13 20:33:11,985 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-12-13 20:33:11,985 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 290211 states and 395223 transitions. [2022-12-13 20:33:12,573 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 289576 [2022-12-13 20:33:12,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:33:12,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:33:12,574 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:33:12,574 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:33:12,574 INFO L748 eck$LassoCheckResult]: Stem: 4507647#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 4507648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 4508591#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4508592#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4508176#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 4507860#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4507861#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4508552#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4508625#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4508606#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4508607#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4508005#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4507988#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4507989#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4507777#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4507778#L951 assume !(0 == ~M_E~0); 4507519#L951-2 assume !(0 == ~T1_E~0); 4507520#L956-1 assume !(0 == ~T2_E~0); 4507671#L961-1 assume !(0 == ~T3_E~0); 4508198#L966-1 assume !(0 == ~T4_E~0); 4508199#L971-1 assume !(0 == ~T5_E~0); 4508356#L976-1 assume !(0 == ~T6_E~0); 4508327#L981-1 assume !(0 == ~T7_E~0); 4508048#L986-1 assume !(0 == ~T8_E~0); 4507723#L991-1 assume !(0 == ~T9_E~0); 4507724#L996-1 assume !(0 == ~E_M~0); 4508680#L1001-1 assume !(0 == ~E_1~0); 4508264#L1006-1 assume !(0 == ~E_2~0); 4508265#L1011-1 assume !(0 == ~E_3~0); 4508626#L1016-1 assume !(0 == ~E_4~0); 4508647#L1021-1 assume !(0 == ~E_5~0); 4507320#L1026-1 assume !(0 == ~E_6~0); 4507321#L1031-1 assume !(0 == ~E_7~0); 4508211#L1036-1 assume !(0 == ~E_8~0); 4508206#L1041-1 assume !(0 == ~E_9~0); 4508207#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4508564#L472 assume !(1 == ~m_pc~0); 4508492#L472-2 is_master_triggered_~__retres1~0#1 := 0; 4508245#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4508246#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4508255#L1179 assume !(0 != activate_threads_~tmp~1#1); 4507328#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4507329#L491 assume !(1 == ~t1_pc~0); 4507823#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4507824#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4507350#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4507302#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 4507303#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4507322#L510 assume !(1 == ~t2_pc~0); 4507291#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4507292#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4507845#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4507846#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 4507571#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4507572#L529 assume !(1 == ~t3_pc~0); 4508057#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4508393#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4507300#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4507301#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 4507494#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4507495#L548 assume !(1 == ~t4_pc~0); 4507387#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4507386#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4507458#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4507429#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 4507430#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4507375#L567 assume !(1 == ~t5_pc~0); 4507376#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4507431#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4508474#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4508475#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 4508546#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4507505#L586 assume !(1 == ~t6_pc~0); 4507506#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4507573#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4507829#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4507830#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 4508536#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4508537#L605 assume !(1 == ~t7_pc~0); 4508021#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4508022#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4508247#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4508740#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 4508737#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4508168#L624 assume !(1 == ~t8_pc~0); 4507566#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4507565#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4508310#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4508388#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 4508500#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4507342#L643 assume !(1 == ~t9_pc~0); 4507343#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4508427#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4507908#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4507728#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 4507729#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4507550#L1059 assume !(1 == ~M_E~0); 4507551#L1059-2 assume !(1 == ~T1_E~0); 4507701#L1064-1 assume !(1 == ~T2_E~0); 4507702#L1069-1 assume !(1 == ~T3_E~0); 4508438#L1074-1 assume !(1 == ~T4_E~0); 4508497#L1079-1 assume !(1 == ~T5_E~0); 4508480#L1084-1 assume !(1 == ~T6_E~0); 4508481#L1089-1 assume !(1 == ~T7_E~0); 4508528#L1094-1 assume !(1 == ~T8_E~0); 4508086#L1099-1 assume !(1 == ~T9_E~0); 4508087#L1104-1 assume !(1 == ~E_M~0); 4508312#L1109-1 assume !(1 == ~E_1~0); 4507847#L1114-1 assume !(1 == ~E_2~0); 4507848#L1119-1 assume !(1 == ~E_3~0); 4507922#L1124-1 assume !(1 == ~E_4~0); 4507338#L1129-1 assume !(1 == ~E_5~0); 4507339#L1134-1 assume !(1 == ~E_6~0); 4507667#L1139-1 assume !(1 == ~E_7~0); 4507668#L1144-1 assume !(1 == ~E_8~0); 4507870#L1149-1 assume !(1 == ~E_9~0); 4507511#L1154-1 assume { :end_inline_reset_delta_events } true; 4507512#L1440-2 assume !false; 4570045#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4570040#L926 [2022-12-13 20:33:12,574 INFO L750 eck$LassoCheckResult]: Loop: 4570040#L926 assume !false; 4570038#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 4570035#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4570033#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4570031#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4570030#L795 assume 0 != eval_~tmp~0#1; 4570027#L795-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 4570025#L803 assume !(0 != eval_~tmp_ndt_1~0#1); 4570024#L800 assume !(0 == ~t1_st~0); 4559297#L814 assume !(0 == ~t2_st~0); 4559292#L828 assume !(0 == ~t3_st~0); 4559288#L842 assume !(0 == ~t4_st~0); 4559280#L856 assume !(0 == ~t5_st~0); 4559265#L870 assume !(0 == ~t6_st~0); 4559263#L884 assume !(0 == ~t7_st~0); 4559261#L898 assume !(0 == ~t8_st~0); 4570044#L912 assume !(0 == ~t9_st~0); 4570040#L926 [2022-12-13 20:33:12,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:33:12,574 INFO L85 PathProgramCache]: Analyzing trace with hash 1363771783, now seen corresponding path program 1 times [2022-12-13 20:33:12,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:33:12,574 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [353722130] [2022-12-13 20:33:12,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:33:12,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:33:12,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:33:12,582 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:33:12,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:33:12,604 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:33:12,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:33:12,604 INFO L85 PathProgramCache]: Analyzing trace with hash 1895676149, now seen corresponding path program 1 times [2022-12-13 20:33:12,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:33:12,604 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409020772] [2022-12-13 20:33:12,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:33:12,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:33:12,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:33:12,607 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:33:12,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:33:12,609 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:33:12,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:33:12,609 INFO L85 PathProgramCache]: Analyzing trace with hash 572699695, now seen corresponding path program 1 times [2022-12-13 20:33:12,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:33:12,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261028242] [2022-12-13 20:33:12,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:33:12,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:33:12,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:33:12,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:33:12,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:33:12,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261028242] [2022-12-13 20:33:12,635 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1261028242] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:33:12,635 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:33:12,635 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:33:12,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318610397] [2022-12-13 20:33:12,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:33:12,725 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:33:12,725 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:33:12,725 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:33:12,725 INFO L87 Difference]: Start difference. First operand 290211 states and 395223 transitions. cyclomatic complexity: 105018 Second operand has 3 states, 3 states have (on average 45.333333333333336) internal successors, (136), 3 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:33:13,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:33:13,899 INFO L93 Difference]: Finished difference Result 560384 states and 758567 transitions. [2022-12-13 20:33:13,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 560384 states and 758567 transitions. [2022-12-13 20:33:15,943 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 559120 [2022-12-13 20:33:16,916 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 560384 states to 560384 states and 758567 transitions. [2022-12-13 20:33:16,916 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 560384 [2022-12-13 20:33:17,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 560384 [2022-12-13 20:33:17,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 560384 states and 758567 transitions. [2022-12-13 20:33:17,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:33:17,273 INFO L218 hiAutomatonCegarLoop]: Abstraction has 560384 states and 758567 transitions. [2022-12-13 20:33:17,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 560384 states and 758567 transitions. [2022-12-13 20:33:20,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 560384 to 546776. [2022-12-13 20:33:21,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546776 states, 546776 states have (on average 1.354571158938944) internal successors, (740647), 546775 states have internal predecessors, (740647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:33:22,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546776 states to 546776 states and 740647 transitions. [2022-12-13 20:33:22,288 INFO L240 hiAutomatonCegarLoop]: Abstraction has 546776 states and 740647 transitions. [2022-12-13 20:33:22,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:33:22,288 INFO L428 stractBuchiCegarLoop]: Abstraction has 546776 states and 740647 transitions. [2022-12-13 20:33:22,289 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-12-13 20:33:22,289 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546776 states and 740647 transitions. [2022-12-13 20:33:23,397 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 545512 [2022-12-13 20:33:23,397 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:33:23,397 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:33:23,398 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:33:23,398 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:33:23,398 INFO L748 eck$LassoCheckResult]: Stem: 5358256#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5358257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5359183#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5359184#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5358780#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 5358460#L670-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 5358461#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5455051#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5455050#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5455049#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5455048#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5455047#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5455046#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5455045#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5455044#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5455043#L951 assume !(0 == ~M_E~0); 5455042#L951-2 assume !(0 == ~T1_E~0); 5455041#L956-1 assume !(0 == ~T2_E~0); 5455040#L961-1 assume !(0 == ~T3_E~0); 5455039#L966-1 assume !(0 == ~T4_E~0); 5455038#L971-1 assume !(0 == ~T5_E~0); 5455037#L976-1 assume !(0 == ~T6_E~0); 5455036#L981-1 assume !(0 == ~T7_E~0); 5455035#L986-1 assume !(0 == ~T8_E~0); 5455034#L991-1 assume !(0 == ~T9_E~0); 5455033#L996-1 assume !(0 == ~E_M~0); 5455032#L1001-1 assume !(0 == ~E_1~0); 5455031#L1006-1 assume !(0 == ~E_2~0); 5455030#L1011-1 assume !(0 == ~E_3~0); 5455029#L1016-1 assume !(0 == ~E_4~0); 5455028#L1021-1 assume !(0 == ~E_5~0); 5455027#L1026-1 assume !(0 == ~E_6~0); 5455026#L1031-1 assume !(0 == ~E_7~0); 5455025#L1036-1 assume !(0 == ~E_8~0); 5455024#L1041-1 assume !(0 == ~E_9~0); 5455023#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5455022#L472 assume !(1 == ~m_pc~0); 5455021#L472-2 is_master_triggered_~__retres1~0#1 := 0; 5455020#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5455019#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5455018#L1179 assume !(0 != activate_threads_~tmp~1#1); 5455017#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5455016#L491 assume !(1 == ~t1_pc~0); 5455015#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5455014#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5455013#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5455012#L1187 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5357906#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5357927#L510 assume !(1 == ~t2_pc~0); 5357894#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5357895#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5358447#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5358448#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 5358176#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5358177#L529 assume !(1 == ~t3_pc~0); 5358653#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5358990#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5357903#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5357904#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 5358098#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5358099#L548 assume !(1 == ~t4_pc~0); 5357991#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5357990#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5358062#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5358033#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 5358034#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5357982#L567 assume !(1 == ~t5_pc~0); 5357983#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5358035#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5359072#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5359073#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 5359136#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5358109#L586 assume !(1 == ~t6_pc~0); 5358110#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5358180#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5358435#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5358436#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 5359128#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5359129#L605 assume !(1 == ~t7_pc~0); 5358626#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5358627#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5358845#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5359353#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 5359347#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5358771#L624 assume !(1 == ~t8_pc~0); 5358171#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5358170#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5358905#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5358987#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 5359097#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5357945#L643 assume !(1 == ~t9_pc~0); 5357946#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5359027#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5358509#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5358334#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 5358335#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5358155#L1059 assume !(1 == ~M_E~0); 5358156#L1059-2 assume !(1 == ~T1_E~0); 5358307#L1064-1 assume !(1 == ~T2_E~0); 5358308#L1069-1 assume !(1 == ~T3_E~0); 5359037#L1074-1 assume !(1 == ~T4_E~0); 5359095#L1079-1 assume !(1 == ~T5_E~0); 5359077#L1084-1 assume !(1 == ~T6_E~0); 5359078#L1089-1 assume !(1 == ~T7_E~0); 5359121#L1094-1 assume !(1 == ~T8_E~0); 5358688#L1099-1 assume !(1 == ~T9_E~0); 5358689#L1104-1 assume !(1 == ~E_M~0); 5358910#L1109-1 assume !(1 == ~E_1~0); 5358449#L1114-1 assume !(1 == ~E_2~0); 5358450#L1119-1 assume !(1 == ~E_3~0); 5358522#L1124-1 assume !(1 == ~E_4~0); 5357943#L1129-1 assume !(1 == ~E_5~0); 5357944#L1134-1 assume !(1 == ~E_6~0); 5358276#L1139-1 assume !(1 == ~E_7~0); 5358277#L1144-1 assume !(1 == ~E_8~0); 5358469#L1149-1 assume !(1 == ~E_9~0); 5358115#L1154-1 assume { :end_inline_reset_delta_events } true; 5358116#L1440-2 assume !false; 5467410#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5467405#L926 [2022-12-13 20:33:23,398 INFO L750 eck$LassoCheckResult]: Loop: 5467405#L926 assume !false; 5467403#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5467400#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5467398#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5467395#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5467393#L795 assume 0 != eval_~tmp~0#1; 5467391#L795-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5467388#L803 assume !(0 != eval_~tmp_ndt_1~0#1); 5404149#L800 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 5404145#L817 assume !(0 != eval_~tmp_ndt_2~0#1); 5404147#L814 assume !(0 == ~t2_st~0); 5468142#L828 assume !(0 == ~t3_st~0); 5468139#L842 assume !(0 == ~t4_st~0); 5468129#L856 assume !(0 == ~t5_st~0); 5468124#L870 assume !(0 == ~t6_st~0); 5468121#L884 assume !(0 == ~t7_st~0); 5467418#L898 assume !(0 == ~t8_st~0); 5467409#L912 assume !(0 == ~t9_st~0); 5467405#L926 [2022-12-13 20:33:23,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:33:23,398 INFO L85 PathProgramCache]: Analyzing trace with hash 981733315, now seen corresponding path program 1 times [2022-12-13 20:33:23,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:33:23,399 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130653603] [2022-12-13 20:33:23,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:33:23,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:33:23,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:33:23,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:33:23,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:33:23,418 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130653603] [2022-12-13 20:33:23,418 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130653603] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:33:23,418 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:33:23,418 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:33:23,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205787059] [2022-12-13 20:33:23,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:33:23,419 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:33:23,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:33:23,419 INFO L85 PathProgramCache]: Analyzing trace with hash 297636057, now seen corresponding path program 1 times [2022-12-13 20:33:23,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:33:23,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1497684617] [2022-12-13 20:33:23,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:33:23,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:33:23,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:33:23,422 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:33:23,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:33:23,425 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:33:23,500 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:33:23,500 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:33:23,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:33:23,500 INFO L87 Difference]: Start difference. First operand 546776 states and 740647 transitions. cyclomatic complexity: 193877 Second operand has 3 states, 3 states have (on average 39.666666666666664) internal successors, (119), 3 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:33:25,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:33:25,091 INFO L93 Difference]: Finished difference Result 546659 states and 740486 transitions. [2022-12-13 20:33:25,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546659 states and 740486 transitions. [2022-12-13 20:33:27,147 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 545512