./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.10.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.10.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 12:30:48,493 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 12:30:48,494 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 12:30:48,507 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 12:30:48,507 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 12:30:48,508 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 12:30:48,508 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 12:30:48,509 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 12:30:48,510 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 12:30:48,511 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 12:30:48,511 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 12:30:48,512 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 12:30:48,512 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 12:30:48,513 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 12:30:48,514 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 12:30:48,514 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 12:30:48,515 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 12:30:48,515 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 12:30:48,516 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 12:30:48,517 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 12:30:48,518 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 12:30:48,520 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 12:30:48,520 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 12:30:48,521 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 12:30:48,523 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 12:30:48,523 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 12:30:48,523 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 12:30:48,524 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 12:30:48,524 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 12:30:48,525 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 12:30:48,525 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 12:30:48,525 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 12:30:48,526 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 12:30:48,526 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 12:30:48,527 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 12:30:48,527 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 12:30:48,527 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 12:30:48,527 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 12:30:48,528 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 12:30:48,528 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 12:30:48,528 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 12:30:48,529 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 12:30:48,543 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 12:30:48,544 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 12:30:48,544 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 12:30:48,544 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 12:30:48,545 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 12:30:48,545 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 12:30:48,545 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 12:30:48,545 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 12:30:48,545 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 12:30:48,545 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 12:30:48,545 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 12:30:48,545 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 12:30:48,546 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 12:30:48,546 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 12:30:48,546 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 12:30:48,546 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 12:30:48,546 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 12:30:48,546 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 12:30:48,546 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 12:30:48,546 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 12:30:48,546 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 12:30:48,546 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 12:30:48,546 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 12:30:48,547 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 12:30:48,547 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 12:30:48,547 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 12:30:48,547 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 12:30:48,547 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 12:30:48,547 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 12:30:48,547 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 12:30:48,547 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 12:30:48,548 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 12:30:48,548 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 [2022-12-13 12:30:48,739 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 12:30:48,758 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 12:30:48,761 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 12:30:48,762 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 12:30:48,762 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 12:30:48,764 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2022-12-13 12:30:51,255 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 12:30:51,414 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 12:30:51,415 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2022-12-13 12:30:51,423 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8/data/10a6566dd/2f49cfee3e7247769cadaffe62808d76/FLAGb439e4a0a [2022-12-13 12:30:51,818 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8/data/10a6566dd/2f49cfee3e7247769cadaffe62808d76 [2022-12-13 12:30:51,821 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 12:30:51,822 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 12:30:51,823 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 12:30:51,823 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 12:30:51,826 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 12:30:51,827 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:30:51" (1/1) ... [2022-12-13 12:30:51,828 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3436e0d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:51, skipping insertion in model container [2022-12-13 12:30:51,828 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:30:51" (1/1) ... [2022-12-13 12:30:51,839 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 12:30:51,867 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 12:30:51,959 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/sv-benchmarks/c/systemc/token_ring.10.cil-2.c[671,684] [2022-12-13 12:30:52,028 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:30:52,042 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 12:30:52,053 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/sv-benchmarks/c/systemc/token_ring.10.cil-2.c[671,684] [2022-12-13 12:30:52,105 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:30:52,123 INFO L208 MainTranslator]: Completed translation [2022-12-13 12:30:52,123 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:52 WrapperNode [2022-12-13 12:30:52,123 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 12:30:52,124 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 12:30:52,125 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 12:30:52,125 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 12:30:52,131 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:52" (1/1) ... [2022-12-13 12:30:52,143 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:52" (1/1) ... [2022-12-13 12:30:52,192 INFO L138 Inliner]: procedures = 48, calls = 61, calls flagged for inlining = 56, calls inlined = 209, statements flattened = 3186 [2022-12-13 12:30:52,193 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 12:30:52,193 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 12:30:52,193 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 12:30:52,193 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 12:30:52,200 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:52" (1/1) ... [2022-12-13 12:30:52,200 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:52" (1/1) ... [2022-12-13 12:30:52,205 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:52" (1/1) ... [2022-12-13 12:30:52,206 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:52" (1/1) ... [2022-12-13 12:30:52,224 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:52" (1/1) ... [2022-12-13 12:30:52,240 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:52" (1/1) ... [2022-12-13 12:30:52,244 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:52" (1/1) ... [2022-12-13 12:30:52,250 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:52" (1/1) ... [2022-12-13 12:30:52,257 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 12:30:52,258 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 12:30:52,258 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 12:30:52,258 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 12:30:52,259 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:52" (1/1) ... [2022-12-13 12:30:52,264 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 12:30:52,271 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 12:30:52,281 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 12:30:52,283 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1c8b3846-d235-4f28-b9d8-5e2374d308a3/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 12:30:52,310 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 12:30:52,310 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 12:30:52,310 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 12:30:52,310 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 12:30:52,399 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 12:30:52,401 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 12:30:53,606 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 12:30:53,626 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 12:30:53,626 INFO L300 CfgBuilder]: Removed 13 assume(true) statements. [2022-12-13 12:30:53,629 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:30:53 BoogieIcfgContainer [2022-12-13 12:30:53,629 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 12:30:53,630 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 12:30:53,630 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 12:30:53,632 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 12:30:53,633 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:30:53,633 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 12:30:51" (1/3) ... [2022-12-13 12:30:53,634 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@863ee98 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:30:53, skipping insertion in model container [2022-12-13 12:30:53,634 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:30:53,634 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:30:52" (2/3) ... [2022-12-13 12:30:53,634 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@863ee98 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:30:53, skipping insertion in model container [2022-12-13 12:30:53,634 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:30:53,634 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:30:53" (3/3) ... [2022-12-13 12:30:53,635 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-2.c [2022-12-13 12:30:53,688 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 12:30:53,688 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 12:30:53,688 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 12:30:53,689 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 12:30:53,689 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 12:30:53,689 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 12:30:53,689 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 12:30:53,689 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 12:30:53,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1367 states, 1366 states have (on average 1.5058565153733527) internal successors, (2057), 1366 states have internal predecessors, (2057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:53,736 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1224 [2022-12-13 12:30:53,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:53,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:53,746 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:53,746 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:53,746 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 12:30:53,748 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1367 states, 1366 states have (on average 1.5058565153733527) internal successors, (2057), 1366 states have internal predecessors, (2057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:53,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1224 [2022-12-13 12:30:53,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:53,757 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:53,760 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:53,760 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:53,766 INFO L748 eck$LassoCheckResult]: Stem: 185#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1250#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 987#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1246#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 583#L719true assume !(1 == ~m_i~0);~m_st~0 := 2; 352#L719-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 557#L724-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 722#L729-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1236#L734-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 471#L739-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 837#L744-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 386#L749-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 677#L754-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 857#L759-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 634#L764-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 565#L769-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 846#L1024true assume !(0 == ~M_E~0); 949#L1024-2true assume !(0 == ~T1_E~0); 183#L1029-1true assume !(0 == ~T2_E~0); 241#L1034-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1315#L1039-1true assume !(0 == ~T4_E~0); 1024#L1044-1true assume !(0 == ~T5_E~0); 401#L1049-1true assume !(0 == ~T6_E~0); 1329#L1054-1true assume !(0 == ~T7_E~0); 582#L1059-1true assume !(0 == ~T8_E~0); 211#L1064-1true assume !(0 == ~T9_E~0); 811#L1069-1true assume !(0 == ~T10_E~0); 1229#L1074-1true assume 0 == ~E_M~0;~E_M~0 := 1; 887#L1079-1true assume !(0 == ~E_1~0); 849#L1084-1true assume !(0 == ~E_2~0); 1049#L1089-1true assume !(0 == ~E_3~0); 921#L1094-1true assume !(0 == ~E_4~0); 463#L1099-1true assume !(0 == ~E_5~0); 1065#L1104-1true assume !(0 == ~E_6~0); 695#L1109-1true assume !(0 == ~E_7~0); 314#L1114-1true assume 0 == ~E_8~0;~E_8~0 := 1; 1279#L1119-1true assume !(0 == ~E_9~0); 359#L1124-1true assume !(0 == ~E_10~0); 38#L1129-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 713#L502true assume 1 == ~m_pc~0; 580#L503true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 99#L513true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 840#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 631#L1273true assume !(0 != activate_threads_~tmp~1#1); 1366#L1273-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1135#L521true assume !(1 == ~t1_pc~0); 1060#L521-2true is_transmit1_triggered_~__retres1~1#1 := 0; 62#L532true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 646#L1281true assume !(0 != activate_threads_~tmp___0~0#1); 55#L1281-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 863#L540true assume 1 == ~t2_pc~0; 1116#L541true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 867#L551true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 312#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1230#L1289true assume !(0 != activate_threads_~tmp___1~0#1); 957#L1289-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200#L559true assume 1 == ~t3_pc~0; 1033#L560true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 371#L570true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 659#L1297true assume !(0 != activate_threads_~tmp___2~0#1); 107#L1297-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1256#L578true assume !(1 == ~t4_pc~0); 817#L578-2true is_transmit4_triggered_~__retres1~4#1 := 0; 843#L589true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1103#L1305true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 613#L1305-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1170#L597true assume 1 == ~t5_pc~0; 1334#L598true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 72#L608true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 844#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1354#L1313true assume !(0 != activate_threads_~tmp___4~0#1); 566#L1313-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 627#L616true assume !(1 == ~t6_pc~0); 1182#L616-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1078#L627true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 298#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 503#L1321true assume !(0 != activate_threads_~tmp___5~0#1); 456#L1321-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 691#L635true assume 1 == ~t7_pc~0; 616#L636true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 251#L646true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1264#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 916#L1329true assume !(0 != activate_threads_~tmp___6~0#1); 561#L1329-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 805#L654true assume !(1 == ~t8_pc~0); 420#L654-2true is_transmit8_triggered_~__retres1~8#1 := 0; 958#L665true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 755#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 808#L1337true assume !(0 != activate_threads_~tmp___7~0#1); 1010#L1337-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 182#L673true assume 1 == ~t9_pc~0; 1027#L674true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1206#L684true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 349#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 759#L1345true assume !(0 != activate_threads_~tmp___8~0#1); 707#L1345-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 876#L692true assume !(1 == ~t10_pc~0); 694#L692-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1017#L703true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 458#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 466#L1353true assume !(0 != activate_threads_~tmp___9~0#1); 781#L1353-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1312#L1142true assume !(1 == ~M_E~0); 136#L1142-2true assume !(1 == ~T1_E~0); 760#L1147-1true assume !(1 == ~T2_E~0); 1311#L1152-1true assume !(1 == ~T3_E~0); 376#L1157-1true assume !(1 == ~T4_E~0); 856#L1162-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 485#L1167-1true assume !(1 == ~T6_E~0); 941#L1172-1true assume !(1 == ~T7_E~0); 971#L1177-1true assume !(1 == ~T8_E~0); 598#L1182-1true assume !(1 == ~T9_E~0); 700#L1187-1true assume !(1 == ~T10_E~0); 749#L1192-1true assume !(1 == ~E_M~0); 282#L1197-1true assume !(1 == ~E_1~0); 764#L1202-1true assume 1 == ~E_2~0;~E_2~0 := 2; 549#L1207-1true assume !(1 == ~E_3~0); 533#L1212-1true assume !(1 == ~E_4~0); 65#L1217-1true assume !(1 == ~E_5~0); 1368#L1222-1true assume !(1 == ~E_6~0); 530#L1227-1true assume !(1 == ~E_7~0); 595#L1232-1true assume !(1 == ~E_8~0); 7#L1237-1true assume !(1 == ~E_9~0); 1070#L1242-1true assume 1 == ~E_10~0;~E_10~0 := 2; 581#L1247-1true assume { :end_inline_reset_delta_events } true; 87#L1553-2true [2022-12-13 12:30:53,768 INFO L750 eck$LassoCheckResult]: Loop: 87#L1553-2true assume !false; 746#L1554true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1338#L999true assume false; 770#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 475#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1292#L1024-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1014#L1024-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 453#L1029-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 429#L1034-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 727#L1039-3true assume !(0 == ~T4_E~0); 778#L1044-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 180#L1049-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 658#L1054-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 63#L1059-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1337#L1064-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 409#L1069-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 702#L1074-3true assume 0 == ~E_M~0;~E_M~0 := 1; 990#L1079-3true assume !(0 == ~E_1~0); 589#L1084-3true assume 0 == ~E_2~0;~E_2~0 := 1; 498#L1089-3true assume 0 == ~E_3~0;~E_3~0 := 1; 656#L1094-3true assume 0 == ~E_4~0;~E_4~0 := 1; 442#L1099-3true assume 0 == ~E_5~0;~E_5~0 := 1; 725#L1104-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1076#L1109-3true assume 0 == ~E_7~0;~E_7~0 := 1; 711#L1114-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1195#L1119-3true assume !(0 == ~E_9~0); 1331#L1124-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1227#L1129-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1110#L502-36true assume !(1 == ~m_pc~0); 262#L502-38true is_master_triggered_~__retres1~0#1 := 0; 2#L513-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 992#is_master_triggered_returnLabel#13true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 212#L1273-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 696#L1273-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 388#L521-36true assume 1 == ~t1_pc~0; 396#L522-12true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 522#L532-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 988#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1200#L1281-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 815#L1281-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1119#L540-36true assume !(1 == ~t2_pc~0); 41#L540-38true is_transmit2_triggered_~__retres1~2#1 := 0; 253#L551-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 816#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1339#L1289-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 482#L1289-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6#L559-36true assume !(1 == ~t3_pc~0); 233#L559-38true is_transmit3_triggered_~__retres1~3#1 := 0; 747#L570-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 347#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 600#L1297-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 882#L1297-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1240#L578-36true assume !(1 == ~t4_pc~0); 540#L578-38true is_transmit4_triggered_~__retres1~4#1 := 0; 1249#L589-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 490#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1310#L1305-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 413#L1305-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 588#L597-36true assume 1 == ~t5_pc~0; 1223#L598-12true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1069#L608-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 956#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 550#L1313-36true assume !(0 != activate_threads_~tmp___4~0#1); 283#L1313-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1121#L616-36true assume !(1 == ~t6_pc~0); 1003#L616-38true is_transmit6_triggered_~__retres1~6#1 := 0; 36#L627-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 332#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 450#L1321-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 745#L1321-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1350#L635-36true assume !(1 == ~t7_pc~0); 1234#L635-38true is_transmit7_triggered_~__retres1~7#1 := 0; 828#L646-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 920#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1272#L1329-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 440#L1329-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1285#L654-36true assume !(1 == ~t8_pc~0); 1022#L654-38true is_transmit8_triggered_~__retres1~8#1 := 0; 1333#L665-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 570#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1181#L1337-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1137#L1337-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 227#L673-36true assume !(1 == ~t9_pc~0); 732#L673-38true is_transmit9_triggered_~__retres1~9#1 := 0; 472#L684-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 374#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1039#L1345-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10#L1345-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1192#L692-36true assume !(1 == ~t10_pc~0); 111#L692-38true is_transmit10_triggered_~__retres1~10#1 := 0; 449#L703-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 272#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 209#L1353-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 448#L1353-38true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 567#L1142-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1176#L1142-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1023#L1147-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1081#L1152-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 507#L1157-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 824#L1162-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1079#L1167-3true assume !(1 == ~T6_E~0); 1000#L1172-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 438#L1177-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 368#L1182-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 855#L1187-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 378#L1192-3true assume 1 == ~E_M~0;~E_M~0 := 2; 260#L1197-3true assume 1 == ~E_1~0;~E_1~0 := 2; 427#L1202-3true assume 1 == ~E_2~0;~E_2~0 := 2; 516#L1207-3true assume !(1 == ~E_3~0); 1117#L1212-3true assume 1 == ~E_4~0;~E_4~0 := 2; 723#L1217-3true assume 1 == ~E_5~0;~E_5~0 := 2; 204#L1222-3true assume 1 == ~E_6~0;~E_6~0 := 2; 47#L1227-3true assume 1 == ~E_7~0;~E_7~0 := 2; 888#L1232-3true assume 1 == ~E_8~0;~E_8~0 := 2; 858#L1237-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1297#L1242-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1254#L1247-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 933#L782-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 119#L839-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 265#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 574#L1572true assume !(0 == start_simulation_~tmp~3#1); 389#L1572-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1222#L782-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1094#L839-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 42#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1288#L1527true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4#L1534true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 493#stop_simulation_returnLabel#1true start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1359#L1585true assume !(0 != start_simulation_~tmp___0~1#1); 87#L1553-2true [2022-12-13 12:30:53,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:53,773 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2022-12-13 12:30:53,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:53,780 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659243172] [2022-12-13 12:30:53,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:53,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:53,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:53,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:53,973 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:53,973 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [659243172] [2022-12-13 12:30:53,974 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [659243172] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:53,974 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:53,974 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:53,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [817376567] [2022-12-13 12:30:53,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:53,980 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:53,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:53,981 INFO L85 PathProgramCache]: Analyzing trace with hash 613481661, now seen corresponding path program 1 times [2022-12-13 12:30:53,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:53,981 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749579036] [2022-12-13 12:30:53,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:53,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:53,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:54,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:54,024 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:54,025 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [749579036] [2022-12-13 12:30:54,025 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [749579036] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:54,025 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:54,025 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:30:54,025 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424872890] [2022-12-13 12:30:54,025 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:54,026 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:54,027 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:54,050 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:30:54,051 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:30:54,055 INFO L87 Difference]: Start difference. First operand has 1367 states, 1366 states have (on average 1.5058565153733527) internal successors, (2057), 1366 states have internal predecessors, (2057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:54,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:54,128 INFO L93 Difference]: Finished difference Result 1366 states and 2028 transitions. [2022-12-13 12:30:54,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2028 transitions. [2022-12-13 12:30:54,139 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:54,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1361 states and 2023 transitions. [2022-12-13 12:30:54,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-12-13 12:30:54,155 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-12-13 12:30:54,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2023 transitions. [2022-12-13 12:30:54,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:54,162 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2023 transitions. [2022-12-13 12:30:54,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2023 transitions. [2022-12-13 12:30:54,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-12-13 12:30:54,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4864070536370315) internal successors, (2023), 1360 states have internal predecessors, (2023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:54,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2023 transitions. [2022-12-13 12:30:54,235 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2023 transitions. [2022-12-13 12:30:54,236 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:30:54,240 INFO L428 stractBuchiCegarLoop]: Abstraction has 1361 states and 2023 transitions. [2022-12-13 12:30:54,240 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 12:30:54,240 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2023 transitions. [2022-12-13 12:30:54,247 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:54,247 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:54,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:54,250 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:54,250 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:54,251 INFO L748 eck$LassoCheckResult]: Stem: 3119#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3120#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4015#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4016#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3699#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3388#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3389#L724-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3669#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3835#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3557#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3558#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3439#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3440#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3790#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3753#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3677#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3678#L1024 assume !(0 == ~M_E~0); 3929#L1024-2 assume !(0 == ~T1_E~0); 3115#L1029-1 assume !(0 == ~T2_E~0); 3116#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3217#L1039-1 assume !(0 == ~T4_E~0); 4039#L1044-1 assume !(0 == ~T5_E~0); 3461#L1049-1 assume !(0 == ~T6_E~0); 3462#L1054-1 assume !(0 == ~T7_E~0); 3698#L1059-1 assume !(0 == ~T8_E~0); 3165#L1064-1 assume !(0 == ~T9_E~0); 3166#L1069-1 assume !(0 == ~T10_E~0); 3897#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3958#L1079-1 assume !(0 == ~E_1~0); 3931#L1084-1 assume !(0 == ~E_2~0); 3932#L1089-1 assume !(0 == ~E_3~0); 3976#L1094-1 assume !(0 == ~E_4~0); 3547#L1099-1 assume !(0 == ~E_5~0); 3548#L1104-1 assume !(0 == ~E_6~0); 3807#L1109-1 assume !(0 == ~E_7~0); 3328#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3329#L1119-1 assume !(0 == ~E_9~0); 3399#L1124-1 assume !(0 == ~E_10~0); 2822#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2823#L502 assume 1 == ~m_pc~0; 3696#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2948#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2949#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3749#L1273 assume !(0 != activate_threads_~tmp~1#1); 3750#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4069#L521 assume !(1 == ~t1_pc~0); 4004#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2873#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2838#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2839#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 2859#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2860#L540 assume 1 == ~t2_pc~0; 3942#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3658#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3324#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3325#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 4000#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3143#L559 assume 1 == ~t3_pc~0; 3144#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3419#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2777#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2778#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 2966#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2967#L578 assume !(1 == ~t4_pc~0); 3087#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3086#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2906#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2907#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3730#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3731#L597 assume 1 == ~t5_pc~0; 4085#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2893#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2894#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3927#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3679#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3680#L616 assume !(1 == ~t6_pc~0); 3695#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3694#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3300#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3301#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3537#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3538#L635 assume 1 == ~t7_pc~0; 3734#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2862#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3235#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3972#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3671#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3672#L654 assume !(1 == ~t8_pc~0); 3488#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3489#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3861#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3862#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3895#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3113#L673 assume 1 == ~t9_pc~0; 3114#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2813#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3383#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3384#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3819#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3820#L692 assume !(1 == ~t10_pc~0); 3766#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3765#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3539#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3540#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3551#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3874#L1142 assume !(1 == ~M_E~0); 3025#L1142-2 assume !(1 == ~T1_E~0); 3026#L1147-1 assume !(1 == ~T2_E~0); 3865#L1152-1 assume !(1 == ~T3_E~0); 3425#L1157-1 assume !(1 == ~T4_E~0); 3426#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3575#L1167-1 assume !(1 == ~T6_E~0); 3576#L1172-1 assume !(1 == ~T7_E~0); 3994#L1177-1 assume !(1 == ~T8_E~0); 3716#L1182-1 assume !(1 == ~T9_E~0); 3717#L1187-1 assume !(1 == ~T10_E~0); 3812#L1192-1 assume !(1 == ~E_M~0); 3280#L1197-1 assume !(1 == ~E_1~0); 3281#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3661#L1207-1 assume !(1 == ~E_3~0); 3636#L1212-1 assume !(1 == ~E_4~0); 2878#L1217-1 assume !(1 == ~E_5~0); 2879#L1222-1 assume !(1 == ~E_6~0); 3633#L1227-1 assume !(1 == ~E_7~0); 3634#L1232-1 assume !(1 == ~E_8~0); 2754#L1237-1 assume !(1 == ~E_9~0); 2755#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3697#L1247-1 assume { :end_inline_reset_delta_events } true; 2923#L1553-2 [2022-12-13 12:30:54,251 INFO L750 eck$LassoCheckResult]: Loop: 2923#L1553-2 assume !false; 2924#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2851#L999 assume !false; 3904#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3009#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2896#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3362#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3363#L854 assume !(0 != eval_~tmp~0#1); 3771#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3560#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3561#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4029#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3533#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3501#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3502#L1039-3 assume !(0 == ~T4_E~0); 3840#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3109#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3110#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2874#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2875#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3471#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3472#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3814#L1079-3 assume !(0 == ~E_1~0); 3709#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3594#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3595#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3520#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3521#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3838#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3826#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3827#L1119-3 assume !(0 == ~E_9~0); 4090#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4097#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4063#L502-36 assume !(1 == ~m_pc~0); 3248#L502-38 is_master_triggered_~__retres1~0#1 := 0; 2742#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2743#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3167#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3168#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3444#L521-36 assume 1 == ~t1_pc~0; 3445#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3455#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3625#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4017#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3899#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3900#L540-36 assume 1 == ~t2_pc~0; 4065#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2830#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3236#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3901#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3570#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2748#L559-36 assume 1 == ~t3_pc~0; 2749#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3199#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3378#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3379#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3718#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3954#L578-36 assume 1 == ~t4_pc~0; 3687#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3643#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3581#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3582#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3477#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3478#L597-36 assume !(1 == ~t5_pc~0); 3706#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4055#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3999#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3660#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 3278#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3279#L616-36 assume 1 == ~t6_pc~0; 4066#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2818#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2819#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3357#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3530#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3855#L635-36 assume 1 == ~t7_pc~0; 4030#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3912#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3913#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3975#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3516#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3517#L654-36 assume !(1 == ~t8_pc~0); 4035#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 4036#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3683#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3684#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4070#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3191#L673-36 assume !(1 == ~t9_pc~0); 3192#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3556#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3421#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3422#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2761#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2762#L692-36 assume 1 == ~t10_pc~0; 3708#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2975#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3262#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3160#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3161#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3527#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3676#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4037#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4038#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3607#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3608#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3908#L1167-3 assume !(1 == ~T6_E~0); 4021#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3515#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3413#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3414#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3428#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3245#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3246#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3498#L1207-3 assume !(1 == ~E_3~0); 3616#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3836#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3153#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2843#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2844#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3937#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3938#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4100#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3986#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2994#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2995#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3252#L1572 assume !(0 == start_simulation_~tmp~3#1); 3283#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3447#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2775#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2831#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 2832#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2746#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2747#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3587#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 2923#L1553-2 [2022-12-13 12:30:54,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:54,252 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2022-12-13 12:30:54,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:54,253 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818024417] [2022-12-13 12:30:54,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:54,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:54,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:54,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:54,334 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:54,334 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [818024417] [2022-12-13 12:30:54,334 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [818024417] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:54,334 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:54,334 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:54,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [796995787] [2022-12-13 12:30:54,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:54,335 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:54,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:54,336 INFO L85 PathProgramCache]: Analyzing trace with hash 1162970293, now seen corresponding path program 1 times [2022-12-13 12:30:54,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:54,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321759210] [2022-12-13 12:30:54,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:54,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:54,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:54,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:54,437 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:54,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321759210] [2022-12-13 12:30:54,437 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321759210] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:54,437 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:54,437 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:54,438 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [688271060] [2022-12-13 12:30:54,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:54,438 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:54,438 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:54,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:30:54,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:30:54,439 INFO L87 Difference]: Start difference. First operand 1361 states and 2023 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:54,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:54,472 INFO L93 Difference]: Finished difference Result 1361 states and 2022 transitions. [2022-12-13 12:30:54,472 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2022 transitions. [2022-12-13 12:30:54,480 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:54,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2022 transitions. [2022-12-13 12:30:54,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-12-13 12:30:54,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-12-13 12:30:54,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2022 transitions. [2022-12-13 12:30:54,491 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:54,491 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2022 transitions. [2022-12-13 12:30:54,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2022 transitions. [2022-12-13 12:30:54,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-12-13 12:30:54,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.485672299779574) internal successors, (2022), 1360 states have internal predecessors, (2022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:54,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2022 transitions. [2022-12-13 12:30:54,516 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2022 transitions. [2022-12-13 12:30:54,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:30:54,517 INFO L428 stractBuchiCegarLoop]: Abstraction has 1361 states and 2022 transitions. [2022-12-13 12:30:54,517 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 12:30:54,517 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2022 transitions. [2022-12-13 12:30:54,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:54,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:54,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:54,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:54,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:54,526 INFO L748 eck$LassoCheckResult]: Stem: 5848#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5849#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6744#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6745#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6428#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 6116#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6117#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6398#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6564#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6285#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6286#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6168#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6169#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6519#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6482#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6405#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6406#L1024 assume !(0 == ~M_E~0); 6658#L1024-2 assume !(0 == ~T1_E~0); 5844#L1029-1 assume !(0 == ~T2_E~0); 5845#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5946#L1039-1 assume !(0 == ~T4_E~0); 6768#L1044-1 assume !(0 == ~T5_E~0); 6188#L1049-1 assume !(0 == ~T6_E~0); 6189#L1054-1 assume !(0 == ~T7_E~0); 6427#L1059-1 assume !(0 == ~T8_E~0); 5894#L1064-1 assume !(0 == ~T9_E~0); 5895#L1069-1 assume !(0 == ~T10_E~0); 6626#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6687#L1079-1 assume !(0 == ~E_1~0); 6660#L1084-1 assume !(0 == ~E_2~0); 6661#L1089-1 assume !(0 == ~E_3~0); 6705#L1094-1 assume !(0 == ~E_4~0); 6276#L1099-1 assume !(0 == ~E_5~0); 6277#L1104-1 assume !(0 == ~E_6~0); 6536#L1109-1 assume !(0 == ~E_7~0); 6057#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6058#L1119-1 assume !(0 == ~E_9~0); 6126#L1124-1 assume !(0 == ~E_10~0); 5551#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5552#L502 assume 1 == ~m_pc~0; 6425#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5677#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5678#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6476#L1273 assume !(0 != activate_threads_~tmp~1#1); 6477#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6798#L521 assume !(1 == ~t1_pc~0); 6733#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5602#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5567#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5568#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 5588#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5589#L540 assume 1 == ~t2_pc~0; 6671#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6387#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6053#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6054#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 6729#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5872#L559 assume 1 == ~t3_pc~0; 5873#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6147#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5506#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5507#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 5695#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5696#L578 assume !(1 == ~t4_pc~0); 5811#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5810#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5634#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5635#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6457#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6458#L597 assume 1 == ~t5_pc~0; 6813#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5622#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5623#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6656#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 6407#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6408#L616 assume !(1 == ~t6_pc~0); 6422#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6421#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6029#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6030#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 6265#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6266#L635 assume 1 == ~t7_pc~0; 6462#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5591#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5962#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6701#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 6400#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6401#L654 assume !(1 == ~t8_pc~0); 6217#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6218#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6587#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6588#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 6624#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5842#L673 assume 1 == ~t9_pc~0; 5843#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5542#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6110#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6111#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 6548#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6549#L692 assume !(1 == ~t10_pc~0); 6495#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6494#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6268#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6269#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 6280#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6603#L1142 assume !(1 == ~M_E~0); 5754#L1142-2 assume !(1 == ~T1_E~0); 5755#L1147-1 assume !(1 == ~T2_E~0); 6594#L1152-1 assume !(1 == ~T3_E~0); 6154#L1157-1 assume !(1 == ~T4_E~0); 6155#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6304#L1167-1 assume !(1 == ~T6_E~0); 6305#L1172-1 assume !(1 == ~T7_E~0); 6722#L1177-1 assume !(1 == ~T8_E~0); 6445#L1182-1 assume !(1 == ~T9_E~0); 6446#L1187-1 assume !(1 == ~T10_E~0); 6541#L1192-1 assume !(1 == ~E_M~0); 6007#L1197-1 assume !(1 == ~E_1~0); 6008#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6389#L1207-1 assume !(1 == ~E_3~0); 6365#L1212-1 assume !(1 == ~E_4~0); 5607#L1217-1 assume !(1 == ~E_5~0); 5608#L1222-1 assume !(1 == ~E_6~0); 6362#L1227-1 assume !(1 == ~E_7~0); 6363#L1232-1 assume !(1 == ~E_8~0); 5483#L1237-1 assume !(1 == ~E_9~0); 5484#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 6426#L1247-1 assume { :end_inline_reset_delta_events } true; 5652#L1553-2 [2022-12-13 12:30:54,527 INFO L750 eck$LassoCheckResult]: Loop: 5652#L1553-2 assume !false; 5653#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5580#L999 assume !false; 6631#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5738#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5625#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6091#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6092#L854 assume !(0 != eval_~tmp~0#1); 6500#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6289#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6290#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6758#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6262#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6230#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6231#L1039-3 assume !(0 == ~T4_E~0); 6569#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5838#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5839#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5603#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5604#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6200#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6201#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6543#L1079-3 assume !(0 == ~E_1~0); 6437#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6323#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6324#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6249#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6250#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6567#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6555#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6556#L1119-3 assume !(0 == ~E_9~0); 6819#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6826#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6792#L502-36 assume !(1 == ~m_pc~0); 5977#L502-38 is_master_triggered_~__retres1~0#1 := 0; 5471#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5472#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5896#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5897#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6173#L521-36 assume 1 == ~t1_pc~0; 6174#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6184#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6354#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6746#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6628#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6629#L540-36 assume !(1 == ~t2_pc~0); 5558#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5559#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5965#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6630#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6299#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5480#L559-36 assume 1 == ~t3_pc~0; 5481#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5933#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6107#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6108#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6447#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6683#L578-36 assume 1 == ~t4_pc~0; 6416#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6375#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6311#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6312#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6208#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6209#L597-36 assume !(1 == ~t5_pc~0); 6435#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 6784#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6728#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6390#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 6009#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6010#L616-36 assume !(1 == ~t6_pc~0); 6754#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 5547#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5548#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6086#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6259#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6584#L635-36 assume 1 == ~t7_pc~0; 6759#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6641#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6642#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6704#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6245#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6246#L654-36 assume 1 == ~t8_pc~0; 6822#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6765#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6412#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6413#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6799#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5920#L673-36 assume !(1 == ~t9_pc~0); 5921#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 6287#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6150#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6151#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5490#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5491#L692-36 assume 1 == ~t10_pc~0; 6438#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5704#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5991#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5889#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5890#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6258#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6409#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6766#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6767#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6336#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6337#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6637#L1167-3 assume !(1 == ~T6_E~0); 6750#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6244#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6142#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6143#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6157#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5974#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5975#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6227#L1207-3 assume !(1 == ~E_3~0); 6345#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6565#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5882#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5572#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5573#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6666#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6667#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6829#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6715#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5723#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5724#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5981#L1572 assume !(0 == start_simulation_~tmp~3#1); 6012#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6176#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5504#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5560#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 5561#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5475#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5476#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6316#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 5652#L1553-2 [2022-12-13 12:30:54,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:54,528 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2022-12-13 12:30:54,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:54,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612401893] [2022-12-13 12:30:54,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:54,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:54,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:54,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:54,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:54,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612401893] [2022-12-13 12:30:54,588 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [612401893] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:54,589 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:54,589 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:54,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [683023662] [2022-12-13 12:30:54,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:54,590 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:54,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:54,591 INFO L85 PathProgramCache]: Analyzing trace with hash 427710326, now seen corresponding path program 1 times [2022-12-13 12:30:54,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:54,591 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433526584] [2022-12-13 12:30:54,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:54,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:54,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:54,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:54,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:54,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433526584] [2022-12-13 12:30:54,659 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [433526584] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:54,659 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:54,659 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:54,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1251044521] [2022-12-13 12:30:54,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:54,660 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:54,660 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:54,660 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:30:54,660 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:30:54,660 INFO L87 Difference]: Start difference. First operand 1361 states and 2022 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:54,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:54,687 INFO L93 Difference]: Finished difference Result 1361 states and 2021 transitions. [2022-12-13 12:30:54,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2021 transitions. [2022-12-13 12:30:54,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:54,701 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2021 transitions. [2022-12-13 12:30:54,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-12-13 12:30:54,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-12-13 12:30:54,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2021 transitions. [2022-12-13 12:30:54,705 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:54,705 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2021 transitions. [2022-12-13 12:30:54,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2021 transitions. [2022-12-13 12:30:54,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-12-13 12:30:54,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4849375459221161) internal successors, (2021), 1360 states have internal predecessors, (2021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:54,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2021 transitions. [2022-12-13 12:30:54,729 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2021 transitions. [2022-12-13 12:30:54,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:30:54,730 INFO L428 stractBuchiCegarLoop]: Abstraction has 1361 states and 2021 transitions. [2022-12-13 12:30:54,730 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 12:30:54,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2021 transitions. [2022-12-13 12:30:54,736 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:54,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:54,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:54,738 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:54,738 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:54,739 INFO L748 eck$LassoCheckResult]: Stem: 8577#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 8578#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9473#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9474#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9157#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 8845#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8846#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9127#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9293#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9014#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9015#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8897#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8898#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9248#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9211#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9134#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9135#L1024 assume !(0 == ~M_E~0); 9387#L1024-2 assume !(0 == ~T1_E~0); 8573#L1029-1 assume !(0 == ~T2_E~0); 8574#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8675#L1039-1 assume !(0 == ~T4_E~0); 9497#L1044-1 assume !(0 == ~T5_E~0); 8917#L1049-1 assume !(0 == ~T6_E~0); 8918#L1054-1 assume !(0 == ~T7_E~0); 9156#L1059-1 assume !(0 == ~T8_E~0); 8623#L1064-1 assume !(0 == ~T9_E~0); 8624#L1069-1 assume !(0 == ~T10_E~0); 9355#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 9416#L1079-1 assume !(0 == ~E_1~0); 9389#L1084-1 assume !(0 == ~E_2~0); 9390#L1089-1 assume !(0 == ~E_3~0); 9434#L1094-1 assume !(0 == ~E_4~0); 9005#L1099-1 assume !(0 == ~E_5~0); 9006#L1104-1 assume !(0 == ~E_6~0); 9265#L1109-1 assume !(0 == ~E_7~0); 8786#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8787#L1119-1 assume !(0 == ~E_9~0); 8855#L1124-1 assume !(0 == ~E_10~0); 8280#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8281#L502 assume 1 == ~m_pc~0; 9154#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8406#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8407#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9205#L1273 assume !(0 != activate_threads_~tmp~1#1); 9206#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9527#L521 assume !(1 == ~t1_pc~0); 9462#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8331#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8296#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8297#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 8317#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8318#L540 assume 1 == ~t2_pc~0; 9400#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9116#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8782#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8783#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 9458#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8601#L559 assume 1 == ~t3_pc~0; 8602#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8876#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8235#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8236#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 8424#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8425#L578 assume !(1 == ~t4_pc~0); 8542#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8541#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8363#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8364#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9188#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9189#L597 assume 1 == ~t5_pc~0; 9542#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8351#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8352#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9385#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 9136#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9137#L616 assume !(1 == ~t6_pc~0); 9151#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9150#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8758#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8759#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 8994#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8995#L635 assume 1 == ~t7_pc~0; 9191#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8320#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8691#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9430#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 9129#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9130#L654 assume !(1 == ~t8_pc~0); 8946#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8947#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9316#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9317#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 9353#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8571#L673 assume 1 == ~t9_pc~0; 8572#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8271#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8839#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8840#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 9277#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9278#L692 assume !(1 == ~t10_pc~0); 9224#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9223#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8997#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8998#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 9009#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9332#L1142 assume !(1 == ~M_E~0); 8483#L1142-2 assume !(1 == ~T1_E~0); 8484#L1147-1 assume !(1 == ~T2_E~0); 9323#L1152-1 assume !(1 == ~T3_E~0); 8883#L1157-1 assume !(1 == ~T4_E~0); 8884#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9033#L1167-1 assume !(1 == ~T6_E~0); 9034#L1172-1 assume !(1 == ~T7_E~0); 9451#L1177-1 assume !(1 == ~T8_E~0); 9174#L1182-1 assume !(1 == ~T9_E~0); 9175#L1187-1 assume !(1 == ~T10_E~0); 9270#L1192-1 assume !(1 == ~E_M~0); 8736#L1197-1 assume !(1 == ~E_1~0); 8737#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9118#L1207-1 assume !(1 == ~E_3~0); 9094#L1212-1 assume !(1 == ~E_4~0); 8336#L1217-1 assume !(1 == ~E_5~0); 8337#L1222-1 assume !(1 == ~E_6~0); 9091#L1227-1 assume !(1 == ~E_7~0); 9092#L1232-1 assume !(1 == ~E_8~0); 8212#L1237-1 assume !(1 == ~E_9~0); 8213#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 9155#L1247-1 assume { :end_inline_reset_delta_events } true; 8381#L1553-2 [2022-12-13 12:30:54,739 INFO L750 eck$LassoCheckResult]: Loop: 8381#L1553-2 assume !false; 8382#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8309#L999 assume !false; 9360#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8467#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8354#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8820#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8821#L854 assume !(0 != eval_~tmp~0#1); 9229#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9018#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9019#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9487#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8991#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8959#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8960#L1039-3 assume !(0 == ~T4_E~0); 9298#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8567#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8568#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8332#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8333#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8929#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8930#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9272#L1079-3 assume !(0 == ~E_1~0); 9166#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9052#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9053#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8978#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8979#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9296#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9284#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9285#L1119-3 assume !(0 == ~E_9~0); 9548#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9555#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9521#L502-36 assume !(1 == ~m_pc~0); 8706#L502-38 is_master_triggered_~__retres1~0#1 := 0; 8200#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8201#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8625#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8626#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8902#L521-36 assume 1 == ~t1_pc~0; 8903#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8913#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9083#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9475#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9357#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9358#L540-36 assume 1 == ~t2_pc~0; 9523#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8288#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8694#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9359#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9028#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8209#L559-36 assume 1 == ~t3_pc~0; 8210#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8662#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8836#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8837#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9176#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9412#L578-36 assume 1 == ~t4_pc~0; 9145#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9104#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9040#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9041#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8937#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8938#L597-36 assume !(1 == ~t5_pc~0); 9164#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 9513#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9457#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9119#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 8738#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8739#L616-36 assume 1 == ~t6_pc~0; 9524#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8276#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8277#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8815#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8988#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9313#L635-36 assume 1 == ~t7_pc~0; 9488#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9370#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9371#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9433#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8974#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8975#L654-36 assume !(1 == ~t8_pc~0); 9493#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 9494#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9141#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9142#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9528#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8649#L673-36 assume !(1 == ~t9_pc~0); 8650#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 9016#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8879#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8880#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8219#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8220#L692-36 assume !(1 == ~t10_pc~0); 8432#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 8433#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8720#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8618#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8619#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8987#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9138#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9495#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9496#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9065#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9066#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9366#L1167-3 assume !(1 == ~T6_E~0); 9479#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8973#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8871#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8872#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8886#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8703#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8704#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8956#L1207-3 assume !(1 == ~E_3~0); 9074#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9294#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8611#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8301#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8302#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9395#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9396#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9558#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9444#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8452#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8453#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8710#L1572 assume !(0 == start_simulation_~tmp~3#1); 8741#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8905#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8233#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8289#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 8290#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8204#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8205#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9045#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 8381#L1553-2 [2022-12-13 12:30:54,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:54,740 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2022-12-13 12:30:54,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:54,741 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207328781] [2022-12-13 12:30:54,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:54,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:54,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:54,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:54,788 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:54,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1207328781] [2022-12-13 12:30:54,788 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1207328781] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:54,788 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:54,789 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:54,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885958320] [2022-12-13 12:30:54,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:54,789 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:54,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:54,790 INFO L85 PathProgramCache]: Analyzing trace with hash 677795574, now seen corresponding path program 1 times [2022-12-13 12:30:54,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:54,790 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189190397] [2022-12-13 12:30:54,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:54,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:54,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:54,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:54,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:54,835 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189190397] [2022-12-13 12:30:54,835 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189190397] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:54,835 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:54,836 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:54,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512163479] [2022-12-13 12:30:54,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:54,836 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:54,836 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:54,837 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:30:54,837 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:30:54,837 INFO L87 Difference]: Start difference. First operand 1361 states and 2021 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:54,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:54,856 INFO L93 Difference]: Finished difference Result 1361 states and 2020 transitions. [2022-12-13 12:30:54,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2020 transitions. [2022-12-13 12:30:54,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:54,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2020 transitions. [2022-12-13 12:30:54,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-12-13 12:30:54,874 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-12-13 12:30:54,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2020 transitions. [2022-12-13 12:30:54,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:54,876 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2020 transitions. [2022-12-13 12:30:54,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2020 transitions. [2022-12-13 12:30:54,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-12-13 12:30:54,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4842027920646583) internal successors, (2020), 1360 states have internal predecessors, (2020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:54,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2020 transitions. [2022-12-13 12:30:54,895 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2020 transitions. [2022-12-13 12:30:54,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:30:54,896 INFO L428 stractBuchiCegarLoop]: Abstraction has 1361 states and 2020 transitions. [2022-12-13 12:30:54,896 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 12:30:54,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2020 transitions. [2022-12-13 12:30:54,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:54,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:54,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:54,903 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:54,903 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:54,903 INFO L748 eck$LassoCheckResult]: Stem: 11306#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11307#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 12202#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12203#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11886#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 11575#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11576#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11856#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12022#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11744#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11745#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11626#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11627#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11977#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11940#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11864#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11865#L1024 assume !(0 == ~M_E~0); 12116#L1024-2 assume !(0 == ~T1_E~0); 11302#L1029-1 assume !(0 == ~T2_E~0); 11303#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11404#L1039-1 assume !(0 == ~T4_E~0); 12226#L1044-1 assume !(0 == ~T5_E~0); 11648#L1049-1 assume !(0 == ~T6_E~0); 11649#L1054-1 assume !(0 == ~T7_E~0); 11885#L1059-1 assume !(0 == ~T8_E~0); 11352#L1064-1 assume !(0 == ~T9_E~0); 11353#L1069-1 assume !(0 == ~T10_E~0); 12084#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 12145#L1079-1 assume !(0 == ~E_1~0); 12118#L1084-1 assume !(0 == ~E_2~0); 12119#L1089-1 assume !(0 == ~E_3~0); 12163#L1094-1 assume !(0 == ~E_4~0); 11734#L1099-1 assume !(0 == ~E_5~0); 11735#L1104-1 assume !(0 == ~E_6~0); 11994#L1109-1 assume !(0 == ~E_7~0); 11515#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11516#L1119-1 assume !(0 == ~E_9~0); 11586#L1124-1 assume !(0 == ~E_10~0); 11009#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11010#L502 assume 1 == ~m_pc~0; 11883#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11135#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11136#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11936#L1273 assume !(0 != activate_threads_~tmp~1#1); 11937#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12256#L521 assume !(1 == ~t1_pc~0); 12191#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11060#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11025#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11026#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 11046#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11047#L540 assume 1 == ~t2_pc~0; 12129#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11845#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11511#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11512#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 12187#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11330#L559 assume 1 == ~t3_pc~0; 11331#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11606#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10964#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10965#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 11153#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11154#L578 assume !(1 == ~t4_pc~0); 11274#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11273#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11093#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11094#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11917#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11918#L597 assume 1 == ~t5_pc~0; 12272#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11080#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11081#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12114#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 11866#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11867#L616 assume !(1 == ~t6_pc~0); 11882#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11881#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11487#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11488#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 11724#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11725#L635 assume 1 == ~t7_pc~0; 11921#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11049#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11422#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12159#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 11858#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11859#L654 assume !(1 == ~t8_pc~0); 11675#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11676#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12048#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12049#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 12082#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11300#L673 assume 1 == ~t9_pc~0; 11301#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11000#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11570#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11571#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 12006#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12007#L692 assume !(1 == ~t10_pc~0); 11953#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11952#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11726#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11727#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 11738#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12061#L1142 assume !(1 == ~M_E~0); 11212#L1142-2 assume !(1 == ~T1_E~0); 11213#L1147-1 assume !(1 == ~T2_E~0); 12052#L1152-1 assume !(1 == ~T3_E~0); 11612#L1157-1 assume !(1 == ~T4_E~0); 11613#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11762#L1167-1 assume !(1 == ~T6_E~0); 11763#L1172-1 assume !(1 == ~T7_E~0); 12181#L1177-1 assume !(1 == ~T8_E~0); 11903#L1182-1 assume !(1 == ~T9_E~0); 11904#L1187-1 assume !(1 == ~T10_E~0); 11999#L1192-1 assume !(1 == ~E_M~0); 11467#L1197-1 assume !(1 == ~E_1~0); 11468#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 11848#L1207-1 assume !(1 == ~E_3~0); 11823#L1212-1 assume !(1 == ~E_4~0); 11065#L1217-1 assume !(1 == ~E_5~0); 11066#L1222-1 assume !(1 == ~E_6~0); 11820#L1227-1 assume !(1 == ~E_7~0); 11821#L1232-1 assume !(1 == ~E_8~0); 10941#L1237-1 assume !(1 == ~E_9~0); 10942#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11884#L1247-1 assume { :end_inline_reset_delta_events } true; 11110#L1553-2 [2022-12-13 12:30:54,904 INFO L750 eck$LassoCheckResult]: Loop: 11110#L1553-2 assume !false; 11111#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11038#L999 assume !false; 12091#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11196#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11083#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11549#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11550#L854 assume !(0 != eval_~tmp~0#1); 11958#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11747#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11748#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12216#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11720#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11688#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11689#L1039-3 assume !(0 == ~T4_E~0); 12027#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11296#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11297#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11061#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11062#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11658#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11659#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12001#L1079-3 assume !(0 == ~E_1~0); 11896#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11781#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11782#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11707#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11708#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12025#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12013#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12014#L1119-3 assume !(0 == ~E_9~0); 12277#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12284#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12250#L502-36 assume !(1 == ~m_pc~0); 11435#L502-38 is_master_triggered_~__retres1~0#1 := 0; 10929#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10930#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11354#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11355#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11631#L521-36 assume 1 == ~t1_pc~0; 11632#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11642#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11812#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12204#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12086#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12087#L540-36 assume !(1 == ~t2_pc~0); 11016#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 11017#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11423#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12088#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11757#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10935#L559-36 assume 1 == ~t3_pc~0; 10936#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11386#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11565#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11566#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11905#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12141#L578-36 assume 1 == ~t4_pc~0; 11874#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11830#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11768#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11769#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11664#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11665#L597-36 assume !(1 == ~t5_pc~0); 11893#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 12242#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12186#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11847#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 11465#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11466#L616-36 assume !(1 == ~t6_pc~0); 12212#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 11005#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11006#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11544#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11717#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12042#L635-36 assume 1 == ~t7_pc~0; 12217#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12099#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12100#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12162#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11703#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11704#L654-36 assume 1 == ~t8_pc~0; 12280#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12223#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11870#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11871#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12257#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11378#L673-36 assume !(1 == ~t9_pc~0); 11379#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 11743#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11608#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11609#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10948#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10949#L692-36 assume 1 == ~t10_pc~0; 11895#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11162#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11449#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11347#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11348#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11714#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11863#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12224#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12225#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11794#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11795#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12095#L1167-3 assume !(1 == ~T6_E~0); 12208#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11702#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11600#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11601#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11615#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11432#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11433#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11685#L1207-3 assume !(1 == ~E_3~0); 11803#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12023#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11340#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11030#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11031#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12124#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12125#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12287#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12173#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11181#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11182#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 11439#L1572 assume !(0 == start_simulation_~tmp~3#1); 11470#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11634#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10962#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11018#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 11019#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10933#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10934#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 11774#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 11110#L1553-2 [2022-12-13 12:30:54,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:54,904 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2022-12-13 12:30:54,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:54,905 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268372287] [2022-12-13 12:30:54,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:54,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:54,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:54,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:54,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:54,943 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268372287] [2022-12-13 12:30:54,943 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [268372287] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:54,943 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:54,944 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:54,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [512421566] [2022-12-13 12:30:54,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:54,944 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:54,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:54,945 INFO L85 PathProgramCache]: Analyzing trace with hash 427710326, now seen corresponding path program 2 times [2022-12-13 12:30:54,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:54,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2067488003] [2022-12-13 12:30:54,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:54,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:54,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:54,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:54,992 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:54,992 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2067488003] [2022-12-13 12:30:54,992 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2067488003] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:54,992 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:54,992 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:54,992 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [323205906] [2022-12-13 12:30:54,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:54,993 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:54,993 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:54,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:30:54,994 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:30:54,994 INFO L87 Difference]: Start difference. First operand 1361 states and 2020 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:55,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:55,014 INFO L93 Difference]: Finished difference Result 1361 states and 2019 transitions. [2022-12-13 12:30:55,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2019 transitions. [2022-12-13 12:30:55,018 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:55,022 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2019 transitions. [2022-12-13 12:30:55,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-12-13 12:30:55,023 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-12-13 12:30:55,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2019 transitions. [2022-12-13 12:30:55,024 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:55,024 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2019 transitions. [2022-12-13 12:30:55,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2019 transitions. [2022-12-13 12:30:55,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-12-13 12:30:55,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4834680382072005) internal successors, (2019), 1360 states have internal predecessors, (2019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:55,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2019 transitions. [2022-12-13 12:30:55,038 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2019 transitions. [2022-12-13 12:30:55,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:30:55,039 INFO L428 stractBuchiCegarLoop]: Abstraction has 1361 states and 2019 transitions. [2022-12-13 12:30:55,039 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 12:30:55,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2019 transitions. [2022-12-13 12:30:55,043 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:55,043 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:55,043 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:55,044 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:55,044 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:55,044 INFO L748 eck$LassoCheckResult]: Stem: 14035#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14036#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 14931#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14932#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14615#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 14303#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14304#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14585#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14751#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14472#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14473#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14355#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14356#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14706#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14669#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14592#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14593#L1024 assume !(0 == ~M_E~0); 14845#L1024-2 assume !(0 == ~T1_E~0); 14031#L1029-1 assume !(0 == ~T2_E~0); 14032#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14133#L1039-1 assume !(0 == ~T4_E~0); 14955#L1044-1 assume !(0 == ~T5_E~0); 14375#L1049-1 assume !(0 == ~T6_E~0); 14376#L1054-1 assume !(0 == ~T7_E~0); 14614#L1059-1 assume !(0 == ~T8_E~0); 14081#L1064-1 assume !(0 == ~T9_E~0); 14082#L1069-1 assume !(0 == ~T10_E~0); 14813#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14874#L1079-1 assume !(0 == ~E_1~0); 14847#L1084-1 assume !(0 == ~E_2~0); 14848#L1089-1 assume !(0 == ~E_3~0); 14892#L1094-1 assume !(0 == ~E_4~0); 14463#L1099-1 assume !(0 == ~E_5~0); 14464#L1104-1 assume !(0 == ~E_6~0); 14723#L1109-1 assume !(0 == ~E_7~0); 14244#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14245#L1119-1 assume !(0 == ~E_9~0); 14313#L1124-1 assume !(0 == ~E_10~0); 13738#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13739#L502 assume 1 == ~m_pc~0; 14612#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13864#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13865#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14663#L1273 assume !(0 != activate_threads_~tmp~1#1); 14664#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14985#L521 assume !(1 == ~t1_pc~0); 14920#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13789#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13754#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13755#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 13775#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13776#L540 assume 1 == ~t2_pc~0; 14858#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14574#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14240#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14241#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 14916#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14059#L559 assume 1 == ~t3_pc~0; 14060#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14334#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13693#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13694#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 13882#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13883#L578 assume !(1 == ~t4_pc~0); 13998#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 13997#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13821#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13822#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14644#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14645#L597 assume 1 == ~t5_pc~0; 15000#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13809#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13810#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14843#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 14594#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14595#L616 assume !(1 == ~t6_pc~0); 14609#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14608#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14216#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14217#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 14452#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14453#L635 assume 1 == ~t7_pc~0; 14649#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13778#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14149#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14888#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 14587#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14588#L654 assume !(1 == ~t8_pc~0); 14404#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14405#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14774#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14775#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 14811#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14029#L673 assume 1 == ~t9_pc~0; 14030#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13729#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14297#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14298#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 14735#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14736#L692 assume !(1 == ~t10_pc~0); 14682#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14681#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14455#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14456#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 14467#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14790#L1142 assume !(1 == ~M_E~0); 13941#L1142-2 assume !(1 == ~T1_E~0); 13942#L1147-1 assume !(1 == ~T2_E~0); 14781#L1152-1 assume !(1 == ~T3_E~0); 14341#L1157-1 assume !(1 == ~T4_E~0); 14342#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14491#L1167-1 assume !(1 == ~T6_E~0); 14492#L1172-1 assume !(1 == ~T7_E~0); 14909#L1177-1 assume !(1 == ~T8_E~0); 14632#L1182-1 assume !(1 == ~T9_E~0); 14633#L1187-1 assume !(1 == ~T10_E~0); 14728#L1192-1 assume !(1 == ~E_M~0); 14194#L1197-1 assume !(1 == ~E_1~0); 14195#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14576#L1207-1 assume !(1 == ~E_3~0); 14552#L1212-1 assume !(1 == ~E_4~0); 13794#L1217-1 assume !(1 == ~E_5~0); 13795#L1222-1 assume !(1 == ~E_6~0); 14549#L1227-1 assume !(1 == ~E_7~0); 14550#L1232-1 assume !(1 == ~E_8~0); 13670#L1237-1 assume !(1 == ~E_9~0); 13671#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14613#L1247-1 assume { :end_inline_reset_delta_events } true; 13839#L1553-2 [2022-12-13 12:30:55,045 INFO L750 eck$LassoCheckResult]: Loop: 13839#L1553-2 assume !false; 13840#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13767#L999 assume !false; 14818#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13925#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13812#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14278#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14279#L854 assume !(0 != eval_~tmp~0#1); 14687#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14476#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14477#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14945#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14449#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14417#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14418#L1039-3 assume !(0 == ~T4_E~0); 14756#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14025#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14026#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13790#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13791#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14387#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14388#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14730#L1079-3 assume !(0 == ~E_1~0); 14624#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14510#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14511#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14436#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14437#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14754#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14742#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14743#L1119-3 assume !(0 == ~E_9~0); 15006#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15013#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14979#L502-36 assume !(1 == ~m_pc~0); 14164#L502-38 is_master_triggered_~__retres1~0#1 := 0; 13658#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13659#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14083#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14084#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14360#L521-36 assume 1 == ~t1_pc~0; 14361#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14371#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14541#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14933#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14815#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14816#L540-36 assume !(1 == ~t2_pc~0); 13745#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 13746#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14152#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14817#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14486#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13667#L559-36 assume 1 == ~t3_pc~0; 13668#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14120#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14294#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14295#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14634#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14870#L578-36 assume !(1 == ~t4_pc~0); 14561#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 14562#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14498#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14499#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14395#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14396#L597-36 assume !(1 == ~t5_pc~0); 14622#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 14971#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14915#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14577#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 14196#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14197#L616-36 assume 1 == ~t6_pc~0; 14982#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13734#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13735#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14273#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14446#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14771#L635-36 assume 1 == ~t7_pc~0; 14946#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14828#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14829#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14891#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14432#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14433#L654-36 assume 1 == ~t8_pc~0; 15009#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14952#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14599#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14600#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14986#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14107#L673-36 assume !(1 == ~t9_pc~0); 14108#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 14474#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14337#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14338#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13677#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13678#L692-36 assume 1 == ~t10_pc~0; 14625#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13891#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14178#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14076#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14077#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14445#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14596#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14953#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14954#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14523#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14524#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14824#L1167-3 assume !(1 == ~T6_E~0); 14937#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14431#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14329#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14330#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14344#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14161#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14162#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14414#L1207-3 assume !(1 == ~E_3~0); 14532#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14752#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14069#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13759#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13760#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14853#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14854#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15016#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14902#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13910#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13911#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 14168#L1572 assume !(0 == start_simulation_~tmp~3#1); 14199#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14363#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13691#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13747#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 13748#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13662#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13663#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14503#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 13839#L1553-2 [2022-12-13 12:30:55,045 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:55,045 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2022-12-13 12:30:55,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:55,046 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937812039] [2022-12-13 12:30:55,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:55,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:55,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:55,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:55,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:55,074 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937812039] [2022-12-13 12:30:55,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1937812039] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:55,075 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:55,075 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:55,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685603363] [2022-12-13 12:30:55,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:55,075 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:55,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:55,076 INFO L85 PathProgramCache]: Analyzing trace with hash -1792246282, now seen corresponding path program 1 times [2022-12-13 12:30:55,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:55,076 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264930173] [2022-12-13 12:30:55,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:55,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:55,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:55,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:55,113 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:55,114 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264930173] [2022-12-13 12:30:55,114 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264930173] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:55,114 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:55,114 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:55,114 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [341230421] [2022-12-13 12:30:55,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:55,114 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:55,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:55,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:30:55,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:30:55,115 INFO L87 Difference]: Start difference. First operand 1361 states and 2019 transitions. cyclomatic complexity: 659 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:55,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:55,134 INFO L93 Difference]: Finished difference Result 1361 states and 2018 transitions. [2022-12-13 12:30:55,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2018 transitions. [2022-12-13 12:30:55,139 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:55,142 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2018 transitions. [2022-12-13 12:30:55,142 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-12-13 12:30:55,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-12-13 12:30:55,143 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2018 transitions. [2022-12-13 12:30:55,144 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:55,144 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2018 transitions. [2022-12-13 12:30:55,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2018 transitions. [2022-12-13 12:30:55,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-12-13 12:30:55,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.482733284349743) internal successors, (2018), 1360 states have internal predecessors, (2018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:55,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2018 transitions. [2022-12-13 12:30:55,168 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2018 transitions. [2022-12-13 12:30:55,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:30:55,169 INFO L428 stractBuchiCegarLoop]: Abstraction has 1361 states and 2018 transitions. [2022-12-13 12:30:55,169 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 12:30:55,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2018 transitions. [2022-12-13 12:30:55,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:55,173 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:55,173 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:55,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:55,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:55,175 INFO L748 eck$LassoCheckResult]: Stem: 16764#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 16765#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 17660#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17661#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17344#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 17032#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17033#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17314#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17480#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17201#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17202#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17084#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17085#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17435#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17398#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17321#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17322#L1024 assume !(0 == ~M_E~0); 17574#L1024-2 assume !(0 == ~T1_E~0); 16760#L1029-1 assume !(0 == ~T2_E~0); 16761#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16862#L1039-1 assume !(0 == ~T4_E~0); 17684#L1044-1 assume !(0 == ~T5_E~0); 17104#L1049-1 assume !(0 == ~T6_E~0); 17105#L1054-1 assume !(0 == ~T7_E~0); 17343#L1059-1 assume !(0 == ~T8_E~0); 16810#L1064-1 assume !(0 == ~T9_E~0); 16811#L1069-1 assume !(0 == ~T10_E~0); 17542#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17603#L1079-1 assume !(0 == ~E_1~0); 17576#L1084-1 assume !(0 == ~E_2~0); 17577#L1089-1 assume !(0 == ~E_3~0); 17621#L1094-1 assume !(0 == ~E_4~0); 17192#L1099-1 assume !(0 == ~E_5~0); 17193#L1104-1 assume !(0 == ~E_6~0); 17452#L1109-1 assume !(0 == ~E_7~0); 16973#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 16974#L1119-1 assume !(0 == ~E_9~0); 17042#L1124-1 assume !(0 == ~E_10~0); 16467#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16468#L502 assume 1 == ~m_pc~0; 17341#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16593#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16594#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17392#L1273 assume !(0 != activate_threads_~tmp~1#1); 17393#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17714#L521 assume !(1 == ~t1_pc~0); 17649#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16518#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16483#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16484#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 16504#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16505#L540 assume 1 == ~t2_pc~0; 17587#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17303#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16969#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16970#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 17645#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16788#L559 assume 1 == ~t3_pc~0; 16789#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17063#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16422#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16423#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 16611#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16612#L578 assume !(1 == ~t4_pc~0); 16727#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16726#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16550#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16551#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17373#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17374#L597 assume 1 == ~t5_pc~0; 17729#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16538#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16539#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17572#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 17323#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17324#L616 assume !(1 == ~t6_pc~0); 17338#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17337#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16945#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16946#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 17181#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17182#L635 assume 1 == ~t7_pc~0; 17378#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16507#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16878#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17617#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 17316#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17317#L654 assume !(1 == ~t8_pc~0); 17133#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17134#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17503#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17504#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 17540#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16758#L673 assume 1 == ~t9_pc~0; 16759#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16458#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17026#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17027#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 17464#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17465#L692 assume !(1 == ~t10_pc~0); 17411#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17410#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17184#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17185#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 17196#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17519#L1142 assume !(1 == ~M_E~0); 16670#L1142-2 assume !(1 == ~T1_E~0); 16671#L1147-1 assume !(1 == ~T2_E~0); 17510#L1152-1 assume !(1 == ~T3_E~0); 17070#L1157-1 assume !(1 == ~T4_E~0); 17071#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17220#L1167-1 assume !(1 == ~T6_E~0); 17221#L1172-1 assume !(1 == ~T7_E~0); 17638#L1177-1 assume !(1 == ~T8_E~0); 17361#L1182-1 assume !(1 == ~T9_E~0); 17362#L1187-1 assume !(1 == ~T10_E~0); 17457#L1192-1 assume !(1 == ~E_M~0); 16923#L1197-1 assume !(1 == ~E_1~0); 16924#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17305#L1207-1 assume !(1 == ~E_3~0); 17281#L1212-1 assume !(1 == ~E_4~0); 16523#L1217-1 assume !(1 == ~E_5~0); 16524#L1222-1 assume !(1 == ~E_6~0); 17278#L1227-1 assume !(1 == ~E_7~0); 17279#L1232-1 assume !(1 == ~E_8~0); 16399#L1237-1 assume !(1 == ~E_9~0); 16400#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 17342#L1247-1 assume { :end_inline_reset_delta_events } true; 16568#L1553-2 [2022-12-13 12:30:55,175 INFO L750 eck$LassoCheckResult]: Loop: 16568#L1553-2 assume !false; 16569#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16496#L999 assume !false; 17547#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16654#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16541#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17007#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17008#L854 assume !(0 != eval_~tmp~0#1); 17416#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17205#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17206#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17674#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17178#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17146#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17147#L1039-3 assume !(0 == ~T4_E~0); 17485#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16754#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16755#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16519#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16520#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17116#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17117#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17459#L1079-3 assume !(0 == ~E_1~0); 17353#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17239#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17240#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17165#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17166#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17483#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17471#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17472#L1119-3 assume !(0 == ~E_9~0); 17735#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17742#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17708#L502-36 assume !(1 == ~m_pc~0); 16893#L502-38 is_master_triggered_~__retres1~0#1 := 0; 16387#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16388#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16812#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16813#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17089#L521-36 assume 1 == ~t1_pc~0; 17090#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17100#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17270#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17662#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17544#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17545#L540-36 assume !(1 == ~t2_pc~0); 16474#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 16475#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16881#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17546#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17215#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16396#L559-36 assume 1 == ~t3_pc~0; 16397#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16849#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17023#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17024#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17363#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17599#L578-36 assume 1 == ~t4_pc~0; 17332#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17291#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17227#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17228#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17124#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17125#L597-36 assume !(1 == ~t5_pc~0); 17351#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 17700#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17644#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17306#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 16925#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16926#L616-36 assume !(1 == ~t6_pc~0); 17670#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 16463#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16464#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17002#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17175#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17500#L635-36 assume 1 == ~t7_pc~0; 17675#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17557#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17558#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17620#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17161#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17162#L654-36 assume !(1 == ~t8_pc~0); 17680#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 17681#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17328#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17329#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17715#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16836#L673-36 assume !(1 == ~t9_pc~0); 16837#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 17203#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17066#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17067#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16406#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16407#L692-36 assume 1 == ~t10_pc~0; 17354#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16620#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16907#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16805#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16806#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17174#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17325#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17682#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17683#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17252#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17253#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17553#L1167-3 assume !(1 == ~T6_E~0); 17666#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17160#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17058#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17059#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17073#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16890#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16891#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17143#L1207-3 assume !(1 == ~E_3~0); 17261#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17481#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16798#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16488#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16489#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17582#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17583#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17745#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17631#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16639#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16640#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 16897#L1572 assume !(0 == start_simulation_~tmp~3#1); 16928#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17092#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16420#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16476#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 16477#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16391#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16392#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17232#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 16568#L1553-2 [2022-12-13 12:30:55,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:55,176 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2022-12-13 12:30:55,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:55,176 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [714534073] [2022-12-13 12:30:55,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:55,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:55,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:55,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:55,203 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:55,203 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [714534073] [2022-12-13 12:30:55,203 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [714534073] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:55,203 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:55,204 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:55,204 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [611697648] [2022-12-13 12:30:55,204 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:55,204 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:55,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:55,204 INFO L85 PathProgramCache]: Analyzing trace with hash 153931831, now seen corresponding path program 1 times [2022-12-13 12:30:55,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:55,205 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765985109] [2022-12-13 12:30:55,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:55,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:55,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:55,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:55,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:55,241 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765985109] [2022-12-13 12:30:55,241 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [765985109] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:55,241 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:55,241 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:55,241 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22537150] [2022-12-13 12:30:55,242 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:55,242 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:55,242 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:55,242 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:30:55,242 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:30:55,243 INFO L87 Difference]: Start difference. First operand 1361 states and 2018 transitions. cyclomatic complexity: 658 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:55,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:55,268 INFO L93 Difference]: Finished difference Result 1361 states and 2017 transitions. [2022-12-13 12:30:55,268 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2017 transitions. [2022-12-13 12:30:55,274 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:55,280 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2017 transitions. [2022-12-13 12:30:55,280 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-12-13 12:30:55,281 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-12-13 12:30:55,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2017 transitions. [2022-12-13 12:30:55,283 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:55,283 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2017 transitions. [2022-12-13 12:30:55,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2017 transitions. [2022-12-13 12:30:55,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-12-13 12:30:55,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4819985304922851) internal successors, (2017), 1360 states have internal predecessors, (2017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:55,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2017 transitions. [2022-12-13 12:30:55,301 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2017 transitions. [2022-12-13 12:30:55,301 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:30:55,301 INFO L428 stractBuchiCegarLoop]: Abstraction has 1361 states and 2017 transitions. [2022-12-13 12:30:55,301 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 12:30:55,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2017 transitions. [2022-12-13 12:30:55,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:55,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:55,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:55,306 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:55,306 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:55,306 INFO L748 eck$LassoCheckResult]: Stem: 19493#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 19494#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 20389#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20390#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20073#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 19762#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19763#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20043#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20209#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19931#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19932#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19813#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19814#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20164#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20127#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20051#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20052#L1024 assume !(0 == ~M_E~0); 20303#L1024-2 assume !(0 == ~T1_E~0); 19489#L1029-1 assume !(0 == ~T2_E~0); 19490#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19591#L1039-1 assume !(0 == ~T4_E~0); 20413#L1044-1 assume !(0 == ~T5_E~0); 19835#L1049-1 assume !(0 == ~T6_E~0); 19836#L1054-1 assume !(0 == ~T7_E~0); 20072#L1059-1 assume !(0 == ~T8_E~0); 19539#L1064-1 assume !(0 == ~T9_E~0); 19540#L1069-1 assume !(0 == ~T10_E~0); 20271#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 20332#L1079-1 assume !(0 == ~E_1~0); 20305#L1084-1 assume !(0 == ~E_2~0); 20306#L1089-1 assume !(0 == ~E_3~0); 20350#L1094-1 assume !(0 == ~E_4~0); 19921#L1099-1 assume !(0 == ~E_5~0); 19922#L1104-1 assume !(0 == ~E_6~0); 20181#L1109-1 assume !(0 == ~E_7~0); 19702#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19703#L1119-1 assume !(0 == ~E_9~0); 19773#L1124-1 assume !(0 == ~E_10~0); 19196#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19197#L502 assume 1 == ~m_pc~0; 20070#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19322#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19323#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20123#L1273 assume !(0 != activate_threads_~tmp~1#1); 20124#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20443#L521 assume !(1 == ~t1_pc~0); 20378#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19247#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19212#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19213#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 19233#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19234#L540 assume 1 == ~t2_pc~0; 20316#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20032#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19698#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19699#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 20374#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19517#L559 assume 1 == ~t3_pc~0; 19518#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19793#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19151#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19152#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 19340#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19341#L578 assume !(1 == ~t4_pc~0); 19461#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19460#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19280#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19281#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20104#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20105#L597 assume 1 == ~t5_pc~0; 20459#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19267#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19268#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20301#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 20053#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20054#L616 assume !(1 == ~t6_pc~0); 20069#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 20068#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19674#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19675#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 19911#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19912#L635 assume 1 == ~t7_pc~0; 20108#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19236#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19609#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20346#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 20045#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20046#L654 assume !(1 == ~t8_pc~0); 19862#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19863#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20235#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20236#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 20269#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19487#L673 assume 1 == ~t9_pc~0; 19488#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19187#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19757#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19758#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 20193#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20194#L692 assume !(1 == ~t10_pc~0); 20140#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20139#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19913#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19914#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 19925#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20248#L1142 assume !(1 == ~M_E~0); 19399#L1142-2 assume !(1 == ~T1_E~0); 19400#L1147-1 assume !(1 == ~T2_E~0); 20239#L1152-1 assume !(1 == ~T3_E~0); 19799#L1157-1 assume !(1 == ~T4_E~0); 19800#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19949#L1167-1 assume !(1 == ~T6_E~0); 19950#L1172-1 assume !(1 == ~T7_E~0); 20368#L1177-1 assume !(1 == ~T8_E~0); 20090#L1182-1 assume !(1 == ~T9_E~0); 20091#L1187-1 assume !(1 == ~T10_E~0); 20186#L1192-1 assume !(1 == ~E_M~0); 19654#L1197-1 assume !(1 == ~E_1~0); 19655#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20035#L1207-1 assume !(1 == ~E_3~0); 20010#L1212-1 assume !(1 == ~E_4~0); 19252#L1217-1 assume !(1 == ~E_5~0); 19253#L1222-1 assume !(1 == ~E_6~0); 20007#L1227-1 assume !(1 == ~E_7~0); 20008#L1232-1 assume !(1 == ~E_8~0); 19128#L1237-1 assume !(1 == ~E_9~0); 19129#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 20071#L1247-1 assume { :end_inline_reset_delta_events } true; 19297#L1553-2 [2022-12-13 12:30:55,306 INFO L750 eck$LassoCheckResult]: Loop: 19297#L1553-2 assume !false; 19298#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19225#L999 assume !false; 20278#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19383#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19270#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19736#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19737#L854 assume !(0 != eval_~tmp~0#1); 20145#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19934#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19935#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20403#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19907#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19875#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19876#L1039-3 assume !(0 == ~T4_E~0); 20214#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19483#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19484#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19248#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19249#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19845#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19846#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20188#L1079-3 assume !(0 == ~E_1~0); 20083#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19968#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19969#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19894#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19895#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20212#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20200#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20201#L1119-3 assume !(0 == ~E_9~0); 20464#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20471#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20437#L502-36 assume !(1 == ~m_pc~0); 19622#L502-38 is_master_triggered_~__retres1~0#1 := 0; 19116#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19117#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19541#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19542#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19818#L521-36 assume 1 == ~t1_pc~0; 19819#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19829#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19999#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20391#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20273#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20274#L540-36 assume !(1 == ~t2_pc~0); 19203#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 19204#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19610#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20275#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19944#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19122#L559-36 assume 1 == ~t3_pc~0; 19123#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19573#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19752#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19753#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20092#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20328#L578-36 assume !(1 == ~t4_pc~0); 20016#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 20017#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19955#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19956#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19851#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19852#L597-36 assume !(1 == ~t5_pc~0); 20077#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 20429#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20373#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20034#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 19652#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19653#L616-36 assume 1 == ~t6_pc~0; 20440#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19192#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19193#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19731#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19904#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20229#L635-36 assume 1 == ~t7_pc~0; 20404#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20286#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20287#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20349#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19890#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19891#L654-36 assume 1 == ~t8_pc~0; 20467#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20410#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20057#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20058#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20444#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19565#L673-36 assume !(1 == ~t9_pc~0); 19566#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 19930#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19795#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19796#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19135#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19136#L692-36 assume 1 == ~t10_pc~0; 20082#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19349#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19636#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19534#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19535#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19901#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20050#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20411#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20412#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19981#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19982#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20282#L1167-3 assume !(1 == ~T6_E~0); 20395#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19889#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19787#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19788#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19802#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19619#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19620#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19872#L1207-3 assume !(1 == ~E_3~0); 19990#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20210#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19527#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19217#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19218#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20311#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20312#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20474#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20360#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19368#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19369#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 19626#L1572 assume !(0 == start_simulation_~tmp~3#1); 19657#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19821#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19149#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19205#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 19206#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19120#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19121#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 19961#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 19297#L1553-2 [2022-12-13 12:30:55,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:55,306 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2022-12-13 12:30:55,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:55,307 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482785486] [2022-12-13 12:30:55,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:55,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:55,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:55,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:55,334 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:55,334 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [482785486] [2022-12-13 12:30:55,334 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [482785486] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:55,335 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:55,335 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:55,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [746918272] [2022-12-13 12:30:55,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:55,335 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:55,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:55,336 INFO L85 PathProgramCache]: Analyzing trace with hash -1792246282, now seen corresponding path program 2 times [2022-12-13 12:30:55,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:55,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124761559] [2022-12-13 12:30:55,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:55,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:55,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:55,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:55,376 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:55,376 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1124761559] [2022-12-13 12:30:55,377 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1124761559] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:55,377 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:55,377 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:55,377 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1578504089] [2022-12-13 12:30:55,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:55,377 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:55,378 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:55,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:30:55,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:30:55,378 INFO L87 Difference]: Start difference. First operand 1361 states and 2017 transitions. cyclomatic complexity: 657 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:55,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:55,397 INFO L93 Difference]: Finished difference Result 1361 states and 2016 transitions. [2022-12-13 12:30:55,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2016 transitions. [2022-12-13 12:30:55,400 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:55,404 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2016 transitions. [2022-12-13 12:30:55,404 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-12-13 12:30:55,404 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-12-13 12:30:55,404 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2016 transitions. [2022-12-13 12:30:55,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:55,406 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2016 transitions. [2022-12-13 12:30:55,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2016 transitions. [2022-12-13 12:30:55,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-12-13 12:30:55,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4812637766348273) internal successors, (2016), 1360 states have internal predecessors, (2016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:55,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2016 transitions. [2022-12-13 12:30:55,429 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2016 transitions. [2022-12-13 12:30:55,430 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:30:55,430 INFO L428 stractBuchiCegarLoop]: Abstraction has 1361 states and 2016 transitions. [2022-12-13 12:30:55,431 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 12:30:55,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2016 transitions. [2022-12-13 12:30:55,434 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:55,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:55,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:55,435 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:55,435 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:55,435 INFO L748 eck$LassoCheckResult]: Stem: 22222#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22223#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23118#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23119#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22802#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 22490#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22491#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22772#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22938#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22659#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22660#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22542#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22543#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22893#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22856#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22779#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22780#L1024 assume !(0 == ~M_E~0); 23032#L1024-2 assume !(0 == ~T1_E~0); 22218#L1029-1 assume !(0 == ~T2_E~0); 22219#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22320#L1039-1 assume !(0 == ~T4_E~0); 23142#L1044-1 assume !(0 == ~T5_E~0); 22562#L1049-1 assume !(0 == ~T6_E~0); 22563#L1054-1 assume !(0 == ~T7_E~0); 22801#L1059-1 assume !(0 == ~T8_E~0); 22268#L1064-1 assume !(0 == ~T9_E~0); 22269#L1069-1 assume !(0 == ~T10_E~0); 23000#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 23061#L1079-1 assume !(0 == ~E_1~0); 23034#L1084-1 assume !(0 == ~E_2~0); 23035#L1089-1 assume !(0 == ~E_3~0); 23079#L1094-1 assume !(0 == ~E_4~0); 22650#L1099-1 assume !(0 == ~E_5~0); 22651#L1104-1 assume !(0 == ~E_6~0); 22910#L1109-1 assume !(0 == ~E_7~0); 22431#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22432#L1119-1 assume !(0 == ~E_9~0); 22500#L1124-1 assume !(0 == ~E_10~0); 21925#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21926#L502 assume 1 == ~m_pc~0; 22799#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22051#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22052#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22850#L1273 assume !(0 != activate_threads_~tmp~1#1); 22851#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23172#L521 assume !(1 == ~t1_pc~0); 23107#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21976#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21941#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21942#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 21962#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21963#L540 assume 1 == ~t2_pc~0; 23045#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22761#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22427#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22428#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 23103#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22246#L559 assume 1 == ~t3_pc~0; 22247#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22521#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21880#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21881#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 22069#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22070#L578 assume !(1 == ~t4_pc~0); 22185#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22184#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22008#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22009#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22831#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22832#L597 assume 1 == ~t5_pc~0; 23187#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21996#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21997#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23030#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 22781#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22782#L616 assume !(1 == ~t6_pc~0); 22796#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22795#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22403#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22404#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 22639#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22640#L635 assume 1 == ~t7_pc~0; 22836#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21965#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22336#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23075#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 22774#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22775#L654 assume !(1 == ~t8_pc~0); 22591#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22592#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22961#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22962#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 22998#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22216#L673 assume 1 == ~t9_pc~0; 22217#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21916#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22484#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22485#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 22922#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22923#L692 assume !(1 == ~t10_pc~0); 22869#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22868#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22642#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22643#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 22654#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22977#L1142 assume !(1 == ~M_E~0); 22128#L1142-2 assume !(1 == ~T1_E~0); 22129#L1147-1 assume !(1 == ~T2_E~0); 22968#L1152-1 assume !(1 == ~T3_E~0); 22528#L1157-1 assume !(1 == ~T4_E~0); 22529#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22678#L1167-1 assume !(1 == ~T6_E~0); 22679#L1172-1 assume !(1 == ~T7_E~0); 23096#L1177-1 assume !(1 == ~T8_E~0); 22819#L1182-1 assume !(1 == ~T9_E~0); 22820#L1187-1 assume !(1 == ~T10_E~0); 22915#L1192-1 assume !(1 == ~E_M~0); 22381#L1197-1 assume !(1 == ~E_1~0); 22382#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22763#L1207-1 assume !(1 == ~E_3~0); 22739#L1212-1 assume !(1 == ~E_4~0); 21981#L1217-1 assume !(1 == ~E_5~0); 21982#L1222-1 assume !(1 == ~E_6~0); 22736#L1227-1 assume !(1 == ~E_7~0); 22737#L1232-1 assume !(1 == ~E_8~0); 21857#L1237-1 assume !(1 == ~E_9~0); 21858#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22800#L1247-1 assume { :end_inline_reset_delta_events } true; 22026#L1553-2 [2022-12-13 12:30:55,435 INFO L750 eck$LassoCheckResult]: Loop: 22026#L1553-2 assume !false; 22027#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21954#L999 assume !false; 23005#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22112#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21999#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22465#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22466#L854 assume !(0 != eval_~tmp~0#1); 22874#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22663#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22664#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23132#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22636#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22604#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22605#L1039-3 assume !(0 == ~T4_E~0); 22943#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22212#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22213#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21977#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21978#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22574#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22575#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22917#L1079-3 assume !(0 == ~E_1~0); 22811#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22697#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22698#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22623#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22624#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22941#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22929#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22930#L1119-3 assume !(0 == ~E_9~0); 23193#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23200#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23166#L502-36 assume 1 == ~m_pc~0; 22944#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21845#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21846#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22270#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22271#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22547#L521-36 assume 1 == ~t1_pc~0; 22548#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22558#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22728#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23120#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23002#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23003#L540-36 assume 1 == ~t2_pc~0; 23168#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21933#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22339#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23004#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22673#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21854#L559-36 assume !(1 == ~t3_pc~0); 21856#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 22307#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22481#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22482#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22821#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23057#L578-36 assume 1 == ~t4_pc~0; 22790#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22749#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22685#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22686#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22582#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22583#L597-36 assume !(1 == ~t5_pc~0); 22809#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 23158#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23102#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22764#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 22383#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22384#L616-36 assume 1 == ~t6_pc~0; 23169#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21921#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21922#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22460#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22633#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22958#L635-36 assume 1 == ~t7_pc~0; 23133#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23015#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23016#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23078#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22619#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22620#L654-36 assume !(1 == ~t8_pc~0); 23138#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 23139#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22786#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22787#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23173#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22294#L673-36 assume !(1 == ~t9_pc~0); 22295#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 22661#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22524#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22525#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21864#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21865#L692-36 assume 1 == ~t10_pc~0; 22812#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22078#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22365#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22263#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22264#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22632#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22783#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23140#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23141#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22710#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22711#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23011#L1167-3 assume !(1 == ~T6_E~0); 23124#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22618#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22516#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22517#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22531#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22348#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22349#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22601#L1207-3 assume !(1 == ~E_3~0); 22719#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22939#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22256#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21946#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21947#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23040#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23041#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23203#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23089#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22097#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22098#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 22355#L1572 assume !(0 == start_simulation_~tmp~3#1); 22386#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22550#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21878#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21934#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 21935#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21849#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21850#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 22690#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 22026#L1553-2 [2022-12-13 12:30:55,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:55,436 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2022-12-13 12:30:55,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:55,436 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368809320] [2022-12-13 12:30:55,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:55,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:55,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:55,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:55,463 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:55,463 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1368809320] [2022-12-13 12:30:55,464 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1368809320] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:55,464 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:55,464 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:55,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1136696147] [2022-12-13 12:30:55,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:55,464 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:55,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:55,465 INFO L85 PathProgramCache]: Analyzing trace with hash 792814325, now seen corresponding path program 1 times [2022-12-13 12:30:55,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:55,465 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669587588] [2022-12-13 12:30:55,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:55,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:55,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:55,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:55,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:55,509 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669587588] [2022-12-13 12:30:55,509 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669587588] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:55,509 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:55,509 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:55,510 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385155495] [2022-12-13 12:30:55,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:55,510 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:55,510 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:55,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:30:55,511 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:30:55,511 INFO L87 Difference]: Start difference. First operand 1361 states and 2016 transitions. cyclomatic complexity: 656 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:55,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:55,529 INFO L93 Difference]: Finished difference Result 1361 states and 2015 transitions. [2022-12-13 12:30:55,529 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2015 transitions. [2022-12-13 12:30:55,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:55,536 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2015 transitions. [2022-12-13 12:30:55,536 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-12-13 12:30:55,537 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-12-13 12:30:55,537 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2015 transitions. [2022-12-13 12:30:55,538 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:55,538 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2015 transitions. [2022-12-13 12:30:55,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2015 transitions. [2022-12-13 12:30:55,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-12-13 12:30:55,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4805290227773695) internal successors, (2015), 1360 states have internal predecessors, (2015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:55,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2015 transitions. [2022-12-13 12:30:55,552 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2015 transitions. [2022-12-13 12:30:55,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:30:55,553 INFO L428 stractBuchiCegarLoop]: Abstraction has 1361 states and 2015 transitions. [2022-12-13 12:30:55,553 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 12:30:55,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2015 transitions. [2022-12-13 12:30:55,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-12-13 12:30:55,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:55,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:55,557 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:55,557 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:55,557 INFO L748 eck$LassoCheckResult]: Stem: 24951#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 24952#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 25847#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25848#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25531#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 25219#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25220#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25501#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25667#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25388#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25389#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25271#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25272#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25622#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25585#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 25508#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25509#L1024 assume !(0 == ~M_E~0); 25761#L1024-2 assume !(0 == ~T1_E~0); 24947#L1029-1 assume !(0 == ~T2_E~0); 24948#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25049#L1039-1 assume !(0 == ~T4_E~0); 25871#L1044-1 assume !(0 == ~T5_E~0); 25291#L1049-1 assume !(0 == ~T6_E~0); 25292#L1054-1 assume !(0 == ~T7_E~0); 25530#L1059-1 assume !(0 == ~T8_E~0); 24997#L1064-1 assume !(0 == ~T9_E~0); 24998#L1069-1 assume !(0 == ~T10_E~0); 25729#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 25790#L1079-1 assume !(0 == ~E_1~0); 25763#L1084-1 assume !(0 == ~E_2~0); 25764#L1089-1 assume !(0 == ~E_3~0); 25808#L1094-1 assume !(0 == ~E_4~0); 25379#L1099-1 assume !(0 == ~E_5~0); 25380#L1104-1 assume !(0 == ~E_6~0); 25639#L1109-1 assume !(0 == ~E_7~0); 25160#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25161#L1119-1 assume !(0 == ~E_9~0); 25229#L1124-1 assume !(0 == ~E_10~0); 24654#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24655#L502 assume 1 == ~m_pc~0; 25528#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24780#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24781#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25579#L1273 assume !(0 != activate_threads_~tmp~1#1); 25580#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25901#L521 assume !(1 == ~t1_pc~0); 25836#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24705#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24670#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24671#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 24691#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24692#L540 assume 1 == ~t2_pc~0; 25774#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25490#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25156#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25157#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 25832#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24975#L559 assume 1 == ~t3_pc~0; 24976#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25250#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24609#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24610#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 24798#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24799#L578 assume !(1 == ~t4_pc~0); 24914#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24913#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24737#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24738#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25560#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25561#L597 assume 1 == ~t5_pc~0; 25916#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24725#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24726#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25759#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 25510#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25511#L616 assume !(1 == ~t6_pc~0); 25525#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25524#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25132#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25133#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 25368#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25369#L635 assume 1 == ~t7_pc~0; 25565#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24694#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25065#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25804#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 25503#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25504#L654 assume !(1 == ~t8_pc~0); 25320#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25321#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25690#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25691#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 25727#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24945#L673 assume 1 == ~t9_pc~0; 24946#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24645#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25213#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25214#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 25651#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25652#L692 assume !(1 == ~t10_pc~0); 25598#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25597#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25371#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25372#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 25383#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25706#L1142 assume !(1 == ~M_E~0); 24857#L1142-2 assume !(1 == ~T1_E~0); 24858#L1147-1 assume !(1 == ~T2_E~0); 25697#L1152-1 assume !(1 == ~T3_E~0); 25257#L1157-1 assume !(1 == ~T4_E~0); 25258#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25407#L1167-1 assume !(1 == ~T6_E~0); 25408#L1172-1 assume !(1 == ~T7_E~0); 25825#L1177-1 assume !(1 == ~T8_E~0); 25548#L1182-1 assume !(1 == ~T9_E~0); 25549#L1187-1 assume !(1 == ~T10_E~0); 25644#L1192-1 assume !(1 == ~E_M~0); 25110#L1197-1 assume !(1 == ~E_1~0); 25111#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25492#L1207-1 assume !(1 == ~E_3~0); 25468#L1212-1 assume !(1 == ~E_4~0); 24710#L1217-1 assume !(1 == ~E_5~0); 24711#L1222-1 assume !(1 == ~E_6~0); 25465#L1227-1 assume !(1 == ~E_7~0); 25466#L1232-1 assume !(1 == ~E_8~0); 24586#L1237-1 assume !(1 == ~E_9~0); 24587#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 25529#L1247-1 assume { :end_inline_reset_delta_events } true; 24755#L1553-2 [2022-12-13 12:30:55,558 INFO L750 eck$LassoCheckResult]: Loop: 24755#L1553-2 assume !false; 24756#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24683#L999 assume !false; 25734#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24841#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24728#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25194#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25195#L854 assume !(0 != eval_~tmp~0#1); 25603#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25392#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25393#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25861#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25365#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25333#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25334#L1039-3 assume !(0 == ~T4_E~0); 25672#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24941#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24942#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24706#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24707#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25303#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25304#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25646#L1079-3 assume !(0 == ~E_1~0); 25540#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25426#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25427#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25352#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25353#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25670#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25658#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25659#L1119-3 assume !(0 == ~E_9~0); 25922#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25929#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25895#L502-36 assume !(1 == ~m_pc~0); 25080#L502-38 is_master_triggered_~__retres1~0#1 := 0; 24574#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24575#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24999#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25000#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25276#L521-36 assume 1 == ~t1_pc~0; 25277#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25287#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25457#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25849#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25731#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25732#L540-36 assume !(1 == ~t2_pc~0); 24661#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 24662#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25068#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25733#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25402#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24583#L559-36 assume 1 == ~t3_pc~0; 24584#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25036#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25210#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25211#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25550#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25786#L578-36 assume !(1 == ~t4_pc~0); 25477#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 25478#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25414#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25415#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25311#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25312#L597-36 assume !(1 == ~t5_pc~0); 25538#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 25887#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25831#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25493#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 25112#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25113#L616-36 assume !(1 == ~t6_pc~0); 25857#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 24650#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24651#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25189#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25362#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25687#L635-36 assume 1 == ~t7_pc~0; 25862#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25744#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25745#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25807#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25348#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25349#L654-36 assume 1 == ~t8_pc~0; 25925#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25868#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25515#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25516#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25902#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25023#L673-36 assume !(1 == ~t9_pc~0); 25024#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 25390#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25253#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25254#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24593#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24594#L692-36 assume 1 == ~t10_pc~0; 25541#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24807#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25094#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24992#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24993#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25361#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25512#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25869#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25870#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25439#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25440#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25740#L1167-3 assume !(1 == ~T6_E~0); 25853#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25347#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25245#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25246#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25260#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25077#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25078#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25330#L1207-3 assume !(1 == ~E_3~0); 25448#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25668#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24985#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24675#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24676#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25769#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25770#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25932#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25818#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24826#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24827#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 25084#L1572 assume !(0 == start_simulation_~tmp~3#1); 25115#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25279#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24607#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24663#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 24664#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24578#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24579#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25419#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 24755#L1553-2 [2022-12-13 12:30:55,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:55,558 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2022-12-13 12:30:55,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:55,558 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1868135419] [2022-12-13 12:30:55,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:55,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:55,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:55,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:55,612 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:55,612 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1868135419] [2022-12-13 12:30:55,612 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1868135419] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:55,613 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:55,613 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:55,613 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [370573340] [2022-12-13 12:30:55,613 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:55,613 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:55,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:55,614 INFO L85 PathProgramCache]: Analyzing trace with hash -1414603465, now seen corresponding path program 1 times [2022-12-13 12:30:55,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:55,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733404642] [2022-12-13 12:30:55,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:55,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:55,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:55,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:55,656 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:55,656 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [733404642] [2022-12-13 12:30:55,656 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [733404642] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:55,656 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:55,656 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:55,657 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543991391] [2022-12-13 12:30:55,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:55,657 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:55,657 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:55,658 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:30:55,658 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:30:55,658 INFO L87 Difference]: Start difference. First operand 1361 states and 2015 transitions. cyclomatic complexity: 655 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:55,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:55,775 INFO L93 Difference]: Finished difference Result 2504 states and 3694 transitions. [2022-12-13 12:30:55,776 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2504 states and 3694 transitions. [2022-12-13 12:30:55,790 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2343 [2022-12-13 12:30:55,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2504 states to 2504 states and 3694 transitions. [2022-12-13 12:30:55,810 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2504 [2022-12-13 12:30:55,813 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2504 [2022-12-13 12:30:55,813 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2504 states and 3694 transitions. [2022-12-13 12:30:55,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:55,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2504 states and 3694 transitions. [2022-12-13 12:30:55,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2504 states and 3694 transitions. [2022-12-13 12:30:55,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2504 to 2504. [2022-12-13 12:30:55,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2504 states, 2504 states have (on average 1.4752396166134185) internal successors, (3694), 2503 states have internal predecessors, (3694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:55,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2504 states to 2504 states and 3694 transitions. [2022-12-13 12:30:55,857 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2504 states and 3694 transitions. [2022-12-13 12:30:55,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:30:55,858 INFO L428 stractBuchiCegarLoop]: Abstraction has 2504 states and 3694 transitions. [2022-12-13 12:30:55,858 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 12:30:55,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2504 states and 3694 transitions. [2022-12-13 12:30:55,865 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2343 [2022-12-13 12:30:55,865 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:55,865 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:55,866 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:55,866 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:55,866 INFO L748 eck$LassoCheckResult]: Stem: 28827#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 28828#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 29754#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29755#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29422#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 29100#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29101#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29390#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29561#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29274#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29275#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29153#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29154#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29514#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29476#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 29398#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29399#L1024 assume !(0 == ~M_E~0); 29661#L1024-2 assume !(0 == ~T1_E~0); 28823#L1029-1 assume !(0 == ~T2_E~0); 28824#L1034-1 assume !(0 == ~T3_E~0); 28925#L1039-1 assume !(0 == ~T4_E~0); 29780#L1044-1 assume !(0 == ~T5_E~0); 29174#L1049-1 assume !(0 == ~T6_E~0); 29175#L1054-1 assume !(0 == ~T7_E~0); 29421#L1059-1 assume !(0 == ~T8_E~0); 28873#L1064-1 assume !(0 == ~T9_E~0); 28874#L1069-1 assume !(0 == ~T10_E~0); 29627#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29692#L1079-1 assume !(0 == ~E_1~0); 29663#L1084-1 assume !(0 == ~E_2~0); 29664#L1089-1 assume !(0 == ~E_3~0); 29711#L1094-1 assume !(0 == ~E_4~0); 29265#L1099-1 assume !(0 == ~E_5~0); 29266#L1104-1 assume !(0 == ~E_6~0); 29531#L1109-1 assume !(0 == ~E_7~0); 29040#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29041#L1119-1 assume !(0 == ~E_9~0); 29111#L1124-1 assume !(0 == ~E_10~0); 28529#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28530#L502 assume 1 == ~m_pc~0; 29419#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28656#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28657#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29470#L1273 assume !(0 != activate_threads_~tmp~1#1); 29471#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29823#L521 assume !(1 == ~t1_pc~0); 29742#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28581#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28545#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28546#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 28567#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28568#L540 assume 1 == ~t2_pc~0; 29674#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29379#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29036#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29037#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 29738#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28851#L559 assume 1 == ~t3_pc~0; 28852#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29132#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28484#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28485#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 28674#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28675#L578 assume !(1 == ~t4_pc~0); 28790#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28789#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28613#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28614#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29451#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29452#L597 assume 1 == ~t5_pc~0; 29847#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28601#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28602#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29658#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 29400#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29401#L616 assume !(1 == ~t6_pc~0); 29416#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29415#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29012#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29013#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 29254#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29255#L635 assume 1 == ~t7_pc~0; 29456#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28570#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28942#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29707#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 29393#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29394#L654 assume !(1 == ~t8_pc~0); 29203#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29204#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29588#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29589#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 29625#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28821#L673 assume 1 == ~t9_pc~0; 28822#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28520#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29094#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29095#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 29543#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29544#L692 assume !(1 == ~t10_pc~0); 29489#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29488#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29257#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29258#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 29269#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29604#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 28733#L1142-2 assume !(1 == ~T1_E~0); 28734#L1147-1 assume !(1 == ~T2_E~0); 29595#L1152-1 assume !(1 == ~T3_E~0); 29139#L1157-1 assume !(1 == ~T4_E~0); 29140#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29293#L1167-1 assume !(1 == ~T6_E~0); 29294#L1172-1 assume !(1 == ~T7_E~0); 29729#L1177-1 assume !(1 == ~T8_E~0); 29439#L1182-1 assume !(1 == ~T9_E~0); 29440#L1187-1 assume !(1 == ~T10_E~0); 29536#L1192-1 assume !(1 == ~E_M~0); 28988#L1197-1 assume !(1 == ~E_1~0); 28989#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 29381#L1207-1 assume !(1 == ~E_3~0); 29357#L1212-1 assume !(1 == ~E_4~0); 28586#L1217-1 assume !(1 == ~E_5~0); 28587#L1222-1 assume !(1 == ~E_6~0); 29872#L1227-1 assume !(1 == ~E_7~0); 29930#L1232-1 assume !(1 == ~E_8~0); 29928#L1237-1 assume !(1 == ~E_9~0); 29926#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29907#L1247-1 assume { :end_inline_reset_delta_events } true; 29902#L1553-2 [2022-12-13 12:30:55,867 INFO L750 eck$LassoCheckResult]: Loop: 29902#L1553-2 assume !false; 29896#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29892#L999 assume !false; 29891#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29890#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 29879#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29878#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 29877#L854 assume !(0 != eval_~tmp~0#1); 29876#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29875#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29873#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29874#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30952#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30951#L1034-3 assume !(0 == ~T3_E~0); 30950#L1039-3 assume !(0 == ~T4_E~0); 30949#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30948#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30947#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30946#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30945#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30944#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30943#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30942#L1079-3 assume !(0 == ~E_1~0); 30941#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30940#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30939#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30938#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30937#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30936#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30935#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30934#L1119-3 assume !(0 == ~E_9~0); 30933#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30932#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30931#L502-36 assume !(1 == ~m_pc~0); 30929#L502-38 is_master_triggered_~__retres1~0#1 := 0; 30928#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30927#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30926#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30925#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30924#L521-36 assume 1 == ~t1_pc~0; 30922#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30921#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30920#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30919#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30918#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30917#L540-36 assume !(1 == ~t2_pc~0); 30915#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 30914#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30913#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30912#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30911#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30910#L559-36 assume 1 == ~t3_pc~0; 30908#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30907#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30906#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30905#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30904#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30903#L578-36 assume !(1 == ~t4_pc~0); 30901#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 30900#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30899#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30898#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30897#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30896#L597-36 assume 1 == ~t5_pc~0; 30894#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30893#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30892#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30891#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 30890#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30889#L616-36 assume 1 == ~t6_pc~0; 30887#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30886#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30885#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30884#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30883#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30882#L635-36 assume 1 == ~t7_pc~0; 30880#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30879#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30878#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30877#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30876#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30875#L654-36 assume 1 == ~t8_pc~0; 30873#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30872#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30871#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30870#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30869#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30868#L673-36 assume !(1 == ~t9_pc~0); 30866#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 30865#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30864#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30863#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30862#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30861#L692-36 assume 1 == ~t10_pc~0; 30859#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30858#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30857#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30856#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30855#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30854#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29402#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30853#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30852#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29806#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30851#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30850#L1167-3 assume !(1 == ~T6_E~0); 30849#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30848#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30847#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30846#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30845#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30844#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30843#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30842#L1207-3 assume !(1 == ~E_3~0); 30841#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30840#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30839#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30838#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30837#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30836#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29866#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29865#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29722#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28949#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30158#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 30157#L1572 assume !(0 == start_simulation_~tmp~3#1); 28993#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29945#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 29934#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29932#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 29931#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29929#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29927#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 29908#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 29902#L1553-2 [2022-12-13 12:30:55,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:55,867 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2022-12-13 12:30:55,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:55,867 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446166125] [2022-12-13 12:30:55,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:55,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:55,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:55,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:55,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:55,911 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446166125] [2022-12-13 12:30:55,911 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1446166125] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:55,911 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:55,911 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:55,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1260053479] [2022-12-13 12:30:55,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:55,911 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:55,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:55,912 INFO L85 PathProgramCache]: Analyzing trace with hash 651122039, now seen corresponding path program 1 times [2022-12-13 12:30:55,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:55,912 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1701563847] [2022-12-13 12:30:55,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:55,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:55,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:55,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:55,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:55,948 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1701563847] [2022-12-13 12:30:55,948 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1701563847] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:55,948 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:55,948 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:55,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1696640956] [2022-12-13 12:30:55,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:55,949 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:55,949 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:55,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:30:55,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:30:55,949 INFO L87 Difference]: Start difference. First operand 2504 states and 3694 transitions. cyclomatic complexity: 1192 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:56,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:56,080 INFO L93 Difference]: Finished difference Result 4620 states and 6803 transitions. [2022-12-13 12:30:56,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4620 states and 6803 transitions. [2022-12-13 12:30:56,094 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4427 [2022-12-13 12:30:56,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4620 states to 4620 states and 6803 transitions. [2022-12-13 12:30:56,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4620 [2022-12-13 12:30:56,120 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4620 [2022-12-13 12:30:56,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4620 states and 6803 transitions. [2022-12-13 12:30:56,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:56,125 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4620 states and 6803 transitions. [2022-12-13 12:30:56,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4620 states and 6803 transitions. [2022-12-13 12:30:56,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4620 to 4618. [2022-12-13 12:30:56,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4618 states, 4618 states have (on average 1.4727154612386315) internal successors, (6801), 4617 states have internal predecessors, (6801), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:56,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4618 states to 4618 states and 6801 transitions. [2022-12-13 12:30:56,192 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4618 states and 6801 transitions. [2022-12-13 12:30:56,192 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:30:56,193 INFO L428 stractBuchiCegarLoop]: Abstraction has 4618 states and 6801 transitions. [2022-12-13 12:30:56,193 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 12:30:56,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4618 states and 6801 transitions. [2022-12-13 12:30:56,206 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4427 [2022-12-13 12:30:56,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:56,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:56,207 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:56,208 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:56,208 INFO L748 eck$LassoCheckResult]: Stem: 35960#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 35961#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 36909#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36910#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36558#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 36233#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36234#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36528#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36699#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36411#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36412#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36290#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36291#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36652#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36614#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36536#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36537#L1024 assume !(0 == ~M_E~0); 36803#L1024-2 assume !(0 == ~T1_E~0); 35956#L1029-1 assume !(0 == ~T2_E~0); 35957#L1034-1 assume !(0 == ~T3_E~0); 36058#L1039-1 assume !(0 == ~T4_E~0); 36937#L1044-1 assume !(0 == ~T5_E~0); 36315#L1049-1 assume !(0 == ~T6_E~0); 36316#L1054-1 assume !(0 == ~T7_E~0); 36557#L1059-1 assume !(0 == ~T8_E~0); 36006#L1064-1 assume !(0 == ~T9_E~0); 36007#L1069-1 assume !(0 == ~T10_E~0); 36771#L1074-1 assume !(0 == ~E_M~0); 36837#L1079-1 assume !(0 == ~E_1~0); 36805#L1084-1 assume !(0 == ~E_2~0); 36806#L1089-1 assume !(0 == ~E_3~0); 36857#L1094-1 assume !(0 == ~E_4~0); 36401#L1099-1 assume !(0 == ~E_5~0); 36402#L1104-1 assume !(0 == ~E_6~0); 36669#L1109-1 assume !(0 == ~E_7~0); 36172#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36173#L1119-1 assume !(0 == ~E_9~0); 36246#L1124-1 assume !(0 == ~E_10~0); 35663#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35664#L502 assume 1 == ~m_pc~0; 36555#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35789#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35790#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36610#L1273 assume !(0 != activate_threads_~tmp~1#1); 36611#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36976#L521 assume !(1 == ~t1_pc~0); 36890#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35714#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35679#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35680#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 35700#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35701#L540 assume 1 == ~t2_pc~0; 36819#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36516#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36168#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36169#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 36883#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35984#L559 assume 1 == ~t3_pc~0; 35985#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36264#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35618#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35619#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 35807#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35808#L578 assume !(1 == ~t4_pc~0); 35928#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35927#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35747#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35748#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36590#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36591#L597 assume 1 == ~t5_pc~0; 36996#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35734#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35735#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36801#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 36538#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36539#L616 assume !(1 == ~t6_pc~0); 36554#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36553#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36144#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36145#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 36391#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36392#L635 assume 1 == ~t7_pc~0; 36594#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35703#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36076#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36853#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 36529#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36530#L654 assume !(1 == ~t8_pc~0); 36342#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36343#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36731#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36732#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 36769#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35954#L673 assume 1 == ~t9_pc~0; 35955#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35654#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36228#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36229#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 36683#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36684#L692 assume !(1 == ~t10_pc~0); 36627#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36626#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36393#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36394#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 36405#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36746#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 35866#L1142-2 assume !(1 == ~T1_E~0); 35867#L1147-1 assume !(1 == ~T2_E~0); 36735#L1152-1 assume !(1 == ~T3_E~0); 36270#L1157-1 assume !(1 == ~T4_E~0); 36271#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37138#L1167-1 assume !(1 == ~T6_E~0); 37136#L1172-1 assume !(1 == ~T7_E~0); 36892#L1177-1 assume !(1 == ~T8_E~0); 36893#L1182-1 assume !(1 == ~T9_E~0); 36674#L1187-1 assume !(1 == ~T10_E~0); 36675#L1192-1 assume !(1 == ~E_M~0); 37116#L1197-1 assume !(1 == ~E_1~0); 37115#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37103#L1207-1 assume !(1 == ~E_3~0); 37101#L1212-1 assume !(1 == ~E_4~0); 37099#L1217-1 assume !(1 == ~E_5~0); 37097#L1222-1 assume !(1 == ~E_6~0); 37095#L1227-1 assume !(1 == ~E_7~0); 37093#L1232-1 assume !(1 == ~E_8~0); 37092#L1237-1 assume !(1 == ~E_9~0); 37088#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37073#L1247-1 assume { :end_inline_reset_delta_events } true; 37066#L1553-2 [2022-12-13 12:30:56,208 INFO L750 eck$LassoCheckResult]: Loop: 37066#L1553-2 assume !false; 37060#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37055#L999 assume !false; 37054#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37053#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37042#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37041#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37039#L854 assume !(0 != eval_~tmp~0#1); 37038#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37037#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37036#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36927#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36387#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36355#L1034-3 assume !(0 == ~T3_E~0); 36356#L1039-3 assume !(0 == ~T4_E~0); 40198#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35950#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35951#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35715#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35716#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36325#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36326#L1074-3 assume !(0 == ~E_M~0); 40055#L1079-3 assume !(0 == ~E_1~0); 40054#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40053#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40052#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40051#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40050#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40049#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40048#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40047#L1119-3 assume !(0 == ~E_9~0); 40046#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40045#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40044#L502-36 assume !(1 == ~m_pc~0); 40042#L502-38 is_master_triggered_~__retres1~0#1 := 0; 40041#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40040#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40039#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40038#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40037#L521-36 assume 1 == ~t1_pc~0; 40035#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40034#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40010#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39780#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36773#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36774#L540-36 assume !(1 == ~t2_pc~0); 35665#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 35666#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36077#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36775#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36424#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35589#L559-36 assume 1 == ~t3_pc~0; 35590#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36040#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36223#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36224#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36578#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36832#L578-36 assume 1 == ~t4_pc~0; 36546#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36501#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36437#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36438#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36333#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36334#L597-36 assume !(1 == ~t5_pc~0); 36565#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 36957#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36882#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36518#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 36121#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36122#L616-36 assume !(1 == ~t6_pc~0); 36923#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 35659#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35660#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36201#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36384#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36721#L635-36 assume 1 == ~t7_pc~0; 39772#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39770#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39768#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39766#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36370#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36371#L654-36 assume 1 == ~t8_pc~0; 37011#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36934#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36542#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36543#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36977#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36032#L673-36 assume !(1 == ~t9_pc~0); 36033#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 36410#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36266#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36267#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35602#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35603#L692-36 assume 1 == ~t10_pc~0; 36567#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35816#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36105#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36001#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36002#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36381#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36535#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36998#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37173#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36960#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37168#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37166#L1167-3 assume !(1 == ~T6_E~0); 37164#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37162#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37160#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37158#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37156#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37154#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37153#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37152#L1207-3 assume !(1 == ~E_3~0); 37151#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37150#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37149#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37148#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37147#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37146#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37145#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37140#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37123#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37121#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37119#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 37117#L1572 assume !(0 == start_simulation_~tmp~3#1); 36126#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37113#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37102#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37100#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 37098#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37096#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37094#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 37074#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 37066#L1553-2 [2022-12-13 12:30:56,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:56,209 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2022-12-13 12:30:56,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:56,209 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1329786995] [2022-12-13 12:30:56,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:56,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:56,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:56,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:56,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:56,254 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1329786995] [2022-12-13 12:30:56,254 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1329786995] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:56,254 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:56,254 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:56,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [150553628] [2022-12-13 12:30:56,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:56,255 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:56,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:56,255 INFO L85 PathProgramCache]: Analyzing trace with hash -1652064902, now seen corresponding path program 1 times [2022-12-13 12:30:56,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:56,255 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230207121] [2022-12-13 12:30:56,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:56,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:56,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:56,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:56,287 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:56,287 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [230207121] [2022-12-13 12:30:56,287 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [230207121] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:56,287 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:56,287 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:56,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917272668] [2022-12-13 12:30:56,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:56,288 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:56,288 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:56,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:30:56,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:30:56,289 INFO L87 Difference]: Start difference. First operand 4618 states and 6801 transitions. cyclomatic complexity: 2187 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:56,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:56,428 INFO L93 Difference]: Finished difference Result 8652 states and 12712 transitions. [2022-12-13 12:30:56,429 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8652 states and 12712 transitions. [2022-12-13 12:30:56,459 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8437 [2022-12-13 12:30:56,481 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8652 states to 8652 states and 12712 transitions. [2022-12-13 12:30:56,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8652 [2022-12-13 12:30:56,486 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8652 [2022-12-13 12:30:56,486 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8652 states and 12712 transitions. [2022-12-13 12:30:56,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:56,511 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8652 states and 12712 transitions. [2022-12-13 12:30:56,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8652 states and 12712 transitions. [2022-12-13 12:30:56,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8652 to 8648. [2022-12-13 12:30:56,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8648 states, 8648 states have (on average 1.469472710453284) internal successors, (12708), 8647 states have internal predecessors, (12708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:56,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8648 states to 8648 states and 12708 transitions. [2022-12-13 12:30:56,603 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8648 states and 12708 transitions. [2022-12-13 12:30:56,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:30:56,603 INFO L428 stractBuchiCegarLoop]: Abstraction has 8648 states and 12708 transitions. [2022-12-13 12:30:56,603 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 12:30:56,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8648 states and 12708 transitions. [2022-12-13 12:30:56,623 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8437 [2022-12-13 12:30:56,623 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:56,623 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:56,625 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:56,625 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:56,625 INFO L748 eck$LassoCheckResult]: Stem: 49241#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 49242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 50173#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50174#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49838#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 49513#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49514#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49806#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49980#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49691#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49692#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49568#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49569#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49933#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49893#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49813#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49814#L1024 assume !(0 == ~M_E~0); 50080#L1024-2 assume !(0 == ~T1_E~0); 49237#L1029-1 assume !(0 == ~T2_E~0); 49238#L1034-1 assume !(0 == ~T3_E~0); 49340#L1039-1 assume !(0 == ~T4_E~0); 50198#L1044-1 assume !(0 == ~T5_E~0); 49589#L1049-1 assume !(0 == ~T6_E~0); 49590#L1054-1 assume !(0 == ~T7_E~0); 49837#L1059-1 assume !(0 == ~T8_E~0); 49287#L1064-1 assume !(0 == ~T9_E~0); 49288#L1069-1 assume !(0 == ~T10_E~0); 50048#L1074-1 assume !(0 == ~E_M~0); 50112#L1079-1 assume !(0 == ~E_1~0); 50082#L1084-1 assume !(0 == ~E_2~0); 50083#L1089-1 assume !(0 == ~E_3~0); 50130#L1094-1 assume !(0 == ~E_4~0); 49682#L1099-1 assume !(0 == ~E_5~0); 49683#L1104-1 assume !(0 == ~E_6~0); 49950#L1109-1 assume !(0 == ~E_7~0); 49453#L1114-1 assume !(0 == ~E_8~0); 49454#L1119-1 assume !(0 == ~E_9~0); 49523#L1124-1 assume !(0 == ~E_10~0); 48943#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48944#L502 assume 1 == ~m_pc~0; 49835#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49069#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49070#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49887#L1273 assume !(0 != activate_threads_~tmp~1#1); 49888#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50237#L521 assume !(1 == ~t1_pc~0); 50161#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48994#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48959#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48960#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 48980#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48981#L540 assume 1 == ~t2_pc~0; 50094#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49795#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49449#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49450#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 50157#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49265#L559 assume 1 == ~t3_pc~0; 49266#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49545#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48898#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48899#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 49087#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49088#L578 assume !(1 == ~t4_pc~0); 49204#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49203#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49026#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49027#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49868#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49869#L597 assume 1 == ~t5_pc~0; 50255#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49014#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49015#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50078#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 49815#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49816#L616 assume !(1 == ~t6_pc~0); 49832#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49831#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49425#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49426#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 49670#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49671#L635 assume 1 == ~t7_pc~0; 49873#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48983#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49356#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50126#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 49808#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49809#L654 assume !(1 == ~t8_pc~0); 49620#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49621#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50006#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50007#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 50045#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49235#L673 assume 1 == ~t9_pc~0; 49236#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48934#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49507#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49508#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 49962#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49963#L692 assume !(1 == ~t10_pc~0); 49906#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49905#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49674#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49675#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 49686#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50023#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 49146#L1142-2 assume !(1 == ~T1_E~0); 49147#L1147-1 assume !(1 == ~T2_E~0); 50285#L1152-1 assume !(1 == ~T3_E~0); 50286#L1157-1 assume !(1 == ~T4_E~0); 52030#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52029#L1167-1 assume !(1 == ~T6_E~0); 50147#L1172-1 assume !(1 == ~T7_E~0); 50148#L1177-1 assume !(1 == ~T8_E~0); 49856#L1182-1 assume !(1 == ~T9_E~0); 49857#L1187-1 assume !(1 == ~T10_E~0); 49955#L1192-1 assume !(1 == ~E_M~0); 50003#L1197-1 assume !(1 == ~E_1~0); 52507#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 52502#L1207-1 assume !(1 == ~E_3~0); 52501#L1212-1 assume !(1 == ~E_4~0); 52496#L1217-1 assume !(1 == ~E_5~0); 52494#L1222-1 assume !(1 == ~E_6~0); 52491#L1227-1 assume !(1 == ~E_7~0); 52489#L1232-1 assume !(1 == ~E_8~0); 52485#L1237-1 assume !(1 == ~E_9~0); 52483#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 50328#L1247-1 assume { :end_inline_reset_delta_events } true; 50321#L1553-2 [2022-12-13 12:30:56,625 INFO L750 eck$LassoCheckResult]: Loop: 50321#L1553-2 assume !false; 50315#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50310#L999 assume !false; 50309#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50308#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50297#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50296#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50294#L854 assume !(0 != eval_~tmp~0#1); 50293#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50292#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50290#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50291#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51325#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51323#L1034-3 assume !(0 == ~T3_E~0); 51321#L1039-3 assume !(0 == ~T4_E~0); 51309#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51307#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51305#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 51302#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51300#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 51298#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51296#L1074-3 assume !(0 == ~E_M~0); 51294#L1079-3 assume !(0 == ~E_1~0); 51292#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51290#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51289#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51284#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51282#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51280#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51268#L1114-3 assume !(0 == ~E_8~0); 51266#L1119-3 assume !(0 == ~E_9~0); 51264#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51261#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51259#L502-36 assume !(1 == ~m_pc~0); 51256#L502-38 is_master_triggered_~__retres1~0#1 := 0; 51254#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51252#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 51250#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51248#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51246#L521-36 assume 1 == ~t1_pc~0; 51242#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 51240#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51238#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51236#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51234#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51078#L540-36 assume !(1 == ~t2_pc~0); 51075#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 51073#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51071#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51069#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51067#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51065#L559-36 assume 1 == ~t3_pc~0; 51061#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 51059#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51057#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51055#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51053#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51051#L578-36 assume !(1 == ~t4_pc~0); 51048#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 51046#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51044#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51042#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51040#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51038#L597-36 assume 1 == ~t5_pc~0; 51035#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51033#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51031#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50962#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 50960#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50958#L616-36 assume 1 == ~t6_pc~0; 50955#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50953#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50951#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50879#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50876#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50874#L635-36 assume 1 == ~t7_pc~0; 50871#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50869#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50867#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50865#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50825#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50730#L654-36 assume 1 == ~t8_pc~0; 50727#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50651#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50614#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50612#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50610#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50608#L673-36 assume !(1 == ~t9_pc~0); 50602#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 50600#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50598#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50596#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50594#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50592#L692-36 assume 1 == ~t10_pc~0; 50551#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50548#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50546#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50544#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50524#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49817#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49818#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50196#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50197#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50221#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50442#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50437#L1167-3 assume !(1 == ~T6_E~0); 50432#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50427#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50422#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50416#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50411#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50405#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50402#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50399#L1207-3 assume !(1 == ~E_3~0); 50396#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50392#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50389#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50386#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50383#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50379#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50377#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 50374#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50362#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50360#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50358#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 50356#L1572 assume !(0 == start_simulation_~tmp~3#1); 49407#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50353#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50341#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50339#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 50337#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50335#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50333#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 50329#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 50321#L1553-2 [2022-12-13 12:30:56,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:56,625 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2022-12-13 12:30:56,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:56,626 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154797716] [2022-12-13 12:30:56,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:56,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:56,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:56,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:56,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:56,664 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1154797716] [2022-12-13 12:30:56,664 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1154797716] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:56,664 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:56,664 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:30:56,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755226313] [2022-12-13 12:30:56,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:56,665 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:56,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:56,666 INFO L85 PathProgramCache]: Analyzing trace with hash -1798258821, now seen corresponding path program 1 times [2022-12-13 12:30:56,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:56,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40848501] [2022-12-13 12:30:56,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:56,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:56,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:56,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:56,699 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:56,699 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40848501] [2022-12-13 12:30:56,699 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [40848501] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:56,699 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:56,699 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:56,699 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190719175] [2022-12-13 12:30:56,699 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:56,700 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:56,700 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:56,700 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:30:56,700 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:30:56,700 INFO L87 Difference]: Start difference. First operand 8648 states and 12708 transitions. cyclomatic complexity: 4068 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:56,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:56,844 INFO L93 Difference]: Finished difference Result 16971 states and 24755 transitions. [2022-12-13 12:30:56,844 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16971 states and 24755 transitions. [2022-12-13 12:30:56,894 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16753 [2022-12-13 12:30:56,930 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16971 states to 16971 states and 24755 transitions. [2022-12-13 12:30:56,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16971 [2022-12-13 12:30:56,937 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16971 [2022-12-13 12:30:56,938 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16971 states and 24755 transitions. [2022-12-13 12:30:56,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:56,948 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16971 states and 24755 transitions. [2022-12-13 12:30:56,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16971 states and 24755 transitions. [2022-12-13 12:30:57,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16971 to 16363. [2022-12-13 12:30:57,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16363 states, 16363 states have (on average 1.4605512436594756) internal successors, (23899), 16362 states have internal predecessors, (23899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:57,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16363 states to 16363 states and 23899 transitions. [2022-12-13 12:30:57,189 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16363 states and 23899 transitions. [2022-12-13 12:30:57,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:30:57,190 INFO L428 stractBuchiCegarLoop]: Abstraction has 16363 states and 23899 transitions. [2022-12-13 12:30:57,190 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 12:30:57,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16363 states and 23899 transitions. [2022-12-13 12:30:57,243 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16145 [2022-12-13 12:30:57,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:57,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:57,245 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:57,245 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:57,246 INFO L748 eck$LassoCheckResult]: Stem: 74882#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 74883#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 75951#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75952#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75540#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 75176#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75177#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75504#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75704#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75369#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75370#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75239#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75240#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75650#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75606#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 75515#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75516#L1024 assume !(0 == ~M_E~0); 75829#L1024-2 assume !(0 == ~T1_E~0); 74877#L1029-1 assume !(0 == ~T2_E~0); 74878#L1034-1 assume !(0 == ~T3_E~0); 74988#L1039-1 assume !(0 == ~T4_E~0); 75990#L1044-1 assume !(0 == ~T5_E~0); 75261#L1049-1 assume !(0 == ~T6_E~0); 75262#L1054-1 assume !(0 == ~T7_E~0); 75539#L1059-1 assume !(0 == ~T8_E~0); 74934#L1064-1 assume !(0 == ~T9_E~0); 74935#L1069-1 assume !(0 == ~T10_E~0); 75791#L1074-1 assume !(0 == ~E_M~0); 75869#L1079-1 assume !(0 == ~E_1~0); 75832#L1084-1 assume !(0 == ~E_2~0); 75833#L1089-1 assume !(0 == ~E_3~0); 75896#L1094-1 assume !(0 == ~E_4~0); 75358#L1099-1 assume !(0 == ~E_5~0); 75359#L1104-1 assume !(0 == ~E_6~0); 75672#L1109-1 assume !(0 == ~E_7~0); 75111#L1114-1 assume !(0 == ~E_8~0); 75112#L1119-1 assume !(0 == ~E_9~0); 75193#L1124-1 assume !(0 == ~E_10~0); 74569#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74570#L502 assume !(1 == ~m_pc~0); 74770#L502-2 is_master_triggered_~__retres1~0#1 := 0; 74701#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74702#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75602#L1273 assume !(0 != activate_threads_~tmp~1#1); 75603#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76066#L521 assume !(1 == ~t1_pc~0); 75932#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 74622#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74585#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 74586#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 74606#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74607#L540 assume 1 == ~t2_pc~0; 75846#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 75485#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75109#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75110#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 75928#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74912#L559 assume 1 == ~t3_pc~0; 74913#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75209#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74524#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 74525#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 74718#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74719#L578 assume !(1 == ~t4_pc~0); 74847#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 74846#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74655#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74656#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75581#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75582#L597 assume 1 == ~t5_pc~0; 76096#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 74641#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74642#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75827#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 75517#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75518#L616 assume !(1 == ~t6_pc~0); 75537#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 75536#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75083#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75084#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 75348#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75349#L635 assume 1 == ~t7_pc~0; 75585#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 74609#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75006#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75891#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 75506#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75507#L654 assume !(1 == ~t8_pc~0); 75290#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75291#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75743#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75744#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 75788#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74875#L673 assume 1 == ~t9_pc~0; 74876#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 74562#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75171#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75172#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 75687#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75688#L692 assume !(1 == ~t10_pc~0); 75623#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75622#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75350#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75351#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 75362#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75762#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 76160#L1142-2 assume !(1 == ~T1_E~0); 82596#L1147-1 assume !(1 == ~T2_E~0); 82594#L1152-1 assume !(1 == ~T3_E~0); 82592#L1157-1 assume !(1 == ~T4_E~0); 82590#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 82588#L1167-1 assume !(1 == ~T6_E~0); 82586#L1172-1 assume !(1 == ~T7_E~0); 82583#L1177-1 assume !(1 == ~T8_E~0); 82581#L1182-1 assume !(1 == ~T9_E~0); 82579#L1187-1 assume !(1 == ~T10_E~0); 82578#L1192-1 assume !(1 == ~E_M~0); 82577#L1197-1 assume !(1 == ~E_1~0); 82576#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 82572#L1207-1 assume !(1 == ~E_3~0); 81483#L1212-1 assume !(1 == ~E_4~0); 81478#L1217-1 assume !(1 == ~E_5~0); 81473#L1222-1 assume !(1 == ~E_6~0); 81472#L1227-1 assume !(1 == ~E_7~0); 77469#L1232-1 assume !(1 == ~E_8~0); 77467#L1237-1 assume !(1 == ~E_9~0); 77466#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 77231#L1247-1 assume { :end_inline_reset_delta_events } true; 77223#L1553-2 [2022-12-13 12:30:57,246 INFO L750 eck$LassoCheckResult]: Loop: 77223#L1553-2 assume !false; 77216#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77211#L999 assume !false; 77210#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77198#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77186#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77184#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 77179#L854 assume !(0 != eval_~tmp~0#1); 77181#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78389#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77174#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77175#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 89118#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 89117#L1034-3 assume !(0 == ~T3_E~0); 89116#L1039-3 assume !(0 == ~T4_E~0); 89115#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 89114#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 89113#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 88649#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 88650#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 88632#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 88633#L1074-3 assume !(0 == ~E_M~0); 88601#L1079-3 assume !(0 == ~E_1~0); 88602#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 86895#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 86896#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 86878#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86879#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 86874#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 86875#L1114-3 assume !(0 == ~E_8~0); 86869#L1119-3 assume !(0 == ~E_9~0); 86870#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76122#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76123#L502-36 assume !(1 == ~m_pc~0); 89019#L502-38 is_master_triggered_~__retres1~0#1 := 0; 89013#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89007#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 89003#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88997#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88992#L521-36 assume !(1 == ~t1_pc~0); 88985#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 88977#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75949#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75950#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75795#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75796#L540-36 assume !(1 == ~t2_pc~0); 88945#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 88528#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77172#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 77170#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77171#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77165#L559-36 assume !(1 == ~t3_pc~0); 77167#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 77161#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77160#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77159#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77158#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77157#L578-36 assume !(1 == ~t4_pc~0); 77155#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 77154#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77153#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77152#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77151#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77150#L597-36 assume !(1 == ~t5_pc~0); 77149#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 77147#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77146#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77135#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 77134#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77133#L616-36 assume 1 == ~t6_pc~0; 77131#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 74565#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74566#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77117#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77116#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77115#L635-36 assume 1 == ~t7_pc~0; 77113#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 77112#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77111#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77110#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 77108#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77107#L654-36 assume 1 == ~t8_pc~0; 77105#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 77104#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77103#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77102#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77101#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77100#L673-36 assume 1 == ~t9_pc~0; 77099#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77097#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77096#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77095#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 77094#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77093#L692-36 assume 1 == ~t10_pc~0; 77090#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 77091#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 84952#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 84951#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84948#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84946#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 77085#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 84943#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 84942#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77081#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 84941#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 84940#L1167-3 assume !(1 == ~T6_E~0); 84939#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 84938#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 84936#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 84934#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83538#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 82420#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 82418#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 82416#L1207-3 assume !(1 == ~E_3~0); 82414#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82412#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 82409#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 82407#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 81779#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 81776#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 81775#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 81774#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 81373#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 81372#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 81370#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 81368#L1572 assume !(0 == start_simulation_~tmp~3#1); 75060#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 79051#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 79040#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 79038#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 79036#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 79034#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 79032#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 77232#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 77223#L1553-2 [2022-12-13 12:30:57,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:57,247 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2022-12-13 12:30:57,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:57,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640218833] [2022-12-13 12:30:57,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:57,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:57,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:57,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:57,315 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:57,315 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640218833] [2022-12-13 12:30:57,315 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [640218833] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:57,316 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:57,316 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:57,316 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [179071191] [2022-12-13 12:30:57,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:57,316 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:57,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:57,317 INFO L85 PathProgramCache]: Analyzing trace with hash 907605245, now seen corresponding path program 1 times [2022-12-13 12:30:57,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:57,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642817692] [2022-12-13 12:30:57,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:57,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:57,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:57,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:57,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:57,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [642817692] [2022-12-13 12:30:57,373 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [642817692] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:57,373 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:57,373 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:57,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830395345] [2022-12-13 12:30:57,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:57,374 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:57,374 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:57,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:30:57,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:30:57,375 INFO L87 Difference]: Start difference. First operand 16363 states and 23899 transitions. cyclomatic complexity: 7552 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:57,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:57,749 INFO L93 Difference]: Finished difference Result 39692 states and 57496 transitions. [2022-12-13 12:30:57,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39692 states and 57496 transitions. [2022-12-13 12:30:57,918 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 38803 [2022-12-13 12:30:57,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39692 states to 39692 states and 57496 transitions. [2022-12-13 12:30:57,997 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39692 [2022-12-13 12:30:58,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39692 [2022-12-13 12:30:58,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39692 states and 57496 transitions. [2022-12-13 12:30:58,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:58,033 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39692 states and 57496 transitions. [2022-12-13 12:30:58,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39692 states and 57496 transitions. [2022-12-13 12:30:58,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39692 to 31057. [2022-12-13 12:30:58,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31057 states, 31057 states have (on average 1.4538751328202981) internal successors, (45153), 31056 states have internal predecessors, (45153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:58,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31057 states to 31057 states and 45153 transitions. [2022-12-13 12:30:58,544 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31057 states and 45153 transitions. [2022-12-13 12:30:58,544 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:30:58,544 INFO L428 stractBuchiCegarLoop]: Abstraction has 31057 states and 45153 transitions. [2022-12-13 12:30:58,544 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 12:30:58,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31057 states and 45153 transitions. [2022-12-13 12:30:58,630 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30832 [2022-12-13 12:30:58,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:30:58,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:30:58,632 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:58,632 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:30:58,632 INFO L748 eck$LassoCheckResult]: Stem: 130940#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 130941#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 131993#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131994#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131583#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 131233#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 131234#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131544#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 131747#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131415#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131416#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 131286#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 131287#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 131698#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 131648#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 131555#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131556#L1024 assume !(0 == ~M_E~0); 131873#L1024-2 assume !(0 == ~T1_E~0); 130936#L1029-1 assume !(0 == ~T2_E~0); 130937#L1034-1 assume !(0 == ~T3_E~0); 131048#L1039-1 assume !(0 == ~T4_E~0); 132029#L1044-1 assume !(0 == ~T5_E~0); 131309#L1049-1 assume !(0 == ~T6_E~0); 131310#L1054-1 assume !(0 == ~T7_E~0); 131582#L1059-1 assume !(0 == ~T8_E~0); 130991#L1064-1 assume !(0 == ~T9_E~0); 130992#L1069-1 assume !(0 == ~T10_E~0); 131834#L1074-1 assume !(0 == ~E_M~0); 131910#L1079-1 assume !(0 == ~E_1~0); 131875#L1084-1 assume !(0 == ~E_2~0); 131876#L1089-1 assume !(0 == ~E_3~0); 131939#L1094-1 assume !(0 == ~E_4~0); 131405#L1099-1 assume !(0 == ~E_5~0); 131406#L1104-1 assume !(0 == ~E_6~0); 131716#L1109-1 assume !(0 == ~E_7~0); 131167#L1114-1 assume !(0 == ~E_8~0); 131168#L1119-1 assume !(0 == ~E_9~0); 131243#L1124-1 assume !(0 == ~E_10~0); 130634#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 130635#L502 assume !(1 == ~m_pc~0); 130831#L502-2 is_master_triggered_~__retres1~0#1 := 0; 130764#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 130765#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 131642#L1273 assume !(0 != activate_threads_~tmp~1#1); 131643#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132090#L521 assume !(1 == ~t1_pc~0); 131977#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 130685#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130650#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 130651#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 130671#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 130672#L540 assume !(1 == ~t2_pc~0); 131528#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131529#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131163#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 131164#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 131969#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130969#L559 assume 1 == ~t3_pc~0; 130970#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 131264#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130589#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 130590#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 130782#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130783#L578 assume !(1 == ~t4_pc~0); 130900#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 130899#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130718#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 130719#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 131622#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131623#L597 assume 1 == ~t5_pc~0; 132112#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 130706#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130707#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 131871#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 131557#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 131558#L616 assume !(1 == ~t6_pc~0); 131577#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 131576#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 131138#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 131139#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 131393#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 131394#L635 assume 1 == ~t7_pc~0; 131627#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 130674#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 131066#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 131935#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 131549#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 131550#L654 assume !(1 == ~t8_pc~0); 131341#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 131342#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 131780#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 131781#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 131830#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 130934#L673 assume 1 == ~t9_pc~0; 130935#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 130625#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 131227#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 131228#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 131729#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 131730#L692 assume !(1 == ~t10_pc~0); 131665#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 131664#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 131396#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 131397#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 131409#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131807#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 132172#L1142-2 assume !(1 == ~T1_E~0); 131788#L1147-1 assume !(1 == ~T2_E~0); 131789#L1152-1 assume !(1 == ~T3_E~0); 139122#L1157-1 assume !(1 == ~T4_E~0); 139120#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 139118#L1167-1 assume !(1 == ~T6_E~0); 139110#L1172-1 assume !(1 == ~T7_E~0); 139109#L1177-1 assume !(1 == ~T8_E~0); 139107#L1182-1 assume !(1 == ~T9_E~0); 139105#L1187-1 assume !(1 == ~T10_E~0); 139103#L1192-1 assume !(1 == ~E_M~0); 139101#L1197-1 assume !(1 == ~E_1~0); 139099#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 139097#L1207-1 assume !(1 == ~E_3~0); 139095#L1212-1 assume !(1 == ~E_4~0); 139093#L1217-1 assume !(1 == ~E_5~0); 139071#L1222-1 assume !(1 == ~E_6~0); 139070#L1227-1 assume !(1 == ~E_7~0); 139069#L1232-1 assume !(1 == ~E_8~0); 139066#L1237-1 assume !(1 == ~E_9~0); 139065#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 139063#L1247-1 assume { :end_inline_reset_delta_events } true; 139053#L1553-2 [2022-12-13 12:30:58,633 INFO L750 eck$LassoCheckResult]: Loop: 139053#L1553-2 assume !false; 139042#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 139033#L999 assume !false; 139029#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 138992#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 138978#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 138972#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 138966#L854 assume !(0 != eval_~tmp~0#1); 138967#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 145767#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 145762#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 145757#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 145752#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 145745#L1034-3 assume !(0 == ~T3_E~0); 145739#L1039-3 assume !(0 == ~T4_E~0); 145734#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 145729#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 145724#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 145719#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 145712#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 145706#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 145701#L1074-3 assume !(0 == ~E_M~0); 145696#L1079-3 assume !(0 == ~E_1~0); 145691#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 145688#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 145686#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 145684#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 145682#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 145680#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 145678#L1114-3 assume !(0 == ~E_8~0); 145677#L1119-3 assume !(0 == ~E_9~0); 145675#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 145673#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 145671#L502-36 assume !(1 == ~m_pc~0); 145669#L502-38 is_master_triggered_~__retres1~0#1 := 0; 145667#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 145664#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 145662#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 145660#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 145658#L521-36 assume 1 == ~t1_pc~0; 145655#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 145653#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 145650#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 145648#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 145646#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 145644#L540-36 assume !(1 == ~t2_pc~0); 134824#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 145641#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 145638#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 145636#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 145635#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 145634#L559-36 assume 1 == ~t3_pc~0; 145632#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 145631#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 145630#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 145591#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 145589#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 145587#L578-36 assume !(1 == ~t4_pc~0); 145584#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 145582#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 145580#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 145577#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 145575#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 145573#L597-36 assume 1 == ~t5_pc~0; 145570#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 145568#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 145566#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 145549#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 145546#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 145542#L616-36 assume 1 == ~t6_pc~0; 145538#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 145533#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 145529#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 145525#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 145521#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 145516#L635-36 assume 1 == ~t7_pc~0; 145511#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 145506#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 145501#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 145497#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 145493#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 145470#L654-36 assume 1 == ~t8_pc~0; 145464#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 145458#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 145454#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 145449#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 145444#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 145437#L673-36 assume !(1 == ~t9_pc~0); 145431#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 145425#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 145419#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 145414#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 145409#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 145402#L692-36 assume 1 == ~t10_pc~0; 145396#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 145389#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 145382#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 145293#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 145249#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 145239#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 140010#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 145222#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 145211#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 145205#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 145199#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 145194#L1167-3 assume !(1 == ~T6_E~0); 145188#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 145183#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 145179#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 145173#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 145167#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 142870#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 145156#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 145149#L1207-3 assume !(1 == ~E_3~0); 145143#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 145138#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 145133#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 145130#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 139966#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 139962#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 139960#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 139958#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 139427#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 139416#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 139406#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 139397#L1572 assume !(0 == start_simulation_~tmp~3#1); 139394#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 139179#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 139161#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 139151#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 139144#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 139137#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 139130#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 139064#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 139053#L1553-2 [2022-12-13 12:30:58,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:58,633 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2022-12-13 12:30:58,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:58,633 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [255136476] [2022-12-13 12:30:58,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:58,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:58,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:58,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:58,685 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:58,685 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [255136476] [2022-12-13 12:30:58,685 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [255136476] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:58,685 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:58,685 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:58,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [799905418] [2022-12-13 12:30:58,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:58,686 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:30:58,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:30:58,686 INFO L85 PathProgramCache]: Analyzing trace with hash -1798258821, now seen corresponding path program 2 times [2022-12-13 12:30:58,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:30:58,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591979044] [2022-12-13 12:30:58,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:30:58,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:30:58,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:30:58,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:30:58,722 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:30:58,723 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [591979044] [2022-12-13 12:30:58,723 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [591979044] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:30:58,723 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:30:58,723 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:30:58,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1801273592] [2022-12-13 12:30:58,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:30:58,723 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:30:58,723 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:30:58,724 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:30:58,724 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:30:58,724 INFO L87 Difference]: Start difference. First operand 31057 states and 45153 transitions. cyclomatic complexity: 14112 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:30:59,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:30:59,198 INFO L93 Difference]: Finished difference Result 75353 states and 108733 transitions. [2022-12-13 12:30:59,198 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75353 states and 108733 transitions. [2022-12-13 12:30:59,433 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 73793 [2022-12-13 12:30:59,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75353 states to 75353 states and 108733 transitions. [2022-12-13 12:30:59,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75353 [2022-12-13 12:30:59,609 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75353 [2022-12-13 12:30:59,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75353 states and 108733 transitions. [2022-12-13 12:30:59,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:30:59,640 INFO L218 hiAutomatonCegarLoop]: Abstraction has 75353 states and 108733 transitions. [2022-12-13 12:30:59,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75353 states and 108733 transitions. [2022-12-13 12:31:00,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75353 to 59020. [2022-12-13 12:31:00,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59020 states, 59020 states have (on average 1.44808539478143) internal successors, (85466), 59019 states have internal predecessors, (85466), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:00,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59020 states to 59020 states and 85466 transitions. [2022-12-13 12:31:00,304 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59020 states and 85466 transitions. [2022-12-13 12:31:00,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:31:00,305 INFO L428 stractBuchiCegarLoop]: Abstraction has 59020 states and 85466 transitions. [2022-12-13 12:31:00,305 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 12:31:00,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59020 states and 85466 transitions. [2022-12-13 12:31:00,468 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 58780 [2022-12-13 12:31:00,468 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:00,468 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:00,470 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:00,471 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:00,471 INFO L748 eck$LassoCheckResult]: Stem: 237353#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 237354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 238314#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 238315#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 237960#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 237637#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 237638#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 237927#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 238111#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 237808#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 237809#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 237689#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 237690#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 238058#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 238016#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 237937#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 237938#L1024 assume !(0 == ~M_E~0); 238220#L1024-2 assume !(0 == ~T1_E~0); 237349#L1029-1 assume !(0 == ~T2_E~0); 237350#L1034-1 assume !(0 == ~T3_E~0); 237456#L1039-1 assume !(0 == ~T4_E~0); 238340#L1044-1 assume !(0 == ~T5_E~0); 237710#L1049-1 assume !(0 == ~T6_E~0); 237711#L1054-1 assume !(0 == ~T7_E~0); 237959#L1059-1 assume !(0 == ~T8_E~0); 237403#L1064-1 assume !(0 == ~T9_E~0); 237404#L1069-1 assume !(0 == ~T10_E~0); 238183#L1074-1 assume !(0 == ~E_M~0); 238254#L1079-1 assume !(0 == ~E_1~0); 238222#L1084-1 assume !(0 == ~E_2~0); 238223#L1089-1 assume !(0 == ~E_3~0); 238272#L1094-1 assume !(0 == ~E_4~0); 237799#L1099-1 assume !(0 == ~E_5~0); 237800#L1104-1 assume !(0 == ~E_6~0); 238079#L1109-1 assume !(0 == ~E_7~0); 237575#L1114-1 assume !(0 == ~E_8~0); 237576#L1119-1 assume !(0 == ~E_9~0); 237648#L1124-1 assume !(0 == ~E_10~0); 237053#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 237054#L502 assume !(1 == ~m_pc~0); 237246#L502-2 is_master_triggered_~__retres1~0#1 := 0; 237178#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 237179#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 238010#L1273 assume !(0 != activate_threads_~tmp~1#1); 238011#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 238386#L521 assume !(1 == ~t1_pc~0); 238304#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 237103#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 237069#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 237070#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 237089#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 237090#L540 assume !(1 == ~t2_pc~0); 237911#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 237912#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 237571#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 237572#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 238298#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 237382#L559 assume !(1 == ~t3_pc~0); 237383#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 237668#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 237008#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 237009#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 237196#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 237197#L578 assume !(1 == ~t4_pc~0); 237316#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 237315#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 237135#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 237136#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 237991#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 237992#L597 assume 1 == ~t5_pc~0; 238405#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 237123#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 237124#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 238218#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 237939#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 237940#L616 assume !(1 == ~t6_pc~0); 237955#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 237954#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 237547#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 237548#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 237788#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 237789#L635 assume 1 == ~t7_pc~0; 237996#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 237092#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 237471#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 238268#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 237932#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 237933#L654 assume !(1 == ~t8_pc~0); 237739#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 237740#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 238138#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 238139#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 238181#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 237347#L673 assume 1 == ~t9_pc~0; 237348#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 237044#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 237631#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 237632#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 238092#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 238093#L692 assume !(1 == ~t10_pc~0); 238030#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 238029#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 237791#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 237792#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 237803#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 238159#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 237258#L1142-2 assume !(1 == ~T1_E~0); 237259#L1147-1 assume !(1 == ~T2_E~0); 238437#L1152-1 assume !(1 == ~T3_E~0); 238438#L1157-1 assume !(1 == ~T4_E~0); 238229#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 238230#L1167-1 assume !(1 == ~T6_E~0); 238289#L1172-1 assume !(1 == ~T7_E~0); 238290#L1177-1 assume !(1 == ~T8_E~0); 237979#L1182-1 assume !(1 == ~T9_E~0); 237980#L1187-1 assume !(1 == ~T10_E~0); 238135#L1192-1 assume !(1 == ~E_M~0); 237519#L1197-1 assume !(1 == ~E_1~0); 237520#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 237915#L1207-1 assume !(1 == ~E_3~0); 237916#L1212-1 assume !(1 == ~E_4~0); 237108#L1217-1 assume !(1 == ~E_5~0); 237109#L1222-1 assume !(1 == ~E_6~0); 237887#L1227-1 assume !(1 == ~E_7~0); 237888#L1232-1 assume !(1 == ~E_8~0); 237976#L1237-1 assume !(1 == ~E_9~0); 293575#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 292405#L1247-1 assume { :end_inline_reset_delta_events } true; 292403#L1553-2 [2022-12-13 12:31:00,471 INFO L750 eck$LassoCheckResult]: Loop: 292403#L1553-2 assume !false; 292401#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 292287#L999 assume !false; 292283#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 290574#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 290561#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 290559#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 290556#L854 assume !(0 != eval_~tmp~0#1); 290557#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 294063#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 294061#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 294059#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 294057#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 294054#L1034-3 assume !(0 == ~T3_E~0); 294052#L1039-3 assume !(0 == ~T4_E~0); 294050#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 294048#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 294046#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 294044#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 294041#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 294039#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 294037#L1074-3 assume !(0 == ~E_M~0); 294035#L1079-3 assume !(0 == ~E_1~0); 294033#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 294031#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 294030#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 294029#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 294026#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 294024#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 294022#L1114-3 assume !(0 == ~E_8~0); 294020#L1119-3 assume !(0 == ~E_9~0); 294018#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 294016#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 294013#L502-36 assume !(1 == ~m_pc~0); 294011#L502-38 is_master_triggered_~__retres1~0#1 := 0; 294009#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 294007#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 294005#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 293900#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 293899#L521-36 assume 1 == ~t1_pc~0; 293897#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 293896#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 293895#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 293893#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 293891#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 293889#L540-36 assume !(1 == ~t2_pc~0); 291332#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 293886#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293884#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 293882#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 293880#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 293878#L559-36 assume !(1 == ~t3_pc~0); 250172#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 293875#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 293873#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 293871#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 293869#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 292615#L578-36 assume !(1 == ~t4_pc~0); 292609#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 292607#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 292605#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 292603#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 292601#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 292599#L597-36 assume 1 == ~t5_pc~0; 292585#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 292582#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 292580#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 292578#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 292576#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 292574#L616-36 assume 1 == ~t6_pc~0; 292569#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 292553#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 292550#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 292548#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 292546#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 292544#L635-36 assume !(1 == ~t7_pc~0); 292540#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 292537#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 292535#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 292533#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 292531#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 292529#L654-36 assume 1 == ~t8_pc~0; 292525#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 292523#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 292521#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 292519#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 292517#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 292515#L673-36 assume 1 == ~t9_pc~0; 292512#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 292509#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 292507#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 292505#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 292503#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 292501#L692-36 assume 1 == ~t10_pc~0; 292497#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 292495#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 292493#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 292491#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 292489#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 292487#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 237941#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 292484#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 292483#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 292481#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 292479#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 292477#L1167-3 assume !(1 == ~T6_E~0); 292475#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 292473#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 292471#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 292469#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 292467#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 286370#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 292465#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 292463#L1207-3 assume !(1 == ~E_3~0); 292461#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 292459#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 292457#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 292455#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 292454#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 292451#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 292450#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 292449#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 292436#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 292435#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 292434#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 292433#L1572 assume !(0 == start_simulation_~tmp~3#1); 237524#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 292427#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 292416#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 292414#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 292412#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 292410#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 292408#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 292406#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 292403#L1553-2 [2022-12-13 12:31:00,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:00,472 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2022-12-13 12:31:00,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:00,472 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898460211] [2022-12-13 12:31:00,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:00,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:00,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:00,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:00,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:00,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1898460211] [2022-12-13 12:31:00,530 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1898460211] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:00,531 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:00,531 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:31:00,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1975945436] [2022-12-13 12:31:00,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:00,531 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:31:00,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:00,532 INFO L85 PathProgramCache]: Analyzing trace with hash 1958672124, now seen corresponding path program 1 times [2022-12-13 12:31:00,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:00,532 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221585756] [2022-12-13 12:31:00,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:00,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:00,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:00,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:00,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:00,584 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221585756] [2022-12-13 12:31:00,585 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221585756] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:00,585 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:00,585 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:00,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785252079] [2022-12-13 12:31:00,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:00,586 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:00,586 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:00,586 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:31:00,586 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:31:00,586 INFO L87 Difference]: Start difference. First operand 59020 states and 85466 transitions. cyclomatic complexity: 26462 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:01,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:01,289 INFO L93 Difference]: Finished difference Result 154975 states and 224919 transitions. [2022-12-13 12:31:01,289 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154975 states and 224919 transitions. [2022-12-13 12:31:01,701 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 154392 [2022-12-13 12:31:02,013 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154975 states to 154975 states and 224919 transitions. [2022-12-13 12:31:02,014 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 154975 [2022-12-13 12:31:02,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 154975 [2022-12-13 12:31:02,066 INFO L73 IsDeterministic]: Start isDeterministic. Operand 154975 states and 224919 transitions. [2022-12-13 12:31:02,145 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:31:02,145 INFO L218 hiAutomatonCegarLoop]: Abstraction has 154975 states and 224919 transitions. [2022-12-13 12:31:02,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154975 states and 224919 transitions. [2022-12-13 12:31:02,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154975 to 60871. [2022-12-13 12:31:02,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60871 states, 60871 states have (on average 1.4344597591628196) internal successors, (87317), 60870 states have internal predecessors, (87317), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:02,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60871 states to 60871 states and 87317 transitions. [2022-12-13 12:31:02,988 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60871 states and 87317 transitions. [2022-12-13 12:31:02,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 12:31:02,989 INFO L428 stractBuchiCegarLoop]: Abstraction has 60871 states and 87317 transitions. [2022-12-13 12:31:02,989 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 12:31:02,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60871 states and 87317 transitions. [2022-12-13 12:31:03,166 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 60628 [2022-12-13 12:31:03,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:03,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:03,168 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:03,168 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:03,168 INFO L748 eck$LassoCheckResult]: Stem: 451360#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 451361#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 452376#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 452377#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 451986#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 451646#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 451647#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 451951#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 452151#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 451827#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 451828#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 451703#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 451704#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 452091#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 452045#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 451961#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 451962#L1024 assume !(0 == ~M_E~0); 452267#L1024-2 assume !(0 == ~T1_E~0); 451356#L1029-1 assume !(0 == ~T2_E~0); 451357#L1034-1 assume !(0 == ~T3_E~0); 451465#L1039-1 assume !(0 == ~T4_E~0); 452409#L1044-1 assume !(0 == ~T5_E~0); 451725#L1049-1 assume !(0 == ~T6_E~0); 451726#L1054-1 assume !(0 == ~T7_E~0); 451985#L1059-1 assume !(0 == ~T8_E~0); 451412#L1064-1 assume !(0 == ~T9_E~0); 451413#L1069-1 assume !(0 == ~T10_E~0); 452231#L1074-1 assume !(0 == ~E_M~0); 452297#L1079-1 assume !(0 == ~E_1~0); 452269#L1084-1 assume !(0 == ~E_2~0); 452270#L1089-1 assume !(0 == ~E_3~0); 452325#L1094-1 assume !(0 == ~E_4~0); 451818#L1099-1 assume !(0 == ~E_5~0); 451819#L1104-1 assume !(0 == ~E_6~0); 452113#L1109-1 assume !(0 == ~E_7~0); 451583#L1114-1 assume !(0 == ~E_8~0); 451584#L1119-1 assume !(0 == ~E_9~0); 451658#L1124-1 assume !(0 == ~E_10~0); 451061#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 451062#L502 assume !(1 == ~m_pc~0); 451254#L502-2 is_master_triggered_~__retres1~0#1 := 0; 451187#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 451188#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 452039#L1273 assume !(0 != activate_threads_~tmp~1#1); 452040#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 452465#L521 assume !(1 == ~t1_pc~0); 452360#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 451112#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 451077#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 451078#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 451098#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 451099#L540 assume !(1 == ~t2_pc~0); 451937#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 451938#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 451579#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 451580#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 452353#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 451391#L559 assume !(1 == ~t3_pc~0); 451392#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 451679#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 451016#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 451017#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 451205#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 451206#L578 assume !(1 == ~t4_pc~0); 451323#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 452237#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 452264#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 452446#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 452019#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 452020#L597 assume 1 == ~t5_pc~0; 452483#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 451132#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 451133#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 452265#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 451963#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 451964#L616 assume !(1 == ~t6_pc~0); 451980#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 451979#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 451555#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 451556#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 451806#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 451807#L635 assume 1 == ~t7_pc~0; 452024#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 451101#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 451480#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 452320#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 451956#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 451957#L654 assume !(1 == ~t8_pc~0); 451755#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 451756#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 452182#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 452183#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 452229#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 451354#L673 assume 1 == ~t9_pc~0; 451355#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 451052#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 451640#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 451641#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 452126#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 452127#L692 assume !(1 == ~t10_pc~0); 452059#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 452058#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 451809#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 451810#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 451822#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 452204#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 451264#L1142-2 assume !(1 == ~T1_E~0); 451265#L1147-1 assume !(1 == ~T2_E~0); 452189#L1152-1 assume !(1 == ~T3_E~0); 451687#L1157-1 assume !(1 == ~T4_E~0); 451688#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 451848#L1167-1 assume !(1 == ~T6_E~0); 451849#L1172-1 assume !(1 == ~T7_E~0); 452343#L1177-1 assume !(1 == ~T8_E~0); 452006#L1182-1 assume !(1 == ~T9_E~0); 452007#L1187-1 assume !(1 == ~T10_E~0); 452119#L1192-1 assume !(1 == ~E_M~0); 452175#L1197-1 assume !(1 == ~E_1~0); 497277#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 497275#L1207-1 assume !(1 == ~E_3~0); 497273#L1212-1 assume !(1 == ~E_4~0); 497272#L1217-1 assume !(1 == ~E_5~0); 497268#L1222-1 assume !(1 == ~E_6~0); 497266#L1227-1 assume !(1 == ~E_7~0); 497264#L1232-1 assume !(1 == ~E_8~0); 490267#L1237-1 assume !(1 == ~E_9~0); 497259#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 496970#L1247-1 assume { :end_inline_reset_delta_events } true; 496967#L1553-2 [2022-12-13 12:31:03,169 INFO L750 eck$LassoCheckResult]: Loop: 496967#L1553-2 assume !false; 496965#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 496959#L999 assume !false; 496957#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 496955#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 496944#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 496925#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 496917#L854 assume !(0 != eval_~tmp~0#1); 452198#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 451831#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 451832#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 452396#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 451803#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 451769#L1034-3 assume !(0 == ~T3_E~0); 451770#L1039-3 assume !(0 == ~T4_E~0); 452156#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 451350#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 451351#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 451113#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 451114#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 511833#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 511831#L1074-3 assume !(0 == ~E_M~0); 511829#L1079-3 assume !(0 == ~E_1~0); 511827#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 451868#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 451869#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 451788#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 451789#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 452154#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 452133#L1114-3 assume !(0 == ~E_8~0); 452134#L1119-3 assume !(0 == ~E_9~0); 452491#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 452543#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 510118#L502-36 assume !(1 == ~m_pc~0); 510116#L502-38 is_master_triggered_~__retres1~0#1 := 0; 510114#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 510113#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 510112#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 510110#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 510108#L521-36 assume !(1 == ~t1_pc~0); 510055#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 510052#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 510050#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 510047#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 510045#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 504095#L540-36 assume !(1 == ~t2_pc~0); 504094#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 504093#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 504092#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 504091#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 504090#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 497193#L559-36 assume !(1 == ~t3_pc~0); 497192#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 497191#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 497190#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 497189#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 497188#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 497187#L578-36 assume !(1 == ~t4_pc~0); 497186#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 497184#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 497182#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 497180#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 497177#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 497175#L597-36 assume !(1 == ~t5_pc~0); 497173#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 497170#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 497167#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 497165#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 497163#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 497161#L616-36 assume !(1 == ~t6_pc~0); 497159#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 497156#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 497153#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 497151#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 497149#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 497147#L635-36 assume !(1 == ~t7_pc~0); 497145#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 497142#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 497139#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 497137#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 497135#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 497133#L654-36 assume !(1 == ~t8_pc~0); 497131#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 497128#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 497125#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 497123#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 497121#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 497119#L673-36 assume 1 == ~t9_pc~0; 497117#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 497114#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 497112#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 497110#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 497108#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 497106#L692-36 assume !(1 == ~t10_pc~0); 497104#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 497101#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 497099#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 497097#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 497095#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 497093#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 452806#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 497090#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 497088#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 452798#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 497085#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 497083#L1167-3 assume !(1 == ~T6_E~0); 497081#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 497079#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 497077#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 497075#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 497073#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 490750#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 497072#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 497071#L1207-3 assume !(1 == ~E_3~0); 497070#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 497067#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 497065#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 497044#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 497042#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 490307#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 497038#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 497036#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 497010#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 497008#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 497006#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 497004#L1572 assume !(0 == start_simulation_~tmp~3#1); 497000#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 496993#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 496981#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 496979#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 496977#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 496975#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 496973#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 496971#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 496967#L1553-2 [2022-12-13 12:31:03,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:03,169 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2022-12-13 12:31:03,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:03,170 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969717235] [2022-12-13 12:31:03,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:03,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:03,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:03,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:03,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:03,218 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969717235] [2022-12-13 12:31:03,218 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969717235] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:03,218 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:03,218 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:31:03,218 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [188501117] [2022-12-13 12:31:03,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:03,219 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:31:03,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:03,220 INFO L85 PathProgramCache]: Analyzing trace with hash 1878888771, now seen corresponding path program 1 times [2022-12-13 12:31:03,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:03,220 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [548006474] [2022-12-13 12:31:03,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:03,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:03,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:03,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:03,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:03,262 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [548006474] [2022-12-13 12:31:03,263 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [548006474] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:03,263 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:03,263 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:03,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1735525949] [2022-12-13 12:31:03,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:03,263 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:03,263 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:03,263 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:31:03,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:31:03,264 INFO L87 Difference]: Start difference. First operand 60871 states and 87317 transitions. cyclomatic complexity: 26462 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:03,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:03,752 INFO L93 Difference]: Finished difference Result 115762 states and 165430 transitions. [2022-12-13 12:31:03,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115762 states and 165430 transitions. [2022-12-13 12:31:04,085 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 115360 [2022-12-13 12:31:04,385 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115762 states to 115762 states and 165430 transitions. [2022-12-13 12:31:04,385 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115762 [2022-12-13 12:31:04,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115762 [2022-12-13 12:31:04,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115762 states and 165430 transitions. [2022-12-13 12:31:04,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:31:04,457 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115762 states and 165430 transitions. [2022-12-13 12:31:04,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115762 states and 165430 transitions. [2022-12-13 12:31:05,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115762 to 115634. [2022-12-13 12:31:05,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115634 states, 115634 states have (on average 1.4295276475777021) internal successors, (165302), 115633 states have internal predecessors, (165302), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:05,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115634 states to 115634 states and 165302 transitions. [2022-12-13 12:31:05,342 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115634 states and 165302 transitions. [2022-12-13 12:31:05,343 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:31:05,343 INFO L428 stractBuchiCegarLoop]: Abstraction has 115634 states and 165302 transitions. [2022-12-13 12:31:05,343 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 12:31:05,343 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115634 states and 165302 transitions. [2022-12-13 12:31:05,610 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 115232 [2022-12-13 12:31:05,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:05,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:05,612 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:05,613 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:05,613 INFO L748 eck$LassoCheckResult]: Stem: 628004#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 628005#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 629006#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 629007#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 628627#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 628285#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 628286#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 628595#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 628782#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 628468#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 628469#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 628343#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 628344#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 628728#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 628685#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 628602#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 628603#L1024 assume !(0 == ~M_E~0); 628900#L1024-2 assume !(0 == ~T1_E~0); 627998#L1029-1 assume !(0 == ~T2_E~0); 627999#L1034-1 assume !(0 == ~T3_E~0); 628103#L1039-1 assume !(0 == ~T4_E~0); 629039#L1044-1 assume !(0 == ~T5_E~0); 628364#L1049-1 assume !(0 == ~T6_E~0); 628365#L1054-1 assume !(0 == ~T7_E~0); 628626#L1059-1 assume !(0 == ~T8_E~0); 628051#L1064-1 assume !(0 == ~T9_E~0); 628052#L1069-1 assume !(0 == ~T10_E~0); 628863#L1074-1 assume !(0 == ~E_M~0); 628935#L1079-1 assume !(0 == ~E_1~0); 628902#L1084-1 assume !(0 == ~E_2~0); 628903#L1089-1 assume !(0 == ~E_3~0); 628960#L1094-1 assume !(0 == ~E_4~0); 628458#L1099-1 assume !(0 == ~E_5~0); 628459#L1104-1 assume !(0 == ~E_6~0); 628750#L1109-1 assume !(0 == ~E_7~0); 628223#L1114-1 assume !(0 == ~E_8~0); 628224#L1119-1 assume !(0 == ~E_9~0); 628300#L1124-1 assume !(0 == ~E_10~0); 627701#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 627702#L502 assume !(1 == ~m_pc~0); 627896#L502-2 is_master_triggered_~__retres1~0#1 := 0; 627828#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 627829#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 628681#L1273 assume !(0 != activate_threads_~tmp~1#1); 628682#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 629096#L521 assume !(1 == ~t1_pc~0); 628992#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 627753#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 627717#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 627718#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 627737#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 627738#L540 assume !(1 == ~t2_pc~0); 628577#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 628578#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 628221#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 628222#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 628986#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 628030#L559 assume !(1 == ~t3_pc~0); 628031#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 628316#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 627656#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 627657#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 627844#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 627845#L578 assume !(1 == ~t4_pc~0); 627970#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 628869#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 627784#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 627785#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 628662#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 628663#L597 assume !(1 == ~t5_pc~0); 628611#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 627771#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 627772#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 628898#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 628604#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 628605#L616 assume !(1 == ~t6_pc~0); 628623#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 628622#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 628195#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 628196#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 628447#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 628448#L635 assume 1 == ~t7_pc~0; 628665#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 627740#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 628121#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 628955#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 628597#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 628598#L654 assume !(1 == ~t8_pc~0); 628392#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 628393#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 628817#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 628818#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 628860#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 627996#L673 assume 1 == ~t9_pc~0; 627997#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 627694#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 628280#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 628281#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 628762#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 628763#L692 assume !(1 == ~t10_pc~0); 628701#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 628700#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 628449#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 628450#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 628462#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 628837#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 627906#L1142-2 assume !(1 == ~T1_E~0); 627907#L1147-1 assume !(1 == ~T2_E~0); 628823#L1152-1 assume !(1 == ~T3_E~0); 628323#L1157-1 assume !(1 == ~T4_E~0); 628324#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 628487#L1167-1 assume !(1 == ~T6_E~0); 628488#L1172-1 assume !(1 == ~T7_E~0); 628978#L1177-1 assume !(1 == ~T8_E~0); 628647#L1182-1 assume !(1 == ~T9_E~0); 628648#L1187-1 assume !(1 == ~T10_E~0); 628755#L1192-1 assume !(1 == ~E_M~0); 628172#L1197-1 assume !(1 == ~E_1~0); 628173#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 628582#L1207-1 assume !(1 == ~E_3~0); 628555#L1212-1 assume !(1 == ~E_4~0); 627756#L1217-1 assume !(1 == ~E_5~0); 627757#L1222-1 assume !(1 == ~E_6~0); 628552#L1227-1 assume !(1 == ~E_7~0); 628553#L1232-1 assume !(1 == ~E_8~0); 628642#L1237-1 assume !(1 == ~E_9~0); 674512#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 672416#L1247-1 assume { :end_inline_reset_delta_events } true; 672414#L1553-2 [2022-12-13 12:31:05,613 INFO L750 eck$LassoCheckResult]: Loop: 672414#L1553-2 assume !false; 672412#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 672406#L999 assume !false; 672404#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 672402#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 672390#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 672388#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 672385#L854 assume !(0 != eval_~tmp~0#1); 672386#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 684061#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 684056#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 684050#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 684045#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 684037#L1034-3 assume !(0 == ~T3_E~0); 684032#L1039-3 assume !(0 == ~T4_E~0); 684027#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 684023#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 684018#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 684013#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 684005#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 684000#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 683996#L1074-3 assume !(0 == ~E_M~0); 683992#L1079-3 assume !(0 == ~E_1~0); 683987#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 683981#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 683976#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 683971#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 683964#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 683961#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 683958#L1114-3 assume !(0 == ~E_8~0); 683955#L1119-3 assume !(0 == ~E_9~0); 683952#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 683949#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 683946#L502-36 assume !(1 == ~m_pc~0); 683065#L502-38 is_master_triggered_~__retres1~0#1 := 0; 683064#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 683063#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 683062#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 683061#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 683060#L521-36 assume !(1 == ~t1_pc~0); 683058#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 683055#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 683053#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 683051#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 683049#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 683047#L540-36 assume !(1 == ~t2_pc~0); 675588#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 683043#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 683041#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 683039#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 680597#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 672626#L559-36 assume !(1 == ~t3_pc~0); 672625#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 672624#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 672623#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 672622#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 672621#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 672620#L578-36 assume 1 == ~t4_pc~0; 672618#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 672617#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 672616#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 672613#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 672611#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 672609#L597-36 assume !(1 == ~t5_pc~0); 672607#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 672605#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 672602#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 672600#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 672598#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 672596#L616-36 assume !(1 == ~t6_pc~0); 672594#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 672591#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 672588#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 672586#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 672584#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 672582#L635-36 assume 1 == ~t7_pc~0; 672579#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 672577#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 672574#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 672572#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 672570#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 672568#L654-36 assume !(1 == ~t8_pc~0); 672566#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 672563#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 672560#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 672558#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 672556#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 672554#L673-36 assume 1 == ~t9_pc~0; 672552#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 672549#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 672546#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 672544#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 672542#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 672540#L692-36 assume !(1 == ~t10_pc~0); 672538#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 672535#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 672533#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 672531#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 672529#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 672527#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 652416#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 672522#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 672520#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 672516#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 672514#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 672512#L1167-3 assume !(1 == ~T6_E~0); 672510#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 672508#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 672506#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 672504#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 672502#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 672498#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 672496#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 672494#L1207-3 assume !(1 == ~E_3~0); 672492#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 672490#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 672488#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 672487#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 672486#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 657533#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 672484#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 672481#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 672458#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 672456#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 672454#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 672452#L1572 assume !(0 == start_simulation_~tmp~3#1); 672449#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 672441#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 672430#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 672426#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 672424#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 672422#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 672420#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 672417#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 672414#L1553-2 [2022-12-13 12:31:05,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:05,614 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2022-12-13 12:31:05,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:05,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1559656704] [2022-12-13 12:31:05,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:05,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:05,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:05,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:05,667 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:05,667 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1559656704] [2022-12-13 12:31:05,667 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1559656704] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:05,667 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:05,668 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:05,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1840788837] [2022-12-13 12:31:05,668 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:05,668 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:31:05,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:05,668 INFO L85 PathProgramCache]: Analyzing trace with hash -1926358657, now seen corresponding path program 1 times [2022-12-13 12:31:05,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:05,669 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169240823] [2022-12-13 12:31:05,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:05,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:05,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:05,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:05,702 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:05,702 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1169240823] [2022-12-13 12:31:05,702 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1169240823] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:05,702 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:05,702 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:05,702 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1004664285] [2022-12-13 12:31:05,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:05,703 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:05,703 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:05,703 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:31:05,703 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:31:05,703 INFO L87 Difference]: Start difference. First operand 115634 states and 165302 transitions. cyclomatic complexity: 49700 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:06,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:06,782 INFO L93 Difference]: Finished difference Result 282901 states and 401407 transitions. [2022-12-13 12:31:06,782 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 282901 states and 401407 transitions. [2022-12-13 12:31:07,896 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 276836 [2022-12-13 12:31:08,327 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 282901 states to 282901 states and 401407 transitions. [2022-12-13 12:31:08,327 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 282901 [2022-12-13 12:31:08,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 282901 [2022-12-13 12:31:08,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 282901 states and 401407 transitions. [2022-12-13 12:31:08,525 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:31:08,525 INFO L218 hiAutomatonCegarLoop]: Abstraction has 282901 states and 401407 transitions. [2022-12-13 12:31:08,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282901 states and 401407 transitions. [2022-12-13 12:31:10,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282901 to 224449. [2022-12-13 12:31:10,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224449 states, 224449 states have (on average 1.4233032893886808) internal successors, (319459), 224448 states have internal predecessors, (319459), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:11,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224449 states to 224449 states and 319459 transitions. [2022-12-13 12:31:11,069 INFO L240 hiAutomatonCegarLoop]: Abstraction has 224449 states and 319459 transitions. [2022-12-13 12:31:11,080 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:31:11,080 INFO L428 stractBuchiCegarLoop]: Abstraction has 224449 states and 319459 transitions. [2022-12-13 12:31:11,080 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 12:31:11,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 224449 states and 319459 transitions. [2022-12-13 12:31:11,511 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 223856 [2022-12-13 12:31:11,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:11,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:11,513 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:11,513 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:11,513 INFO L748 eck$LassoCheckResult]: Stem: 1026548#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1026549#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1027606#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1027607#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1027189#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 1026840#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1026841#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1027151#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1027357#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1027022#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1027023#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1026895#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1026896#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1027294#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1027252#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1027162#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1027163#L1024 assume !(0 == ~M_E~0); 1027484#L1024-2 assume !(0 == ~T1_E~0); 1026544#L1029-1 assume !(0 == ~T2_E~0); 1026545#L1034-1 assume !(0 == ~T3_E~0); 1026653#L1039-1 assume !(0 == ~T4_E~0); 1027640#L1044-1 assume !(0 == ~T5_E~0); 1026916#L1049-1 assume !(0 == ~T6_E~0); 1026917#L1054-1 assume !(0 == ~T7_E~0); 1027188#L1059-1 assume !(0 == ~T8_E~0); 1026599#L1064-1 assume !(0 == ~T9_E~0); 1026600#L1069-1 assume !(0 == ~T10_E~0); 1027449#L1074-1 assume !(0 == ~E_M~0); 1027522#L1079-1 assume !(0 == ~E_1~0); 1027486#L1084-1 assume !(0 == ~E_2~0); 1027487#L1089-1 assume !(0 == ~E_3~0); 1027550#L1094-1 assume !(0 == ~E_4~0); 1027012#L1099-1 assume !(0 == ~E_5~0); 1027013#L1104-1 assume !(0 == ~E_6~0); 1027317#L1109-1 assume !(0 == ~E_7~0); 1026776#L1114-1 assume !(0 == ~E_8~0); 1026777#L1119-1 assume !(0 == ~E_9~0); 1026851#L1124-1 assume !(0 == ~E_10~0); 1026246#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1026247#L502 assume !(1 == ~m_pc~0); 1026439#L502-2 is_master_triggered_~__retres1~0#1 := 0; 1026373#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1026374#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1027246#L1273 assume !(0 != activate_threads_~tmp~1#1); 1027247#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1027724#L521 assume !(1 == ~t1_pc~0); 1027592#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1026296#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1026262#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1026263#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 1026282#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1026283#L540 assume !(1 == ~t2_pc~0); 1027134#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1027135#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1026772#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1026773#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 1027587#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1026576#L559 assume !(1 == ~t3_pc~0); 1026577#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1026872#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1026201#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1026202#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 1026391#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1026392#L578 assume !(1 == ~t4_pc~0); 1026509#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1027455#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1026329#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1026330#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 1027226#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1027227#L597 assume !(1 == ~t5_pc~0); 1027173#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1026317#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1026318#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1027482#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 1027164#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1027165#L616 assume !(1 == ~t6_pc~0); 1027183#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1027182#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1026742#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1026743#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 1027001#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1027002#L635 assume !(1 == ~t7_pc~0); 1026284#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1026285#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1026670#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1027545#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 1027157#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1027158#L654 assume !(1 == ~t8_pc~0); 1026947#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1026948#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1027397#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1027398#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 1027447#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1026542#L673 assume 1 == ~t9_pc~0; 1026543#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1026237#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1026834#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1026835#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 1027332#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1027333#L692 assume !(1 == ~t10_pc~0); 1027266#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1027265#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1027004#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1027005#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 1027016#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1027420#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 1026451#L1142-2 assume !(1 == ~T1_E~0); 1026452#L1147-1 assume !(1 == ~T2_E~0); 1027819#L1152-1 assume !(1 == ~T3_E~0); 1027820#L1157-1 assume !(1 == ~T4_E~0); 1027494#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1027495#L1167-1 assume !(1 == ~T6_E~0); 1027572#L1172-1 assume !(1 == ~T7_E~0); 1027573#L1177-1 assume !(1 == ~T8_E~0); 1027210#L1182-1 assume !(1 == ~T9_E~0); 1027211#L1187-1 assume !(1 == ~T10_E~0); 1027392#L1192-1 assume !(1 == ~E_M~0); 1027393#L1197-1 assume !(1 == ~E_1~0); 1118126#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1118125#L1207-1 assume !(1 == ~E_3~0); 1118124#L1212-1 assume !(1 == ~E_4~0); 1118123#L1217-1 assume !(1 == ~E_5~0); 1118122#L1222-1 assume !(1 == ~E_6~0); 1118121#L1227-1 assume !(1 == ~E_7~0); 1118120#L1232-1 assume !(1 == ~E_8~0); 1027206#L1237-1 assume !(1 == ~E_9~0); 1118119#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1118117#L1247-1 assume { :end_inline_reset_delta_events } true; 1118114#L1553-2 [2022-12-13 12:31:11,513 INFO L750 eck$LassoCheckResult]: Loop: 1118114#L1553-2 assume !false; 1118112#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1118106#L999 assume !false; 1118104#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1118102#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1118090#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1118089#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1118086#L854 assume !(0 != eval_~tmp~0#1); 1118087#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1133831#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1133827#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1133823#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1133819#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1133815#L1034-3 assume !(0 == ~T3_E~0); 1133811#L1039-3 assume !(0 == ~T4_E~0); 1133807#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1133803#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1133796#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1133792#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1133788#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1133784#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1133777#L1074-3 assume !(0 == ~E_M~0); 1133775#L1079-3 assume !(0 == ~E_1~0); 1133772#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1133770#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1133768#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1133766#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1133764#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1133763#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1133762#L1114-3 assume !(0 == ~E_8~0); 1133760#L1119-3 assume !(0 == ~E_9~0); 1133758#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1133756#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1133754#L502-36 assume !(1 == ~m_pc~0); 1133752#L502-38 is_master_triggered_~__retres1~0#1 := 0; 1133750#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1133748#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1133745#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1133743#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1133741#L521-36 assume !(1 == ~t1_pc~0); 1133739#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1133736#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1133735#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1133734#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1133732#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1133730#L540-36 assume !(1 == ~t2_pc~0); 1133435#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1133727#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1133725#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1133723#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1133721#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1118364#L559-36 assume !(1 == ~t3_pc~0); 1118362#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1118360#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1118358#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1118356#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1118354#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1118352#L578-36 assume !(1 == ~t4_pc~0); 1118348#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1118346#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1118343#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1118341#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 1118338#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1118336#L597-36 assume !(1 == ~t5_pc~0); 1118334#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1118332#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1118331#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1118329#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 1118327#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1118325#L616-36 assume !(1 == ~t6_pc~0); 1118323#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1118320#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1118319#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1118317#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1118315#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1118313#L635-36 assume !(1 == ~t7_pc~0); 1080542#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1118308#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1118306#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1118304#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1118302#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1118299#L654-36 assume !(1 == ~t8_pc~0); 1118297#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1118294#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1118292#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1118290#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1118288#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1118286#L673-36 assume !(1 == ~t9_pc~0); 1118283#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1118281#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1118278#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1118276#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1118274#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1118272#L692-36 assume 1 == ~t10_pc~0; 1118269#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1118267#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1118266#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1118264#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1118262#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1118260#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1093781#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1118255#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1118252#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1118248#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1118246#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1118244#L1167-3 assume !(1 == ~T6_E~0); 1118242#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1118240#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1118237#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1118235#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1118233#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1118201#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1118230#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1118228#L1207-3 assume !(1 == ~E_3~0); 1118225#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1118223#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1118221#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1118219#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1118217#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1118213#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1118211#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1118209#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1118187#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1118185#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1118183#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1118181#L1572 assume !(0 == start_simulation_~tmp~3#1); 1118178#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1118146#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1118135#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1118133#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1118131#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1118129#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1118127#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1118118#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 1118114#L1553-2 [2022-12-13 12:31:11,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:11,514 INFO L85 PathProgramCache]: Analyzing trace with hash 1730432140, now seen corresponding path program 1 times [2022-12-13 12:31:11,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:11,514 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680264144] [2022-12-13 12:31:11,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:11,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:11,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:11,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:11,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:11,556 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1680264144] [2022-12-13 12:31:11,556 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1680264144] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:11,556 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:11,556 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:11,556 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [772785209] [2022-12-13 12:31:11,556 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:11,557 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:31:11,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:11,557 INFO L85 PathProgramCache]: Analyzing trace with hash 470621315, now seen corresponding path program 1 times [2022-12-13 12:31:11,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:11,557 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316846867] [2022-12-13 12:31:11,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:11,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:11,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:11,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:11,583 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:11,583 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1316846867] [2022-12-13 12:31:11,583 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1316846867] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:11,584 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:11,584 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:11,584 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024815791] [2022-12-13 12:31:11,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:11,584 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:11,584 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:11,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:31:11,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:31:11,585 INFO L87 Difference]: Start difference. First operand 224449 states and 319459 transitions. cyclomatic complexity: 95042 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:13,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:13,200 INFO L93 Difference]: Finished difference Result 534336 states and 755904 transitions. [2022-12-13 12:31:13,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 534336 states and 755904 transitions. [2022-12-13 12:31:15,284 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 522480 [2022-12-13 12:31:16,352 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 534336 states to 534336 states and 755904 transitions. [2022-12-13 12:31:16,352 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 534336 [2022-12-13 12:31:16,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 534336 [2022-12-13 12:31:16,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 534336 states and 755904 transitions. [2022-12-13 12:31:16,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:31:16,706 INFO L218 hiAutomatonCegarLoop]: Abstraction has 534336 states and 755904 transitions. [2022-12-13 12:31:16,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 534336 states and 755904 transitions. [2022-12-13 12:31:20,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 534336 to 425552. [2022-12-13 12:31:20,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425552 states, 425552 states have (on average 1.4192954092566832) internal successors, (603984), 425551 states have internal predecessors, (603984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:21,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425552 states to 425552 states and 603984 transitions. [2022-12-13 12:31:21,178 INFO L240 hiAutomatonCegarLoop]: Abstraction has 425552 states and 603984 transitions. [2022-12-13 12:31:21,179 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:31:21,179 INFO L428 stractBuchiCegarLoop]: Abstraction has 425552 states and 603984 transitions. [2022-12-13 12:31:21,180 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 12:31:21,180 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425552 states and 603984 transitions. [2022-12-13 12:31:22,339 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 424576 [2022-12-13 12:31:22,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:22,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:22,342 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:22,342 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:22,342 INFO L748 eck$LassoCheckResult]: Stem: 1785342#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1785343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1786393#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1786394#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1785982#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 1785626#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1785627#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1785944#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1786144#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1785811#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1785812#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1785682#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1785683#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1786086#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1786040#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1785952#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1785953#L1024 assume !(0 == ~M_E~0); 1786276#L1024-2 assume !(0 == ~T1_E~0); 1785338#L1029-1 assume !(0 == ~T2_E~0); 1785339#L1034-1 assume !(0 == ~T3_E~0); 1785441#L1039-1 assume !(0 == ~T4_E~0); 1786425#L1044-1 assume !(0 == ~T5_E~0); 1785704#L1049-1 assume !(0 == ~T6_E~0); 1785705#L1054-1 assume !(0 == ~T7_E~0); 1785981#L1059-1 assume !(0 == ~T8_E~0); 1785390#L1064-1 assume !(0 == ~T9_E~0); 1785391#L1069-1 assume !(0 == ~T10_E~0); 1786235#L1074-1 assume !(0 == ~E_M~0); 1786317#L1079-1 assume !(0 == ~E_1~0); 1786279#L1084-1 assume !(0 == ~E_2~0); 1786280#L1089-1 assume !(0 == ~E_3~0); 1786338#L1094-1 assume !(0 == ~E_4~0); 1785802#L1099-1 assume !(0 == ~E_5~0); 1785803#L1104-1 assume !(0 == ~E_6~0); 1786108#L1109-1 assume !(0 == ~E_7~0); 1785560#L1114-1 assume !(0 == ~E_8~0); 1785561#L1119-1 assume !(0 == ~E_9~0); 1785637#L1124-1 assume !(0 == ~E_10~0); 1785040#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1785041#L502 assume !(1 == ~m_pc~0); 1785231#L502-2 is_master_triggered_~__retres1~0#1 := 0; 1785164#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1785165#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1786034#L1273 assume !(0 != activate_threads_~tmp~1#1); 1786035#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1786478#L521 assume !(1 == ~t1_pc~0); 1786378#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1785090#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1785056#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1785057#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 1785076#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1785077#L540 assume !(1 == ~t2_pc~0); 1785928#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1785929#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1785556#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1785557#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 1786370#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1785369#L559 assume !(1 == ~t3_pc~0); 1785370#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1785658#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1784995#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1784996#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 1785182#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1785183#L578 assume !(1 == ~t4_pc~0); 1785304#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1786241#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1785122#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1785123#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 1786014#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1786015#L597 assume !(1 == ~t5_pc~0); 1785966#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1785110#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1785111#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1786273#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 1785954#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1785955#L616 assume !(1 == ~t6_pc~0); 1785976#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1785975#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1785532#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1785533#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 1785790#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1785791#L635 assume !(1 == ~t7_pc~0); 1785078#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1785079#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1785459#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1786334#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 1785947#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1785948#L654 assume !(1 == ~t8_pc~0); 1785735#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1785736#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1786176#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1786177#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 1786232#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1785337#L673 assume !(1 == ~t9_pc~0); 1785030#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1785031#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1785620#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1785621#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 1786122#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1786123#L692 assume !(1 == ~t10_pc~0); 1786057#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1786056#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1785793#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1785794#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 1785806#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1786203#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 1785243#L1142-2 assume !(1 == ~T1_E~0); 1785244#L1147-1 assume !(1 == ~T2_E~0); 1786569#L1152-1 assume !(1 == ~T3_E~0); 1786570#L1157-1 assume !(1 == ~T4_E~0); 1786290#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1786291#L1167-1 assume !(1 == ~T6_E~0); 1786355#L1172-1 assume !(1 == ~T7_E~0); 1786356#L1177-1 assume !(1 == ~T8_E~0); 1786002#L1182-1 assume !(1 == ~T9_E~0); 1786003#L1187-1 assume !(1 == ~T10_E~0); 1786172#L1192-1 assume !(1 == ~E_M~0); 1785509#L1197-1 assume !(1 == ~E_1~0); 1785510#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1979997#L1207-1 assume !(1 == ~E_3~0); 1979996#L1212-1 assume !(1 == ~E_4~0); 1979995#L1217-1 assume !(1 == ~E_5~0); 1979994#L1222-1 assume !(1 == ~E_6~0); 1785900#L1227-1 assume !(1 == ~E_7~0); 1785901#L1232-1 assume !(1 == ~E_8~0); 1784973#L1237-1 assume !(1 == ~E_9~0); 1784974#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1785979#L1247-1 assume { :end_inline_reset_delta_events } true; 1785980#L1553-2 [2022-12-13 12:31:22,342 INFO L750 eck$LassoCheckResult]: Loop: 1785980#L1553-2 assume !false; 1982831#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1982818#L999 assume !false; 1982752#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1972021#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1972009#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1972008#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1972003#L854 assume !(0 != eval_~tmp~0#1); 1972004#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2078942#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2078929#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2078922#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2078914#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2078906#L1034-3 assume !(0 == ~T3_E~0); 2078898#L1039-3 assume !(0 == ~T4_E~0); 2078889#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2078882#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2078875#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2078869#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2078863#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2078857#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2078852#L1074-3 assume !(0 == ~E_M~0); 2078847#L1079-3 assume !(0 == ~E_1~0); 2078842#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2078834#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2078828#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2078822#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2078814#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2078807#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2078803#L1114-3 assume !(0 == ~E_8~0); 2078797#L1119-3 assume !(0 == ~E_9~0); 2078793#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2078774#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2078770#L502-36 assume !(1 == ~m_pc~0); 2078758#L502-38 is_master_triggered_~__retres1~0#1 := 0; 2078751#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2078742#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2078735#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2078727#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2078719#L521-36 assume !(1 == ~t1_pc~0); 2078712#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 2078705#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2077830#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2077829#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2077828#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2077827#L540-36 assume !(1 == ~t2_pc~0); 1976020#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2077825#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2077822#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2077820#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2077818#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2077816#L559-36 assume !(1 == ~t3_pc~0); 1965723#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2077813#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2077812#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2077811#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2077810#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2077809#L578-36 assume 1 == ~t4_pc~0; 2077807#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2077808#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2077806#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2077800#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2077797#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2077795#L597-36 assume !(1 == ~t5_pc~0); 2077793#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2077791#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2061224#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2061153#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 2061152#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2061151#L616-36 assume !(1 == ~t6_pc~0); 2061145#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 2061142#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2061140#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2061138#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2061136#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2061134#L635-36 assume !(1 == ~t7_pc~0); 1961424#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2061131#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2061129#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2061127#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2061125#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2061123#L654-36 assume !(1 == ~t8_pc~0); 2061121#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 2061118#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2061116#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2061115#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2061051#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2061046#L673-36 assume !(1 == ~t9_pc~0); 1874372#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 2061034#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2061028#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2060983#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2058992#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2058991#L692-36 assume !(1 == ~t10_pc~0); 2058990#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2058986#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2058983#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2058980#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2058977#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2058974#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1892098#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2058971#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2058968#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1904552#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2058963#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2058958#L1167-3 assume !(1 == ~T6_E~0); 2058957#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2058956#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2058954#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2058952#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2058949#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1959986#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2058946#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2058943#L1207-3 assume !(1 == ~E_3~0); 2058939#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2058936#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2058935#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2058933#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2058932#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1980515#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2058928#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2058926#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2057979#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2057977#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2057975#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1785969#L1572 assume !(0 == start_simulation_~tmp~3#1); 1785970#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1982856#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1982845#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1982843#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1982841#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1982839#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1982837#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1982834#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 1785980#L1553-2 [2022-12-13 12:31:22,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:22,343 INFO L85 PathProgramCache]: Analyzing trace with hash -1513086067, now seen corresponding path program 1 times [2022-12-13 12:31:22,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:22,343 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304275036] [2022-12-13 12:31:22,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:22,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:22,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:22,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:22,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:22,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304275036] [2022-12-13 12:31:22,387 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [304275036] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:22,387 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:22,387 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:31:22,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814617932] [2022-12-13 12:31:22,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:22,388 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:31:22,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:22,388 INFO L85 PathProgramCache]: Analyzing trace with hash -556164351, now seen corresponding path program 1 times [2022-12-13 12:31:22,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:22,389 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622240692] [2022-12-13 12:31:22,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:22,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:22,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:22,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:22,417 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:22,417 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [622240692] [2022-12-13 12:31:22,417 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [622240692] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:22,417 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:22,417 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:22,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [261632385] [2022-12-13 12:31:22,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:22,418 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:22,418 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:22,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:31:22,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:31:22,419 INFO L87 Difference]: Start difference. First operand 425552 states and 603984 transitions. cyclomatic complexity: 178464 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:23,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:23,993 INFO L93 Difference]: Finished difference Result 483101 states and 685545 transitions. [2022-12-13 12:31:23,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 483101 states and 685545 transitions. [2022-12-13 12:31:26,031 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 482048 [2022-12-13 12:31:26,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 483101 states to 483101 states and 685545 transitions. [2022-12-13 12:31:26,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 483101 [2022-12-13 12:31:27,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 483101 [2022-12-13 12:31:27,115 INFO L73 IsDeterministic]: Start isDeterministic. Operand 483101 states and 685545 transitions. [2022-12-13 12:31:27,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:31:27,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 483101 states and 685545 transitions. [2022-12-13 12:31:27,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 483101 states and 685545 transitions. [2022-12-13 12:31:29,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 483101 to 120328. [2022-12-13 12:31:29,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120328 states, 120328 states have (on average 1.4233594840768566) internal successors, (171270), 120327 states have internal predecessors, (171270), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:29,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120328 states to 120328 states and 171270 transitions. [2022-12-13 12:31:29,562 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120328 states and 171270 transitions. [2022-12-13 12:31:29,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:31:29,563 INFO L428 stractBuchiCegarLoop]: Abstraction has 120328 states and 171270 transitions. [2022-12-13 12:31:29,563 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 12:31:29,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120328 states and 171270 transitions. [2022-12-13 12:31:29,937 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 120000 [2022-12-13 12:31:29,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:29,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:29,942 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:29,942 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:29,942 INFO L748 eck$LassoCheckResult]: Stem: 2694006#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 2694007#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 2695061#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2695062#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2694647#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 2694288#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2694289#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2694604#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2694810#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2694479#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2694480#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2694346#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2694347#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2694751#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2694701#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2694616#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2694617#L1024 assume !(0 == ~M_E~0); 2694942#L1024-2 assume !(0 == ~T1_E~0); 2694002#L1029-1 assume !(0 == ~T2_E~0); 2694003#L1034-1 assume !(0 == ~T3_E~0); 2694108#L1039-1 assume !(0 == ~T4_E~0); 2695095#L1044-1 assume !(0 == ~T5_E~0); 2694370#L1049-1 assume !(0 == ~T6_E~0); 2694371#L1054-1 assume !(0 == ~T7_E~0); 2694646#L1059-1 assume !(0 == ~T8_E~0); 2694056#L1064-1 assume !(0 == ~T9_E~0); 2694057#L1069-1 assume !(0 == ~T10_E~0); 2694901#L1074-1 assume !(0 == ~E_M~0); 2694985#L1079-1 assume !(0 == ~E_1~0); 2694945#L1084-1 assume !(0 == ~E_2~0); 2694946#L1089-1 assume !(0 == ~E_3~0); 2695013#L1094-1 assume !(0 == ~E_4~0); 2694468#L1099-1 assume !(0 == ~E_5~0); 2694469#L1104-1 assume !(0 == ~E_6~0); 2694772#L1109-1 assume !(0 == ~E_7~0); 2694221#L1114-1 assume !(0 == ~E_8~0); 2694222#L1119-1 assume !(0 == ~E_9~0); 2694300#L1124-1 assume !(0 == ~E_10~0); 2693700#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2693701#L502 assume !(1 == ~m_pc~0); 2693896#L502-2 is_master_triggered_~__retres1~0#1 := 0; 2693828#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2693829#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2694695#L1273 assume !(0 != activate_threads_~tmp~1#1); 2694696#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2695165#L521 assume !(1 == ~t1_pc~0); 2695051#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2693751#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2693716#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2693717#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 2693736#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2693737#L540 assume !(1 == ~t2_pc~0); 2694589#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2694590#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2694217#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2694218#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 2695044#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2694034#L559 assume !(1 == ~t3_pc~0); 2694035#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2694322#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2693655#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2693656#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 2693846#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2693847#L578 assume !(1 == ~t4_pc~0); 2693968#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2694909#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2694939#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2695146#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 2694678#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2694679#L597 assume !(1 == ~t5_pc~0); 2694630#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2693772#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2693773#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2694940#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 2694618#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2694619#L616 assume !(1 == ~t6_pc~0); 2694641#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2694640#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2694194#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2694195#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 2694457#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2694458#L635 assume !(1 == ~t7_pc~0); 2693738#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2693739#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2694123#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2695008#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 2694610#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2694611#L654 assume !(1 == ~t8_pc~0); 2694401#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2694402#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2694845#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2694846#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 2694899#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2694001#L673 assume !(1 == ~t9_pc~0); 2693690#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2693691#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2694282#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2694283#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 2694787#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2694788#L692 assume !(1 == ~t10_pc~0); 2694721#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2694720#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2694460#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2694461#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 2694472#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2694872#L1142 assume !(1 == ~M_E~0); 2693908#L1142-2 assume !(1 == ~T1_E~0); 2693909#L1147-1 assume !(1 == ~T2_E~0); 2694853#L1152-1 assume !(1 == ~T3_E~0); 2694330#L1157-1 assume !(1 == ~T4_E~0); 2694331#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2694501#L1167-1 assume !(1 == ~T6_E~0); 2694502#L1172-1 assume !(1 == ~T7_E~0); 2695031#L1177-1 assume !(1 == ~T8_E~0); 2694664#L1182-1 assume !(1 == ~T9_E~0); 2694665#L1187-1 assume !(1 == ~T10_E~0); 2694779#L1192-1 assume !(1 == ~E_M~0); 2694170#L1197-1 assume !(1 == ~E_1~0); 2694171#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2694593#L1207-1 assume !(1 == ~E_3~0); 2694566#L1212-1 assume !(1 == ~E_4~0); 2693756#L1217-1 assume !(1 == ~E_5~0); 2693757#L1222-1 assume !(1 == ~E_6~0); 2694563#L1227-1 assume !(1 == ~E_7~0); 2694564#L1232-1 assume !(1 == ~E_8~0); 2693633#L1237-1 assume !(1 == ~E_9~0); 2693634#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2694644#L1247-1 assume { :end_inline_reset_delta_events } true; 2694645#L1553-2 [2022-12-13 12:31:29,943 INFO L750 eck$LassoCheckResult]: Loop: 2694645#L1553-2 assume !false; 2735561#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2735555#L999 assume !false; 2735553#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2735551#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2735536#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2735529#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2735522#L854 assume !(0 != eval_~tmp~0#1); 2735523#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2809977#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2809975#L1024-3 assume !(0 == ~M_E~0); 2809973#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2809971#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2809969#L1034-3 assume !(0 == ~T3_E~0); 2809967#L1039-3 assume !(0 == ~T4_E~0); 2809966#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2809964#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2809962#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2809960#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2809958#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2809954#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2809952#L1074-3 assume !(0 == ~E_M~0); 2809950#L1079-3 assume !(0 == ~E_1~0); 2809948#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2809945#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2809943#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2809941#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2809938#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2809936#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2809934#L1114-3 assume !(0 == ~E_8~0); 2809932#L1119-3 assume !(0 == ~E_9~0); 2809930#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2809928#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2809925#L502-36 assume !(1 == ~m_pc~0); 2809923#L502-38 is_master_triggered_~__retres1~0#1 := 0; 2809921#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2809919#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2809917#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2809915#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2809914#L521-36 assume 1 == ~t1_pc~0; 2809912#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2809909#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2809907#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2809905#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2809903#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2809901#L540-36 assume !(1 == ~t2_pc~0); 2751760#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2809897#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2809895#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2809894#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2809774#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2750455#L559-36 assume !(1 == ~t3_pc~0); 2750452#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2750449#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2750445#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2750441#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2750438#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2750435#L578-36 assume !(1 == ~t4_pc~0); 2750432#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2809814#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2809798#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2750403#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 2750398#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2750394#L597-36 assume !(1 == ~t5_pc~0); 2750384#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2750373#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2750363#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2750354#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 2750346#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2750326#L616-36 assume !(1 == ~t6_pc~0); 2750328#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 2809671#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2809669#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2750266#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2750256#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2750050#L635-36 assume !(1 == ~t7_pc~0); 2750042#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2750034#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2750026#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2749798#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2748698#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2748689#L654-36 assume 1 == ~t8_pc~0; 2748681#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2748674#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2748668#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2748661#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2748552#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2737350#L673-36 assume !(1 == ~t9_pc~0); 2737348#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 2737346#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2737344#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2737342#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2737340#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2737337#L692-36 assume !(1 == ~t10_pc~0); 2737335#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2737332#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2737330#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2737328#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2737326#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2737325#L1142-3 assume !(1 == ~M_E~0); 2725482#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2737322#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2737320#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2737318#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2737316#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2737314#L1167-3 assume !(1 == ~T6_E~0); 2737312#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2737310#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2737308#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2737306#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2737304#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2737302#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2737300#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2737298#L1207-3 assume !(1 == ~E_3~0); 2737296#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2737294#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2737292#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2737290#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2737288#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2737286#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2737284#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2737283#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2737270#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2737161#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2695627#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 2695621#L1572 assume !(0 == start_simulation_~tmp~3#1); 2695622#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2735702#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2735683#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2735674#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 2735667#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2735661#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2735655#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2735615#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 2694645#L1553-2 [2022-12-13 12:31:29,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:29,943 INFO L85 PathProgramCache]: Analyzing trace with hash 976442895, now seen corresponding path program 1 times [2022-12-13 12:31:29,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:29,944 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911460647] [2022-12-13 12:31:29,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:29,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:29,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:30,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:30,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:30,017 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911460647] [2022-12-13 12:31:30,018 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1911460647] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:30,018 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:30,018 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:30,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1372867444] [2022-12-13 12:31:30,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:30,018 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:31:30,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:30,019 INFO L85 PathProgramCache]: Analyzing trace with hash 489333954, now seen corresponding path program 1 times [2022-12-13 12:31:30,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:30,019 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288852782] [2022-12-13 12:31:30,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:30,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:30,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:30,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:30,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:30,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1288852782] [2022-12-13 12:31:30,053 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1288852782] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:30,053 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:30,053 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:30,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726186507] [2022-12-13 12:31:30,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:30,054 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:30,054 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:30,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:31:30,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:31:30,054 INFO L87 Difference]: Start difference. First operand 120328 states and 171270 transitions. cyclomatic complexity: 50946 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:30,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:30,609 INFO L93 Difference]: Finished difference Result 189402 states and 269167 transitions. [2022-12-13 12:31:30,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 189402 states and 269167 transitions. [2022-12-13 12:31:31,195 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 188864 [2022-12-13 12:31:31,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 189402 states to 189402 states and 269167 transitions. [2022-12-13 12:31:31,681 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 189402 [2022-12-13 12:31:31,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 189402 [2022-12-13 12:31:31,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 189402 states and 269167 transitions. [2022-12-13 12:31:31,802 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:31:31,802 INFO L218 hiAutomatonCegarLoop]: Abstraction has 189402 states and 269167 transitions. [2022-12-13 12:31:31,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189402 states and 269167 transitions. [2022-12-13 12:31:32,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189402 to 133225. [2022-12-13 12:31:32,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133225 states, 133225 states have (on average 1.4254231563145054) internal successors, (189902), 133224 states have internal predecessors, (189902), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:32,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133225 states to 133225 states and 189902 transitions. [2022-12-13 12:31:32,989 INFO L240 hiAutomatonCegarLoop]: Abstraction has 133225 states and 189902 transitions. [2022-12-13 12:31:32,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:31:32,991 INFO L428 stractBuchiCegarLoop]: Abstraction has 133225 states and 189902 transitions. [2022-12-13 12:31:32,991 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 12:31:32,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 133225 states and 189902 transitions. [2022-12-13 12:31:33,325 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 132800 [2022-12-13 12:31:33,326 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:33,326 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:33,331 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:33,331 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:33,331 INFO L748 eck$LassoCheckResult]: Stem: 3003746#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3003747#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3004798#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3004799#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3004374#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3004025#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3004026#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3004339#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3004543#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3004215#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3004216#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3004087#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3004088#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3004483#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3004429#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3004346#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3004347#L1024 assume !(0 == ~M_E~0); 3004677#L1024-2 assume !(0 == ~T1_E~0); 3003740#L1029-1 assume !(0 == ~T2_E~0); 3003741#L1034-1 assume !(0 == ~T3_E~0); 3003844#L1039-1 assume !(0 == ~T4_E~0); 3004835#L1044-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3004836#L1049-1 assume !(0 == ~T6_E~0); 3005029#L1054-1 assume !(0 == ~T7_E~0); 3005030#L1059-1 assume !(0 == ~T8_E~0); 3003794#L1064-1 assume !(0 == ~T9_E~0); 3003795#L1069-1 assume !(0 == ~T10_E~0); 3004972#L1074-1 assume !(0 == ~E_M~0); 3004973#L1079-1 assume !(0 == ~E_1~0); 3004679#L1084-1 assume !(0 == ~E_2~0); 3004680#L1089-1 assume !(0 == ~E_3~0); 3004743#L1094-1 assume !(0 == ~E_4~0); 3004744#L1099-1 assume !(0 == ~E_5~0); 3004861#L1104-1 assume !(0 == ~E_6~0); 3004862#L1109-1 assume !(0 == ~E_7~0); 3003961#L1114-1 assume !(0 == ~E_8~0); 3003962#L1119-1 assume !(0 == ~E_9~0); 3004040#L1124-1 assume !(0 == ~E_10~0); 3004041#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3004531#L502 assume !(1 == ~m_pc~0); 3004532#L502-2 is_master_triggered_~__retres1~0#1 := 0; 3003569#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3003570#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3004425#L1273 assume !(0 != activate_threads_~tmp~1#1); 3004426#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3004904#L521 assume !(1 == ~t1_pc~0); 3004905#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3003491#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3003492#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3004448#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 3004449#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3004694#L540 assume !(1 == ~t2_pc~0); 3004695#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3004698#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3004699#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3004975#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 3004976#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3003773#L559 assume !(1 == ~t3_pc~0); 3003774#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3004058#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3004059#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3004464#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 3004465#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3004991#L578 assume !(1 == ~t4_pc~0); 3004992#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3004672#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3004673#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3004883#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 3004884#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3004938#L597 assume !(1 == ~t5_pc~0); 3004939#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3003511#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3003512#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3005035#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3005036#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3004418#L616 assume !(1 == ~t6_pc~0); 3004419#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3004868#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3004869#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3005049#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3004192#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3004193#L635 assume !(1 == ~t7_pc~0); 3003477#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3003478#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3005000#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3005001#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3004341#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3004342#L654 assume !(1 == ~t8_pc~0); 3004133#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3004134#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3004579#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3004580#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3004814#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3004815#L673 assume !(1 == ~t9_pc~0); 3003431#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3003432#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3004019#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3004020#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3004520#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3004521#L692 assume !(1 == ~t10_pc~0); 3004454#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3004453#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3004822#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3004207#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3004208#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3005015#L1142 assume !(1 == ~M_E~0); 3005016#L1142-2 assume !(1 == ~T1_E~0); 3004585#L1147-1 assume !(1 == ~T2_E~0); 3004586#L1152-1 assume !(1 == ~T3_E~0); 3004066#L1157-1 assume !(1 == ~T4_E~0); 3004067#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3004233#L1167-1 assume !(1 == ~T6_E~0); 3004234#L1172-1 assume !(1 == ~T7_E~0); 3004763#L1177-1 assume !(1 == ~T8_E~0); 3004390#L1182-1 assume !(1 == ~T9_E~0); 3004391#L1187-1 assume !(1 == ~T10_E~0); 3004513#L1192-1 assume !(1 == ~E_M~0); 3003909#L1197-1 assume !(1 == ~E_1~0); 3003910#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3004329#L1207-1 assume !(1 == ~E_3~0); 3004301#L1212-1 assume !(1 == ~E_4~0); 3003495#L1217-1 assume !(1 == ~E_5~0); 3003496#L1222-1 assume !(1 == ~E_6~0); 3004298#L1227-1 assume !(1 == ~E_7~0); 3004299#L1232-1 assume !(1 == ~E_8~0); 3003373#L1237-1 assume !(1 == ~E_9~0); 3003374#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3004370#L1247-1 assume { :end_inline_reset_delta_events } true; 3004371#L1553-2 [2022-12-13 12:31:33,332 INFO L750 eck$LassoCheckResult]: Loop: 3004371#L1553-2 assume !false; 3059508#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3059498#L999 assume !false; 3059491#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3059308#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3059296#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3059294#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3059290#L854 assume !(0 != eval_~tmp~0#1); 3059291#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3066575#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3066576#L1024-3 assume !(0 == ~M_E~0); 3066564#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3066559#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3066554#L1034-3 assume !(0 == ~T3_E~0); 3066549#L1039-3 assume !(0 == ~T4_E~0); 3066516#L1044-3 assume !(0 == ~T5_E~0); 3066518#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3136004#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3136003#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3136002#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3136001#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3136000#L1074-3 assume !(0 == ~E_M~0); 3135999#L1079-3 assume !(0 == ~E_1~0); 3135998#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3135997#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3135996#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3135995#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3135994#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3135993#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3135992#L1114-3 assume !(0 == ~E_8~0); 3135991#L1119-3 assume !(0 == ~E_9~0); 3135990#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3135989#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3135988#L502-36 assume !(1 == ~m_pc~0); 3135987#L502-38 is_master_triggered_~__retres1~0#1 := 0; 3135986#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3135985#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3135984#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3135983#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3135982#L521-36 assume !(1 == ~t1_pc~0); 3135981#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 3135979#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3135978#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3068106#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3068107#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3066577#L540-36 assume !(1 == ~t2_pc~0); 3066578#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3066565#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3066566#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3066555#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3066556#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3066546#L559-36 assume !(1 == ~t3_pc~0); 3066545#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3066544#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3066543#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3066542#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3066541#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3066540#L578-36 assume 1 == ~t4_pc~0; 3066538#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3066536#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3066534#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3066532#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3066531#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3066530#L597-36 assume !(1 == ~t5_pc~0); 3066529#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3066528#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3066527#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3066526#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 3066525#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3066524#L616-36 assume 1 == ~t6_pc~0; 3066522#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3066521#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3066520#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3066519#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3066515#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3066512#L635-36 assume !(1 == ~t7_pc~0); 3041729#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3066507#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3066504#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3066501#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3066498#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3066495#L654-36 assume !(1 == ~t8_pc~0); 3066492#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3066488#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3066485#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3066482#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3066479#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3066476#L673-36 assume !(1 == ~t9_pc~0); 3058461#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3066471#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3066468#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3066465#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3066462#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3066459#L692-36 assume !(1 == ~t10_pc~0); 3066456#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3066452#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3066449#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3066446#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3066442#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3066438#L1142-3 assume !(1 == ~M_E~0); 3029284#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3066433#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3066430#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3066425#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3066362#L1162-3 assume !(1 == ~T5_E~0); 3066360#L1167-3 assume !(1 == ~T6_E~0); 3066359#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3066358#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3066357#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3066356#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3066355#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3066354#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3066353#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3066352#L1207-3 assume !(1 == ~E_3~0); 3066351#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3066350#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3066349#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3066346#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3066345#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3066344#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3066343#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3066342#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3066331#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3005237#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3005198#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3005199#L1572 assume !(0 == start_simulation_~tmp~3#1); 3029402#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3059620#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3059609#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3059606#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 3059604#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3059602#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3059600#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3059526#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 3004371#L1553-2 [2022-12-13 12:31:33,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:33,332 INFO L85 PathProgramCache]: Analyzing trace with hash -1176663923, now seen corresponding path program 1 times [2022-12-13 12:31:33,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:33,332 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178491710] [2022-12-13 12:31:33,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:33,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:33,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:33,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:33,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:33,369 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1178491710] [2022-12-13 12:31:33,369 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1178491710] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:33,369 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:33,369 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:33,369 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2078534980] [2022-12-13 12:31:33,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:33,370 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:31:33,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:33,370 INFO L85 PathProgramCache]: Analyzing trace with hash -2090314816, now seen corresponding path program 1 times [2022-12-13 12:31:33,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:33,371 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130851593] [2022-12-13 12:31:33,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:33,371 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:33,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:33,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:33,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:33,394 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2130851593] [2022-12-13 12:31:33,395 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2130851593] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:33,395 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:33,395 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:33,395 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523681046] [2022-12-13 12:31:33,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:33,395 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:33,395 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:33,396 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:31:33,396 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:31:33,396 INFO L87 Difference]: Start difference. First operand 133225 states and 189902 transitions. cyclomatic complexity: 56681 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:34,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:34,070 INFO L93 Difference]: Finished difference Result 176488 states and 250052 transitions. [2022-12-13 12:31:34,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176488 states and 250052 transitions. [2022-12-13 12:31:34,671 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 176064 [2022-12-13 12:31:35,149 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176488 states to 176488 states and 250052 transitions. [2022-12-13 12:31:35,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176488 [2022-12-13 12:31:35,208 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176488 [2022-12-13 12:31:35,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176488 states and 250052 transitions. [2022-12-13 12:31:35,268 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:31:35,268 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176488 states and 250052 transitions. [2022-12-13 12:31:35,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176488 states and 250052 transitions. [2022-12-13 12:31:36,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176488 to 120328. [2022-12-13 12:31:36,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120328 states, 120328 states have (on average 1.4201515856658466) internal successors, (170884), 120327 states have internal predecessors, (170884), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:36,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120328 states to 120328 states and 170884 transitions. [2022-12-13 12:31:36,463 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120328 states and 170884 transitions. [2022-12-13 12:31:36,463 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:31:36,464 INFO L428 stractBuchiCegarLoop]: Abstraction has 120328 states and 170884 transitions. [2022-12-13 12:31:36,464 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 12:31:36,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120328 states and 170884 transitions. [2022-12-13 12:31:36,743 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 120000 [2022-12-13 12:31:36,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:36,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:36,747 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:36,747 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:36,747 INFO L748 eck$LassoCheckResult]: Stem: 3313468#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3313469#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3314506#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3314507#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3314105#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3313746#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3313747#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3314069#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3314269#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3313935#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3313936#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3313806#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3313807#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3314211#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3314163#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3314077#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3314078#L1024 assume !(0 == ~M_E~0); 3314385#L1024-2 assume !(0 == ~T1_E~0); 3313462#L1029-1 assume !(0 == ~T2_E~0); 3313463#L1034-1 assume !(0 == ~T3_E~0); 3313567#L1039-1 assume !(0 == ~T4_E~0); 3314539#L1044-1 assume !(0 == ~T5_E~0); 3313827#L1049-1 assume !(0 == ~T6_E~0); 3313828#L1054-1 assume !(0 == ~T7_E~0); 3314104#L1059-1 assume !(0 == ~T8_E~0); 3313516#L1064-1 assume !(0 == ~T9_E~0); 3313517#L1069-1 assume !(0 == ~T10_E~0); 3314347#L1074-1 assume !(0 == ~E_M~0); 3314424#L1079-1 assume !(0 == ~E_1~0); 3314387#L1084-1 assume !(0 == ~E_2~0); 3314388#L1089-1 assume !(0 == ~E_3~0); 3314449#L1094-1 assume !(0 == ~E_4~0); 3313925#L1099-1 assume !(0 == ~E_5~0); 3313926#L1104-1 assume !(0 == ~E_6~0); 3314235#L1109-1 assume !(0 == ~E_7~0); 3313681#L1114-1 assume !(0 == ~E_8~0); 3313682#L1119-1 assume !(0 == ~E_9~0); 3313761#L1124-1 assume !(0 == ~E_10~0); 3313163#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3313164#L502 assume !(1 == ~m_pc~0); 3313357#L502-2 is_master_triggered_~__retres1~0#1 := 0; 3313289#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3313290#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3314159#L1273 assume !(0 != activate_threads_~tmp~1#1); 3314160#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3314601#L521 assume !(1 == ~t1_pc~0); 3314491#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3313215#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3313179#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3313180#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 3313199#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3313200#L540 assume !(1 == ~t2_pc~0); 3314049#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3314050#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3313679#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3313680#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 3314484#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3313493#L559 assume !(1 == ~t3_pc~0); 3313494#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3313779#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3313118#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3313119#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 3313305#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3313306#L578 assume !(1 == ~t4_pc~0); 3313432#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3314352#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3314382#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3314585#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 3314142#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3314143#L597 assume !(1 == ~t5_pc~0); 3314088#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3313233#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3313234#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3314383#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3314079#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3314080#L616 assume !(1 == ~t6_pc~0); 3314101#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3314100#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3313654#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3313655#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3313915#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3313916#L635 assume !(1 == ~t7_pc~0); 3313201#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3313202#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3313586#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3314443#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3314071#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3314072#L654 assume !(1 == ~t8_pc~0); 3313856#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3313857#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3314306#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3314307#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3314345#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3313461#L673 assume !(1 == ~t9_pc~0); 3313155#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3313156#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3313740#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3313741#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3314248#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3314249#L692 assume !(1 == ~t10_pc~0); 3314184#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3314183#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3313917#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3313918#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3313929#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3314320#L1142 assume !(1 == ~M_E~0); 3313365#L1142-2 assume !(1 == ~T1_E~0); 3313366#L1147-1 assume !(1 == ~T2_E~0); 3314310#L1152-1 assume !(1 == ~T3_E~0); 3313785#L1157-1 assume !(1 == ~T4_E~0); 3313786#L1162-1 assume !(1 == ~T5_E~0); 3313955#L1167-1 assume !(1 == ~T6_E~0); 3313956#L1172-1 assume !(1 == ~T7_E~0); 3314469#L1177-1 assume !(1 == ~T8_E~0); 3314122#L1182-1 assume !(1 == ~T9_E~0); 3314123#L1187-1 assume !(1 == ~T10_E~0); 3314241#L1192-1 assume !(1 == ~E_M~0); 3313631#L1197-1 assume !(1 == ~E_1~0); 3313632#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3314054#L1207-1 assume !(1 == ~E_3~0); 3314025#L1212-1 assume !(1 == ~E_4~0); 3313218#L1217-1 assume !(1 == ~E_5~0); 3313219#L1222-1 assume !(1 == ~E_6~0); 3314022#L1227-1 assume !(1 == ~E_7~0); 3314023#L1232-1 assume !(1 == ~E_8~0); 3313096#L1237-1 assume !(1 == ~E_9~0); 3313097#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3314102#L1247-1 assume { :end_inline_reset_delta_events } true; 3314103#L1553-2 [2022-12-13 12:31:36,747 INFO L750 eck$LassoCheckResult]: Loop: 3314103#L1553-2 assume !false; 3358665#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3358659#L999 assume !false; 3358657#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3358655#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3358643#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3358642#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3358637#L854 assume !(0 != eval_~tmp~0#1); 3358638#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3371638#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3371636#L1024-3 assume !(0 == ~M_E~0); 3371469#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3371470#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3371464#L1034-3 assume !(0 == ~T3_E~0); 3371465#L1039-3 assume !(0 == ~T4_E~0); 3371458#L1044-3 assume !(0 == ~T5_E~0); 3371459#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3371449#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3371450#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3371437#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3371438#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3371425#L1074-3 assume !(0 == ~E_M~0); 3371426#L1079-3 assume !(0 == ~E_1~0); 3371415#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3371416#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3371404#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3371405#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3371394#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3371395#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3371384#L1114-3 assume !(0 == ~E_8~0); 3371385#L1119-3 assume !(0 == ~E_9~0); 3371373#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3371374#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3371363#L502-36 assume !(1 == ~m_pc~0); 3371364#L502-38 is_master_triggered_~__retres1~0#1 := 0; 3371353#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3371354#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3371344#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3371345#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3371333#L521-36 assume !(1 == ~t1_pc~0); 3371335#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 3371322#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3371323#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3371311#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3371312#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3371285#L540-36 assume !(1 == ~t2_pc~0); 3371283#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3371282#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3371281#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3371280#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3371279#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3367269#L559-36 assume !(1 == ~t3_pc~0); 3367267#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3367265#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3367263#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3367261#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3367259#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3367257#L578-36 assume 1 == ~t4_pc~0; 3367254#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3367252#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3367250#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3366860#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3366858#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3366856#L597-36 assume !(1 == ~t5_pc~0); 3366853#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3366851#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3366849#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3366847#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 3366845#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3366843#L616-36 assume !(1 == ~t6_pc~0); 3366842#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 3366839#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3366837#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3366835#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3364849#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3352032#L635-36 assume !(1 == ~t7_pc~0); 3352027#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3352025#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3352022#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3352019#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3352017#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3352015#L654-36 assume !(1 == ~t8_pc~0); 3352013#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3352010#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3352008#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3352007#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3352005#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3343287#L673-36 assume !(1 == ~t9_pc~0); 3343285#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3343283#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3343281#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3343278#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3343275#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3343273#L692-36 assume !(1 == ~t10_pc~0); 3343270#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3343266#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3343263#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3343260#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3343258#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3343256#L1142-3 assume !(1 == ~M_E~0); 3340414#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3343251#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3343248#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3342915#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3342909#L1162-3 assume !(1 == ~T5_E~0); 3342906#L1167-3 assume !(1 == ~T6_E~0); 3342903#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3342900#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3342896#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3342893#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3342875#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3342867#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3342860#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3342852#L1207-3 assume !(1 == ~E_3~0); 3342844#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3342836#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3342826#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3342817#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3342809#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3342802#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3342795#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3342790#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3342622#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3341882#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3341235#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3340689#L1572 assume !(0 == start_simulation_~tmp~3#1); 3340690#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3358689#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3358678#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3358677#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 3358675#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3358673#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3358671#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3358669#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 3314103#L1553-2 [2022-12-13 12:31:36,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:36,748 INFO L85 PathProgramCache]: Analyzing trace with hash -1017701811, now seen corresponding path program 1 times [2022-12-13 12:31:36,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:36,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [422305772] [2022-12-13 12:31:36,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:36,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:36,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:36,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:36,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:36,790 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [422305772] [2022-12-13 12:31:36,790 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [422305772] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:36,790 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:36,790 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:31:36,790 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [493601389] [2022-12-13 12:31:36,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:36,790 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:31:36,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:36,790 INFO L85 PathProgramCache]: Analyzing trace with hash -1712671999, now seen corresponding path program 1 times [2022-12-13 12:31:36,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:36,790 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061500631] [2022-12-13 12:31:36,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:36,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:36,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:36,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:36,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:36,814 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061500631] [2022-12-13 12:31:36,814 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2061500631] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:36,814 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:36,815 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:36,815 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1014233336] [2022-12-13 12:31:36,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:36,815 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:36,815 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:36,815 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:31:36,815 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:31:36,815 INFO L87 Difference]: Start difference. First operand 120328 states and 170884 transitions. cyclomatic complexity: 50560 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:37,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:37,127 INFO L93 Difference]: Finished difference Result 120328 states and 169922 transitions. [2022-12-13 12:31:37,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120328 states and 169922 transitions. [2022-12-13 12:31:37,688 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 120000 [2022-12-13 12:31:37,913 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120328 states to 120328 states and 169922 transitions. [2022-12-13 12:31:37,913 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120328 [2022-12-13 12:31:37,967 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120328 [2022-12-13 12:31:37,967 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120328 states and 169922 transitions. [2022-12-13 12:31:38,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:31:38,015 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120328 states and 169922 transitions. [2022-12-13 12:31:38,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120328 states and 169922 transitions. [2022-12-13 12:31:38,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120328 to 120328. [2022-12-13 12:31:38,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120328 states, 120328 states have (on average 1.4121567714912573) internal successors, (169922), 120327 states have internal predecessors, (169922), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:39,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120328 states to 120328 states and 169922 transitions. [2022-12-13 12:31:39,208 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120328 states and 169922 transitions. [2022-12-13 12:31:39,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:31:39,209 INFO L428 stractBuchiCegarLoop]: Abstraction has 120328 states and 169922 transitions. [2022-12-13 12:31:39,209 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 12:31:39,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120328 states and 169922 transitions. [2022-12-13 12:31:39,590 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 120000 [2022-12-13 12:31:39,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:39,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:39,595 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:39,595 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:39,595 INFO L748 eck$LassoCheckResult]: Stem: 3554127#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3554128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3555195#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3555196#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3554760#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3554407#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3554408#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3554723#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3554938#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3554594#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3554595#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3554463#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3554464#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3554876#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3554824#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3554731#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3554732#L1024 assume !(0 == ~M_E~0); 3555072#L1024-2 assume !(0 == ~T1_E~0); 3554123#L1029-1 assume !(0 == ~T2_E~0); 3554124#L1034-1 assume !(0 == ~T3_E~0); 3554227#L1039-1 assume !(0 == ~T4_E~0); 3555228#L1044-1 assume !(0 == ~T5_E~0); 3554485#L1049-1 assume !(0 == ~T6_E~0); 3554486#L1054-1 assume !(0 == ~T7_E~0); 3554759#L1059-1 assume !(0 == ~T8_E~0); 3554177#L1064-1 assume !(0 == ~T9_E~0); 3554178#L1069-1 assume !(0 == ~T10_E~0); 3555030#L1074-1 assume !(0 == ~E_M~0); 3555111#L1079-1 assume !(0 == ~E_1~0); 3555075#L1084-1 assume !(0 == ~E_2~0); 3555076#L1089-1 assume !(0 == ~E_3~0); 3555139#L1094-1 assume !(0 == ~E_4~0); 3554583#L1099-1 assume !(0 == ~E_5~0); 3554584#L1104-1 assume !(0 == ~E_6~0); 3554899#L1109-1 assume !(0 == ~E_7~0); 3554343#L1114-1 assume !(0 == ~E_8~0); 3554344#L1119-1 assume !(0 == ~E_9~0); 3554418#L1124-1 assume !(0 == ~E_10~0); 3553825#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3553826#L502 assume !(1 == ~m_pc~0); 3554017#L502-2 is_master_triggered_~__retres1~0#1 := 0; 3553948#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3553949#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3554818#L1273 assume !(0 != activate_threads_~tmp~1#1); 3554819#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3555298#L521 assume !(1 == ~t1_pc~0); 3555182#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3553874#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3553840#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3553841#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 3553860#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3553861#L540 assume !(1 == ~t2_pc~0); 3554707#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3554708#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3554339#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3554340#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 3555175#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3554156#L559 assume !(1 == ~t3_pc~0); 3554157#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3554440#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3553780#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3553781#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 3553966#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3553967#L578 assume !(1 == ~t4_pc~0); 3554089#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3555035#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3555069#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3555278#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 3554797#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3554798#L597 assume !(1 == ~t5_pc~0); 3554743#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3553895#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3553896#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3555070#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3554733#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3554734#L616 assume !(1 == ~t6_pc~0); 3554754#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3554753#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3554315#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3554316#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3554572#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3554573#L635 assume !(1 == ~t7_pc~0); 3553862#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3553863#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3554242#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3555135#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3554726#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3554727#L654 assume !(1 == ~t8_pc~0); 3554515#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3554516#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3554974#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3554975#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3555027#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3554122#L673 assume !(1 == ~t9_pc~0); 3553815#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3553816#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3554401#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3554402#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3554914#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3554915#L692 assume !(1 == ~t10_pc~0); 3554843#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3554842#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3554575#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3554576#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3554588#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3554996#L1142 assume !(1 == ~M_E~0); 3554029#L1142-2 assume !(1 == ~T1_E~0); 3554030#L1147-1 assume !(1 == ~T2_E~0); 3554981#L1152-1 assume !(1 == ~T3_E~0); 3554447#L1157-1 assume !(1 == ~T4_E~0); 3554448#L1162-1 assume !(1 == ~T5_E~0); 3554615#L1167-1 assume !(1 == ~T6_E~0); 3554616#L1172-1 assume !(1 == ~T7_E~0); 3555158#L1177-1 assume !(1 == ~T8_E~0); 3554778#L1182-1 assume !(1 == ~T9_E~0); 3554779#L1187-1 assume !(1 == ~T10_E~0); 3554906#L1192-1 assume !(1 == ~E_M~0); 3554291#L1197-1 assume !(1 == ~E_1~0); 3554292#L1202-1 assume !(1 == ~E_2~0); 3554711#L1207-1 assume !(1 == ~E_3~0); 3554686#L1212-1 assume !(1 == ~E_4~0); 3553879#L1217-1 assume !(1 == ~E_5~0); 3553880#L1222-1 assume !(1 == ~E_6~0); 3554682#L1227-1 assume !(1 == ~E_7~0); 3554683#L1232-1 assume !(1 == ~E_8~0); 3553759#L1237-1 assume !(1 == ~E_9~0); 3553760#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3554757#L1247-1 assume { :end_inline_reset_delta_events } true; 3554758#L1553-2 [2022-12-13 12:31:39,596 INFO L750 eck$LassoCheckResult]: Loop: 3554758#L1553-2 assume !false; 3640223#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3640218#L999 assume !false; 3640216#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3640214#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3640202#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3640201#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3640196#L854 assume !(0 != eval_~tmp~0#1); 3640197#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3672782#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3672765#L1024-3 assume !(0 == ~M_E~0); 3672763#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3672760#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3672757#L1034-3 assume !(0 == ~T3_E~0); 3672754#L1039-3 assume !(0 == ~T4_E~0); 3672751#L1044-3 assume !(0 == ~T5_E~0); 3672748#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3672746#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3672743#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3672740#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3672736#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3672733#L1074-3 assume !(0 == ~E_M~0); 3672731#L1079-3 assume !(0 == ~E_1~0); 3672728#L1084-3 assume !(0 == ~E_2~0); 3672725#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3672721#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3672718#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3672716#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3672714#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3672712#L1114-3 assume !(0 == ~E_8~0); 3672710#L1119-3 assume !(0 == ~E_9~0); 3672708#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3672706#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3672704#L502-36 assume !(1 == ~m_pc~0); 3672702#L502-38 is_master_triggered_~__retres1~0#1 := 0; 3672701#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3672693#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3672691#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3672689#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3672686#L521-36 assume 1 == ~t1_pc~0; 3672683#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3672681#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3672679#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3672677#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3672674#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3672654#L540-36 assume !(1 == ~t2_pc~0); 3657025#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3662243#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3662242#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3662241#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3662239#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3642712#L559-36 assume !(1 == ~t3_pc~0); 3642700#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3642698#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3642696#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3642694#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3642692#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3642690#L578-36 assume !(1 == ~t4_pc~0); 3642686#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3642684#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3642678#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3642676#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 3642673#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3642661#L597-36 assume !(1 == ~t5_pc~0); 3642659#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3642657#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3642654#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3642652#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 3642650#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3642648#L616-36 assume !(1 == ~t6_pc~0); 3642646#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 3642643#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3642641#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3642639#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3642637#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3640374#L635-36 assume !(1 == ~t7_pc~0); 3640372#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3640370#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3640368#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3640366#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3640364#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3640362#L654-36 assume 1 == ~t8_pc~0; 3640359#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3640356#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3640354#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3640352#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3640350#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3640348#L673-36 assume !(1 == ~t9_pc~0); 3625019#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3640346#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3640344#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3640342#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3640340#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3640338#L692-36 assume !(1 == ~t10_pc~0); 3640336#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3640332#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3640330#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3640328#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3640326#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3640324#L1142-3 assume !(1 == ~M_E~0); 3640320#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3640318#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3640316#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3640314#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3640312#L1162-3 assume !(1 == ~T5_E~0); 3640310#L1167-3 assume !(1 == ~T6_E~0); 3640308#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3640306#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3640304#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3640302#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3640300#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3640298#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3640296#L1202-3 assume !(1 == ~E_2~0); 3640294#L1207-3 assume !(1 == ~E_3~0); 3640292#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3640290#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3640288#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3640286#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3640284#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3640282#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3640280#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3640278#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3640264#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3640262#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3640260#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3640258#L1572 assume !(0 == start_simulation_~tmp~3#1); 3640255#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3640247#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3640236#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3640235#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 3640233#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3640231#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3640229#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3640227#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 3554758#L1553-2 [2022-12-13 12:31:39,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:39,596 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728821, now seen corresponding path program 1 times [2022-12-13 12:31:39,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:39,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246355738] [2022-12-13 12:31:39,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:39,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:39,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:39,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:39,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:39,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246355738] [2022-12-13 12:31:39,650 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246355738] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:39,650 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:39,650 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:39,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439489291] [2022-12-13 12:31:39,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:39,651 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:31:39,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:39,651 INFO L85 PathProgramCache]: Analyzing trace with hash 2096252994, now seen corresponding path program 1 times [2022-12-13 12:31:39,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:39,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1226596277] [2022-12-13 12:31:39,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:39,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:39,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:39,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:39,688 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:39,688 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1226596277] [2022-12-13 12:31:39,689 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1226596277] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:39,689 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:39,689 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:39,689 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184486707] [2022-12-13 12:31:39,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:39,689 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:39,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:39,690 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:31:39,690 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:31:39,690 INFO L87 Difference]: Start difference. First operand 120328 states and 169922 transitions. cyclomatic complexity: 49598 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:40,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:40,280 INFO L93 Difference]: Finished difference Result 187285 states and 262600 transitions. [2022-12-13 12:31:40,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 187285 states and 262600 transitions. [2022-12-13 12:31:40,843 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 186704 [2022-12-13 12:31:41,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 187285 states to 187285 states and 262600 transitions. [2022-12-13 12:31:41,347 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 187285 [2022-12-13 12:31:41,383 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 187285 [2022-12-13 12:31:41,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 187285 states and 262600 transitions. [2022-12-13 12:31:41,426 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:31:41,426 INFO L218 hiAutomatonCegarLoop]: Abstraction has 187285 states and 262600 transitions. [2022-12-13 12:31:41,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187285 states and 262600 transitions. [2022-12-13 12:31:42,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187285 to 133225. [2022-12-13 12:31:42,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133225 states, 133225 states have (on average 1.4061700131356727) internal successors, (187337), 133224 states have internal predecessors, (187337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:42,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133225 states to 133225 states and 187337 transitions. [2022-12-13 12:31:42,638 INFO L240 hiAutomatonCegarLoop]: Abstraction has 133225 states and 187337 transitions. [2022-12-13 12:31:42,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:31:42,639 INFO L428 stractBuchiCegarLoop]: Abstraction has 133225 states and 187337 transitions. [2022-12-13 12:31:42,639 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 12:31:42,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 133225 states and 187337 transitions. [2022-12-13 12:31:42,948 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 132800 [2022-12-13 12:31:42,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:42,948 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:42,953 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:42,953 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:42,953 INFO L748 eck$LassoCheckResult]: Stem: 3861746#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3861747#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3862788#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3862789#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3862379#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3862027#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3862028#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3862339#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3862542#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3862216#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3862217#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3862082#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3862083#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3862486#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3862438#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3862347#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3862348#L1024 assume !(0 == ~M_E~0); 3862669#L1024-2 assume !(0 == ~T1_E~0); 3861742#L1029-1 assume !(0 == ~T2_E~0); 3861743#L1034-1 assume !(0 == ~T3_E~0); 3861844#L1039-1 assume !(0 == ~T4_E~0); 3862822#L1044-1 assume !(0 == ~T5_E~0); 3862104#L1049-1 assume !(0 == ~T6_E~0); 3862105#L1054-1 assume !(0 == ~T7_E~0); 3862378#L1059-1 assume !(0 == ~T8_E~0); 3861793#L1064-1 assume !(0 == ~T9_E~0); 3861794#L1069-1 assume !(0 == ~T10_E~0); 3862626#L1074-1 assume !(0 == ~E_M~0); 3862707#L1079-1 assume !(0 == ~E_1~0); 3862671#L1084-1 assume !(0 == ~E_2~0); 3862672#L1089-1 assume !(0 == ~E_3~0); 3862732#L1094-1 assume !(0 == ~E_4~0); 3862205#L1099-1 assume !(0 == ~E_5~0); 3862206#L1104-1 assume !(0 == ~E_6~0); 3862507#L1109-1 assume !(0 == ~E_7~0); 3861963#L1114-1 assume !(0 == ~E_8~0); 3861964#L1119-1 assume !(0 == ~E_9~0); 3862037#L1124-1 assume 0 == ~E_10~0;~E_10~0 := 1; 3861448#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3861449#L502 assume !(1 == ~m_pc~0); 3862533#L502-2 is_master_triggered_~__retres1~0#1 := 0; 3863084#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3863083#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3862432#L1273 assume !(0 != activate_threads_~tmp~1#1); 3862433#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3863007#L521 assume !(1 == ~t1_pc~0); 3862775#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3861497#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3861463#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3861464#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 3861483#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3861484#L540 assume !(1 == ~t2_pc~0); 3862685#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3863076#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3861959#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3861960#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 3863075#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3863074#L559 assume !(1 == ~t3_pc~0); 3863073#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3863072#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3863071#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3863068#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 3863067#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3862960#L578 assume !(1 == ~t4_pc~0); 3861708#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3863069#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3863070#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3862868#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 3862411#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3862412#L597 assume !(1 == ~t5_pc~0); 3862919#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3861518#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3861519#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3862667#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3863002#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3863057#L616 assume !(1 == ~t6_pc~0); 3862373#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3862372#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3863056#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3863055#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3863054#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3863053#L635 assume !(1 == ~t7_pc~0); 3863052#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3863051#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3863050#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3863049#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3862342#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3862343#L654 assume !(1 == ~t8_pc~0); 3862135#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3862136#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3862573#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3862574#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3862623#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3861741#L673 assume !(1 == ~t9_pc~0); 3861438#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3861439#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3863039#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3863038#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3863037#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3863036#L692 assume !(1 == ~t10_pc~0); 3863034#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3863033#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3863032#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3863031#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3863030#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3863029#L1142 assume !(1 == ~M_E~0); 3863028#L1142-2 assume !(1 == ~T1_E~0); 3863027#L1147-1 assume !(1 == ~T2_E~0); 3863026#L1152-1 assume !(1 == ~T3_E~0); 3863025#L1157-1 assume !(1 == ~T4_E~0); 3863024#L1162-1 assume !(1 == ~T5_E~0); 3863023#L1167-1 assume !(1 == ~T6_E~0); 3863022#L1172-1 assume !(1 == ~T7_E~0); 3863021#L1177-1 assume !(1 == ~T8_E~0); 3863020#L1182-1 assume !(1 == ~T9_E~0); 3863019#L1187-1 assume !(1 == ~T10_E~0); 3863018#L1192-1 assume !(1 == ~E_M~0); 3863017#L1197-1 assume !(1 == ~E_1~0); 3863016#L1202-1 assume !(1 == ~E_2~0); 3863015#L1207-1 assume !(1 == ~E_3~0); 3863014#L1212-1 assume !(1 == ~E_4~0); 3863013#L1217-1 assume !(1 == ~E_5~0); 3863012#L1222-1 assume !(1 == ~E_6~0); 3863011#L1227-1 assume !(1 == ~E_7~0); 3863010#L1232-1 assume !(1 == ~E_8~0); 3863009#L1237-1 assume !(1 == ~E_9~0); 3863008#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3862376#L1247-1 assume { :end_inline_reset_delta_events } true; 3862377#L1553-2 [2022-12-13 12:31:42,954 INFO L750 eck$LassoCheckResult]: Loop: 3862377#L1553-2 assume !false; 3972651#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3972647#L999 assume !false; 3972646#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3972645#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3972634#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3972633#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3972631#L854 assume !(0 != eval_~tmp~0#1); 3972632#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3979904#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3979902#L1024-3 assume !(0 == ~M_E~0); 3979901#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3979900#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3979899#L1034-3 assume !(0 == ~T3_E~0); 3979898#L1039-3 assume !(0 == ~T4_E~0); 3979896#L1044-3 assume !(0 == ~T5_E~0); 3979895#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3979894#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3979893#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3979892#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3979890#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3979888#L1074-3 assume !(0 == ~E_M~0); 3979886#L1079-3 assume !(0 == ~E_1~0); 3979884#L1084-3 assume !(0 == ~E_2~0); 3979882#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3979880#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3979878#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3979875#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3979873#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3979871#L1114-3 assume !(0 == ~E_8~0); 3979869#L1119-3 assume !(0 == ~E_9~0); 3979679#L1124-3 assume !(0 == ~E_10~0); 3979680#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3994260#L502-36 assume !(1 == ~m_pc~0); 3993639#L502-38 is_master_triggered_~__retres1~0#1 := 0; 3993638#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3993637#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3993636#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3993635#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3993634#L521-36 assume 1 == ~t1_pc~0; 3993632#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3993630#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3993628#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3993626#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3993624#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3993622#L540-36 assume !(1 == ~t2_pc~0); 3991388#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3993619#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3993616#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3993614#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3993612#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3975154#L559-36 assume !(1 == ~t3_pc~0); 3975152#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3975151#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3975150#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3975147#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3975145#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3975143#L578-36 assume 1 == ~t4_pc~0; 3975141#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3975140#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3975139#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3975060#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3975055#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3975048#L597-36 assume !(1 == ~t5_pc~0); 3975042#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3975037#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3975034#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3974688#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 3974687#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3974686#L616-36 assume 1 == ~t6_pc~0; 3974684#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3974683#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3974682#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3974681#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3974680#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3974678#L635-36 assume !(1 == ~t7_pc~0); 3967258#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3974677#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3974676#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3974675#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3974673#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3974671#L654-36 assume 1 == ~t8_pc~0; 3974668#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3974468#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3974450#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3974440#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3974430#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3967893#L673-36 assume !(1 == ~t9_pc~0); 3967891#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3967889#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3967887#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3967885#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3967881#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3967879#L692-36 assume !(1 == ~t10_pc~0); 3967876#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3967874#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3967871#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3967869#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3967867#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3967865#L1142-3 assume !(1 == ~M_E~0); 3894954#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3967862#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3967860#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3967858#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3967856#L1162-3 assume !(1 == ~T5_E~0); 3967853#L1167-3 assume !(1 == ~T6_E~0); 3967851#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3967849#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3967847#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3967845#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3967843#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3967840#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3967838#L1202-3 assume !(1 == ~E_2~0); 3967836#L1207-3 assume !(1 == ~E_3~0); 3967834#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3967832#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3967830#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3967827#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3967825#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3967823#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3967821#L1242-3 assume !(1 == ~E_10~0); 3967818#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3967802#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3967800#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3967798#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3895166#L1572 assume !(0 == start_simulation_~tmp~3#1); 3895167#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3972672#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3972662#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3972661#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 3972657#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3972655#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3972653#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3972652#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 3862377#L1553-2 [2022-12-13 12:31:42,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:42,954 INFO L85 PathProgramCache]: Analyzing trace with hash 529853193, now seen corresponding path program 1 times [2022-12-13 12:31:42,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:42,954 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611714963] [2022-12-13 12:31:42,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:42,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:42,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:42,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:42,988 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:42,989 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611714963] [2022-12-13 12:31:42,989 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [611714963] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:42,989 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:42,989 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:42,989 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116394174] [2022-12-13 12:31:42,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:42,989 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:31:42,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:42,990 INFO L85 PathProgramCache]: Analyzing trace with hash -1867512066, now seen corresponding path program 1 times [2022-12-13 12:31:42,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:42,990 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040196348] [2022-12-13 12:31:42,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:42,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:42,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:43,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:43,010 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:43,011 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040196348] [2022-12-13 12:31:43,011 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2040196348] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:43,011 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:43,011 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:43,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1433778688] [2022-12-13 12:31:43,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:43,011 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:43,011 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:43,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:31:43,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:31:43,012 INFO L87 Difference]: Start difference. First operand 133225 states and 187337 transitions. cyclomatic complexity: 54116 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:43,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:43,646 INFO L93 Difference]: Finished difference Result 173976 states and 243087 transitions. [2022-12-13 12:31:43,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 173976 states and 243087 transitions. [2022-12-13 12:31:44,230 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 173520 [2022-12-13 12:31:44,506 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 173976 states to 173976 states and 243087 transitions. [2022-12-13 12:31:44,506 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 173976 [2022-12-13 12:31:44,562 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 173976 [2022-12-13 12:31:44,562 INFO L73 IsDeterministic]: Start isDeterministic. Operand 173976 states and 243087 transitions. [2022-12-13 12:31:44,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:31:44,616 INFO L218 hiAutomatonCegarLoop]: Abstraction has 173976 states and 243087 transitions. [2022-12-13 12:31:44,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173976 states and 243087 transitions. [2022-12-13 12:31:45,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173976 to 120328. [2022-12-13 12:31:45,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120328 states, 120328 states have (on average 1.3993667309354432) internal successors, (168383), 120327 states have internal predecessors, (168383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:45,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120328 states to 120328 states and 168383 transitions. [2022-12-13 12:31:45,812 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120328 states and 168383 transitions. [2022-12-13 12:31:45,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:31:45,813 INFO L428 stractBuchiCegarLoop]: Abstraction has 120328 states and 168383 transitions. [2022-12-13 12:31:45,813 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 12:31:45,813 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120328 states and 168383 transitions. [2022-12-13 12:31:46,208 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 120000 [2022-12-13 12:31:46,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:46,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:46,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:46,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:46,212 INFO L748 eck$LassoCheckResult]: Stem: 4168956#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4168957#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4169971#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4169972#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4169582#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 4169231#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4169232#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4169544#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4169746#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4169417#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4169418#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4169287#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4169288#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4169687#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4169643#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4169553#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4169554#L1024 assume !(0 == ~M_E~0); 4169864#L1024-2 assume !(0 == ~T1_E~0); 4168952#L1029-1 assume !(0 == ~T2_E~0); 4168953#L1034-1 assume !(0 == ~T3_E~0); 4169053#L1039-1 assume !(0 == ~T4_E~0); 4170004#L1044-1 assume !(0 == ~T5_E~0); 4169310#L1049-1 assume !(0 == ~T6_E~0); 4169311#L1054-1 assume !(0 == ~T7_E~0); 4169581#L1059-1 assume !(0 == ~T8_E~0); 4169004#L1064-1 assume !(0 == ~T9_E~0); 4169005#L1069-1 assume !(0 == ~T10_E~0); 4169826#L1074-1 assume !(0 == ~E_M~0); 4169902#L1079-1 assume !(0 == ~E_1~0); 4169867#L1084-1 assume !(0 == ~E_2~0); 4169868#L1089-1 assume !(0 == ~E_3~0); 4169923#L1094-1 assume !(0 == ~E_4~0); 4169407#L1099-1 assume !(0 == ~E_5~0); 4169408#L1104-1 assume !(0 == ~E_6~0); 4169711#L1109-1 assume !(0 == ~E_7~0); 4169167#L1114-1 assume !(0 == ~E_8~0); 4169168#L1119-1 assume !(0 == ~E_9~0); 4169242#L1124-1 assume !(0 == ~E_10~0); 4168659#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4168660#L502 assume !(1 == ~m_pc~0); 4168848#L502-2 is_master_triggered_~__retres1~0#1 := 0; 4168783#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4168784#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4169637#L1273 assume !(0 != activate_threads_~tmp~1#1); 4169638#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4170070#L521 assume !(1 == ~t1_pc~0); 4169961#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4168708#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4168674#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4168675#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 4168694#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4168695#L540 assume !(1 == ~t2_pc~0); 4169527#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4169528#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4169163#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4169164#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 4169954#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4168982#L559 assume !(1 == ~t3_pc~0); 4168983#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4169263#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4168614#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4168615#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 4168801#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4168802#L578 assume !(1 == ~t4_pc~0); 4168918#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4169831#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4169861#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4170045#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 4169619#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4169620#L597 assume !(1 == ~t5_pc~0); 4169566#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4168729#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4168730#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4169862#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 4169555#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4169556#L616 assume !(1 == ~t6_pc~0); 4169576#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4169575#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4169139#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4169140#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 4169396#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4169397#L635 assume !(1 == ~t7_pc~0); 4168696#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4168697#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4169070#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4169919#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 4169548#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4169549#L654 assume !(1 == ~t8_pc~0); 4169341#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4169342#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4169776#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4169777#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 4169823#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4168951#L673 assume !(1 == ~t9_pc~0); 4168649#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4168650#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4169225#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4169226#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 4169725#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4169726#L692 assume !(1 == ~t10_pc~0); 4169660#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4169710#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4169399#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4169400#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 4169411#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4169796#L1142 assume !(1 == ~M_E~0); 4168860#L1142-2 assume !(1 == ~T1_E~0); 4168861#L1147-1 assume !(1 == ~T2_E~0); 4169783#L1152-1 assume !(1 == ~T3_E~0); 4169271#L1157-1 assume !(1 == ~T4_E~0); 4169272#L1162-1 assume !(1 == ~T5_E~0); 4169436#L1167-1 assume !(1 == ~T6_E~0); 4169437#L1172-1 assume !(1 == ~T7_E~0); 4169940#L1177-1 assume !(1 == ~T8_E~0); 4169603#L1182-1 assume !(1 == ~T9_E~0); 4169604#L1187-1 assume !(1 == ~T10_E~0); 4169717#L1192-1 assume !(1 == ~E_M~0); 4169116#L1197-1 assume !(1 == ~E_1~0); 4169117#L1202-1 assume !(1 == ~E_2~0); 4169531#L1207-1 assume !(1 == ~E_3~0); 4169505#L1212-1 assume !(1 == ~E_4~0); 4168713#L1217-1 assume !(1 == ~E_5~0); 4168714#L1222-1 assume !(1 == ~E_6~0); 4169502#L1227-1 assume !(1 == ~E_7~0); 4169503#L1232-1 assume !(1 == ~E_8~0); 4168593#L1237-1 assume !(1 == ~E_9~0); 4168594#L1242-1 assume !(1 == ~E_10~0); 4169579#L1247-1 assume { :end_inline_reset_delta_events } true; 4169580#L1553-2 [2022-12-13 12:31:46,212 INFO L750 eck$LassoCheckResult]: Loop: 4169580#L1553-2 assume !false; 4262992#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4262987#L999 assume !false; 4262985#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4262983#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4262971#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4262970#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4262965#L854 assume !(0 != eval_~tmp~0#1); 4262966#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4288408#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4288407#L1024-3 assume !(0 == ~M_E~0); 4288406#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4288405#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4288404#L1034-3 assume !(0 == ~T3_E~0); 4288403#L1039-3 assume !(0 == ~T4_E~0); 4288402#L1044-3 assume !(0 == ~T5_E~0); 4288400#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4288398#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4288396#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4288394#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4288392#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4288390#L1074-3 assume !(0 == ~E_M~0); 4288388#L1079-3 assume !(0 == ~E_1~0); 4288386#L1084-3 assume !(0 == ~E_2~0); 4288384#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4288382#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4288380#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4288378#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4288376#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4288374#L1114-3 assume !(0 == ~E_8~0); 4288372#L1119-3 assume !(0 == ~E_9~0); 4288370#L1124-3 assume !(0 == ~E_10~0); 4288368#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4288366#L502-36 assume !(1 == ~m_pc~0); 4288364#L502-38 is_master_triggered_~__retres1~0#1 := 0; 4288362#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4288359#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4288360#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4288785#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4288783#L521-36 assume !(1 == ~t1_pc~0); 4288349#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 4288345#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4288343#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4288341#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4288339#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4288337#L540-36 assume !(1 == ~t2_pc~0); 4288031#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 4288180#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4288179#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4288178#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4288177#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4168591#L559-36 assume !(1 == ~t3_pc~0); 4168592#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 4169042#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4169221#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4169222#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4169605#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4169895#L578-36 assume 1 == ~t4_pc~0; 4169567#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4169568#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4288864#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4288863#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4169331#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4169332#L597-36 assume !(1 == ~t5_pc~0); 4169587#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4288455#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4288452#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4288449#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 4288444#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4288442#L616-36 assume 1 == ~t6_pc~0; 4288439#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4288437#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4288435#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4288433#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4169771#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4169772#L635-36 assume !(1 == ~t7_pc~0); 4283226#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4283225#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4283223#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4283221#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4283219#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4283217#L654-36 assume 1 == ~t8_pc~0; 4283213#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4283211#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4283209#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4283207#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4282944#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4236443#L673-36 assume !(1 == ~t9_pc~0); 4236441#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4236439#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4236435#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4236433#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4236431#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4236429#L692-36 assume !(1 == ~t10_pc~0); 4236425#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4236423#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4236421#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4236418#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4236416#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4236414#L1142-3 assume !(1 == ~M_E~0); 4197868#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4236411#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4236409#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4236406#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4236404#L1162-3 assume !(1 == ~T5_E~0); 4236402#L1167-3 assume !(1 == ~T6_E~0); 4236400#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4236398#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4236395#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4236394#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4236391#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4236389#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4236387#L1202-3 assume !(1 == ~E_2~0); 4236385#L1207-3 assume !(1 == ~E_3~0); 4236383#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4236381#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4236378#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4236376#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4236374#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4236372#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4236370#L1242-3 assume !(1 == ~E_10~0); 4236367#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4236342#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4236341#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4236339#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 4213323#L1572 assume !(0 == start_simulation_~tmp~3#1); 4213324#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4263016#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4263005#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4263004#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 4263002#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4263000#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4262998#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4262996#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 4169580#L1553-2 [2022-12-13 12:31:46,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:46,212 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 1 times [2022-12-13 12:31:46,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:46,212 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [595652074] [2022-12-13 12:31:46,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:46,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:46,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:31:46,218 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:31:46,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:31:46,263 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:31:46,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:46,263 INFO L85 PathProgramCache]: Analyzing trace with hash -1994588545, now seen corresponding path program 1 times [2022-12-13 12:31:46,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:46,263 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164872059] [2022-12-13 12:31:46,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:46,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:46,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:46,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:46,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:46,286 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [164872059] [2022-12-13 12:31:46,286 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [164872059] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:46,286 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:46,286 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:46,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675850706] [2022-12-13 12:31:46,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:46,287 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:46,287 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:46,287 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:31:46,287 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:31:46,287 INFO L87 Difference]: Start difference. First operand 120328 states and 168383 transitions. cyclomatic complexity: 48059 Second operand has 3 states, 3 states have (on average 44.666666666666664) internal successors, (134), 3 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:46,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:46,554 INFO L93 Difference]: Finished difference Result 133225 states and 186563 transitions. [2022-12-13 12:31:46,554 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 133225 states and 186563 transitions. [2022-12-13 12:31:46,992 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 132800 [2022-12-13 12:31:47,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 133225 states to 133225 states and 186563 transitions. [2022-12-13 12:31:47,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 133225 [2022-12-13 12:31:47,308 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 133225 [2022-12-13 12:31:47,308 INFO L73 IsDeterministic]: Start isDeterministic. Operand 133225 states and 186563 transitions. [2022-12-13 12:31:47,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:31:47,540 INFO L218 hiAutomatonCegarLoop]: Abstraction has 133225 states and 186563 transitions. [2022-12-13 12:31:47,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133225 states and 186563 transitions. [2022-12-13 12:31:48,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133225 to 133225. [2022-12-13 12:31:48,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133225 states, 133225 states have (on average 1.4003602927378496) internal successors, (186563), 133224 states have internal predecessors, (186563), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:48,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133225 states to 133225 states and 186563 transitions. [2022-12-13 12:31:48,703 INFO L240 hiAutomatonCegarLoop]: Abstraction has 133225 states and 186563 transitions. [2022-12-13 12:31:48,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:31:48,704 INFO L428 stractBuchiCegarLoop]: Abstraction has 133225 states and 186563 transitions. [2022-12-13 12:31:48,704 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-12-13 12:31:48,704 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 133225 states and 186563 transitions. [2022-12-13 12:31:49,082 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 132800 [2022-12-13 12:31:49,082 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:49,082 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:49,087 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:49,088 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:49,088 INFO L748 eck$LassoCheckResult]: Stem: 4422519#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4422520#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4423576#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4423577#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4423155#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 4422798#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4422799#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4423115#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4423333#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4422987#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4422988#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4422854#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4422855#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4423268#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4423215#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4423125#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4423126#L1024 assume !(0 == ~M_E~0); 4423461#L1024-2 assume !(0 == ~T1_E~0); 4422515#L1029-1 assume !(0 == ~T2_E~0); 4422516#L1034-1 assume !(0 == ~T3_E~0); 4422616#L1039-1 assume !(0 == ~T4_E~0); 4423613#L1044-1 assume !(0 == ~T5_E~0); 4422877#L1049-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4422878#L1054-1 assume !(0 == ~T7_E~0); 4423790#L1059-1 assume !(0 == ~T8_E~0); 4423854#L1064-1 assume !(0 == ~T9_E~0); 4423853#L1069-1 assume !(0 == ~T10_E~0); 4423742#L1074-1 assume !(0 == ~E_M~0); 4423498#L1079-1 assume !(0 == ~E_1~0); 4423463#L1084-1 assume !(0 == ~E_2~0); 4423464#L1089-1 assume !(0 == ~E_3~0); 4423850#L1094-1 assume !(0 == ~E_4~0); 4423849#L1099-1 assume !(0 == ~E_5~0); 4423640#L1104-1 assume !(0 == ~E_6~0); 4423641#L1109-1 assume !(0 == ~E_7~0); 4422733#L1114-1 assume !(0 == ~E_8~0); 4422734#L1119-1 assume !(0 == ~E_9~0); 4422808#L1124-1 assume !(0 == ~E_10~0); 4422809#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4423320#L502 assume !(1 == ~m_pc~0); 4423321#L502-2 is_master_triggered_~__retres1~0#1 := 0; 4423848#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4423847#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4423209#L1273 assume !(0 != activate_threads_~tmp~1#1); 4423210#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4423682#L521 assume !(1 == ~t1_pc~0); 4423683#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4423846#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4422232#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4422233#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 4423845#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4423844#L540 assume !(1 == ~t2_pc~0); 4423097#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4423098#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4423482#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4423743#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 4423553#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4422546#L559 assume !(1 == ~t3_pc~0); 4422547#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4422829#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4422172#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4422173#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 4423837#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4423756#L578 assume !(1 == ~t4_pc~0); 4423428#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4423429#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4423458#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4423664#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 4423665#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4423708#L597 assume !(1 == ~t5_pc~0); 4423709#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4422288#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4422289#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4423459#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 4423127#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4423128#L616 assume !(1 == ~t6_pc~0); 4423149#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4423148#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4422703#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4422704#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 4422965#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4422966#L635 assume !(1 == ~t7_pc~0); 4423832#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4423831#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4423761#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4423514#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 4423515#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4423829#L654 assume !(1 == ~t8_pc~0); 4423827#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4423826#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4423825#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4423824#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 4423823#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4423822#L673 assume !(1 == ~t9_pc~0); 4422207#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4422208#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4423821#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4423820#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 4423819#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4423817#L692 assume !(1 == ~t10_pc~0); 4423816#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4423815#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4423814#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4423813#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 4423812#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4423777#L1142 assume !(1 == ~M_E~0); 4423778#L1142-2 assume !(1 == ~T1_E~0); 4423811#L1147-1 assume !(1 == ~T2_E~0); 4423776#L1152-1 assume !(1 == ~T3_E~0); 4422837#L1157-1 assume !(1 == ~T4_E~0); 4422838#L1162-1 assume !(1 == ~T5_E~0); 4423006#L1167-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4423007#L1172-1 assume !(1 == ~T7_E~0); 4423538#L1177-1 assume !(1 == ~T8_E~0); 4423174#L1182-1 assume !(1 == ~T9_E~0); 4423175#L1187-1 assume !(1 == ~T10_E~0); 4423299#L1192-1 assume !(1 == ~E_M~0); 4422679#L1197-1 assume !(1 == ~E_1~0); 4422680#L1202-1 assume !(1 == ~E_2~0); 4423101#L1207-1 assume !(1 == ~E_3~0); 4423074#L1212-1 assume !(1 == ~E_4~0); 4422272#L1217-1 assume !(1 == ~E_5~0); 4422273#L1222-1 assume !(1 == ~E_6~0); 4423070#L1227-1 assume !(1 == ~E_7~0); 4423071#L1232-1 assume !(1 == ~E_8~0); 4422152#L1237-1 assume !(1 == ~E_9~0); 4422153#L1242-1 assume !(1 == ~E_10~0); 4423152#L1247-1 assume { :end_inline_reset_delta_events } true; 4423153#L1553-2 [2022-12-13 12:31:49,088 INFO L750 eck$LassoCheckResult]: Loop: 4423153#L1553-2 assume !false; 4512183#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4512178#L999 assume !false; 4512177#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4512176#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4512165#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4512164#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4512161#L854 assume !(0 != eval_~tmp~0#1); 4512162#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4520918#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4520917#L1024-3 assume !(0 == ~M_E~0); 4520916#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4520914#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4520912#L1034-3 assume !(0 == ~T3_E~0); 4520910#L1039-3 assume !(0 == ~T4_E~0); 4520908#L1044-3 assume !(0 == ~T5_E~0); 4520905#L1049-3 assume !(0 == ~T6_E~0); 4520903#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4520901#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4520899#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4520897#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4520895#L1074-3 assume !(0 == ~E_M~0); 4520893#L1079-3 assume !(0 == ~E_1~0); 4520891#L1084-3 assume !(0 == ~E_2~0); 4520889#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4520887#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4520885#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4520883#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4520881#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4520879#L1114-3 assume !(0 == ~E_8~0); 4520877#L1119-3 assume !(0 == ~E_9~0); 4520875#L1124-3 assume !(0 == ~E_10~0); 4520873#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4520871#L502-36 assume !(1 == ~m_pc~0); 4520869#L502-38 is_master_triggered_~__retres1~0#1 := 0; 4520866#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4520864#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4520862#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4520860#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4520858#L521-36 assume 1 == ~t1_pc~0; 4520855#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4520853#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4520851#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4520849#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4520847#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4512522#L540-36 assume !(1 == ~t2_pc~0); 4512520#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 4512518#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4512515#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4512513#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4512511#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4512509#L559-36 assume !(1 == ~t3_pc~0); 4475728#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 4512506#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4512505#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4512503#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4512501#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4512499#L578-36 assume !(1 == ~t4_pc~0); 4512495#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 4512494#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4512491#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4512489#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 4512486#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4512484#L597-36 assume !(1 == ~t5_pc~0); 4512482#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4512480#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4512479#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4512478#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 4512474#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4512472#L616-36 assume 1 == ~t6_pc~0; 4512469#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4512468#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4512467#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4512466#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4512465#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4512464#L635-36 assume !(1 == ~t7_pc~0); 4480379#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4512463#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4512462#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4512461#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4512460#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4512459#L654-36 assume 1 == ~t8_pc~0; 4512457#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4512455#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4512453#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4512451#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4512449#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4512447#L673-36 assume !(1 == ~t9_pc~0); 4471613#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4512444#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4512442#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4512440#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4512438#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4512436#L692-36 assume !(1 == ~t10_pc~0); 4512433#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4512431#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4512429#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4512427#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4512425#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4512423#L1142-3 assume !(1 == ~M_E~0); 4473346#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4512420#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4512418#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4512417#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4512416#L1162-3 assume !(1 == ~T5_E~0); 4512300#L1167-3 assume !(1 == ~T6_E~0); 4512298#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4512296#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4512294#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4512292#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4512290#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4512288#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4512286#L1202-3 assume !(1 == ~E_2~0); 4512283#L1207-3 assume !(1 == ~E_3~0); 4512281#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4512279#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4512277#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4512275#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4512273#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4512272#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4512270#L1242-3 assume !(1 == ~E_10~0); 4512268#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4512245#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4512243#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4512241#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 4512238#L1572 assume !(0 == start_simulation_~tmp~3#1); 4512235#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4512219#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4512207#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4512202#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 4512199#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4512194#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4512191#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4512186#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 4423153#L1553-2 [2022-12-13 12:31:49,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:49,089 INFO L85 PathProgramCache]: Analyzing trace with hash 800900745, now seen corresponding path program 1 times [2022-12-13 12:31:49,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:49,089 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903258027] [2022-12-13 12:31:49,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:49,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:49,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:49,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:49,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:49,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [903258027] [2022-12-13 12:31:49,140 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [903258027] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:49,140 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:49,140 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:49,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [171717330] [2022-12-13 12:31:49,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:49,140 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:31:49,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:49,141 INFO L85 PathProgramCache]: Analyzing trace with hash 1126590463, now seen corresponding path program 1 times [2022-12-13 12:31:49,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:49,141 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098610888] [2022-12-13 12:31:49,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:49,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:49,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:49,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:49,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:49,183 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1098610888] [2022-12-13 12:31:49,183 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1098610888] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:49,183 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:49,183 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:49,183 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [950050596] [2022-12-13 12:31:49,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:49,184 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:49,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:49,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:31:49,184 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:31:49,184 INFO L87 Difference]: Start difference. First operand 133225 states and 186563 transitions. cyclomatic complexity: 53342 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:49,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:49,621 INFO L93 Difference]: Finished difference Result 176504 states and 246315 transitions. [2022-12-13 12:31:49,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176504 states and 246315 transitions. [2022-12-13 12:31:50,401 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 176064 [2022-12-13 12:31:50,656 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176504 states to 176504 states and 246315 transitions. [2022-12-13 12:31:50,656 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176504 [2022-12-13 12:31:50,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176504 [2022-12-13 12:31:50,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176504 states and 246315 transitions. [2022-12-13 12:31:50,764 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:31:50,764 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176504 states and 246315 transitions. [2022-12-13 12:31:50,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176504 states and 246315 transitions. [2022-12-13 12:31:51,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176504 to 120328. [2022-12-13 12:31:51,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120328 states, 120328 states have (on average 1.3982946612592249) internal successors, (168254), 120327 states have internal predecessors, (168254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:51,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120328 states to 120328 states and 168254 transitions. [2022-12-13 12:31:51,877 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120328 states and 168254 transitions. [2022-12-13 12:31:51,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:31:51,878 INFO L428 stractBuchiCegarLoop]: Abstraction has 120328 states and 168254 transitions. [2022-12-13 12:31:51,878 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-12-13 12:31:51,878 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120328 states and 168254 transitions. [2022-12-13 12:31:52,168 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 120000 [2022-12-13 12:31:52,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:52,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:52,172 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:52,172 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:52,173 INFO L748 eck$LassoCheckResult]: Stem: 4732256#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4732257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4733276#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4733277#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4732884#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 4732540#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4732541#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4732847#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4733038#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4732724#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4732725#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4732596#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4732597#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4732983#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4732941#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4732856#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4732857#L1024 assume !(0 == ~M_E~0); 4733158#L1024-2 assume !(0 == ~T1_E~0); 4732252#L1029-1 assume !(0 == ~T2_E~0); 4732253#L1034-1 assume !(0 == ~T3_E~0); 4732356#L1039-1 assume !(0 == ~T4_E~0); 4733306#L1044-1 assume !(0 == ~T5_E~0); 4732617#L1049-1 assume !(0 == ~T6_E~0); 4732618#L1054-1 assume !(0 == ~T7_E~0); 4732883#L1059-1 assume !(0 == ~T8_E~0); 4732305#L1064-1 assume !(0 == ~T9_E~0); 4732306#L1069-1 assume !(0 == ~T10_E~0); 4733123#L1074-1 assume !(0 == ~E_M~0); 4733195#L1079-1 assume !(0 == ~E_1~0); 4733160#L1084-1 assume !(0 == ~E_2~0); 4733161#L1089-1 assume !(0 == ~E_3~0); 4733218#L1094-1 assume !(0 == ~E_4~0); 4732712#L1099-1 assume !(0 == ~E_5~0); 4732713#L1104-1 assume !(0 == ~E_6~0); 4733004#L1109-1 assume !(0 == ~E_7~0); 4732473#L1114-1 assume !(0 == ~E_8~0); 4732474#L1119-1 assume !(0 == ~E_9~0); 4732552#L1124-1 assume !(0 == ~E_10~0); 4731957#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4731958#L502 assume !(1 == ~m_pc~0); 4732148#L502-2 is_master_triggered_~__retres1~0#1 := 0; 4732080#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4732081#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4732937#L1273 assume !(0 != activate_threads_~tmp~1#1); 4732938#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4733362#L521 assume !(1 == ~t1_pc~0); 4733262#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4732007#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4731972#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4731973#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 4731993#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4731994#L540 assume !(1 == ~t2_pc~0); 4732832#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4732833#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4732471#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4732472#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 4733252#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4732283#L559 assume !(1 == ~t3_pc~0); 4732284#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4732571#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4731912#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4731913#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 4732098#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4732099#L578 assume !(1 == ~t4_pc~0); 4732218#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4733128#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4732040#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4732041#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 4732917#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4732918#L597 assume !(1 == ~t5_pc~0); 4732868#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4732028#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4732029#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4733156#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 4732858#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4732859#L616 assume !(1 == ~t6_pc~0); 4732880#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4732879#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4732445#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4732446#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 4732701#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4732702#L635 assume !(1 == ~t7_pc~0); 4731995#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4731996#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4732375#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4733214#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 4732850#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4732851#L654 assume !(1 == ~t8_pc~0); 4732645#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4732646#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4733072#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4733073#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 4733120#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4732251#L673 assume !(1 == ~t9_pc~0); 4731947#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4731948#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4732533#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4732534#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 4733017#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4733018#L692 assume !(1 == ~t10_pc~0); 4732956#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4733003#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4732703#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4732704#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 4732717#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4733095#L1142 assume !(1 == ~M_E~0); 4732156#L1142-2 assume !(1 == ~T1_E~0); 4732157#L1147-1 assume !(1 == ~T2_E~0); 4733078#L1152-1 assume !(1 == ~T3_E~0); 4732577#L1157-1 assume !(1 == ~T4_E~0); 4732578#L1162-1 assume !(1 == ~T5_E~0); 4732742#L1167-1 assume !(1 == ~T6_E~0); 4732743#L1172-1 assume !(1 == ~T7_E~0); 4733237#L1177-1 assume !(1 == ~T8_E~0); 4732901#L1182-1 assume !(1 == ~T9_E~0); 4732902#L1187-1 assume !(1 == ~T10_E~0); 4733010#L1192-1 assume !(1 == ~E_M~0); 4732420#L1197-1 assume !(1 == ~E_1~0); 4732421#L1202-1 assume !(1 == ~E_2~0); 4732838#L1207-1 assume !(1 == ~E_3~0); 4732809#L1212-1 assume !(1 == ~E_4~0); 4732012#L1217-1 assume !(1 == ~E_5~0); 4732013#L1222-1 assume !(1 == ~E_6~0); 4732806#L1227-1 assume !(1 == ~E_7~0); 4732807#L1232-1 assume !(1 == ~E_8~0); 4731891#L1237-1 assume !(1 == ~E_9~0); 4731892#L1242-1 assume !(1 == ~E_10~0); 4732881#L1247-1 assume { :end_inline_reset_delta_events } true; 4732882#L1553-2 [2022-12-13 12:31:52,173 INFO L750 eck$LassoCheckResult]: Loop: 4732882#L1553-2 assume !false; 4786360#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4786354#L999 assume !false; 4785832#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4785486#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4785474#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4785363#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4785352#L854 assume !(0 != eval_~tmp~0#1); 4785353#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4842678#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4842677#L1024-3 assume !(0 == ~M_E~0); 4842676#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4842675#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4842674#L1034-3 assume !(0 == ~T3_E~0); 4842673#L1039-3 assume !(0 == ~T4_E~0); 4842672#L1044-3 assume !(0 == ~T5_E~0); 4842671#L1049-3 assume !(0 == ~T6_E~0); 4842670#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4842669#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4790357#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4790355#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4790352#L1074-3 assume !(0 == ~E_M~0); 4790353#L1079-3 assume !(0 == ~E_1~0); 4842660#L1084-3 assume !(0 == ~E_2~0); 4842658#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4842656#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4842654#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4842652#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4842649#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4842647#L1114-3 assume !(0 == ~E_8~0); 4842645#L1119-3 assume !(0 == ~E_9~0); 4842643#L1124-3 assume !(0 == ~E_10~0); 4842641#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4842638#L502-36 assume !(1 == ~m_pc~0); 4842636#L502-38 is_master_triggered_~__retres1~0#1 := 0; 4842634#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4842632#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4842630#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4842628#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4842625#L521-36 assume 1 == ~t1_pc~0; 4842621#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4842619#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4842617#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4842615#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4842613#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4790027#L540-36 assume !(1 == ~t2_pc~0); 4790025#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 4790023#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4790020#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4790017#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4790014#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4790011#L559-36 assume !(1 == ~t3_pc~0); 4787593#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 4790008#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4790004#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4789999#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4789995#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4789991#L578-36 assume !(1 == ~t4_pc~0); 4789987#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 4789982#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4789976#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4789970#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 4789964#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4789959#L597-36 assume !(1 == ~t5_pc~0); 4789954#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4789950#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4789947#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4789943#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 4789939#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4789935#L616-36 assume !(1 == ~t6_pc~0); 4789931#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 4789926#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4789921#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4789916#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4788356#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4763533#L635-36 assume !(1 == ~t7_pc~0); 4763525#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4763517#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4763510#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4763503#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4763496#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4763485#L654-36 assume 1 == ~t8_pc~0; 4763474#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4763463#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4763454#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4763445#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4763436#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4763068#L673-36 assume !(1 == ~t9_pc~0); 4763064#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4763061#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4763058#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4763055#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4763052#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4763049#L692-36 assume !(1 == ~t10_pc~0); 4763045#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4763042#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4763038#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4763034#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4763031#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4763029#L1142-3 assume !(1 == ~M_E~0); 4747263#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4762996#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4762994#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4762992#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4762990#L1162-3 assume !(1 == ~T5_E~0); 4762988#L1167-3 assume !(1 == ~T6_E~0); 4762986#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4762984#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4762982#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4762980#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4762977#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4762975#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4762973#L1202-3 assume !(1 == ~E_2~0); 4762971#L1207-3 assume !(1 == ~E_3~0); 4762969#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4762966#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4762965#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4762962#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4762960#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4762958#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4762956#L1242-3 assume !(1 == ~E_10~0); 4762954#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4762932#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4762926#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4762920#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 4762719#L1572 assume !(0 == start_simulation_~tmp~3#1); 4762720#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4786387#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4786375#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4786370#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 4786367#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4786366#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4786365#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4786363#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 4732882#L1553-2 [2022-12-13 12:31:52,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:52,173 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 2 times [2022-12-13 12:31:52,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:52,174 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775556302] [2022-12-13 12:31:52,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:52,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:52,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:31:52,182 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:31:52,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:31:52,219 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:31:52,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:52,220 INFO L85 PathProgramCache]: Analyzing trace with hash 1504233280, now seen corresponding path program 1 times [2022-12-13 12:31:52,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:52,220 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054576950] [2022-12-13 12:31:52,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:52,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:52,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:52,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:52,240 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:52,240 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054576950] [2022-12-13 12:31:52,240 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1054576950] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:52,240 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:52,240 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:52,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1620706133] [2022-12-13 12:31:52,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:52,241 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:52,241 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:52,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:31:52,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:31:52,241 INFO L87 Difference]: Start difference. First operand 120328 states and 168254 transitions. cyclomatic complexity: 47930 Second operand has 3 states, 3 states have (on average 44.666666666666664) internal successors, (134), 3 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:52,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:52,950 INFO L93 Difference]: Finished difference Result 224473 states and 311251 transitions. [2022-12-13 12:31:52,950 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 224473 states and 311251 transitions. [2022-12-13 12:31:53,726 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 223856 [2022-12-13 12:31:54,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 224473 states to 224473 states and 311251 transitions. [2022-12-13 12:31:54,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 224473 [2022-12-13 12:31:54,182 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 224473 [2022-12-13 12:31:54,182 INFO L73 IsDeterministic]: Start isDeterministic. Operand 224473 states and 311251 transitions. [2022-12-13 12:31:54,414 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:31:54,414 INFO L218 hiAutomatonCegarLoop]: Abstraction has 224473 states and 311251 transitions. [2022-12-13 12:31:54,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224473 states and 311251 transitions. [2022-12-13 12:31:55,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224473 to 224409. [2022-12-13 12:31:56,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224409 states, 224409 states have (on average 1.3866957207598625) internal successors, (311187), 224408 states have internal predecessors, (311187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:56,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224409 states to 224409 states and 311187 transitions. [2022-12-13 12:31:56,334 INFO L240 hiAutomatonCegarLoop]: Abstraction has 224409 states and 311187 transitions. [2022-12-13 12:31:56,335 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:31:56,335 INFO L428 stractBuchiCegarLoop]: Abstraction has 224409 states and 311187 transitions. [2022-12-13 12:31:56,335 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-12-13 12:31:56,336 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 224409 states and 311187 transitions. [2022-12-13 12:31:57,011 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 223792 [2022-12-13 12:31:57,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:31:57,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:31:57,016 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:57,016 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:31:57,016 INFO L748 eck$LassoCheckResult]: Stem: 5077057#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5077058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 5078126#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5078127#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5077698#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 5077341#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5077342#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5077660#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5077870#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5077534#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5077535#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5077399#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5077400#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5077815#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5077761#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 5077670#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5077671#L1024 assume !(0 == ~M_E~0); 5078004#L1024-2 assume !(0 == ~T1_E~0); 5077053#L1029-1 assume !(0 == ~T2_E~0); 5077054#L1034-1 assume !(0 == ~T3_E~0); 5077155#L1039-1 assume !(0 == ~T4_E~0); 5078161#L1044-1 assume !(0 == ~T5_E~0); 5077421#L1049-1 assume !(0 == ~T6_E~0); 5077422#L1054-1 assume !(0 == ~T7_E~0); 5077697#L1059-1 assume !(0 == ~T8_E~0); 5077105#L1064-1 assume !(0 == ~T9_E~0); 5077106#L1069-1 assume !(0 == ~T10_E~0); 5077961#L1074-1 assume !(0 == ~E_M~0); 5078045#L1079-1 assume !(0 == ~E_1~0); 5078007#L1084-1 assume !(0 == ~E_2~0); 5078008#L1089-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5078072#L1094-1 assume !(0 == ~E_4~0); 5077521#L1099-1 assume !(0 == ~E_5~0); 5077522#L1104-1 assume !(0 == ~E_6~0); 5077835#L1109-1 assume !(0 == ~E_7~0); 5077836#L1114-1 assume !(0 == ~E_8~0); 5078317#L1119-1 assume !(0 == ~E_9~0); 5077352#L1124-1 assume !(0 == ~E_10~0); 5077353#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5078424#L502 assume !(1 == ~m_pc~0); 5076951#L502-2 is_master_triggered_~__retres1~0#1 := 0; 5076885#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5076886#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5077998#L1273 assume !(0 != activate_threads_~tmp~1#1); 5078356#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5078357#L521 assume !(1 == ~t1_pc~0); 5078110#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5076811#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5076777#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5076778#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 5078419#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5078418#L540 assume !(1 == ~t2_pc~0); 5077644#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5077645#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5078026#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5078294#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 5078102#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5077084#L559 assume !(1 == ~t3_pc~0); 5077085#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5077375#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5076717#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5076718#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 5076903#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5076904#L578 assume !(1 == ~t4_pc~0); 5077966#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5077967#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5078001#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5078209#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 5078210#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5078259#L597 assume !(1 == ~t5_pc~0); 5078260#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5076832#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5076833#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5078002#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 5078348#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5077749#L616 assume !(1 == ~t6_pc~0); 5077692#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5077691#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5077248#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5077249#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 5077510#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5077511#L635 assume !(1 == ~t7_pc~0); 5076799#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5076800#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5077172#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5078393#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 5077664#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5077665#L654 assume !(1 == ~t8_pc~0); 5077451#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5077452#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5077905#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5077906#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 5077958#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5077052#L673 assume !(1 == ~t9_pc~0); 5076752#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5076753#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5077335#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5077336#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 5077849#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5077850#L692 assume !(1 == ~t10_pc~0); 5077784#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5077834#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5077513#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5077514#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 5077527#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5077931#L1142 assume !(1 == ~M_E~0); 5076962#L1142-2 assume !(1 == ~T1_E~0); 5076963#L1147-1 assume !(1 == ~T2_E~0); 5077912#L1152-1 assume !(1 == ~T3_E~0); 5077384#L1157-1 assume !(1 == ~T4_E~0); 5077385#L1162-1 assume !(1 == ~T5_E~0); 5077554#L1167-1 assume !(1 == ~T6_E~0); 5077555#L1172-1 assume !(1 == ~T7_E~0); 5078089#L1177-1 assume !(1 == ~T8_E~0); 5077717#L1182-1 assume !(1 == ~T9_E~0); 5077718#L1187-1 assume !(1 == ~T10_E~0); 5077842#L1192-1 assume !(1 == ~E_M~0); 5077222#L1197-1 assume !(1 == ~E_1~0); 5077223#L1202-1 assume !(1 == ~E_2~0); 5077648#L1207-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5077621#L1212-1 assume !(1 == ~E_4~0); 5076816#L1217-1 assume !(1 == ~E_5~0); 5076817#L1222-1 assume !(1 == ~E_6~0); 5077618#L1227-1 assume !(1 == ~E_7~0); 5077619#L1232-1 assume !(1 == ~E_8~0); 5076697#L1237-1 assume !(1 == ~E_9~0); 5076698#L1242-1 assume !(1 == ~E_10~0); 5077695#L1247-1 assume { :end_inline_reset_delta_events } true; 5077696#L1553-2 [2022-12-13 12:31:57,016 INFO L750 eck$LassoCheckResult]: Loop: 5077696#L1553-2 assume !false; 5267646#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5267641#L999 assume !false; 5267640#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5267639#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5267628#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5267626#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5267624#L854 assume !(0 != eval_~tmp~0#1); 5267625#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5275627#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5258682#L1024-3 assume !(0 == ~M_E~0); 5258677#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5258673#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5258667#L1034-3 assume !(0 == ~T3_E~0); 5258659#L1039-3 assume !(0 == ~T4_E~0); 5258653#L1044-3 assume !(0 == ~T5_E~0); 5258647#L1049-3 assume !(0 == ~T6_E~0); 5258641#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5258635#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5258631#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5258626#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5258624#L1074-3 assume !(0 == ~E_M~0); 5258618#L1079-3 assume !(0 == ~E_1~0); 5258613#L1084-3 assume !(0 == ~E_2~0); 5258607#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5258608#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5276767#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5276766#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5276765#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5276764#L1114-3 assume !(0 == ~E_8~0); 5276763#L1119-3 assume !(0 == ~E_9~0); 5276762#L1124-3 assume !(0 == ~E_10~0); 5276761#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5276760#L502-36 assume !(1 == ~m_pc~0); 5276759#L502-38 is_master_triggered_~__retres1~0#1 := 0; 5276758#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5276757#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5276753#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5276751#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5276749#L521-36 assume 1 == ~t1_pc~0; 5276745#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5276743#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5276741#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5276739#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5276737#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5276735#L540-36 assume !(1 == ~t2_pc~0); 5213958#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5276731#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5276729#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5276727#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5276725#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5257923#L559-36 assume !(1 == ~t3_pc~0); 5257921#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 5257919#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5257648#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5257637#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5257626#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5257617#L578-36 assume 1 == ~t4_pc~0; 5257607#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5257552#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5257384#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5257375#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5257367#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5257359#L597-36 assume !(1 == ~t5_pc~0); 5257350#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 5257342#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5257306#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5257301#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 5257293#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5257268#L616-36 assume 1 == ~t6_pc~0; 5257266#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5257265#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5257264#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5257263#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5257261#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5257259#L635-36 assume !(1 == ~t7_pc~0); 5149545#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 5257256#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5257254#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5257252#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5257250#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5257247#L654-36 assume 1 == ~t8_pc~0; 5257219#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5257207#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5257196#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5257183#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5257029#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5255318#L673-36 assume !(1 == ~t9_pc~0); 5255313#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5255125#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5255124#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5255122#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5255120#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5255083#L692-36 assume !(1 == ~t10_pc~0); 5255077#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 5255069#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5255064#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5255059#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5255050#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5255036#L1142-3 assume !(1 == ~M_E~0); 5255035#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5256944#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5256943#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5256942#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5256941#L1162-3 assume !(1 == ~T5_E~0); 5256940#L1167-3 assume !(1 == ~T6_E~0); 5256939#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5256938#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5256937#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5256936#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5256935#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5256934#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5256933#L1202-3 assume !(1 == ~E_2~0); 5256932#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5256930#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5256929#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5256928#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5256927#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5256926#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5256925#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5254730#L1242-3 assume !(1 == ~E_10~0); 5254723#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5254724#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5254646#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5254647#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5254629#L1572 assume !(0 == start_simulation_~tmp~3#1); 5254630#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5267673#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5267660#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5267658#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 5267656#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5267655#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5267654#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 5267650#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 5077696#L1553-2 [2022-12-13 12:31:57,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:57,017 INFO L85 PathProgramCache]: Analyzing trace with hash -184383863, now seen corresponding path program 1 times [2022-12-13 12:31:57,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:57,017 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1166297594] [2022-12-13 12:31:57,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:57,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:57,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:57,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:57,058 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:57,058 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1166297594] [2022-12-13 12:31:57,058 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1166297594] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:57,058 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:57,058 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:31:57,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1218825562] [2022-12-13 12:31:57,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:57,059 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:31:57,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:31:57,059 INFO L85 PathProgramCache]: Analyzing trace with hash 162277690, now seen corresponding path program 1 times [2022-12-13 12:31:57,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:31:57,059 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429574477] [2022-12-13 12:31:57,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:31:57,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:31:57,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:31:57,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:31:57,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:31:57,104 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [429574477] [2022-12-13 12:31:57,104 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [429574477] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:31:57,104 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:31:57,105 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:31:57,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280370559] [2022-12-13 12:31:57,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:31:57,105 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:31:57,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:31:57,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:31:57,106 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:31:57,106 INFO L87 Difference]: Start difference. First operand 224409 states and 311187 transitions. cyclomatic complexity: 86782 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:31:58,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:31:58,039 INFO L93 Difference]: Finished difference Result 328640 states and 454939 transitions. [2022-12-13 12:31:58,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 328640 states and 454939 transitions. [2022-12-13 12:31:59,101 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 320432 [2022-12-13 12:31:59,789 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 328640 states to 328640 states and 454939 transitions. [2022-12-13 12:31:59,789 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 328640 [2022-12-13 12:31:59,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 328640 [2022-12-13 12:31:59,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 328640 states and 454939 transitions. [2022-12-13 12:32:00,002 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:32:00,002 INFO L218 hiAutomatonCegarLoop]: Abstraction has 328640 states and 454939 transitions. [2022-12-13 12:32:00,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 328640 states and 454939 transitions. [2022-12-13 12:32:01,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 328640 to 224312. [2022-12-13 12:32:01,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224312 states, 224312 states have (on average 1.3861273583223368) internal successors, (310925), 224311 states have internal predecessors, (310925), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:32:02,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224312 states to 224312 states and 310925 transitions. [2022-12-13 12:32:02,279 INFO L240 hiAutomatonCegarLoop]: Abstraction has 224312 states and 310925 transitions. [2022-12-13 12:32:02,279 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:32:02,280 INFO L428 stractBuchiCegarLoop]: Abstraction has 224312 states and 310925 transitions. [2022-12-13 12:32:02,280 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-12-13 12:32:02,280 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 224312 states and 310925 transitions. [2022-12-13 12:32:02,742 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 223792 [2022-12-13 12:32:02,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:32:02,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:32:02,747 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:32:02,747 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:32:02,747 INFO L748 eck$LassoCheckResult]: Stem: 5630120#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5630121#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 5631146#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5631147#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5630754#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 5630403#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5630404#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5630716#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5630917#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5630591#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5630592#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5630459#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5630460#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5630860#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5630812#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 5630726#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5630727#L1024 assume !(0 == ~M_E~0); 5631038#L1024-2 assume !(0 == ~T1_E~0); 5630116#L1029-1 assume !(0 == ~T2_E~0); 5630117#L1034-1 assume !(0 == ~T3_E~0); 5630219#L1039-1 assume !(0 == ~T4_E~0); 5631182#L1044-1 assume !(0 == ~T5_E~0); 5630481#L1049-1 assume !(0 == ~T6_E~0); 5630482#L1054-1 assume !(0 == ~T7_E~0); 5630753#L1059-1 assume !(0 == ~T8_E~0); 5630170#L1064-1 assume !(0 == ~T9_E~0); 5630171#L1069-1 assume !(0 == ~T10_E~0); 5630999#L1074-1 assume !(0 == ~E_M~0); 5631076#L1079-1 assume !(0 == ~E_1~0); 5631040#L1084-1 assume !(0 == ~E_2~0); 5631041#L1089-1 assume !(0 == ~E_3~0); 5631097#L1094-1 assume !(0 == ~E_4~0); 5630579#L1099-1 assume !(0 == ~E_5~0); 5630580#L1104-1 assume !(0 == ~E_6~0); 5630881#L1109-1 assume !(0 == ~E_7~0); 5630337#L1114-1 assume !(0 == ~E_8~0); 5630338#L1119-1 assume !(0 == ~E_9~0); 5630414#L1124-1 assume !(0 == ~E_10~0); 5629824#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5629825#L502 assume !(1 == ~m_pc~0); 5630014#L502-2 is_master_triggered_~__retres1~0#1 := 0; 5629948#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5629949#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5630806#L1273 assume !(0 != activate_threads_~tmp~1#1); 5630807#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5631249#L521 assume !(1 == ~t1_pc~0); 5631134#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5629874#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5629839#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5629840#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 5629859#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5629860#L540 assume !(1 == ~t2_pc~0); 5630701#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5630702#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5630333#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5630334#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 5631127#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5630149#L559 assume !(1 == ~t3_pc~0); 5630150#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5630435#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5629779#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5629780#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 5629966#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5629967#L578 assume !(1 == ~t4_pc~0); 5630082#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5631008#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5629907#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5629908#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 5630786#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5630787#L597 assume !(1 == ~t5_pc~0); 5630737#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5629895#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5629896#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5631036#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 5630724#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5630725#L616 assume !(1 == ~t6_pc~0); 5630748#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5630747#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5630309#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5630310#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 5630567#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5630568#L635 assume !(1 == ~t7_pc~0); 5629861#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5629862#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5630236#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5631091#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 5630719#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5630720#L654 assume !(1 == ~t8_pc~0); 5630511#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5630512#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5630947#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5630948#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 5630996#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5630115#L673 assume !(1 == ~t9_pc~0); 5629814#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5629815#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5630397#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5630398#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 5630896#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5630897#L692 assume !(1 == ~t10_pc~0); 5630831#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5630880#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5630571#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5630572#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 5630584#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5630969#L1142 assume !(1 == ~M_E~0); 5630025#L1142-2 assume !(1 == ~T1_E~0); 5630026#L1147-1 assume !(1 == ~T2_E~0); 5630954#L1152-1 assume !(1 == ~T3_E~0); 5630443#L1157-1 assume !(1 == ~T4_E~0); 5630444#L1162-1 assume !(1 == ~T5_E~0); 5630610#L1167-1 assume !(1 == ~T6_E~0); 5630611#L1172-1 assume !(1 == ~T7_E~0); 5631114#L1177-1 assume !(1 == ~T8_E~0); 5630771#L1182-1 assume !(1 == ~T9_E~0); 5630772#L1187-1 assume !(1 == ~T10_E~0); 5630888#L1192-1 assume !(1 == ~E_M~0); 5630283#L1197-1 assume !(1 == ~E_1~0); 5630284#L1202-1 assume !(1 == ~E_2~0); 5630705#L1207-1 assume !(1 == ~E_3~0); 5630679#L1212-1 assume !(1 == ~E_4~0); 5629879#L1217-1 assume !(1 == ~E_5~0); 5629880#L1222-1 assume !(1 == ~E_6~0); 5630676#L1227-1 assume !(1 == ~E_7~0); 5630677#L1232-1 assume !(1 == ~E_8~0); 5629758#L1237-1 assume !(1 == ~E_9~0); 5629759#L1242-1 assume !(1 == ~E_10~0); 5630751#L1247-1 assume { :end_inline_reset_delta_events } true; 5630752#L1553-2 [2022-12-13 12:32:02,748 INFO L750 eck$LassoCheckResult]: Loop: 5630752#L1553-2 assume !false; 5795949#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5795938#L999 assume !false; 5795931#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5795736#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5795719#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5795712#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5795706#L854 assume !(0 != eval_~tmp~0#1); 5795707#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5839393#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5839386#L1024-3 assume !(0 == ~M_E~0); 5839378#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5839370#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5839364#L1034-3 assume !(0 == ~T3_E~0); 5839357#L1039-3 assume !(0 == ~T4_E~0); 5839350#L1044-3 assume !(0 == ~T5_E~0); 5839343#L1049-3 assume !(0 == ~T6_E~0); 5839336#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5839335#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5839334#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5839333#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5839332#L1074-3 assume !(0 == ~E_M~0); 5839331#L1079-3 assume !(0 == ~E_1~0); 5839329#L1084-3 assume !(0 == ~E_2~0); 5839327#L1089-3 assume !(0 == ~E_3~0); 5839325#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5839323#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5839321#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5839319#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5839317#L1114-3 assume !(0 == ~E_8~0); 5839314#L1119-3 assume !(0 == ~E_9~0); 5839312#L1124-3 assume !(0 == ~E_10~0); 5839310#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5839308#L502-36 assume !(1 == ~m_pc~0); 5839306#L502-38 is_master_triggered_~__retres1~0#1 := 0; 5839304#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5839303#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5839301#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5839299#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5839297#L521-36 assume !(1 == ~t1_pc~0); 5839295#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 5839292#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5839290#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5839289#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5839287#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5839285#L540-36 assume !(1 == ~t2_pc~0); 5821960#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5839204#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5839195#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5839188#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5838643#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5819936#L559-36 assume !(1 == ~t3_pc~0); 5819934#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 5819932#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5819930#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5819927#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5819925#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5819897#L578-36 assume 1 == ~t4_pc~0; 5819892#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5819887#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5819882#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5819869#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5819863#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5819856#L597-36 assume !(1 == ~t5_pc~0); 5819851#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 5819848#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5819843#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5819829#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 5819825#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5819818#L616-36 assume 1 == ~t6_pc~0; 5819814#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5819810#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5819806#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5819794#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5819786#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5782469#L635-36 assume !(1 == ~t7_pc~0); 5782467#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 5782465#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5782463#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5782461#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5782459#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5782458#L654-36 assume 1 == ~t8_pc~0; 5782454#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5782452#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5782450#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5782448#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5782446#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5762347#L673-36 assume !(1 == ~t9_pc~0); 5762345#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5762344#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5762342#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5762340#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5762338#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5762336#L692-36 assume !(1 == ~t10_pc~0); 5762332#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 5762330#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5762328#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5762326#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5762324#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5762322#L1142-3 assume !(1 == ~M_E~0); 5719797#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5762320#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5762318#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5762316#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5762314#L1162-3 assume !(1 == ~T5_E~0); 5762312#L1167-3 assume !(1 == ~T6_E~0); 5762310#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5762308#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5762306#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5762304#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5762302#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5762300#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5762298#L1202-3 assume !(1 == ~E_2~0); 5762295#L1207-3 assume !(1 == ~E_3~0); 5762294#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5762293#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5762292#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5762291#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5762290#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5762289#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5762288#L1242-3 assume !(1 == ~E_10~0); 5762286#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5762275#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5762274#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5762272#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5720076#L1572 assume !(0 == start_simulation_~tmp~3#1); 5720077#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5796148#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5796137#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5796135#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 5796134#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5796131#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5796129#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 5796102#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 5630752#L1553-2 [2022-12-13 12:32:02,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:02,748 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 3 times [2022-12-13 12:32:02,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:02,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120904445] [2022-12-13 12:32:02,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:02,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:02,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:02,758 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:32:02,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:02,798 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:32:02,798 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:02,798 INFO L85 PathProgramCache]: Analyzing trace with hash -1673447685, now seen corresponding path program 1 times [2022-12-13 12:32:02,798 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:02,798 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [521855129] [2022-12-13 12:32:02,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:02,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:02,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:32:02,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:32:02,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:32:02,838 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [521855129] [2022-12-13 12:32:02,838 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [521855129] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:32:02,838 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:32:02,839 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:32:02,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [6284618] [2022-12-13 12:32:02,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:32:02,839 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:32:02,839 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:32:02,839 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:32:02,839 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:32:02,840 INFO L87 Difference]: Start difference. First operand 224312 states and 310925 transitions. cyclomatic complexity: 86617 Second operand has 5 states, 5 states have (on average 26.8) internal successors, (134), 5 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:32:04,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:32:04,053 INFO L93 Difference]: Finished difference Result 416040 states and 572381 transitions. [2022-12-13 12:32:04,053 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 416040 states and 572381 transitions. [2022-12-13 12:32:05,637 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 415136 [2022-12-13 12:32:06,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 416040 states to 416040 states and 572381 transitions. [2022-12-13 12:32:06,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 416040 [2022-12-13 12:32:06,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 416040 [2022-12-13 12:32:06,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 416040 states and 572381 transitions. [2022-12-13 12:32:06,837 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:32:06,837 INFO L218 hiAutomatonCegarLoop]: Abstraction has 416040 states and 572381 transitions. [2022-12-13 12:32:07,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416040 states and 572381 transitions. [2022-12-13 12:32:08,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416040 to 225080. [2022-12-13 12:32:08,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225080 states, 225080 states have (on average 1.3848098453883064) internal successors, (311693), 225079 states have internal predecessors, (311693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:32:09,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225080 states to 225080 states and 311693 transitions. [2022-12-13 12:32:09,302 INFO L240 hiAutomatonCegarLoop]: Abstraction has 225080 states and 311693 transitions. [2022-12-13 12:32:09,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 12:32:09,303 INFO L428 stractBuchiCegarLoop]: Abstraction has 225080 states and 311693 transitions. [2022-12-13 12:32:09,303 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-12-13 12:32:09,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225080 states and 311693 transitions. [2022-12-13 12:32:10,018 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 224560 [2022-12-13 12:32:10,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:32:10,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:32:10,024 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:32:10,024 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:32:10,024 INFO L748 eck$LassoCheckResult]: Stem: 6270488#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 6270489#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6271541#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6271542#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6271127#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 6270775#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6270776#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6271091#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6271291#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6270963#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6270964#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 6270833#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 6270834#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 6271236#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6271183#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 6271102#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6271103#L1024 assume !(0 == ~M_E~0); 6271426#L1024-2 assume !(0 == ~T1_E~0); 6270484#L1029-1 assume !(0 == ~T2_E~0); 6270485#L1034-1 assume !(0 == ~T3_E~0); 6270587#L1039-1 assume !(0 == ~T4_E~0); 6271577#L1044-1 assume !(0 == ~T5_E~0); 6270855#L1049-1 assume !(0 == ~T6_E~0); 6270856#L1054-1 assume !(0 == ~T7_E~0); 6271126#L1059-1 assume !(0 == ~T8_E~0); 6270536#L1064-1 assume !(0 == ~T9_E~0); 6270537#L1069-1 assume !(0 == ~T10_E~0); 6271387#L1074-1 assume !(0 == ~E_M~0); 6271465#L1079-1 assume !(0 == ~E_1~0); 6271429#L1084-1 assume !(0 == ~E_2~0); 6271430#L1089-1 assume !(0 == ~E_3~0); 6271493#L1094-1 assume !(0 == ~E_4~0); 6270951#L1099-1 assume !(0 == ~E_5~0); 6270952#L1104-1 assume !(0 == ~E_6~0); 6271255#L1109-1 assume !(0 == ~E_7~0); 6270708#L1114-1 assume !(0 == ~E_8~0); 6270709#L1119-1 assume !(0 == ~E_9~0); 6270787#L1124-1 assume !(0 == ~E_10~0); 6270191#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6270192#L502 assume !(1 == ~m_pc~0); 6270381#L502-2 is_master_triggered_~__retres1~0#1 := 0; 6270314#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6270315#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6271177#L1273 assume !(0 != activate_threads_~tmp~1#1); 6271178#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6271640#L521 assume !(1 == ~t1_pc~0); 6271529#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6270240#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6270206#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6270207#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 6270226#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6270227#L540 assume !(1 == ~t2_pc~0); 6271074#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6271075#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6270704#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6270705#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 6271522#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6270515#L559 assume !(1 == ~t3_pc~0); 6270516#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6270809#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6270146#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6270147#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 6270332#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6270333#L578 assume !(1 == ~t4_pc~0); 6270450#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6271392#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6271423#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6271623#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 6271158#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6271159#L597 assume !(1 == ~t5_pc~0); 6271112#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6270261#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6270262#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6271424#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 6271100#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6271101#L616 assume !(1 == ~t6_pc~0); 6271121#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6271120#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6270679#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6270680#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 6270940#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6270941#L635 assume !(1 == ~t7_pc~0); 6270228#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6270229#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6270604#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6271489#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 6271094#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6271095#L654 assume !(1 == ~t8_pc~0); 6270885#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6270886#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6271330#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6271331#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 6271384#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6270483#L673 assume !(1 == ~t9_pc~0); 6270181#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6270182#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6270769#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6270770#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 6271269#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6271270#L692 assume !(1 == ~t10_pc~0); 6271202#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6271254#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6270943#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6270944#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 6270957#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6271354#L1142 assume !(1 == ~M_E~0); 6270392#L1142-2 assume !(1 == ~T1_E~0); 6270393#L1147-1 assume !(1 == ~T2_E~0); 6271337#L1152-1 assume !(1 == ~T3_E~0); 6270817#L1157-1 assume !(1 == ~T4_E~0); 6270818#L1162-1 assume !(1 == ~T5_E~0); 6270984#L1167-1 assume !(1 == ~T6_E~0); 6270985#L1172-1 assume !(1 == ~T7_E~0); 6271511#L1177-1 assume !(1 == ~T8_E~0); 6271144#L1182-1 assume !(1 == ~T9_E~0); 6271145#L1187-1 assume !(1 == ~T10_E~0); 6271261#L1192-1 assume !(1 == ~E_M~0); 6270652#L1197-1 assume !(1 == ~E_1~0); 6270653#L1202-1 assume !(1 == ~E_2~0); 6271078#L1207-1 assume !(1 == ~E_3~0); 6271051#L1212-1 assume !(1 == ~E_4~0); 6270245#L1217-1 assume !(1 == ~E_5~0); 6270246#L1222-1 assume !(1 == ~E_6~0); 6271048#L1227-1 assume !(1 == ~E_7~0); 6271049#L1232-1 assume !(1 == ~E_8~0); 6270126#L1237-1 assume !(1 == ~E_9~0); 6270127#L1242-1 assume !(1 == ~E_10~0); 6271124#L1247-1 assume { :end_inline_reset_delta_events } true; 6271125#L1553-2 [2022-12-13 12:32:10,024 INFO L750 eck$LassoCheckResult]: Loop: 6271125#L1553-2 assume !false; 6362847#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6362658#L999 assume !false; 6362652#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6362635#L782 assume !(0 == ~m_st~0); 6362629#L786 assume !(0 == ~t1_st~0); 6362630#L790 assume !(0 == ~t2_st~0); 6362633#L794 assume !(0 == ~t3_st~0); 6362627#L798 assume !(0 == ~t4_st~0); 6362628#L802 assume !(0 == ~t5_st~0); 6362632#L806 assume !(0 == ~t6_st~0); 6362625#L810 assume !(0 == ~t7_st~0); 6362626#L814 assume !(0 == ~t8_st~0); 6362631#L818 assume !(0 == ~t9_st~0); 6362634#L822 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 6362636#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6351169#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6351170#L854 assume !(0 != eval_~tmp~0#1); 6362617#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6362615#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6362613#L1024-3 assume !(0 == ~M_E~0); 6362611#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6362609#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6362607#L1034-3 assume !(0 == ~T3_E~0); 6362605#L1039-3 assume !(0 == ~T4_E~0); 6362603#L1044-3 assume !(0 == ~T5_E~0); 6362601#L1049-3 assume !(0 == ~T6_E~0); 6362599#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6362597#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6362595#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6362593#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6362591#L1074-3 assume !(0 == ~E_M~0); 6362589#L1079-3 assume !(0 == ~E_1~0); 6362587#L1084-3 assume !(0 == ~E_2~0); 6362585#L1089-3 assume !(0 == ~E_3~0); 6362583#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6362581#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6362579#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6362577#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6362575#L1114-3 assume !(0 == ~E_8~0); 6362573#L1119-3 assume !(0 == ~E_9~0); 6362571#L1124-3 assume !(0 == ~E_10~0); 6362569#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6362567#L502-36 assume !(1 == ~m_pc~0); 6362565#L502-38 is_master_triggered_~__retres1~0#1 := 0; 6362563#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6362561#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6362559#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6362557#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6362555#L521-36 assume 1 == ~t1_pc~0; 6362551#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6362549#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6362547#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6362545#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6362543#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6362541#L540-36 assume !(1 == ~t2_pc~0); 6357194#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 6362539#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6362537#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6362535#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6362533#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6362531#L559-36 assume !(1 == ~t3_pc~0); 6353275#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 6362529#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6362527#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6362525#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6362523#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6362521#L578-36 assume 1 == ~t4_pc~0; 6362517#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6362513#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6362509#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6362505#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6362503#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6362501#L597-36 assume !(1 == ~t5_pc~0); 6362499#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 6362497#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6362495#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6362493#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 6362491#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6362489#L616-36 assume 1 == ~t6_pc~0; 6362485#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6362483#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6362481#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6362479#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6362477#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6362475#L635-36 assume !(1 == ~t7_pc~0); 6361638#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 6362473#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6362471#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6362469#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6362467#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6362465#L654-36 assume 1 == ~t8_pc~0; 6362461#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6362459#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6362457#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6362455#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6362453#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6362451#L673-36 assume !(1 == ~t9_pc~0); 6341448#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 6362449#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6362447#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6362445#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6362443#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6362440#L692-36 assume !(1 == ~t10_pc~0); 6362437#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 6362435#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6362433#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6362431#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6362429#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6362427#L1142-3 assume !(1 == ~M_E~0); 6339813#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6362425#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6362423#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6362421#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6362419#L1162-3 assume !(1 == ~T5_E~0); 6362417#L1167-3 assume !(1 == ~T6_E~0); 6362415#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6362413#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6362411#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6362409#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6362407#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6362405#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6362403#L1202-3 assume !(1 == ~E_2~0); 6362401#L1207-3 assume !(1 == ~E_3~0); 6362400#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6362399#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6362398#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6362397#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6362396#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6362395#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6362394#L1242-3 assume !(1 == ~E_10~0); 6362393#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6362382#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 6362380#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6362378#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 6362374#L1572 assume !(0 == start_simulation_~tmp~3#1); 6362375#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6362863#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 6362853#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6362852#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 6362851#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6362850#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6362849#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6362848#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 6271125#L1553-2 [2022-12-13 12:32:10,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:10,024 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 4 times [2022-12-13 12:32:10,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:10,025 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420213629] [2022-12-13 12:32:10,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:10,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:10,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:10,031 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:32:10,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:10,053 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:32:10,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:10,053 INFO L85 PathProgramCache]: Analyzing trace with hash 2008555199, now seen corresponding path program 1 times [2022-12-13 12:32:10,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:10,053 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848622861] [2022-12-13 12:32:10,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:10,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:10,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:32:10,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:32:10,109 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:32:10,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848622861] [2022-12-13 12:32:10,110 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [848622861] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:32:10,110 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:32:10,110 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:32:10,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1384118742] [2022-12-13 12:32:10,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:32:10,110 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:32:10,110 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:32:10,110 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:32:10,111 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:32:10,111 INFO L87 Difference]: Start difference. First operand 225080 states and 311693 transitions. cyclomatic complexity: 86617 Second operand has 5 states, 5 states have (on average 28.8) internal successors, (144), 5 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:32:11,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:32:11,295 INFO L93 Difference]: Finished difference Result 450952 states and 621532 transitions. [2022-12-13 12:32:11,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 450952 states and 621532 transitions. [2022-12-13 12:32:12,938 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 450176 [2022-12-13 12:32:13,660 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 450952 states to 450952 states and 621532 transitions. [2022-12-13 12:32:13,660 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 450952 [2022-12-13 12:32:13,836 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 450952 [2022-12-13 12:32:13,836 INFO L73 IsDeterministic]: Start isDeterministic. Operand 450952 states and 621532 transitions. [2022-12-13 12:32:14,135 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:32:14,135 INFO L218 hiAutomatonCegarLoop]: Abstraction has 450952 states and 621532 transitions. [2022-12-13 12:32:14,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 450952 states and 621532 transitions. [2022-12-13 12:32:16,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 450952 to 228728. [2022-12-13 12:32:16,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 228728 states, 228728 states have (on average 1.3739113707110628) internal successors, (314252), 228727 states have internal predecessors, (314252), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:32:16,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228728 states to 228728 states and 314252 transitions. [2022-12-13 12:32:16,816 INFO L240 hiAutomatonCegarLoop]: Abstraction has 228728 states and 314252 transitions. [2022-12-13 12:32:16,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 12:32:16,817 INFO L428 stractBuchiCegarLoop]: Abstraction has 228728 states and 314252 transitions. [2022-12-13 12:32:16,817 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-12-13 12:32:16,817 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 228728 states and 314252 transitions. [2022-12-13 12:32:17,235 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 228208 [2022-12-13 12:32:17,236 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:32:17,236 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:32:17,240 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:32:17,240 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:32:17,241 INFO L748 eck$LassoCheckResult]: Stem: 6946534#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 6946535#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6947625#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6947626#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6947181#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 6946821#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6946822#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6947141#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6947359#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6947008#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6947009#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 6946876#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 6946877#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 6947300#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6947241#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 6947153#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6947154#L1024 assume !(0 == ~M_E~0); 6947496#L1024-2 assume !(0 == ~T1_E~0); 6946530#L1029-1 assume !(0 == ~T2_E~0); 6946531#L1034-1 assume !(0 == ~T3_E~0); 6946630#L1039-1 assume !(0 == ~T4_E~0); 6947662#L1044-1 assume !(0 == ~T5_E~0); 6946900#L1049-1 assume !(0 == ~T6_E~0); 6946901#L1054-1 assume !(0 == ~T7_E~0); 6947180#L1059-1 assume !(0 == ~T8_E~0); 6946580#L1064-1 assume !(0 == ~T9_E~0); 6946581#L1069-1 assume !(0 == ~T10_E~0); 6947452#L1074-1 assume !(0 == ~E_M~0); 6947537#L1079-1 assume !(0 == ~E_1~0); 6947500#L1084-1 assume !(0 == ~E_2~0); 6947501#L1089-1 assume !(0 == ~E_3~0); 6947562#L1094-1 assume !(0 == ~E_4~0); 6946998#L1099-1 assume !(0 == ~E_5~0); 6946999#L1104-1 assume !(0 == ~E_6~0); 6947322#L1109-1 assume !(0 == ~E_7~0); 6946755#L1114-1 assume !(0 == ~E_8~0); 6946756#L1119-1 assume !(0 == ~E_9~0); 6946832#L1124-1 assume !(0 == ~E_10~0); 6946236#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6946237#L502 assume !(1 == ~m_pc~0); 6946426#L502-2 is_master_triggered_~__retres1~0#1 := 0; 6946361#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6946362#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6947235#L1273 assume !(0 != activate_threads_~tmp~1#1); 6947236#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6947734#L521 assume !(1 == ~t1_pc~0); 6947610#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6946287#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6946251#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6946252#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 6946272#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6946273#L540 assume !(1 == ~t2_pc~0); 6947124#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6947125#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6946751#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6946752#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 6947601#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6946559#L559 assume !(1 == ~t3_pc~0); 6946560#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6946853#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6946191#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6946192#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 6946380#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6946381#L578 assume !(1 == ~t4_pc~0); 6946494#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6947460#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6947493#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6947712#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 6947212#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6947213#L597 assume !(1 == ~t5_pc~0); 6947166#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6946308#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6946309#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6947494#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 6947155#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6947156#L616 assume !(1 == ~t6_pc~0); 6947175#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6947174#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6946727#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6946728#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 6946986#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6946987#L635 assume !(1 == ~t7_pc~0); 6946274#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6946275#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6946647#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6947558#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 6947146#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6947147#L654 assume !(1 == ~t8_pc~0); 6946932#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6946933#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6947392#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6947393#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 6947449#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6946529#L673 assume !(1 == ~t9_pc~0); 6946226#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6946227#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6946815#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6946816#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 6947337#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6947338#L692 assume !(1 == ~t10_pc~0); 6947262#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6947321#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6946989#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6946990#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 6947002#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6947420#L1142 assume !(1 == ~M_E~0); 6946437#L1142-2 assume !(1 == ~T1_E~0); 6946438#L1147-1 assume !(1 == ~T2_E~0); 6947399#L1152-1 assume !(1 == ~T3_E~0); 6946861#L1157-1 assume !(1 == ~T4_E~0); 6946862#L1162-1 assume !(1 == ~T5_E~0); 6947029#L1167-1 assume !(1 == ~T6_E~0); 6947030#L1172-1 assume !(1 == ~T7_E~0); 6947583#L1177-1 assume !(1 == ~T8_E~0); 6947197#L1182-1 assume !(1 == ~T9_E~0); 6947198#L1187-1 assume !(1 == ~T10_E~0); 6947328#L1192-1 assume !(1 == ~E_M~0); 6946700#L1197-1 assume !(1 == ~E_1~0); 6946701#L1202-1 assume !(1 == ~E_2~0); 6947128#L1207-1 assume !(1 == ~E_3~0); 6947099#L1212-1 assume !(1 == ~E_4~0); 6946292#L1217-1 assume !(1 == ~E_5~0); 6946293#L1222-1 assume !(1 == ~E_6~0); 6947095#L1227-1 assume !(1 == ~E_7~0); 6947096#L1232-1 assume !(1 == ~E_8~0); 6946171#L1237-1 assume !(1 == ~E_9~0); 6946172#L1242-1 assume !(1 == ~E_10~0); 6947178#L1247-1 assume { :end_inline_reset_delta_events } true; 6947179#L1553-2 [2022-12-13 12:32:17,241 INFO L750 eck$LassoCheckResult]: Loop: 6947179#L1553-2 assume !false; 6988115#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6988109#L999 assume !false; 6988107#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6985787#L782 assume !(0 == ~m_st~0); 6985782#L786 assume !(0 == ~t1_st~0); 6985783#L790 assume !(0 == ~t2_st~0); 6985786#L794 assume !(0 == ~t3_st~0); 6985778#L798 assume !(0 == ~t4_st~0); 6985779#L802 assume !(0 == ~t5_st~0); 6985785#L806 assume !(0 == ~t6_st~0); 6985776#L810 assume !(0 == ~t7_st~0); 6985777#L814 assume !(0 == ~t8_st~0); 6985784#L818 assume !(0 == ~t9_st~0); 6985780#L822 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 6985781#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 7052103#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7052102#L854 assume !(0 != eval_~tmp~0#1); 7052101#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7052100#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7052099#L1024-3 assume !(0 == ~M_E~0); 7052098#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7052097#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7052096#L1034-3 assume !(0 == ~T3_E~0); 7052095#L1039-3 assume !(0 == ~T4_E~0); 7052094#L1044-3 assume !(0 == ~T5_E~0); 7052093#L1049-3 assume !(0 == ~T6_E~0); 7052092#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7052064#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7051471#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7051472#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7051464#L1074-3 assume !(0 == ~E_M~0); 7051465#L1079-3 assume !(0 == ~E_1~0); 7051458#L1084-3 assume !(0 == ~E_2~0); 7051459#L1089-3 assume !(0 == ~E_3~0); 7051452#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7051453#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7051446#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7051447#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7051439#L1114-3 assume !(0 == ~E_8~0); 7051440#L1119-3 assume !(0 == ~E_9~0); 7051433#L1124-3 assume !(0 == ~E_10~0); 7051434#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7051427#L502-36 assume !(1 == ~m_pc~0); 7051428#L502-38 is_master_triggered_~__retres1~0#1 := 0; 7051422#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7051423#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7051416#L1273-36 assume !(0 != activate_threads_~tmp~1#1); 7051414#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7051412#L521-36 assume !(1 == ~t1_pc~0); 7051410#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 7051407#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7051404#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7051366#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7051217#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7008972#L540-36 assume !(1 == ~t2_pc~0); 7008970#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 7008966#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7008967#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7049346#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7049345#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7003737#L559-36 assume !(1 == ~t3_pc~0); 7003735#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 7003733#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7003731#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7003729#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7003725#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7003723#L578-36 assume 1 == ~t4_pc~0; 7003721#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7003722#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7003741#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7003711#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7003709#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7003707#L597-36 assume !(1 == ~t5_pc~0); 7003705#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 7003703#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7003701#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7003699#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 7003697#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7003694#L616-36 assume 1 == ~t6_pc~0; 7003691#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7003689#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7003687#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7003685#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7003683#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7003682#L635-36 assume !(1 == ~t7_pc~0); 6992801#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 7003679#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7003677#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7003675#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7003673#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7003670#L654-36 assume 1 == ~t8_pc~0; 7003667#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7003665#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7003663#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7003662#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7003430#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6988302#L673-36 assume !(1 == ~t9_pc~0); 6988300#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 6988298#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6988294#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6988292#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6988290#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6988288#L692-36 assume !(1 == ~t10_pc~0); 6988284#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 6988282#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6988280#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6988278#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6988276#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6988274#L1142-3 assume !(1 == ~M_E~0); 6988270#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6988268#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6988266#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6988263#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6988261#L1162-3 assume !(1 == ~T5_E~0); 6988259#L1167-3 assume !(1 == ~T6_E~0); 6988257#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6988255#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6988252#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6988251#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6988250#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6988249#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6988248#L1202-3 assume !(1 == ~E_2~0); 6988189#L1207-3 assume !(1 == ~E_3~0); 6988187#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6988185#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6988183#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6988181#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6988179#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6988177#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6988175#L1242-3 assume !(1 == ~E_10~0); 6988173#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6988151#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 6988149#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6988147#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 6988145#L1572 assume !(0 == start_simulation_~tmp~3#1); 6988143#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6988141#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 6988129#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6988127#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 6988125#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6988123#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6988121#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6988119#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 6947179#L1553-2 [2022-12-13 12:32:17,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:17,242 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 5 times [2022-12-13 12:32:17,242 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:17,242 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290227014] [2022-12-13 12:32:17,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:17,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:17,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:17,257 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:32:17,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:17,293 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:32:17,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:17,294 INFO L85 PathProgramCache]: Analyzing trace with hash -812417470, now seen corresponding path program 1 times [2022-12-13 12:32:17,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:17,294 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297706754] [2022-12-13 12:32:17,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:17,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:17,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:32:17,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:32:17,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:32:17,321 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297706754] [2022-12-13 12:32:17,321 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1297706754] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:32:17,321 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:32:17,321 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:32:17,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [805214296] [2022-12-13 12:32:17,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:32:17,321 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:32:17,321 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:32:17,322 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:32:17,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:32:17,322 INFO L87 Difference]: Start difference. First operand 228728 states and 314252 transitions. cyclomatic complexity: 85528 Second operand has 3 states, 3 states have (on average 48.0) internal successors, (144), 3 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:32:18,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:32:18,223 INFO L93 Difference]: Finished difference Result 381890 states and 520694 transitions. [2022-12-13 12:32:18,223 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 381890 states and 520694 transitions. [2022-12-13 12:32:19,677 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 381240 [2022-12-13 12:32:20,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 381890 states to 381890 states and 520694 transitions. [2022-12-13 12:32:20,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 381890 [2022-12-13 12:32:20,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 381890 [2022-12-13 12:32:20,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 381890 states and 520694 transitions. [2022-12-13 12:32:20,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:32:20,640 INFO L218 hiAutomatonCegarLoop]: Abstraction has 381890 states and 520694 transitions. [2022-12-13 12:32:20,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 381890 states and 520694 transitions. [2022-12-13 12:32:22,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 381890 to 372642. [2022-12-13 12:32:23,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 372642 states, 372642 states have (on average 1.364499975848133) internal successors, (508470), 372641 states have internal predecessors, (508470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:32:23,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 372642 states to 372642 states and 508470 transitions. [2022-12-13 12:32:23,811 INFO L240 hiAutomatonCegarLoop]: Abstraction has 372642 states and 508470 transitions. [2022-12-13 12:32:23,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:32:23,812 INFO L428 stractBuchiCegarLoop]: Abstraction has 372642 states and 508470 transitions. [2022-12-13 12:32:23,812 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2022-12-13 12:32:23,812 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 372642 states and 508470 transitions. [2022-12-13 12:32:24,624 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 371992 [2022-12-13 12:32:24,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:32:24,625 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:32:24,625 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:32:24,625 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:32:24,626 INFO L748 eck$LassoCheckResult]: Stem: 7557160#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 7557161#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 7558256#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7558257#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7557808#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 7557450#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7557451#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7557773#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7557984#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7557636#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7557637#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7557510#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 7557511#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 7557927#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7557868#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 7557780#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7557781#L1024 assume !(0 == ~M_E~0); 7558134#L1024-2 assume !(0 == ~T1_E~0); 7557154#L1029-1 assume !(0 == ~T2_E~0); 7557155#L1034-1 assume !(0 == ~T3_E~0); 7557258#L1039-1 assume !(0 == ~T4_E~0); 7558298#L1044-1 assume !(0 == ~T5_E~0); 7557528#L1049-1 assume !(0 == ~T6_E~0); 7557529#L1054-1 assume !(0 == ~T7_E~0); 7557807#L1059-1 assume !(0 == ~T8_E~0); 7557206#L1064-1 assume !(0 == ~T9_E~0); 7557207#L1069-1 assume !(0 == ~T10_E~0); 7558092#L1074-1 assume !(0 == ~E_M~0); 7558174#L1079-1 assume !(0 == ~E_1~0); 7558136#L1084-1 assume !(0 == ~E_2~0); 7558137#L1089-1 assume !(0 == ~E_3~0); 7558197#L1094-1 assume !(0 == ~E_4~0); 7557624#L1099-1 assume !(0 == ~E_5~0); 7557625#L1104-1 assume !(0 == ~E_6~0); 7557947#L1109-1 assume !(0 == ~E_7~0); 7557380#L1114-1 assume !(0 == ~E_8~0); 7557381#L1119-1 assume !(0 == ~E_9~0); 7557464#L1124-1 assume !(0 == ~E_10~0); 7556860#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7556861#L502 assume !(1 == ~m_pc~0); 7557053#L502-2 is_master_triggered_~__retres1~0#1 := 0; 7556986#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7556987#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7557864#L1273 assume !(0 != activate_threads_~tmp~1#1); 7557865#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7558378#L521 assume !(1 == ~t1_pc~0); 7558241#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7556912#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7556875#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7556876#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 7556896#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7556897#L540 assume !(1 == ~t2_pc~0); 7557754#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7557755#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7557378#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7557379#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 7558229#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7557184#L559 assume !(1 == ~t3_pc~0); 7557185#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7557482#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7556815#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7556816#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 7557002#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7557003#L578 assume !(1 == ~t4_pc~0); 7557126#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7558100#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7558131#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7558352#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 7557840#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7557841#L597 assume !(1 == ~t5_pc~0); 7557792#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7556931#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7556932#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7558132#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 7557782#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7557783#L616 assume !(1 == ~t6_pc~0); 7557804#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7557803#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7557352#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7557353#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 7557614#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7557615#L635 assume !(1 == ~t7_pc~0); 7556898#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7556899#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7557276#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7558191#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 7557775#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7557776#L654 assume !(1 == ~t8_pc~0); 7557556#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7557557#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7558032#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7558033#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 7558087#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7557153#L673 assume !(1 == ~t9_pc~0); 7556852#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 7556853#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7557443#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7557444#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 7557961#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7557962#L692 assume !(1 == ~t10_pc~0); 7557888#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7557946#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7557616#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7557617#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 7557630#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7558053#L1142 assume !(1 == ~M_E~0); 7557062#L1142-2 assume !(1 == ~T1_E~0); 7557063#L1147-1 assume !(1 == ~T2_E~0); 7558038#L1152-1 assume !(1 == ~T3_E~0); 7557488#L1157-1 assume !(1 == ~T4_E~0); 7557489#L1162-1 assume !(1 == ~T5_E~0); 7557657#L1167-1 assume !(1 == ~T6_E~0); 7557658#L1172-1 assume !(1 == ~T7_E~0); 7558217#L1177-1 assume !(1 == ~T8_E~0); 7557824#L1182-1 assume !(1 == ~T9_E~0); 7557825#L1187-1 assume !(1 == ~T10_E~0); 7557953#L1192-1 assume !(1 == ~E_M~0); 7557325#L1197-1 assume !(1 == ~E_1~0); 7557326#L1202-1 assume !(1 == ~E_2~0); 7557759#L1207-1 assume !(1 == ~E_3~0); 7557728#L1212-1 assume !(1 == ~E_4~0); 7556915#L1217-1 assume !(1 == ~E_5~0); 7556916#L1222-1 assume !(1 == ~E_6~0); 7557725#L1227-1 assume !(1 == ~E_7~0); 7557726#L1232-1 assume !(1 == ~E_8~0); 7556795#L1237-1 assume !(1 == ~E_9~0); 7556796#L1242-1 assume !(1 == ~E_10~0); 7557805#L1247-1 assume { :end_inline_reset_delta_events } true; 7557806#L1553-2 assume !false; 7622904#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7622897#L999 [2022-12-13 12:32:24,626 INFO L750 eck$LassoCheckResult]: Loop: 7622897#L999 assume !false; 7622895#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 7622892#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7622890#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 7622888#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7622886#L854 assume 0 != eval_~tmp~0#1; 7622884#L854-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 7622879#L862 assume !(0 != eval_~tmp_ndt_1~0#1); 7622874#L859 assume !(0 == ~t1_st~0); 7622847#L873 assume !(0 == ~t2_st~0); 7622839#L887 assume !(0 == ~t3_st~0); 7622832#L901 assume !(0 == ~t4_st~0); 7622827#L915 assume !(0 == ~t5_st~0); 7622822#L929 assume !(0 == ~t6_st~0); 7622818#L943 assume !(0 == ~t7_st~0); 7622817#L957 assume !(0 == ~t8_st~0); 7622909#L971 assume !(0 == ~t9_st~0); 7622903#L985 assume !(0 == ~t10_st~0); 7622897#L999 [2022-12-13 12:32:24,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:24,626 INFO L85 PathProgramCache]: Analyzing trace with hash 1499347499, now seen corresponding path program 1 times [2022-12-13 12:32:24,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:24,626 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260679891] [2022-12-13 12:32:24,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:24,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:24,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:24,637 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:32:24,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:24,664 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:32:24,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:24,665 INFO L85 PathProgramCache]: Analyzing trace with hash -1138232242, now seen corresponding path program 1 times [2022-12-13 12:32:24,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:24,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989207227] [2022-12-13 12:32:24,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:24,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:24,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:24,667 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:32:24,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:24,670 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:32:24,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:24,670 INFO L85 PathProgramCache]: Analyzing trace with hash 304068600, now seen corresponding path program 1 times [2022-12-13 12:32:24,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:24,670 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200653167] [2022-12-13 12:32:24,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:24,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:24,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:32:24,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:32:24,698 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:32:24,699 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1200653167] [2022-12-13 12:32:24,699 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1200653167] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:32:24,699 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:32:24,699 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:32:24,699 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1941172542] [2022-12-13 12:32:24,699 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:32:24,797 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:32:24,798 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:32:24,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:32:24,798 INFO L87 Difference]: Start difference. First operand 372642 states and 508470 transitions. cyclomatic complexity: 135834 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:32:26,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:32:26,564 INFO L93 Difference]: Finished difference Result 720382 states and 977765 transitions. [2022-12-13 12:32:26,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 720382 states and 977765 transitions. [2022-12-13 12:32:29,091 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 719088 [2022-12-13 12:32:30,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 720382 states to 720382 states and 977765 transitions. [2022-12-13 12:32:30,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 720382 [2022-12-13 12:32:30,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 720382 [2022-12-13 12:32:30,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 720382 states and 977765 transitions. [2022-12-13 12:32:30,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:32:30,814 INFO L218 hiAutomatonCegarLoop]: Abstraction has 720382 states and 977765 transitions. [2022-12-13 12:32:31,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 720382 states and 977765 transitions. [2022-12-13 12:32:35,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 720382 to 690254. [2022-12-13 12:32:35,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 690254 states, 690254 states have (on average 1.359414070762357) internal successors, (938341), 690253 states have internal predecessors, (938341), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:32:36,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 690254 states to 690254 states and 938341 transitions. [2022-12-13 12:32:36,670 INFO L240 hiAutomatonCegarLoop]: Abstraction has 690254 states and 938341 transitions. [2022-12-13 12:32:36,671 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:32:36,671 INFO L428 stractBuchiCegarLoop]: Abstraction has 690254 states and 938341 transitions. [2022-12-13 12:32:36,671 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2022-12-13 12:32:36,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 690254 states and 938341 transitions. [2022-12-13 12:32:38,270 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 688960 [2022-12-13 12:32:38,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:32:38,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:32:38,271 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:32:38,271 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:32:38,271 INFO L748 eck$LassoCheckResult]: Stem: 8650191#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 8650192#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8651305#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8651306#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8650864#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 8650482#L719-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 8650483#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8728021#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8728020#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8728019#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8728018#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8728017#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 8728016#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 8728015#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8728014#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 8728013#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8728012#L1024 assume !(0 == ~M_E~0); 8728011#L1024-2 assume !(0 == ~T1_E~0); 8728010#L1029-1 assume !(0 == ~T2_E~0); 8728009#L1034-1 assume !(0 == ~T3_E~0); 8728008#L1039-1 assume !(0 == ~T4_E~0); 8728007#L1044-1 assume !(0 == ~T5_E~0); 8728006#L1049-1 assume !(0 == ~T6_E~0); 8728005#L1054-1 assume !(0 == ~T7_E~0); 8728004#L1059-1 assume !(0 == ~T8_E~0); 8728003#L1064-1 assume !(0 == ~T9_E~0); 8728002#L1069-1 assume !(0 == ~T10_E~0); 8728001#L1074-1 assume !(0 == ~E_M~0); 8728000#L1079-1 assume !(0 == ~E_1~0); 8727999#L1084-1 assume !(0 == ~E_2~0); 8727998#L1089-1 assume !(0 == ~E_3~0); 8727997#L1094-1 assume !(0 == ~E_4~0); 8727996#L1099-1 assume !(0 == ~E_5~0); 8727995#L1104-1 assume !(0 == ~E_6~0); 8727994#L1109-1 assume !(0 == ~E_7~0); 8727993#L1114-1 assume !(0 == ~E_8~0); 8727992#L1119-1 assume !(0 == ~E_9~0); 8727991#L1124-1 assume !(0 == ~E_10~0); 8727990#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8727989#L502 assume !(1 == ~m_pc~0); 8727988#L502-2 is_master_triggered_~__retres1~0#1 := 0; 8727987#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8727986#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8727985#L1273 assume !(0 != activate_threads_~tmp~1#1); 8727984#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8727983#L521 assume !(1 == ~t1_pc~0); 8727981#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8727980#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8727979#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8727978#L1281 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8649929#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8649930#L540 assume !(1 == ~t2_pc~0); 8650807#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8650808#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8650410#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8650411#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 8651276#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8650216#L559 assume !(1 == ~t3_pc~0); 8650217#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8650518#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8649848#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8649849#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 8650036#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8650037#L578 assume !(1 == ~t4_pc~0); 8650155#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8651135#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8651165#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8651394#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 8650899#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8650900#L597 assume !(1 == ~t5_pc~0); 8650846#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8649965#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8649966#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8651166#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 8650836#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8650837#L616 assume !(1 == ~t6_pc~0); 8650860#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8650859#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8650384#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8650385#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 8650657#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8650658#L635 assume !(1 == ~t7_pc~0); 8649931#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8649932#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8650308#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8651240#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 8650829#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8650830#L654 assume !(1 == ~t8_pc~0); 8650598#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8650599#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8651070#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8651071#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 8651124#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8650184#L673 assume !(1 == ~t9_pc~0); 8649885#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 8649886#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8650473#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8650474#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 8651008#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8651009#L692 assume !(1 == ~t10_pc~0); 8650943#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8650993#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8650659#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8650660#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 8650672#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8651097#L1142 assume !(1 == ~M_E~0); 8650094#L1142-2 assume !(1 == ~T1_E~0); 8650095#L1147-1 assume !(1 == ~T2_E~0); 8651077#L1152-1 assume !(1 == ~T3_E~0); 8650525#L1157-1 assume !(1 == ~T4_E~0); 8650526#L1162-1 assume !(1 == ~T5_E~0); 8650702#L1167-1 assume !(1 == ~T6_E~0); 8650703#L1172-1 assume !(1 == ~T7_E~0); 8651266#L1177-1 assume !(1 == ~T8_E~0); 8650882#L1182-1 assume !(1 == ~T9_E~0); 8650883#L1187-1 assume !(1 == ~T10_E~0); 8651000#L1192-1 assume !(1 == ~E_M~0); 8650358#L1197-1 assume !(1 == ~E_1~0); 8650359#L1202-1 assume !(1 == ~E_2~0); 8650812#L1207-1 assume !(1 == ~E_3~0); 8650781#L1212-1 assume !(1 == ~E_4~0); 8649949#L1217-1 assume !(1 == ~E_5~0); 8649950#L1222-1 assume !(1 == ~E_6~0); 8650774#L1227-1 assume !(1 == ~E_7~0); 8650775#L1232-1 assume !(1 == ~E_8~0); 8727836#L1237-1 assume !(1 == ~E_9~0); 8727833#L1242-1 assume !(1 == ~E_10~0); 8650861#L1247-1 assume { :end_inline_reset_delta_events } true; 8650862#L1553-2 assume !false; 8737238#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8737232#L999 [2022-12-13 12:32:38,272 INFO L750 eck$LassoCheckResult]: Loop: 8737232#L999 assume !false; 8737230#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8737227#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8737224#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8737222#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8737220#L854 assume 0 != eval_~tmp~0#1; 8737217#L854-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 8737214#L862 assume !(0 != eval_~tmp_ndt_1~0#1); 8737211#L859 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 8719232#L876 assume !(0 != eval_~tmp_ndt_2~0#1); 8737209#L873 assume !(0 == ~t2_st~0); 8737207#L887 assume !(0 == ~t3_st~0); 8737202#L901 assume !(0 == ~t4_st~0); 8737197#L915 assume !(0 == ~t5_st~0); 8737193#L929 assume !(0 == ~t6_st~0); 8737188#L943 assume !(0 == ~t7_st~0); 8737186#L957 assume !(0 == ~t8_st~0); 8737244#L971 assume !(0 == ~t9_st~0); 8737237#L985 assume !(0 == ~t10_st~0); 8737232#L999 [2022-12-13 12:32:38,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:38,272 INFO L85 PathProgramCache]: Analyzing trace with hash 1850588971, now seen corresponding path program 1 times [2022-12-13 12:32:38,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:38,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530304215] [2022-12-13 12:32:38,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:38,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:38,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:32:38,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:32:38,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:32:38,290 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1530304215] [2022-12-13 12:32:38,290 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1530304215] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:32:38,290 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:32:38,290 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:32:38,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [910849815] [2022-12-13 12:32:38,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:32:38,290 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:32:38,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:38,291 INFO L85 PathProgramCache]: Analyzing trace with hash -493734524, now seen corresponding path program 1 times [2022-12-13 12:32:38,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:38,291 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954185201] [2022-12-13 12:32:38,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:38,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:38,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:38,294 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:32:38,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:38,297 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:32:38,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:32:38,652 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:32:38,652 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:32:38,652 INFO L87 Difference]: Start difference. First operand 690254 states and 938341 transitions. cyclomatic complexity: 248093 Second operand has 3 states, 3 states have (on average 43.333333333333336) internal successors, (130), 3 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:32:40,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:32:40,343 INFO L93 Difference]: Finished difference Result 690122 states and 938157 transitions. [2022-12-13 12:32:40,344 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 690122 states and 938157 transitions. [2022-12-13 12:32:42,876 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 688960 [2022-12-13 12:32:44,279 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 690122 states to 690122 states and 938157 transitions. [2022-12-13 12:32:44,279 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 690122 [2022-12-13 12:32:44,538 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 690122 [2022-12-13 12:32:44,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 690122 states and 938157 transitions. [2022-12-13 12:32:44,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:32:44,768 INFO L218 hiAutomatonCegarLoop]: Abstraction has 690122 states and 938157 transitions. [2022-12-13 12:32:45,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 690122 states and 938157 transitions. [2022-12-13 12:32:49,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 690122 to 690122. [2022-12-13 12:32:49,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 690122 states, 690122 states have (on average 1.3594074670855298) internal successors, (938157), 690121 states have internal predecessors, (938157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:32:51,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 690122 states to 690122 states and 938157 transitions. [2022-12-13 12:32:51,015 INFO L240 hiAutomatonCegarLoop]: Abstraction has 690122 states and 938157 transitions. [2022-12-13 12:32:51,015 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:32:51,016 INFO L428 stractBuchiCegarLoop]: Abstraction has 690122 states and 938157 transitions. [2022-12-13 12:32:51,016 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2022-12-13 12:32:51,016 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 690122 states and 938157 transitions. [2022-12-13 12:32:52,887 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 688960 [2022-12-13 12:32:52,887 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:32:52,887 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:32:52,888 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:32:52,888 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:32:52,888 INFO L748 eck$LassoCheckResult]: Stem: 10030573#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 10030574#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 10031640#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10031641#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10031206#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 10030857#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10030858#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10031172#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10031380#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10031045#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10031046#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10030917#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 10030918#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 10031320#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10031268#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 10031179#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10031180#L1024 assume !(0 == ~M_E~0); 10031517#L1024-2 assume !(0 == ~T1_E~0); 10030567#L1029-1 assume !(0 == ~T2_E~0); 10030568#L1034-1 assume !(0 == ~T3_E~0); 10030672#L1039-1 assume !(0 == ~T4_E~0); 10031679#L1044-1 assume !(0 == ~T5_E~0); 10030935#L1049-1 assume !(0 == ~T6_E~0); 10030936#L1054-1 assume !(0 == ~T7_E~0); 10031205#L1059-1 assume !(0 == ~T8_E~0); 10030620#L1064-1 assume !(0 == ~T9_E~0); 10030621#L1069-1 assume !(0 == ~T10_E~0); 10031474#L1074-1 assume !(0 == ~E_M~0); 10031555#L1079-1 assume !(0 == ~E_1~0); 10031519#L1084-1 assume !(0 == ~E_2~0); 10031520#L1089-1 assume !(0 == ~E_3~0); 10031582#L1094-1 assume !(0 == ~E_4~0); 10031035#L1099-1 assume !(0 == ~E_5~0); 10031036#L1104-1 assume !(0 == ~E_6~0); 10031344#L1109-1 assume !(0 == ~E_7~0); 10030792#L1114-1 assume !(0 == ~E_8~0); 10030793#L1119-1 assume !(0 == ~E_9~0); 10030872#L1124-1 assume !(0 == ~E_10~0); 10030275#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10030276#L502 assume !(1 == ~m_pc~0); 10030465#L502-2 is_master_triggered_~__retres1~0#1 := 0; 10030399#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10030400#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10031264#L1273 assume !(0 != activate_threads_~tmp~1#1); 10031265#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10031750#L521 assume !(1 == ~t1_pc~0); 10031623#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10030326#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10030290#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10030291#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 10030310#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10030311#L540 assume !(1 == ~t2_pc~0); 10031152#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10031153#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10030790#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10030791#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 10031613#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10030597#L559 assume !(1 == ~t3_pc~0); 10030598#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10030890#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10030230#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10030231#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 10030415#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10030416#L578 assume !(1 == ~t4_pc~0); 10030539#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10031480#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10031514#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10031724#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 10031244#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10031245#L597 assume !(1 == ~t5_pc~0); 10031190#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10030345#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10030346#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10031515#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 10031181#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10031182#L616 assume !(1 == ~t6_pc~0); 10031202#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10031201#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10030763#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10030764#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 10031024#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10031025#L635 assume !(1 == ~t7_pc~0); 10030312#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10030313#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10030691#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10031578#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 10031174#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10031175#L654 assume !(1 == ~t8_pc~0); 10030963#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10030964#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10031421#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10031422#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 10031472#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10030566#L673 assume !(1 == ~t9_pc~0); 10030267#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 10030268#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10030852#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10030853#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 10031358#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10031359#L692 assume !(1 == ~t10_pc~0); 10031287#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10031342#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10031026#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10031027#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 10031039#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10031444#L1142 assume !(1 == ~M_E~0); 10030474#L1142-2 assume !(1 == ~T1_E~0); 10030475#L1147-1 assume !(1 == ~T2_E~0); 10031426#L1152-1 assume !(1 == ~T3_E~0); 10030896#L1157-1 assume !(1 == ~T4_E~0); 10030897#L1162-1 assume !(1 == ~T5_E~0); 10031063#L1167-1 assume !(1 == ~T6_E~0); 10031064#L1172-1 assume !(1 == ~T7_E~0); 10031603#L1177-1 assume !(1 == ~T8_E~0); 10031223#L1182-1 assume !(1 == ~T9_E~0); 10031224#L1187-1 assume !(1 == ~T10_E~0); 10031350#L1192-1 assume !(1 == ~E_M~0); 10030737#L1197-1 assume !(1 == ~E_1~0); 10030738#L1202-1 assume !(1 == ~E_2~0); 10031158#L1207-1 assume !(1 == ~E_3~0); 10031128#L1212-1 assume !(1 == ~E_4~0); 10030329#L1217-1 assume !(1 == ~E_5~0); 10030330#L1222-1 assume !(1 == ~E_6~0); 10031125#L1227-1 assume !(1 == ~E_7~0); 10031126#L1232-1 assume !(1 == ~E_8~0); 10030209#L1237-1 assume !(1 == ~E_9~0); 10030210#L1242-1 assume !(1 == ~E_10~0); 10031203#L1247-1 assume { :end_inline_reset_delta_events } true; 10031204#L1553-2 assume !false; 10198393#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10198386#L999 [2022-12-13 12:32:52,888 INFO L750 eck$LassoCheckResult]: Loop: 10198386#L999 assume !false; 10198384#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 10198051#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10198049#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10198047#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10198046#L854 assume 0 != eval_~tmp~0#1; 10198044#L854-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 10198039#L862 assume !(0 != eval_~tmp_ndt_1~0#1); 10198037#L859 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 10198034#L876 assume !(0 != eval_~tmp_ndt_2~0#1); 10198033#L873 assume !(0 == ~t2_st~0); 10196149#L887 assume !(0 == ~t3_st~0); 10198032#L901 assume !(0 == ~t4_st~0); 10198408#L915 assume !(0 == ~t5_st~0); 10198405#L929 assume !(0 == ~t6_st~0); 10198401#L943 assume !(0 == ~t7_st~0); 10198398#L957 assume !(0 == ~t8_st~0); 10198394#L971 assume !(0 == ~t9_st~0); 10157702#L985 assume !(0 == ~t10_st~0); 10198386#L999 [2022-12-13 12:32:52,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:52,889 INFO L85 PathProgramCache]: Analyzing trace with hash 1499347499, now seen corresponding path program 2 times [2022-12-13 12:32:52,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:52,889 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936721676] [2022-12-13 12:32:52,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:52,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:52,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:52,896 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:32:52,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:52,924 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:32:52,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:52,924 INFO L85 PathProgramCache]: Analyzing trace with hash -493734524, now seen corresponding path program 2 times [2022-12-13 12:32:52,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:52,924 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259238521] [2022-12-13 12:32:52,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:52,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:52,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:52,928 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:32:52,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:32:52,930 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:32:52,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:32:52,930 INFO L85 PathProgramCache]: Analyzing trace with hash 1267918618, now seen corresponding path program 1 times [2022-12-13 12:32:52,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:32:52,930 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090465035] [2022-12-13 12:32:52,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:32:52,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:32:52,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:32:52,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:32:52,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:32:52,960 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090465035] [2022-12-13 12:32:52,960 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1090465035] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:32:52,961 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:32:52,961 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:32:52,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334683961] [2022-12-13 12:32:52,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:32:53,040 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:32:53,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:32:53,040 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:32:53,041 INFO L87 Difference]: Start difference. First operand 690122 states and 938157 transitions. cyclomatic complexity: 248041 Second operand has 3 states, 3 states have (on average 49.666666666666664) internal successors, (149), 3 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:32:56,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:32:56,144 INFO L93 Difference]: Finished difference Result 1350794 states and 1831165 transitions. [2022-12-13 12:32:56,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1350794 states and 1831165 transitions. [2022-12-13 12:33:00,857 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1348608 [2022-12-13 12:33:03,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1350794 states to 1350794 states and 1831165 transitions. [2022-12-13 12:33:03,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1350794 [2022-12-13 12:33:03,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1350794 [2022-12-13 12:33:03,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1350794 states and 1831165 transitions. [2022-12-13 12:33:03,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:33:03,899 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1350794 states and 1831165 transitions. [2022-12-13 12:33:04,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1350794 states and 1831165 transitions.